TW201030935A - Semiconductor die interconnect formed by aerosol application of electrically conductive material - Google Patents

Abstract

An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.

Description

201030935 VI. Description of invention [Related application] This application and J.  U.S. Provisional Application No. 61/121,138, entitled "Semiconductor die interconnect terminal formed by aerosol application of electrically conductive material", issued on December 9, 2008. φ [Technical Field of the Invention] The present invention relates to an electrical interconnection of a die in a stacked die assembly. [Prior Art] A typical semiconductor die has a positive ("active"' The integrated circuit is formed on the front surface, a back surface and a side wall. The side wall and the front surface meet at the leading edge and the back surface at the trailing edge. The semiconductor die is typically provided with an interconnect pad (crystal) a grain pad) on the front side for electrically interconnecting circuitry on the die with other circuitry on the component on which the die is located. Some of the die are along one or more die sides on the front side thereof The grains may be referred to as peripheral pad grains. The grain pads of other grains are arranged on the front side near one or more columns in the center of the grains. These grains are called central pad crystals. Grains. Grains can be "rerouted" to provide the appropriate interconnect pad configuration at the margins of one or more grains ("interconnect margins") or near interconnect margins. Semiconductor dies can be used in any of several ways with a -5 - 201030935 Other circuits in the package (such as 'circuits on a package substrate or a lead frame') are electrically connected. This Z-type interconnect can be borrowed by, for example, wire bonding, or by flip-chip interconnects, or This is achieved by a tab interconnect. The package substrate or leadframe provides the underlying circuitry (second interconnect) of the package and the components on which the package is mounted, such as a printed circuit Electrical connections between the circuits on the board. Several methods have been provided to increase the density of effective semiconductor circuits in integrated circuit chip packages while minimizing package size (package footprint, package thickness). In a method for fabricating a high density package having a smaller footprint, two or more semiconductor dies of the same or different function are stacked and mounted and attached to a package substrate. Electrical interconnects of stacked semiconductor dies have several challenges. For example, two or more dies in a stack can be mounted on the substrate with their front faces facing away from a substrate, and The die-to-substrate or die-to-die wire bonding is connected. The size of the grain on the die-bonded interconnect line can be above The fabrication or arrangement of the upper die does not cover the margin of the underlying die to which it is attached so that sufficient horizontal clearance is provided to accommodate the wire bonding tool. If the amount of offset is too small, the wire bonding tool will strike and damage the upper die. In addition, the bias must be wider so that the bonding wires between the upper die pad and the lower die pad do not touch. To the upper grain margin. When the upper grain area is narrower than the lower grain, or when the upper grain is set by -6 - 201030935, the upper grain coverage area is related to the lower grain side When there is enough offset, sufficient clearance can be provided. However, the need for a sufficient amount of offset to accommodate the wire bonding tool and leads limits the size of the die stacked in this manner. When the interconnect pads are only disposed along a margin of the die, the die can be placed in a step-by-step manner, in which way the interconnect margins of all of the die are oriented the same In the direction of the interconnect, the interconnect pads on each die are exposed by biasing the stacked die. Sufficient offset is required to accommodate the wire bond tool and leads to limit the number of dies that are stacked in this manner because the footprint of the die stack becomes larger as the number of dies increases. Alternatively, the grains in the die stack can be directly interconnected by connecting them to a common substrate on which the die stack is mounted. When a lower die in the die stack is wire bonded to the substrate, and a footprint of the upper die covers the margin of the underlying die, a spacer can be inserted for A sufficient gap is provided between the upper die and the lower die to accommodate the wire loop on the lower die. In this configuration, the die-to-substrate connection of the lower die must be completed before the spacer and the upper die are stacked thereon, that is, the die must be in situ. Stacked on the substrate and the dies must be stacked and connected in series. U.S. Patent No. 7,245,021 describes a vertically stacked assembly which includes a plurality of integrated circuit dies which are electrically connected by "vertical conductive elements". The die is covered with an electrically insulating conformal coating. The vertical conductive elements are made of a conductive polymer based material that is applied at the edges of the die. The die is provided with a metallic conductive element, one end of each of the gold 201030935 conductive elements is attached to an electrical connection point on the periphery of the die, and the other end is embedded in a vertical conductive polymer component. In this configuration, the metal conductive element or interconnect terminal is bonded to an interconnect pad (die pad), which may be a peripheral die pad within the die, or it may be The dipole of the die circuit is placed at or near the periphery of the die. The interconnect terminal extends outward beyond the edge of the die and, therefore, may be referred to as an "off-die" terminal. The die external interconnect terminal can be, for example, a wire (e.g., formed in a wire bonding operation) or an ear or strip (e.g., formed in a tape bonding operation). Alternatively, the interconnect terminal can be a bump or agglomerate of a conductive polymer material disposed on the die pad. The mass may be shaped such that it extends toward the edge of the die and may extend to the edge of the die or slightly beyond the edge of the grain (to form a die external terminal); it may be in the shape of a thumb. Alternatively, the mass may be formed entirely on the mat. The conductive polymer-based material may be, for example, a hardenable conductive polymer material such as a conductive epoxy. The dies can be arranged in a pair of dies such that the interconnect line margins are vertically aligned (and thus the dies are "vertically stacked"), as shown in U.S. Patent No. 7,245,021, The side walls adjacent to the interconnect margin form a stacking surface. Out-of-grain terminals (wires, tabs, strips, or agglomerates) protrude from the stacking surface so that they can be joined by various methods, such as, for example, using an application to the stacking surface to form a "vertical conductive element" Conductive epoxy traces. When the conductive material agglomerates extend to the stack -8 - 201030935, the agglomerates can likewise be joined by various methods. In configurations having out-of-grain interconnect terminals, or having bumps or bumps of conductive material on the die pad, the terminals are standing above the front side of the die and adjacent grains in the die pair Separated by a gap between the front side of the die and the back side of the previous die to accommodate the terminals. A spacer may be inserted into the gap to support adjacent dies; the spacer may be a film φ adhesive having a thickness suitable to fill the gap and bond the dies to each other. The spacer is configured or sized (eg, it is made smaller than the die, or the edge of the spacer is biased to expose interconnect margins) so that it does not block the interconnects Terminal. Eliminating the need for contacts outside the die is preferred. Thus, the interconnect terminal can be formed in or on the active face of the die at or near the edge of the die where the active face of the die meets the sidewall of the die. The interconnect terminal on the margin may be a die pad or an extension of a die pad; and it may be disposed at or near the die margin due to the die circuit rerouting Grain margins. Alternatively, for example, the interconnect terminal can be formed on the sidewall of the die and can be connected to the integrated circuit of the die by attaching a trace of a conductive material to an extension of the die pad Or connected to the rerouting circuit. Alternatively, for example, the interconnect terminal can be formed to wrap around a chamfer at the edge of the front grain (the intersection of the sidewall of the die and the active face of the die). A portion of the wrap-around terminal is on the chamfer and a portion is on the sidewall of the die. A similar wrap-around terminal can be formed on the back grain edge (the intersection of the grain sidewalls and the back side of the die) where no chamfers are present. Alternatively, for example, the interconnect line 201030935 terminal may be formed such that it wraps around a chamfer formed at the edge of the front die and is further wrapped around a chamfer formed at the edge of the back die. A portion of the wrap-around terminal is chamfered on the front edge of the portion of the die sidewall and partially chamfered at the back edge. In each of these configurations, at least a portion of the interconnect terminal is located on the stacking surface, and thus can be formed into a "vertical conductive" by various methods, such as, for example, application to the stacked face. The conductive epoxy traces of the component are connected at the stacking face. Examples of various interconnect terminal configurations can be found, for example, in S. J. S.  U.S. Patent Application Serial No. 12/124,077, entitled "Electrically interconnected stacked die assemblies", is issued on May 20, 2008. Methods for forming various interconnect terminal terminals at wafer processing levels or wafer array processing levels are described, for example, in L. D.  Andrews, Jr. U.S. Patent Application Serial No. 1 2/143,1,57, entitled "Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication", is incorporated herein by reference. As mentioned above, the peripheral pad die and the redirected die generally have interconnect pads disposed at or near one or more margins ("interconnect line margins") of the die. When the interconnect pads are in close proximity to the die edge and a portion of the die that is not provided within the die pair, the interconnect of the die can be vertically oriented The interconnect is achieved as long as the interconnect protrudes between adjacent dies on the mat. For example, interconnect material (e.g., conductive epoxy) has the ability to flow between gaps between adjacent dies at the margins for use with the edge on the active side of the die Electrically connected to the pads within -10- 201030935. Formed by a flowable and hardenable intrusion to a gap between the grains, see, for example, T. Caskey et al., August 20, 2008, "Electrical Interconnection by Pulsed National Patent Application No. 12/124,097 This patent requires an adjacent die to be sufficient to allow separation of the intervention. φ [Invention] In a general aspect of the invention, a method of providing a wire terminal to a plurality of dies is provided, each die having An interconnect pad margin and an interconnect sidewall having an interconnect pad disposed within a margin of the interconnect with an interconnect, the step of: forming a die of the die, wherein The continuous dies are separated by spacers, and wherein the interconnected sidewalls are substantially in a plane perpendicular to the dies of the dies and the spacers are associated with the interconnects At least a portion of the interconnect line margin is exposed; and the plane of the active face of the grain is less than 90 degrees and greater than 〇 to direct an aerosolized conductive material. Each die overhangs - the underlying exposed Interconnect line margins and during deposition The overhang will interconnect the line margins, the degree of shading and the angle of the jet and the die. That is, at a given jet angle, the gap will be inboard on the interconnect line margin (inboard). The farther the material is involved (the interconnection of the grains can be called the name of the dispersion), the beauty is provided to have an effective surface for forming the interconnection, the edges are adjacent and the particles are contained in the grain stack. Arranged such that the plane edges of the active faces are offset such that the gap between the "shadows" underneath the grains separated by the spray angle associated with the crystal is greater than the deposition: and at a given 11 - 201030935 The gap between the grains, the smaller the injection angle, the farther the deposition reaches the inboard on the interconnect margin, the further the deposition reaches the inner side of the interconnect margin. When the spray angle is close to 90 degrees (close to the extent of the effective plane of the grain), the margin becomes almost completely obscured by the shadow of the upper grain; the spray angle is close to the twist (close to the vertical side of the sidewall) Almost no degree of plane) Substances are deposited on the interconnect margins or pads. At a spray angle of, for example, about 45 degrees, the deposited thickness on all exposed surfaces is expected to be substantially uniform, and the deposition is pre-filled to the bottom. The edge of the grain is at an inner side that is approximately equal to the distance of the gap between the grains. In some embodiments, the grains may be separated and processed independently. In other embodiments, the grains are The spacers are further processed as a stack of die members. In some embodiments, additional grains constitute the spacers. In some embodiments, the additional grains are "dummy" crystals. Granules; in other embodiments the additional grains are effective grains. In another general aspect, the present invention provides a method for forming interconnection terminals on a stacked die assembly, each die having an active face, an interconnect margin and a mutual The wiring sidewall is adjacent to an interconnecting edge and has an interconnect pad disposed within the interconnecting margin, the method comprising the steps of: forming a die of the die, wherein The continuous grains in the die stack are separated by spacers, and wherein the grains are disposed such that the interconnect sidewalls are substantially in a plane perpendicular to a plane of the active face of the die and The spacers are offset relative to the interconnect line edges by -12-201030935 such that at least a portion of the interconnect line margins are exposed; and the plane of the manganes with respect to the effective face of the die is less than 90 degrees And an injection angle greater than 0 degrees to direct an aerosolized electrically conductive material. In some embodiments, additional grains constitute the spacers. In some embodiments, the additional grains are "dummy" grains; in other embodiments the additional grains are effective grains, the additional grains being arranged such that their The interconnect sidewalls are located substantially in a plane perpendicular to the plane of the active surface of the die, and such that at least a portion of their interconnect margins are exposed; and the additional die can also be An interconnecting wire terminal is provided by directing an aerosolized conductive material at an ejection angle of less than 90 degrees and greater than 0 degrees with respect to a plane of the effective face of the die. In another general aspect, the present invention provides a use for forming interconnection terminals on a stacked die assembly and then applying a trace of conductive interconnect material to connect the interconnect terminations A method of fabricating an electrically interconnected layer • stacked die assembly. In another general aspect, the present invention provides a plurality of dies each having an active surface, an interconnect margin and an interconnect sidewall adjacent to an interconnect edge and having An interconnect pad disposed within the interconnect margin and having an interconnect terminal that forms a line formed by the pad on the interconnect and the interconnect sidewall. In another general aspect, the present invention provides a stacked die assembly, each die having an active face, an interconnect margin and an interconnect sidewall that is associated with an interconnect edge Adjacent to and having an interconnect pad within the interconnect margin - 13-201030935; the component has a die of the die, wherein successive die in the die are spacers Separating, and wherein the grains are disposed such that the sidewalls of the interconnect are substantially in a plane perpendicular to a plane of the active face of the die and the spacers are offset relative to the edges of the interconnects And an interconnect terminal that forms a line formed by the pad to the edge of the interconnect and on the edge of the interconnect and on the sidewall of the interconnect. In another general aspect, the present invention provides an electrically interconnected biased die stack assembly and a method for interconnecting the biased die stack assemblies. According to this aspect, a uderfill is deposited on an inside angle formed by a sidewall of the die and a bottom surface to form a fillet; and an interconnect trace It is formed which passes over the surface of the fillet. The sidewall of the die may be, for example, a sidewall of the interconnect of the bottom die; and the underlying surface may be, for example, a region of the die attach side of the substrate, the inside of the bond pad (inboard) And adjacent to the grain side. Alternatively, for example, the interconnect sidewall may be an upper interconnect sidewall of the die; and the underlying surface may be an electrically insulating region on the front side of the underlying die, the crystal on the underlying die The inside of the pad is adjacent to the upper sidewall of the die. Alternatively, for example, the sidewall of the die may be a flip-chip die sidewall that is oriented downwardly on the substrate and is electrically connected to the substrate within the die coverage region. The bottom surface may be, for example, a region on the die attach side of the substrate, the inner side of the bond pads being inboard and adjacent to the die side. Alternatively, for example, the interconnect sidewall may be an interconnect sidewall of a die stacked on a flip chip; and the underlying surface may be, for example, -14-201030935, the back of the underlying flip chip An electrically insulating area. The lower jaw can be formed such that it forms a fillet near a right triangle cross section; the bevel of the triangle is a bevel on which an interconnect trace can be formed; a vertical edge of the triangle The hypotenuse forms an angle at or near the edge of the upper die interconnect. The bevel of the fillet may be slightly concave or convex, or a more complicated slightly curved surface. The chin can be CTE compliant to help stabilize the assembly and reduce the delamination effect. Furthermore, the lower jaw shaped as described above can provide a gentle transition from grain to grain or from grain to substrate, eliminating the edge of the interconnect at the die and at the die The rear edge of the side wall transitions at a sudden angle (about a right angle) at the inner corner where the bottom surface meets. In some configurations, a first lower fillet formed at a sidewall of a bottom die can support a first set of electrical interconnect traces that connect the bond pads on the bottom die to the base The bonding pads in the first row of bonding pads on the material are connected; and an additional mandrel fillet is formed on the first interconnecting trace line on the first # 塡 of the sidewall of the upper die And the bottom die can support a second set of interconnect traces, wherein the die pad on the upper die is bonded to the second row of bond pads on the substrate outside the first column of adhesive pads. pad. The interconnect trace can be formed by directing an aerosolized conductive material into a line that contacts a first pad, above the surface of the fillet, and the contact one will be electrically connected to the The second pad of the first pad. The deposition for the interconnect traces can be performed in a single pass of the jetting device; or in two or more sweeps to increase the amount of material being deposited. -15- 201030935 The dies and components in accordance with the present invention can be used in computers, communication devices' and consumer and industrial electronic devices. The present invention will now be described in more detail by reference to the accompanying drawings in which FIG. These drawings are schematic representations showing the features of the present invention and other features and structures, and are not drawn to scale. In order to improve the clarity of the presentation, in the figures showing the embodiment of the present invention, elements in one figure corresponding to the elements in the other figures are not all relabeled because they are in all the figures. It is easy to recognize. Moreover, some features are not shown in the drawings for clarity of presentation, when it is not necessary to understand the invention. In some places in this description, terms of relative positional relationship, such as "above", "below", "upper", "lower", "top" , "bottom" and the like are used with reference to the directions in the drawing; these terms are not intended to limit the direction of the element when it is used. 1A-1C show stages in progress 2, 4, and 6 during interconnection of stacked die assemblies in accordance with an embodiment of the present invention. In this example, four dies 1 '10 2, 11" are stacked on each other. Each die has an active ("positive") face 12, an opposite back face 16, and a side wall 14. A front side grain 13 is defined at the intersection of the front side and the grain side wall, and a back side die edge 15 is defined at the intersection of the back side of the crystal grain and the grain side wall. An interconnect pad, such as 18, is disposed 16 - 201030935 within the margin of the die of the active face of the die adjacent the edge of the front die; thus an interconnect pad is disposed therein The die margin may be referred to as "interconnect line margin", and the front die edge may be referred to as an "interconnect line edge" and adjacent to the interconnect edge The sidewalls of the die can be referred to as "interconnect sidewalls." The interconnect pads may be peripheral pads disposed within the die as the die are provided; or rerouting may be grouped for a different φ than the die pad in the die The interconnect pad configuration is provided. Adjacent grains in the die stack are separated by spacers 1 , U_L, 11^, the spacers are sized and arranged to be spacer walls, and ir_» 1911 is depressed relative to the sidewalls of the die 'Let the die pad 18 uncovered. The dies are arranged such that the ridges of the interconnects are disposed substantially vertically (and not necessarily absolutely perpendicular) over another dies, and such sidewalls of the interconnects are substantially ( It is not absolutely flat) lying flat on a plane substantially perpendicular to the plane of the effective face of any of the grains. In the example Φ shown in these figures, each of the grains is covered by a conformal electrically insulating coating 17, which may be made of an organic polymer such as, for example, a parylene. ), to manufacture. The spacer J_J_, ' i 11 may be, for example, a "dummy" crystal grain, or an adhesive film. Or, for example, the spacer, 1JJ_, 1_1_M pj, is an additional interposed effective die that is oriented such that their respective interconnect sidewalls protrude beyond the die, 1 〇I , 1 〇" , 1^11 other side walls. Such a die stack can be referred to as a "staggered die stack" and the configuration of the various staggered die stacks is disclosed in the above-cited -17-201030935 U.S. Patent Application Serial No. 12/124,077 When the spacers are an adhesive film, the spacers are used to bond the grains in the die stack. When the spacers are "dummy" grains, or When intervening effective grains, they may be bonded to the grain pile by an additional adhesive. For example, the adhesive may be a grain adhesion adhesive and may be applied as a liquid or may be applied as a thin film. Alternatively, when the grains are provided with a conformal dielectric polymer coating, the dielectric coating can be used to bond the grains to each other in the grain stack. @图1B Figure 1A shows the stacked die assembly in the case of stage 4, according to the present invention, in this stage each die has an interconnect line terminal 40. - 40' » 40", 40. ". According to the present invention, the interconnection terminals are made of a conductive material to be applied in the form of an aerosol, which will be described later. The interconnect terminal is electrically connected to the interconnect pad 18 and extends from the pad over the electrically insulating coating 17 around the interconnect edge 13 and overlying the interconnect sidewall 14» because of the interconnect terminal The material is applied in the form of an aerosol, so the interconnect terminal follows the shape of these surfaces, ie, 'follow the shape of the G die pad', i.e., I18 in the figure, an electrically insulating coating on the edge of the interconnect. The shape of the surface, that is, the 113' in the figure and the shape of the side wall of the interconnect, that is, 114 in the figure. In this example, the interconnect terminal does not extend to 19,192. ,19"Bu. Nor does it extend to the back side of the die, i.e., the outer portion from the spacer wall. In other configurations, the electrically conductive material can contact the spacer wall. Therefore, there is no electrical continuity of the grains to the grains between the interconnect terminals of adjacent dies. The method for forming the interconnection terminal will be described below with reference to Figs. 2' -18- 201030935 3 A-3D ' 4A - 4C ' 5 . Conductive materials suitable for use in the interconnect terminal include materials that can be applied in the form of an aerosol, such as, for example, a conductive ink, such as any non-particulate ink and the like. The interconnect terminal material may be a hardenable material. Suitable interconnect materials are, for example, the "ElectroSperse" series of inks supplied by Five Star Technology, Inc., of Independence, Ohio. At the stage shown in Figure 1B, the grains in the die are not electrically connected. At this stage, individual dies (each die is provided with a complete set of interconnect terminals) will be separated at the die-spacer interface in some applications' and then subjected to subsequent processing. In these applications, the spacers are discarded after separation; or the spacers are left on the selected die to serve as die spacers in the environment of use. Regardless of whether the spacer is temporary, the separated dies can be mounted, for example, separately on a support and electrically connected to circuitry in the environment of use. Alternatively, the spacers may form part of a complete and interconnected stacked die set. 1C shows the stacked die assembly of FIG. 1B in the stage 6 with a vertical electrical interconnect 216 of electrically conductive material and respective interconnect terminals 1Q_,,: 2, 40,, ', for electrical connection Interconnect pads on each die. The vertical interconnect 216 contacts the interconnect terminal surface jJJ_, 113, 113 ", 113' " at the edge of the die, and the interconnect terminal surface 114, 114', 114" at the sidewall of the die, 114''. As shown, the interconnect material need not be introduced into the gap between adjacent dies because the terminals provide the smear through the interconnected die edge and interconnect interconnect the die sidewalls. Electrical continuity of the grain pad to the edge of the interconnected die. -19- 201030935 A conductive material suitable for the vertical electrical interconnection is provided in a flowable form 'which can be subsequently hardened. The vertical interconnect material may be a conductive polymer; or a conductive ink, such as a hardenable epoxy; and the interconnect processing may include forming a trace of the uncured material to a predetermined The pattern is then hardened to hold the electrical contacts together with the pads and to maintain the mechanical integrity of the traces between them. The interconnect material is applied using an application tool such as a syringe or nozzle or needle. The material is applied to the sidewall surface by the tool in a sinking direction generally toward the end of the lead, and the tool is moved in the working direction on the surface of the die of the die face. The material can be extruded from the tool in a continuous stream' or the material can exit the tool in the form of droplets. In some embodiments, the material exits the tool' in the form of a droplet jet and is deposited as a dot that coalesces upon contact with the surface of the interconnect or after contact. In some embodiments, the deposition direction is substantially perpendicular to the grain sidewall surface, and in other embodiments the deposition direction is at an angle to the direction perpendicular to the surface of the die stack. Depending on the location on the die and the substrate on which the die pad is to be attached, the tool can be moved in a substantially straight working direction or in a tooth-like working direction. Optionally, the plurality of deposition tools can be maintained in a group of components or an array of tools and operated to deposit one or more material traces during a single sweep. Alternatively, the material can be deposited by needle transport or pad transport using a needle or a pad or group of components or a needle or array of needles. -20- 201030935 The application of materials for vertical interconnects can be automated; that is, the movement of the assembly or array of components or arrays of the work or tool can be controlled automatically, by the operator appropriately Stylized. Alternatively, the material for the vertical interconnects can be applied by printing, for example, using a row of printheads (which have an array of nozzles), or applied, for example, by screen printing or using a mask. A variety of methods for forming vertical electrical interconnections are described, for example, in the above-referenced U.S. Patent Application Serial No. 1 2/1,24,097. As mentioned above, the interconnect terminal material is applied in the form of an aerosol. Preferably, the terminal material is applied by aerosol jet printing. In aerosol jet printing, the material is aerosolized and then introduced into a carrier into a gas powered focused droplet stream that is directed through a nozzle to a target surface. Suitable aerosol spray equipment can include, for example, the M3D system sold by Optomec Corporation of Albuquerque, New Mexico, USA. Figure 2 shows a nozzle of an example of a suitable aerosol spray device in a manner indicated by a section of the nozzle axis. The nozzle 8 has a lumen 24 defined by an inner surface 22 of a tubular wall 20. An aerosol head (not shown) forms a sheath gas 25 that surrounds an aerosolized material stream 23. The sheathing gas and the entrained aerosolized material stream are ejected from the tip end 26 of the nozzle along a flow axis 27. The profile of the jet of the aerosolized material (i.e., the shape of the cross-section) and size can be controlled by selecting the size of the nozzle lumen and controlling the gas flow at various points around the flow axis. The jet profile can be substantially circular, for example, oval. The apparatus can be operated to direct the jet toward a target surface, and the target and the nozzle can be moved relative to one another as indicated by arrow 29 to form a line of material on the target surface. Figures 3A-3C show the resulting material lines. In the example shown here, the profile of the jet has an elongated rounded end shape such that at any time the material will be deposited into a corresponding shape as shown at 32 in Figure 3A. The nozzle tip moves over the target surface in the direction indicated by arrow 39 in Figure 3A and forms a line 34 which, as shown in Figure 3B, has a width of 0 w which is approximately equivalent to the width of the jet profile. Figure 3C shows a cross-sectional view of a line of material 34 deposited on a target surface 35 having a width w and a thickness t. The profile of the jet may have other shapes than the shape having an elongated rounded end. Figures 3D and 3E show the line of material obtained in the embodiment in which the jet has a substantially circular shape such that at any point in time the material will be deposited into a corresponding shape as indicated at 36 in Figure 3D. The nozzle tip moves over the target surface in a direction 所示 indicated by arrow 39 in Figure 3D and forms a line 38 having a width that corresponds approximately to the width of the jet profile as shown in Figure 3D ( diameter). The thickness of the deposited material line is, in some embodiments, between about 10 nanometers or less to about 4 micrometers or more, typically in the range of about 5 microns to about 20 microns. In some particular embodiments it is about 10 microns. The width of the line of deposited material is in some embodiments between about 1 micron or narrower to about 150 microns or more. The stages in the method for forming interconnection terminals in a die stack as shown in Fig. 1A-22-201030935 and obtaining the results shown in Fig. 1B are shown in Fig. 4A, 4B' 4C. ; 5A, 5B; and 6A, 6B. These figures show a nozzle 8 as generally illustrated in Figure 2 which directs an aerosol material spray 23 from the nozzle tip 26 along a jet axis 27 toward the die stack 2 shown in Figure 1A. The nozzle is moved in the direction indicated by arrow 49 such that it accumulates a line of material on the target surface of the die. The nozzle is positioned such that the jet axis 27 is at an angle Φ 0 with respect to the effective faces of the grains. Figure 4A shows a stage in which the moving jet has left a line of deposited material (44 turns) on the die LQ-: the line begins at 418 on the die pad 18, at 413 It passes through the interconnect edge 13 and partially passes over the interconnect sidewall 14 at 414. The insulating conformal coating 17 prevents the material from contacting the die, but is exceptional at the die pad 18. The conformal coating is open at the pad 18 and exposes the pad. The interconnect margins of the die lfi_ are shown in partial plan view in FIG. 4C, and the faces of the die, ML '10 2, L〇", are shown in partial plan view - in FIG. 4B . In Figures 4C and 4B, an interconnect terminal column has been completed, and a subsequent interconnect terminal column has been started to the stage shown in Figure 4A; line A-A' shows the cross-section of Figure 4A. Later, as shown in FIG. 5A, as the nozzle is further moved along the arrow 49, the spray circulates the back grain edge 15 and begins to deposit material on the exposed die pad 18' as shown in FIG. . The overhanging portion of the die 10 provides a "shadow" that prevents material from depositing on the underlying grain 10' at a position further inside than the point 418'. It will be appreciated that the point at which the underlying grain begins to deposit will be from angle 0 and by the thickness of the spacer between adjacent grains in the stack of grains 23-201030935 or between adjacent crystals The distance established by the thickness of the grains between the grains is determined. Figure 5B shows the die stack of Figure 5A in a partial front view. The interconnect terminal 440 at the die has been completed at this stage, and the interconnect terminal on the die 1 is not shown in this figure. Later, as shown in FIG. 6A, as the nozzle is further moved along arrow 49, the jet moves over the exposed target surface of the die 1113b and begins to deposit material material 41<" in the die 10," The exposed die pad is 18''' on. The projections of each of the grains in the die stack provide a "shadow" which prevents material from depositing on the adjacent underlying crystal grains at a position further inside than the deposition starting point. Figure 6B shows the 6A die stack in partial front view. The interconnect terminal 1H on the die 10, the interconnect terminal 440 on the die 10', and the interconnect terminal 440'1 on the die 10" have been completed at this stage, and The interconnect terminal of the die 10'_± is not present in this figure. Figure 7 shows the grain separated by a thinner spacer 5丄, ILL, 5 1" in a stage similar to the deposition procedure shown in Figures 5A and 5B, 10', LQ1L, 10'&quot ;^Grade stack 52. Figure 7 shows a stage in which the moving jet has left a deposited material line (540) on the die j_Q_: the material line begins at 518 on the die pad 18 and passes at 513 Interconnecting edge 13 and passing through interconnecting sidewall 14 at 514: the jet has passed through the back grain edge 15 and has begun to deposit material on the exposed die pad IV on die JJ1, as in 518' Show. As already described in the above example, the overhanging portion of the die 10 provides a "shadow (shad〇w 201030935)" which prevents material from being deposited on the underlying die 101 at a position further inside than the point 5 18 ' At the office. As mentioned above, the position at which the underlying grain begins to deposit will be determined by the angle Θ and by the thickness of the spacer or between the adjacent grains between adjacent grains in the grain stack. The distance established by the thickness of the granules is determined. Since the distance between adjacent grains in the grain stack is less than the distance in the above example, the nozzle must be arranged to sandwich the jet along a small angle with the active face of the die. The axis guides the jet. In the above illustration, the nozzle is moving along a track that is substantially parallel to the plane in which the effective face of the die lies. In other embodiments, the nozzle is moved along a track that is substantially perpendicular to the plane in which the effective face of the die lies. In still other embodiments, the nozzle is moved along a track at other angles to the plane from which the active face of the die is located. The above-mentioned U.S. Patent Application Serial No. 1 2/1,24,077 discloses a stacked die unit and a stacked die assembly having different stacked configurations. φ For example, in some embodiments, each die has an interconnect pad positioned within a grain margin along at least one first die edge, and subsequent grains in the die stack They may be arranged such that their respective first grain edges face the same face of the die stack. This configuration presents a "stepped" die stack with interconnects formed on the steps. In other embodiments, for example, each die has interconnect land margins along at least one first die edge, but subsequent dielines in the die stack are set to their respective A die edge is facing a different (e.g., opposite) face of the die stack. When the first die edge faces an opposite die face, this configuration presents a - "staggered" die stack of -25-201030935, where (from the bottom of the die stack) The first grain edge of the odd-numbered grains faces one die face and the first die edge of the even-numbered die faces an opposite die face. In the staggered die stack, the first die edges of the odd-numbered die are vertically aligned on a die stack surface, and the corresponding upper interconnect pads are connected by a vertical interconnect; The first die edges of the even die are vertically aligned on an opposite die stack, and the corresponding upper interconnect pads can be connected by another vertical interconnect. In the configuration of the staggered die stack, even grains 0 are used as spacers between odd grains, and odd grains are used as spacers between even grains. Because the spacers between the dies are relatively high (approximately the thickness of the intervening dies), the interconnect traces are formed into traversing portions of the unsupported interconnect distance. In other embodiments, for example, grains having an X-direction dimension greater than a gamma-direction dimension are stacked, wherein subsequent grains in the grain stack are vertically adjacent grains above or below It is layered 90 degrees to stratify. In these embodiments, each of the dies has a mutual margin within a grain margin along at least one of the first narrower grain edges (typically along two narrower grain edges) a wire pad, and (from the bottom of the die stack) the first grain edge of the even grain faces a first die face of the die stack, and the first crystal of the odd grain The edge of the grain faces a second die face that is at 90 degrees to the first die face. In any of these embodiments, each die may additionally have an interconnect located within a die margin along a second die edge other than the first die edge The wire mat, and the grain edge can be an opposite edge or an adjacent (90 degree) grain -26-201030935 edge. 8A-8C are in progress of stages 82, 84 and 86 during interconnection of stacked die assemblies in accordance with another embodiment of the present invention. In this example, seven grains i, 3, ill, m, L〇lLJ U1L' 10'" are stacked on each other. As with the example shown in Figures 1A-1C, 'each die 10, l_OJ_, 1 0", 1 0, " has an active ("positive") face 12, an opposite back face 16, and a side wall. 14. A front die 13 is defined at the intersection of the front side 12 φ and the die sidewalls 14, and a back die edge 15 is defined at the intersection of the back face 16 of the die and the die sidewalls 14. Interconnect pads, such as 18, are placed in the die! _0_, 101' '10, " the effective area of the die is adjacent to the margin of the front grain edge; thus the die margin of the interconnect pad is disposed therein May be referred to as "interconnect line margins", which may be referred to as "interconnect line edges," and the sidewalls of the die adjacent to the interconnect line edge may be referred to as "interconnect lines" "" sidewalls". The interconnect pads may be peripheral pads disposed within the die as the die is being supplied; or rerouting may be different from die pads in the die The original configuration of the interconnect pad configuration is provided. The grains m, ιοί, 1^2' intervening grain grains U·, ill, 8JJ1 are separated in the die stack, they are Can be invalid grains' or they can be additional effective grains that are oriented differently than the grains, J_01, JL〇lL '10^1, such that their respective interconnect sidewalls do not appear in this pattern That is, when the intervening grains are effective grains, they can be rotated (for example, related to the grains 15_, 151 '2' 1^ It is rotated by 90 degrees or 180 degrees. The size and setting of these intermediate grains are set to -27-201030935 as the spacer wall, 89', 8£11 relative to the grain grain 1 'Lfil ' 1 〇 The sidewalls of the interconnects of '1, 10, " are recessed 'so that the die pad 18 is uncovered. In the embodiment where the intervening grains are effective grains, 'the intervening grains iJ_, Bil, 8 1 11 of these interconnect line margins 'interconnect line edges and interconnect sidewalls are not shown in these figures. The grains are placed in the die stack such that the grains H, 1 The interconnect edges 13 of -0^- '10'" are disposed substantially perpendicular to each other such that the interconnect sidewalls 14 are substantially (although not absolutely) flat in a direction substantially perpendicular to the grains Any of the grains has a plane on which the @ 面面 lies. This grain stack can be called a "staggered" grain stack, and the configuration of various staggered grain stacks is revealed in In the above-referenced U.S. Patent Application Serial No. 1 2/1,24,077, the disclosure of which is incorporated herein by reference in its entirety, in the <RTIgt; The intervening grains can be interconnected in accordance with the present invention. Figures 9A, 9B, 9C show a staggered die stack configuration. Figures 9A, 9B show an embodiment of a stacked die assembly, in this embodiment the crystal The alternating grains within the heap are placed one on top of the other such that the edges of the interconnects are vertically aligned. In this configuration, adjacent grains in the stack, such as the top two crystals The particles 91, 92 are oriented oppositely (one die is rotated by 180 degrees relative to the other die) such that the interconnect margins 93 and 94 are on opposite sides of the die stack. This configuration is described in more detail. Shown in Figure 9C. Referring now to Figure 9C, the die 91 is stacked on the die 92h. The interconnect line margins 93 of the grains 2_1_ are oriented toward the right side of the figure, and the interconnect line margins of the grains 2_2_ are oriented toward the left. The dies are offset such that the interconnect terminals of the interconnect margin 94 are exposed. -28- 201030935 Interconnect pad 95, 9. 6 are each provided with interconnect terminal 930, 940 which is formed as described above to provide the location of the trace or column 916, 926 contact of the interconnect material formed on these faces. . As shown in FIG. 9C, each of the first pair of dies, 互连1, of each of the interconnecting line margins 93, 94 is suspended above the interconnecting line edge of the pair of dies; thus, for example, The interconnect margin of the grain, 94 is suspended in the pair of die 2J_L below, and the interconnect margin is £11,9_4'± square. The configuration of the edge φ distance (right or left side of the figure) of each group is similar to the structure shown in Fig. 8C, in which (even) grains 92, 9Y, etc. are used as (odd) grains 91, 91', etc. Equal spacers. Thus, interconnect traces 926 provide electrical continuity between the grain grains, £11, £1, and 2_2"; and interconnect traces 9 1 6 provide between the grain grains § Hey, 9JJ.  >91"> 91’', electrical continuity between. In the examples shown in these figures, each of the dies is covered by a conformal electrical insulating coating 97 which may be fabricated from an organic polymer such as, for example, poly(p-xylyl). As mentioned above, certain dies, as they are provided, have a die pad on the front side along one or more die margins, and these dies may be referred to as peripheral pad dies. The die pads of the other grains are disposed on the front side adjacent to one or more columns of the center of the crystal grains, and these crystal grains are referred to as central pad crystal grains. When the die is provided with a central pad or has a peripheral pad in an undesired configuration, a redirect circuit can be provided on the die to provide a suitable interconnect pad disposed on one or more In the desired interconnect margin. In the example of Figs. 9A-9C, for example, interconnects 每一 -29- 201030935 on each die are disposed in a die margin along a grain edge. When necessary, the die can be redirected as provided to provide this configuration. As described above, U.S. Patent Application Serial No. 12/124, No. 77, discloses a stacked die unit and a stacked die assembly having different stacked configurations. For example, in some embodiments, each die has an interconnect pad positioned within a die margin along at least one first die edge, and subsequent die in the die stack can They are arranged such that their respective first grain edges face the same face of the die stack. This configuration presents a stepped die stack with interconnects formed on the steps. 10A, 10B, and 10C show a stacked die assembly having a staggered configuration in which interconnect pads on each die (e.g., die 1 〇 1 ) are placed along two The grain margins of the opposite grain edges are within 1 〇 3, 10 04, and the dies may be diverted as provided to provide this configuration. In this example, the dies, Ϊ0Γ, 101", 101"| all have the same orientation in the die stack such that the interconnect margins 103, 104 are on the opposite side of the die stack. The dies are stacked such that their interconnect edges are vertically aligned and the dies are spaced apart by spacers, 102, M2J1. This configuration is shown in more detail in Figure 10C. Referring now to Figure 10C, interconnect pads 1〇5, 106 are each provided with interconnect terminals 1 030, 1 040 which are formed as described above to provide mutual formation on these faces The trace of the wiring material or the position where the columns 1016, 1026 are in contact. The spacer, 1^11, 1〇2_, may be a film adhesive having a thickness suitable for filling the gap and bonding the grains to each other. Or 'for example, such intervals 201030935 may be intermediate grains' which may be invalid grains, or may be effective grains which are oriented differently than the grains 10丄, 10Γ 101'" such that their respective mutual The dimensions of the interconnected sidewalls that do not appear in the interconnect sidewalls are such that the dummy die pads in the die stack are left uncovered. That is, when the intermediate grains are in effect, they can be rotated by 90 degrees with respect to the grains 101, 101, 101 " and in these embodiments, the intervening crystals φ 102', 102" Interconnect line margins, interconnect line edges, and interconnect lines are shown in some of the figures. It will be appreciated that all of the interconnect dies are provided with interconnect terminations which are formed as described above for the interconnect material formed on each side of the die stack. The location of the column contact. The intervening crystal grains may optionally be covered with a film as shown in Fig. 1 〇 c. In the foregoing examples, the stacked die assemblies are electrically interconnected with each other after the formation of the display terminal. Φ Yes, in other embodiments, the dies may be temporarily stacked for the formation of interconnect lines, after the interconnection of the interconnect terminals, the detachment, resulting in a number of individual dies - each crystal There are wire terminals on the grain. Thereafter, the individual dies can be, for example, by mounting them and electrically connecting them to a support: or by, for example, by configuring any of its desired stacked dies and in the die stack The interconnect is interconnected and/or the die stack is electrically connected to a support member. In the example described above, the aerosol spray width is in the extra > 101,,» schema. There are grains on the same grain, 101'" is sized, and the sidewalls are not interconnected with a pad to provide a trace or a thin dielectric as shown in the die at the mutually understood terminals. There are interconnections of individual lands that are laminated into a die electrical that is further integrated into the interconnect-31 - 201030935 wire terminal width, and each is connected by the gas interconnect terminal (or interconnected wire terminal) When wide enough, one at each of the jetting tools (pass wiring terminals. In this method, the one or more adjacent interconnect pads are used to prevent any adjacent interconnect material deposition The number of tools that can be sprayed at each time is limited by the maximum spray width. In principle, the entire length of the interconnecting wire terminal of the jetting tool. In the foregoing example, the interconnect glue spray deposition is Formed on the die, wherein the interconnects are vertically aligned, and the die can be electrically connected to a die or die by the same place of the conductive interconnect material in contact with the die terminal Forming a trace or vertical with the interconnect terminal and the material to which the substrate is bonded An example of a sol-jet deposition of an assembly having a die-laminated die is shown below to form contact-connected interconnect traces. These uderfill materials are deposited in a sol-jet deposition. The lines all form a vertical series). In other instances, the masking and jetting methods can be used to deposit two more individual cross-sectional profile widths across the die and between the patterned masked pads being undesired between the pads. The end of the interconnect that is formed during the sweep of conductivity and in relation to the pitch of the interconnect pads can form a gas-dissolved use of the conductive material along the edge of the die. A die stack is constructed such that the interconnect faces of the interconnecting wire stacks that make up the die stack are electrically interconnected with interconnect traces or columns. A circuit that is connected to a substrate can be contacted by a conductive interconnect on a position (which includes a stepped configuration in which the electrical interconnects are interconnected by using a gas pad) In the inter alia embodiment, the inner corner (inner corner) formed by the surface of a grain and a bottom surface of the special 201030935 feature to form a fillet, and a mutual A wiring trace is formed over the fillet. Figure 1 1 A shows a configuration in which the sidewall of the die is an interconnect sidewall 1 104 of an upper die 1153, and the underlying surface is a An electrically insulating region 1196 on the front side of the underlying die 1152 is on the inside of the die pad of the underlying die and adjacent to the upper die sidewall. The deposited lower φ 塡 material forms an inner circle An angle 1190 provides a gentle ramp-down surface extending from the edge of the upper die interconnect line to a bottom surface of the die at the inner side of the die pad, and an electrical interconnect trace 1191 can be formed on the fillet , which pads the upper die 1153 h and the underlying die 1152 (and connects additional grains) The die 1151) is electrically connected to circuitry within the substrate 1500. The electrical interconnect traces in this example are formed by aerosol spray deposition of a conductive material as described above. Formed such that it forms a fillet near the right triangle cross section φ; the hypotenuse of the triangle is a bevel, an interconnect line trace can be formed on the slope; a vertical edge of the triangle and the slope Forming an angle at or near the edge of the upper die interconnect. The bevel of the fillet may be slightly concave or convex, or a more complex slightly curved surface. The lower jaw may be CTE compliant. To help stabilize the assembly and reduce the delamination effect. Furthermore, the lower jaw shaped as described above provides a gentle transition from grain to grain or from grain to substrate. Eliminating a sudden angular (about right angle) transition at the edge of the interconnect of the die and at the inner corner where the trailing edge of the sidewall of the die meets the underlying surface. In some configurations, -33-201030935 Formed in a first lower jaw at the sidewall of a bottom die The fillet supports a first set of electrical interconnect traces that connect the bond pads on the bottom die to the bond pads in the first row of bond pads on the substrate, and an additional chin a fillet that is formed on a first interconnect trace on the first lower sidewall of a sidewall of the upper die and the bottom die can support a second set of interconnect traces from which the epitaxial a grain pad on the grain to the bonding pad in the second row of bonding pads on the substrate outside the first column of bonding pads. A standard chin material can be used to form the fillet, and @ deposited using standard fine-tray application equipment. The preferred chin material can be a high modulus material that has good CTE compatibility with other materials in the assembly. For example, a suitable standard squat Materials are marketed under the name Namics U8439-1. The interconnect traces are substantially conformal to the surface on which the interconnect material is aerosol spray deposited. When no lower jaw is provided, for example, the trace will follow the edge of the grain and the adjacent side surfaces of the grain sidewalls and underlying features. In some configurations where the interconnect is very thin, cracks or cracks in the interconnect line @ will appear at the "inner corner" after thermal stress, ie the back edge of a die in the die and the bottom The surfaces of the materials meet at each other. As shown, when the interconnect traces are formed on a fillet, the sharp corners do not create a surface on which the interconnect traces are formed. In particular, for example, the surface of the fillet (e.g., the fillet 1190 of Figure 11A) is gently sloped down to the surface of the underlying feature (e.g., surface 1196 of the underlying die 1152 in Figure 11A). . Moreover, in the examples of -34-201030935, the fillet intersects the edge of the interconnect on the upper sidewall of the die (e.g., sidewall 1 1 〇 4 of die 1 153 in Figure 11 A) The top portion is such that the outer corner on the edge of the interconnect of the upper die (through which the interconnect trace passes) is much smaller than the right angle. The interconnect traces formed on this gently abutting surface are much stronger and more reliable than traces formed on steeply angled surfaces, particularly very thin traces. Fig. 11B shows another example in which the inner fillet 193 2 is formed by φ at the inner corner between the side wall of the interconnect of a die 1153 and the surface of a bottom die; A fillet 1 934 is formed at the inner corner between the side wall of the interconnect of a bottom die 1151 and the surface of a bottom substrate 1550. In this configuration, an interconnect trace 193 1 is deposited over the fillet 1934 for attaching the bottom die 1 1 5 1 to the first column of bonding pads of the substrate 1 550 h; A fillet fillet 1936 is formed on the fillet 1934 and the trace 1931; then an interconnect trace 1941 is formed on the fillet 1932 and the fillet 1936 to The upper die 1153 is connected to the die 1 152 and the second (outer) bond pad on the L5 50. Figure 11C shows a configuration in which the dies 1151 and 1152 are die-up mounted by a die in a die-down manner on a substrate 1 555 h of flip chip A pellet 1161 h, and a middle turn inner fillet 1 900 are formed at the inner corner, the inner corner being the side wall 1914 of the die 1151, 1 924 and the flip chip 1161 and the underlying material i- 5 5 5 . Formed on the surface 1916 inside the bond pad. In this example, an additional lower jaw 1 902 is formed at the inner corner formed by the sidewalls of the interconnects of the die 1152 and the underside of the die 1151 at the inner side of the bonding pads of -35-201030935. . The lower jaws 1900, 1902 provide a gently ramped surface extending from the edge of the interconnect of the upper die 1152 to the surface of the underlying die on the inside of the die pad, and then from the die 1151 The wire edge extends to the bottom substrate at a surface inside the bonding pads, and an electrical interconnect trace can be formed on the sloped surface, which is the upper die 1 1 5 2. The pads on the underside of the die 1151 are electrically connected to circuitry within the substrate 1555. In the example of Figure 1 1 C, the interconnect sidewalls 1 9 1 4 of the die 1161 are shown as being vertically aligned with the sidewall 1924 of the underlying flip chip 1161. In other embodiments, these features are not vertically aligned. For example, Figure 11D shows an embodiment in which the flip chip 1, 1, The sidewall 1 964 of 7 1 protrudes beyond the sidewall 1 9 1 4 of the upper die 1151. The inner fillet 1962 is formed at an inner corner between the side wall of the interconnect of the die 1152 and the surface of the underlying die 1151. A second lower cymbal fillet 1 966 is formed to be formed between the sidewalls of the interconnect line 1 914 of the die 1151 and the protruding surface of the flip chip 1171, and between the overlying crystal grains 1171 The inner corner of the Q side wall 1 964 and the bottom substrate 1 565 between the inner surfaces of the bonding pads. The fillet 1 966, 1 962 provides a gently ramped surface extending from the edge of the interconnect of the upper die 1152 to an electrical interconnect trace at the surface of the substrate on the inside of the bond pads 1961 can be formed on the ramp-down surface that electrically connects the upper die 1152 and the underlying die 1111__ to the circuitry within the substrate 1 55 5 . As mentioned above, the interconnect material deposited by aerosol spraying conforms to the contours of other deposited surfaces. These surfaces can make electrical contact with the conductive traces -36- 201030935, with the exception of where the surfaces are electrically insulated. Therefore, it should be understood that the surface where the die will be in contact with the trace traces and where electrical contact is not desired should be electrically insulated. This can be achieved by applying a conformal boundary dielectric film to the surfaces and then opening the electrically insulating film where electrical contact is desired. The dielectric film is shown in Figures 11A-11D; suitable films are shown in other figures herein. A particularly suitable boundary electrical film is a parylene film which can be applied φ prior to assembly into the grain stack; or after assembly but prior to formation of one or more fillets; or It is applied at any time prior to forming one or more interconnect traces. It will be appreciated that the deposition of the tantalum material in a controlled manner can be formed on the underlying features on the inner surface of the mat - a good fillet surface profile without the need for the fillet material Perforations are formed in the upper surface to ensure that the pads for electrical connection are exposed. In forming interconnect line terminals or interconnect traces by aerosol injection, an insufficient amount of material can be applied during a single sweep of the spray tool. Φ Depositing the material in two or more tool sweeps may be desired or required (depending on the nature of the interconnect material and the parameters of the jet itself) to accumulate enough The amount of material. The jetting tool can be moved in a first direction upon the first sweep and then moved in the opposite direction during the second sweep. Alternatively, the tool can pass repeatedly in the same direction on the same path. For example, it may take up to ten sweeps. When repeated sweeps are carried out, depending on the physical properties of the material, subsequent sweeps will cause the deposit to be widened due to the flow of material. In this case, the material may be hardened or partially hardened after one or more sweeps; or the material may be hardened or partially hardened after each sweep or a specific number of sweeps. This hardening or partial hardening helps to limit the width of the material being deposited. The transverse profile of the trace obtained after multiple sweeps will be thicker in the central portion than the edge portion. When repeated sweeps are performed, more material mass will be deposited at the start and end points, and the material will be ejected at these locations into a larger width trace, ie, the trace The line will swell at these locations. The excessive swelling of the trace increases the likelihood that adjacent traces will contact each other. In order to reduce the extent of this swelling, when multiple sweeps are performed on a given trace, the start and end points of these sweeps can be staggered. That is, not all sweeps are at the beginning and end at the same point along the trace. Therefore, there are two or more smaller swellings at the ends near a completed trace, rather than a large swelling; and the smaller swelling does not cause too much trace at these locations. Line width. These sweeps do not have to start at or near the center of a pad; when the pad is elongated in the direction of the trace, multiple sweeps can begin at different positions along the length of the pad. point. Again, these sweeps do not have to start on a pad; they can begin on the inside of a pad (e. g., on a die) or on the outside of a pad (e.g., on the substrate). Alternatively, when repeated sweeps are performed, the points at the beginning and end of the adjacent traces may be staggered such that the swelling or enlargement from the trace is tied to the swelling or enlargement of the adjacent traces. Outside or inside. In a simple example, the sweep for each trace can begin and end at the end of the trace; and the beginning and end of a trace can be at the beginning of the adjacent trace -38-201030935 and end Inside or outside. It will be appreciated that some combinations of the starting and ending parental errors of the traced start and end points of the deposition sweep can be used. In the example shown in Figures lie and 11D, a conventional chin is shown to be additionally provided between the flip chip and the substrate. The various underlying materials may be the same word dwarf or they may be of different materials. This conventional jaw can optionally be delivered in a separate jaw delivery procedure, or in the lower jaw fillet (1900 in Figure 11C; 1966 in Figure 11D). In the program, it is provided. The grains in the grain stack may have the same or similar function, or one or more of them may have a function different from the other grains. For example, referring to Figures 11C and 11D, the flip chip can include processor functionality, and the die stacked thereon can be a billion-body die. Other die combinations can also be implemented. Additional dies may be laminated and provided with internal fillets and interconnects as described above. It will be appreciated that the use of a lower fillet to provide a gentle contoured surface on which interconnect traces can be formed can be applied to have a grain stack other than the example shown in Figures 11 A-11D. In the configuration. For example, one or more of the grains stacked on the lowermost die in the die stack may be oriented differently than the bottommost die in the die stack, and/or stacked on top of the die The other grains of the grains are different. All of the patent applications referenced herein are hereby incorporated by reference. -39-201030935 Other embodiments are included in the scope of the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic view showing a partial cross section showing a crystal grain stack. 1B and FIG. 1A are schematic views, partially in cross-section, showing a die stack having interconnect terminals in accordance with an embodiment of the present invention.

1C is a schematic cross-sectional view, partly in cross-section, showing a die stack interconnected in accordance with one embodiment of the present invention. Q Figure 2 is a cross-sectional view showing a portion of an aerosol application tool suitable for use in fabricating interconnect terminals in accordance with an embodiment of the present invention. 3A and 3B are plan views showing stages during deposition of interconnect material in accordance with an embodiment of the present invention. Figures 3D and 3E are schematic plan views showing stages during deposition of interconnect material in accordance with another embodiment of the present invention. Figure 3C is a cross-sectional view of a deposited interconnect material taken along line C-C of Figure 3B. 4A-4C, 5A-5B, 6A-6B are schematic views showing stages in depositing interconnect material on a die stack in accordance with an embodiment of the present invention. 4A, 5A, and 6A are partial cross-sectional views; Figs. 4B, 5B, and 6B are partial front views; and Fig. 4C is a partial plan view. Figure 7 is a partial cross-sectional view showing the stage of depositing interconnect material on a die stack in accordance with another embodiment of the present invention. Figure 8A is a partial cross-sectional view showing a grain stack. Fig. 8B is a schematic view, partly in section, of Fig. 8A, showing a die stack having interconnecting terminals in accordance with an embodiment of the present invention. Figure 8C is a schematic cross-sectional view of Figure 8A showing an interconnected die stack in accordance with an embodiment of the present invention. Figure 9A is a plan view showing a die stack in accordance with another embodiment of the present invention. 9B and 9C are schematic views showing a cross-sectional view taken along line 9B-9B of Fig. 9A to show another embodiment of an interconnected stacked die assembly. Fig. 10A is a plane not intended to be displayed. A die stack according to another embodiment of the present invention. Figures 10B and 10C are cross-sectional views taken along line 10B-10B of Figure 10A showing another embodiment of an interconnected stacked die assembly. Figures 11A, 11B, 11C and 11D show examples of stacked die assemblies that include electrical interconnections of stepped configuration of biased dies. [Main component symbol description] 1 〇: Grain 1 0': Grain 1 〇 ": Grain 10"': Grain 12: Effective (Positive) surface 1 6 : Back surface 1 4: Side wall 1 3 : Front crystal Grain edge -41 - 201030935 1 5 : Back grain edge 18 : Interconnect pad 1 1 : Spacer 1 1 ^ Spacer 1 1 '' : Spacer 40 : Interconnect terminal 4 0 ' : Interconnect terminal 40'': interconnect terminal 40,,,: interconnect terminal 1 7 : electrically insulating coating 1 1 8 : die pad 1 13 : interconnect edge 1 1 4 : interconnect sidewall 1 9 : spacing Wall 19': spacer wall 19": spacer wall 216: vertical electrical interconnection 1 1 3: terminal surface at the edge of the die 1 1 3 ': terminal surface at the edge of the die 1 13" Terminal surface of the die edge 1 13'": terminal surface at the edge of the die 1 1 4 : terminal surface at the sidewall of the die 1 1 4': at the terminal surface of the die sidewall 1 1 4 ": in the die Terminal surface of the side wall -42- 201030935 114, 8 : C 20 : 22 : 24 : 25 : 23 : φ 26 : 27 : 29 : 34 : 39 : 35 : 38 : 32 : φ 36 : 49 : 440 18 , : 4 18' 4 18' 18"' 440' 440, Μ: in the crystal Terminal surface of the grain side wall nozzle tube inner wall inner surface lumen sheath gas aerosolized material nozzle tip jet axis arrow line arrow target surface line shape shape arrow: interconnected wire terminal exposed pad: point: point: exposed surface : interconnect terminal ': interconnect terminal -43- 201030935 52 : die stack 5 1 : spacer 5 Γ : spacer 5 1 '1 : spacer 8 1 : die 8 1 , die 8 Γ ' : Die 89: Sidewall _ 8 9 ': Sidewall 89": Sidewall 91: Die 92: Grain 93: Interconnect Margin 94: Interconnect Margin 95: Interconnect Pad 9 6 : Interconnect Pad 〇9 3 0 : Interconnect terminal 940 : Interconnect terminal 9 1 6 : Interconnect trace (column) 926 : Interconnect trace (column) 9 3 ': Interconnect margin 94' : Interconnect Margin 9 Γ : Grain 92': Grain -44 - 201030935 9 1" = Grain 92" : Grain 9 1"': Grain 92'" : Grain 101: Grain 10 1': grain 10 1": grain φ ιοί'": grain 103: interconnect line margin 1 〇 4: interconnect line margin 102: spacer 102': spacer 1 0 2 ' ' : Spacer 1 〇5: Interconnect pad 1 〇6: Interconnect pad φ 1〇3〇: Interconnect terminal 1040: Interconnect terminal 1 〇1 6 : Interconnect trace (column) 1 026 : Interconnection Line trace (column) 1 104 : Interconnect sidewall 1153: Upper die 1196: Electrically insulating region 1 1 5 2 : Bottom grain 1 1 90 : Fillet -45- 201030935 119 1: 115 1: 1 500: 1 932 : 1 934 : 1931 : 194 1 : 1161 : 1 900 : 1 902 : 19 11: 1 5 5 5 : 1914 : 1 924 : 1 964 : 117 1: 1 966 : 1 962 : 1 5 65 : 19 11: Electrical interconnect traces grain substrate lower 塡 fillet lower 塡 fillet trace interconnect trace traced grain die fillet fillet electrical interconnect trace substrate The side wall under the side wall of the wiring is covered with a crystal grain. The bottom of the side wall is filled with a rounded corner.

Claims (1)

201030935 VII. Application for Patent Park 1· A method for forming interconnection terminals on a plurality of dies, each of which has an effective surface, an interconnect margin, and an interconnect sidewall a wire edge adjacent and having an interconnect pad disposed within the interconnect margin, the method comprising: forming a die of the die, wherein the die in the die Separated by spacers, and wherein the dies are disposed such that the interconnect sidewalls of the # are substantially in a plane perpendicular to a plane of the active face of the die and the spacers are associated with the The interconnect edges are biased such that at least a portion of the interconnect margins are exposed; and an aerosol is directed at a plane angle less than 90 degrees and greater than the plane associated with the effective faces of the grains Conductive material. The method of claim 1, wherein the dies are separated and processed separately after forming the interconnect terminals. 3. The method of claim 1, wherein the dies and spacers are further processed as a stacked die assembly. 4- The method of claim 1, wherein the additional grains constitute the spacers. 5. The method of claim 4, wherein the additional grains are "dummy" crystals grain. 6- The method of claim 4, wherein the additional grains are effective grains. 7. A method of forming interconnect terminals on a stacked die assembly, each die having an active face, an interconnect margin, and an interconnect -47-201030935 sidewalls a wire edge adjacent and having an interconnect pad disposed within the interconnect margin, the method comprising: forming a die of the die, wherein the die in the die Separated by spacers, and wherein the dies are disposed such that the interconnect sidewalls are substantially in a plane perpendicular to a plane of the active face of the die and the spacers are associated with the interconnects The edge is biased such that at least a portion of the interconnect margin is exposed; and the plane associated with the effective faces of the grains is at a spray angle less than 90 degrees and greater than the twist to induce an aerosolized Conductive material. 8. The method of claim 7, wherein the additional grains constitute the spacers. 9. The method of claim 7, wherein the additional grains are "dummy" grains. 10. The method of claim 7, wherein the additional grains are effective grains. 11. The method of claim 10, wherein the additional germanium grains are arranged such that their interconnect sidewalls are substantially in a plane that is perpendicular to the plane of the effective face of the die And causing at least a portion of their interconnect margins to be exposed. 12. The method of claim 1, wherein the additional dies are directed to aerosolization by a jet angle of less than 90 degrees and greater than the enthalpy of the plane associated with the effective faces of the dies. The conductive material is provided with interconnect terminal. 13. A method of fabricating an electrically interconnected stacked die assembly, the package of -48 - 201030935 comprising: forming an interconnect terminal on a stacked die assembly by the method of claim 7 and thereafter Traces of a conductive interconnect material are applied to connect the interconnect terminals. 14. A plurality of dies in a stack, each dies having an active face, an interconnect margin, and an interconnect sidewall adjacent to an interconnect edge φ and having a set An interconnect pad within the interconnect margin and having an interconnect terminal forming a line formed by the pad to the interconnect edge and on the interconnect edge and at the interconnect Connect the side walls. A stacked die assembly, each die having an active face, an interconnect margin, and an interconnect sidewall adjacent to an interconnect edge and having an interconnect disposed therebetween An interconnect pad within the line margin; the assembly includes: a die of the die, wherein successive grains in the die are separated by a spacer, and wherein the die is Arranging such that the interconnecting sidewalls are substantially in a plane perpendicular to a plane of the active face of the die and the spacers are biased with respect to the interconnecting edges; and an interconnect terminal It constitutes a line formed by the pad to the edge of the interconnect and on the edge of the interconnect and on the sidewall of the interconnect. 16. A method for interconnecting a biased die stack assembly, comprising: depositing an underfill at an inside angle formed by a sidewall of a die and a bottom surface Forming a fillet; and forming an interconnect trace passing through the surface of the fillet -49-201030935 1 7 - as in the method of claim 16th, wherein the deposition is performed Forming the fillet includes depositing a tantalum material such that it forms a fillet having a sloped surface, wherein forming the interconnect trace comprises directing an aerosolized conductive material to form a line in the fillet The method of claim 17, wherein depositing the tantalum material comprises forming a substantially flat ramped surface. 19. The method of claim 17, wherein the depositing-underlying material comprises forming a slightly concave ramp-down surface. 20. The method of claim 17, wherein depositing the tantalum material comprises forming a slightly convex ramp down surface. 21. The method of claim 17, wherein depositing the tantalum material comprises forming a complex slightly curved ramp down surface. The method of claim 16, wherein forming the interconnect trace comprises directing an aerosolized conductive material into a line that contacts a pad on the first die, through the inner Above the rounded surface, and contacting a second turn that will be electrically connected to the turns on the first die. 23. The method of claim 22, wherein forming the interconnect trace comprises forming the line in a single pass. 24. The method of claim 22, wherein forming the interconnect trace comprises forming the line in two or more sweeps. 25. An electrically interconnected biased stacked die assembly comprising: - a die and a bottom feature having an interconnect pad on the side wall of the 201030935 interconnect, An interconnecting sidewall and a surface of the underlying feature form an internal angle; an internal fillet having an internal fillet at an internal corner formed by the interconnect sidewall and the surface of the underlying feature a ramp-down surface; and an interconnect trace that contacts the pad and passes over the surface of the fillet " 26. The assembly of claim 25, wherein the fillet surface of the fillet φ It is roughly flat. 27. The assembly of claim 25, wherein the ramped surface of the fillet is slightly concave. 28. The assembly of claim 25, wherein the ramp-down surface of the fillet is slightly convex. 29. The assembly of claim 25, wherein the fillet material is substantially CTE compatible with the material of one or more of the set of members. Φ 3 0. An electrically interconnected biased stacked die assembly comprising: a substrate, a bottom die mounted on the substrate, and a first upper die; a first lower a fillet, which is formed at a first inner corner formed by a sidewall of the bottom die and a surface of the substrate; a first set of electrical interconnect traces connected to the bottom a pad on the die and an adhesive pad in the first row on the substrate and passing over a sloped surface of the first chin; a second chin fillet formed in the first The -51 - 201030935 on the fillet, the first interconnect trace and the surface formed by the sidewall of the first upper die and the inner surface of the pad on the bottom die a second set of electrical interconnect traces connecting the die pad on the first upper die to the substrate in a second column outside the first column Bonding pad. 3 1 _ The component of claim 30, wherein the bottom grain sidewall comprises interconnect sidewalls of the bottom die. 32. The assembly of claim 30, wherein the W surface of the substrate comprises a region of the die attach surface of the substrate adjacent the pad and adjacent the sidewall of the die. 33. An electrically interconnected biased stacked die assembly comprising: a first die having a sidewall and a bottom feature having a surface, the die sidewall and the The surface meets at a first interior angle; a first chin fillet, which is formed at the first interior corner; & a first set of electrical interconnect traces, and the first die The upper jaw passes over a sloped surface of the first lower jaw. ® 3 4. The assembly of claim 33, wherein the first granule sidewall comprises an interconnect sidewall. 35. The assembly of claim 3, wherein the first portion of the stomach grain sidewall comprises an interconnect sidewall of an upper die. 3. The assembly of claim 33, wherein the surface on the bottom τ _ characteristic structure comprises a front-to-electrical region of the underlying die, the die pad on the underlying die The inside is adjacent to the __ -52- 201030935 grain sidewall. 37. The assembly of claim 33, wherein the underlying feature structure comprises a substrate and the first die sidewall comprises a flip chip oriented on the substrate in a die-down manner A sidewall of the die, the flip chip being electrically connected to circuitry within the substrate within the die footprint. 38. The assembly of claim 37, wherein the surface of the underlying φ feature comprises an electrically insulating region of the die attach surface of the substrate, the inner side of the bond pad on the substrate and The sidewalls of the grains are adjacent. 3. The component of claim 33, wherein the underlying feature structure comprises a flip chip and the first interconnect sidewall comprises an interconnect of crystal grains stacked on the flip chip Side wall. 40. The assembly of claim 33, wherein the underlying features comprise a flip chip and the surface of the underlying feature comprises an electrically insulating region on the back side of the underlying flip chip. Φ 4 1 . The assembly of claim 3, wherein the interconnect trace is guided by an aerosolized conductive material into a pad contacting the first die, through the inner circle Above the surface of the corner, and contacting a line of a second pad that will be electrically connected to the pad on the first die. -53-