201030532 九、發明說明： 【發明所屬之技術領域】 本案為-種多處理物_更新及運作方法，尤指能經由主 處理器下載程式至從處理器中執行，並可藉由外部主機更新主處 理器及從處理器之幢程式之多處理器記憶體更新及運作方法。 '【先前技術】 β 3 _ USB 多電腦切換系統(Keyboard Video Mouse，KVM)主 由個主處理器及夕個從處理器所構成。主處理器端連接發 鍵盤及/滅等週邊設備，而每—做處理器_連接至一台 主機。主處理狀多做處理器之_互連接，並 的傳輸恤彳爾。軸雜_，卩賴主處理器 與多個從處理器之間的傳輸訊號，即可讓使用者經由主處理料 的同-套週邊設備操作任—台從處職端的主機，並且能在需要 的時候’隨時切換連接至另一個從處理器端所連接之主機。如此 之機制可保證在快速切換時不至造成因湖須重新啟用（職nfig) 而延遲太久或各種不_作㈣統㈣相容性的問題。 在習用USB多電腦切換系統的主處理器及多個從處理器之 口中，皆具有唯讀記憶體及隨機存取記憶體。主處理器及從處理器 可透過個自的唯讀記鋪執行欲進行之程式，並且當程式在執行 的時候’可利用個自的隨機存取記憶體暫存程式的資料。當欲進 種式更新時，則必需--更新主處理器與每-個從處理器♦的201030532 IX. Inventive description: [Technical field of invention] This case is a multi-processing object_update and operation method, especially that the program can be downloaded to the slave processor via the main processor, and the main host can be updated by the external host. Multiprocessor memory update and operation methods for processors and slaves. '[Prior Art] β 3 _ USB Multi-Computer Switching System (KVM) consists of a main processor and a slave processor. The main processor is connected to a peripheral device such as a keyboard and/or a peripheral device, and each processor is connected to a host. The main processing is to do the _ interconnection of the processor, and the transmission of the shirt. Axis _, depending on the transmission signal between the main processor and the multiple slave processors, allows the user to operate any of the host-side peripherals through the same-set peripheral device of the main processing material, and can At the time of 'switching to connect to another host connected from the processor side. Such a mechanism can ensure that the problem of delay in the fast switching is not caused by the lake being re-enabled (professional nfig), or the various (4) compatibility. In the main processor of the USB multi-computer switching system and the plurality of slave processors, both the read-only memory and the random access memory are provided. The main processor and the slave processor can execute the program to be executed through a self-explanatory memory, and can use the data of the random access memory to temporarily store the program when the program is executed. When you want to update, you must update the main processor and each slave processor.
201030532 唯讀記憶體。 習用的技術，具有以下缺點： 1. 習用的USB多電腦切換系统，所 、轉所雜處理H所需執行的程 式都必須存放至該從處理器的唯讀記憶體中，將造成硬體 成本的負擔； 2. 習用的龍多電腦切換系統，必須―更新主處理器與每 -個從處理H㈣唯軌㈣，財版本更新過程相當費 3. 習用的USB多電腦切_統，並沒有—套完麵程式版本 集體更新方法，將造成版本控管不易之問題； 4. 習用的USB多電腦切換祕’主要是糊各職錄方式更 新程式，不齡增加題成本，更容纽使錯誤發生； 5·習用的USB多電腦切換系統，一旦系統發生問題，即需要 檢測每-個唯讀記憶體之程式之正確性，增加問題排除之 困難度； 6. 習用的USB多電腦切換祕，程式皆必須儲存至每一舰 處理器之唯讀記憶射，若遭遇竊取時，所有技術資料皆 會被盜取，缺乏保密性； 7. 習用的USB多電腦切換系統，即使程式資料皆於加密後儲 存’當系統在運作時，亦需進行解密執行，目前工具易於 同時拆解其過程，故保密性問題依舊存在。 6 201030532 /此，如何改進上述㈣的缺點，避免將所有程式資料儲存 至每-個從處理器之唯讀記鐘巾，並能以纽之方式進行 版本更新’係為本案所關注者。 【發明内容】 ，本案的目的在於提丨-_且進频多處麵峨體更新及 ❿運作方法，使得從纽n之財可經由线麵下載取得，並且 能透過外部的主機集體快速更新主處理器及從處理器之程式版 ；φ^ 〇 為達上述目的’本案提出一種多處理器記憶體更新及運作方 法包3 S處理器及一從處理器，其中該主處理器中係具一主 啟動載入器（boot loader)，該從處理器中係具一從啟動載入器； 处里器係連接该從處理器及一第一記憶單元’該第一記憶單 鬱元中係具一第—程式，該從處理器係連接-第二記憶單元，並包 含下列步驟： 因應一一般模式，由該主處理器將該第一記憶單元之一應用 程式傳至該從處理器之靜態隨機存取記憶體⑽AM);以及 因應一更新模式，由該從處理器上傳一最新版程式至該主處 理器之該第一記憶單元。 如所述之多處理器記憶體更新及運作方法，其中該主處理器 及該從處理_為_單晶片處理器。 201030532 如所述之多處理器記憶體更新及運作方法，其中該第一記憶 單元及該第二記憶單元係為快閃記憶體(Flash ROM)或EEPR0M，可 讀寫非揮發性記憶體。 如所述之多處理器記憶體更新及運作方法，其中該主處理器 與該第一記憶單元之間，以及該從處理器與該第二記憶單元之間 係透過 I2C (Inter-Integrated Circuit)匯流排連接。 φ 如所述之多處理器記憶體更新及運作方法，其係應用於多電 腦切換器（Keyboard Video Mouse，KVM)。 本案更提出一種多處理器記憶體更新及運作方法，包含一主 處理器及-從處理H ’其中該主處理H係連接_第_記憶單元及 該從處理器，該從處理H係連接—主機及—第二記憶單元，並包 含下列步驟： 利用该主機偵測與該主處理器及該從處理器之硬體連接及設 定之正轉性； 檢查該主機上之一最新版程式之正確性； 利用該主機傳輸該最新版程式至該從處理^，並藉由該從處 理器將該最新版程式更新至該第一記憶單元中； 檢查該主機上之一主處理器程式之正確性； 利用該主機傳輸該主處理H程式至社處理器，並藉由該主 處理器將該主處理器程式更新至該第一記憶單元中； 完成更新作業。 8 201030532 【實施方式】 第一圖為本案較佳實施例之多處理器記憶體更新及運作方法 之系統架構圖’其中包含了 VGA溝通控制13、USB鍵盤14、USB滑 鼠15、主處理器16、主啟動載入器π、記憶單元18、丨弋傳輸介 面19、SPI傳輸介面11〇、從處理器1U、從啟動載入器112、代 傳輸介面113、§己憶單元114、主機115、SRAM記憶體116及最新 版程式12卜在主處理器16端可連接USB鍵盤14、USB滑鼠15 ❿以及透過VGA溝通控制13連接螢幕等週邊設備，而從處理器I。 端正常運作下連接了至少一部主機115,更新運作時則可連接具有 最新版程式121的主機。記憶單元18透過傳統匯流排(π〗）傳輸 介面19連接至主處理器16，並且在主處理器16中具有主啟動載 入器17 ’而記憶單元18在小量產階段亦可以採外掛方式(虛線部 份）。而另一方面，記憶單元114透過ιΐ (Inter_Integrated Circuit)匯流排傳輸介面113連接至從處理器m，並且在從處理 ❿器ιη中具有從啟動載入器112。主處理器π與從處理器in之 間是透過 SPI 介面(Serial Peripheral interface)11〇 進行通訊 溝通。其中，主處理器16及從處理器hi二者皆為8〇51單晶片 處理器’記憶單元18及114為可讀寫之非揮發性記憶體，如快閃 記憶體(Flash ROM) ’或是同時具備快閃記憶體與唯讀記憶體，再 分別經由主處理器16及從處理器hi切換存取。 第二圖為本錄佳實侧之域理H記倾麟及運作流程 圖，其中包含了下列步驟： 201030532 步驟21 ·主處理ϋ啟動載人ϋ ; 步称22，檢查更新按钮被按超過三秒鐘； 步驟221:等待從處理n送來的最新版程式； 步驟222:查檢更新完成； 步驟23 :檢查快閃記憶體(記憶單元18)内容〇k ; 步驟231 :系統中止； 鲁 步驟24 .透過SPI下載程式到從處理器的SRAM記憶體116 ; 以及 步驟25 :開始執行應用程式。 、本案所提出的多處理器記憶體更新及運作方法，在從處理器 欲執行程式日f ’會先於步驟21由主處理器啟動載人器，準備進行 弋下載或上傳的動作，接著步驟Μ檢查更新按紐被按超過三秒 鐘如果疋則進入步驟22卜如果否則進入步驟23。在步驟221 _ +主處理器16會與從處理器ηι連線，並等待從處理器⑴送 來的最新_式’ _把最新絲式更賴記鮮元18，接著進 入步驟222。在步驟222 ’會檢查最新版程式是否更新完成，如果 疋則回到步驟22，如果否則回到步驟221繼續更新。 在步驟23中’會檢查快閃記憶體（即記憶單元18)裡的内容 (包含最新版程式）是否無誤，例如透過checksum等機制進行驗 證，如果是則進入步驟24，如果否則進入步驟231。當檢查閃圮 憶體（即記憶單元18)裡的内容產生錯誤時，在步驟231則強制 201030532 系統中止。當檢查閃記憶體（即記憶單元18)裡的内容沒問題時， 步驟24會透過SPI110下载程式到從處理器111的麵記憶體 116’接著步驟25則主處理器16及從處理器⑴開始執行應用程 式（例如KVM的應用程式）。 第二圖為本紐佳實施例之從處理器記碰更新及運作流程 圖，其中包含了下列步驟： 參 步驟31 :從處理器執行從啟動载入器⑸ave Boot Loader); 步驟32 :檢查是否有來自主處理器奶傳輸介面的命令； ッ驟33 .檢查為—般模式（此酿1船此）或更新模式 (Upgrade mode)； 步驟331 :檢查是否有外部記憶單元； 步驟332 :透過SPI從主處理器下載程式到飄； 步驟333:從外部記憶單元114載入程式到疆記憶體116; Φ 步驟334 :執行所載之程式； v驟34 .從USB琿上傳最新版程式，並透過spl傳送到主處 理器； 步驟35 :檢查是否上傳完成。 本案所翻❹處理更新及運作綠，在進行程式 版本更新時’必顯最新版程式121的主機(如第一圖）用腳線 與從處理ϋ端的一個USB埠連接，接著在步驟Μ從處理器啟動載 入器，準備進行上傳最新版程式的動作。 201030532 接著步驟32檢查是否有來自主處理器的SPI命令要求進行更 新模式aiPgrade她)或者進行—賴式。更贿㈣指整個系 統必須全面更新，更新的部份包含主處理器端的補㈣瞭e) 及從處理H端的姆’更新的方法則透過_部具有最新版程式的 主機’透過腿埠將最新版程式上傳到主處理器及從處理器之記 憶單元。而-般模式係«統正常運作的時候，從處理器的漏 ❹201030532 Read-only memory. The conventional technology has the following disadvantages: 1. The conventional USB multi-computer switching system must be stored in the read-only memory of the slave processor, which will cause hardware cost. The burden; 2. The conventional dragon multi-computer switching system must be updated with the main processor and each one from the processing H (four) track-only (four), the financial version update process is quite expensive 3. The conventional USB multi-computer cut _ system, and no - The method of collective update of the finished version of the program will cause problems in the control of the version; 4. The USB multi-computer switching secret used by us is mainly to update the program of each job registration mode, and the cost of the problem is increased. 5·Using the USB multi-computer switching system, once the system has a problem, it is necessary to detect the correctness of each program of the read-only memory, and increase the difficulty of troubleshooting; 6. The USB multi-computer switching secret, the program All must be stored in the read-only memory of each ship processor. If it is stolen, all technical data will be stolen and lack confidentiality. 7. The conventional USB multi-computer switching system, even the program The data is stored after encryption. When the system is in operation, it needs to be decrypted and executed. At present, the tool is easy to disassemble the process at the same time, so the confidentiality problem still exists. 6 201030532 / This, how to improve the shortcomings of (4) above, avoid storing all the program data to the read-only clock towel of each slave processor, and can update the version in the way of the case. [Draft] The purpose of this case is to improve the 丨-_ and the multi-faceted 峨 更新 update and ❿ operation method, so that the wealth can be downloaded from the line, and can be quickly updated by the external host. Processor and slave processor version; φ^ 〇 for the above purpose 'This case proposes a multi-processor memory update and operation method package 3 S processor and a slave processor, wherein the master processor has a a boot loader, the slave processor is a slave boot loader; the slave device is connected to the slave processor and a first memory unit a first program, the slave processor is coupled to the second memory unit, and includes the following steps: in response to a general mode, the host processor transmits the application of the first memory unit to the static of the slave processor Random access memory (10) AM); and in response to an update mode, the slave processor uploads a latest version of the program to the first memory unit of the host processor. The multiprocessor memory update and operation method as described, wherein the main processor and the slave processing are single-chip processors. 201030532 The multi-processor memory update and operation method, wherein the first memory unit and the second memory unit are flash ROM or EEPROM, and can read and write non-volatile memory. The multi-processor memory update and operation method, wherein the main processor and the first memory unit, and the slave processor and the second memory unit pass through an I2C (Inter-Integrated Circuit) Bus connection. φ As described in the multiprocessor memory update and operation method, it is applied to a Keyboard Video Mouse (KVM). The present invention further proposes a multiprocessor memory update and operation method, comprising a main processor and a slave processing H 'where the main processing H system is connected to the _ memory unit and the slave processor, the slave processing H system connection - a host and a second memory unit, and comprising the steps of: detecting, by the host, the hardware connection and setting of the main processor and the slave processor; checking that the latest version of the program is correct Using the host to transmit the latest version of the program to the slave processing, and updating the latest version of the program to the first memory unit by the slave processor; checking the correctness of one of the host processor programs on the host And transmitting, by the host, the main processing H program to the social processor, and updating the main processor program to the first memory unit by the main processor; completing the update operation. 8 201030532 [Embodiment] The first figure is a system architecture diagram of a multi-processor memory update and operation method according to a preferred embodiment of the present invention, which includes a VGA communication control 13, a USB keyboard 14, a USB mouse 15, and a main processor. 16. Main boot loader π, memory unit 18, UI transport interface 19, SPI transport interface 11A, slave processor 1U, slave boot loader 112, generation transfer interface 113, § memory unit 114, host 115 The SRAM memory 116 and the latest version of the program 12 can be connected to the USB keyboard 14 and the USB mouse 15 on the main processor 16 side, and the peripheral device such as the screen through the VGA communication control 13 is connected to the processor I. At least one host 115 is connected to the normal operation, and the host with the latest version of the program 121 can be connected during the update operation. The memory unit 18 is connected to the main processor 16 through a conventional bus (π) transmission interface 19, and has a main boot loader 17' in the main processor 16, and the memory unit 18 can also be plugged in a small production stage. (dotted line). On the other hand, the memory unit 114 is connected to the slave processor m through an inter-integrated circuit bus interface 113, and has a slave slave loader 112 in the slave processor. The main processor π communicates with the slave processor in the SPI interface (11) through the SPI interface (Internal Peripheral interface). Wherein, the main processor 16 and the slave processor hi are both 8 〇 51 single-chip processors 'memory units 18 and 114 are readable and writable non-volatile memory such as flash ROM ' or The flash memory and the read-only memory are simultaneously provided, and the access is switched between the main processor 16 and the slave processor hi, respectively. The second picture is the flow chart of the H-direction and operation of the real side of the record, which includes the following steps: 201030532 Step 21 · Main processing ϋ start the manned ϋ; Step 22, check the update button is pressed more than three Seconds; Step 221: Waiting for the latest version of the program sent from process n; Step 222: Checking that the update is complete; Step 23: Checking the contents of the flash memory (memory unit 18) ;k; Step 231: System abort; Download the program to the SRAM memory 116 of the slave processor via SPI; and step 25: Start executing the application. The multiprocessor memory update and operation method proposed in the present case, in the slave processor to execute the program day f', the host processor is started by the main processor before step 21, and the downloading or uploading operation is prepared, and then the steps are performed. Μ Check that the update button has been pressed for more than three seconds. If 疋, proceed to step 22 if otherwise proceed to step 23. At step 221 _ + the main processor 16 will be connected to the slave processor ηι, and wait for the latest _-style _ sent from the processor (1) to change the latest silk type 18, and then proceeds to step 222. At step 222', it is checked whether the latest version of the program is updated, if 疋, then return to step 22, and if not, return to step 221 to continue the update. In step 23, it is checked whether the contents of the flash memory (i.e., the memory unit 18) (including the latest version of the program) are correct, for example, by a checksum mechanism, and if so, the process proceeds to step 24, and if not, the process proceeds to step 231. When checking that the contents of the flash memory (ie, memory unit 18) generate an error, in step 231, the 201030532 system is forced to abort. When it is checked that the contents of the flash memory (ie, the memory unit 18) are ok, step 24 downloads the program to the face memory 116' of the slave processor 111 via the SPI 110. Then, the main processor 16 and the slave processor (1) start with step 25. Execute the application (for example, KVM application). The second figure is a flowchart of the slave processor update and operation of the embodiment of the New Zealand, which includes the following steps: Step 31: From the processor, execute the slave loader (5) ave Boot Loader; Step 32: Check whether There is a command from the main processor milk transmission interface; Step 33. Check for the general mode (this is a ship) or the update mode (Step upgrade mode); Step 331: Check if there is an external memory unit; Step 332: Through the SPI Downloading the program from the main processor to the floating; Step 333: Loading the program from the external memory unit 114 to the memory 116; Φ Step 334: Execute the program included; vStep 34. Upload the latest version of the program from the USB port and pass through Spl is transferred to the main processor; Step 35: Check if the upload is complete. In this case, the update and operation green are processed. When the program version is updated, the host of the latest version of the program 121 (such as the first figure) is connected with a USB port from the processing terminal, and then processed in the step. The boot loader is ready to upload the latest version of the program. 201030532 Next, step 32 checks if there is an SPI command from the host processor that requires the update mode aiPgrade to be her) or does it. More bribes (4) means that the entire system must be fully updated, the updated part contains the main processor side of the supplement (4) e) and the method of processing the H end of the 'updated through the _ department with the latest version of the program' through the leg 埠 will be the latest The program is uploaded to the memory unit of the main processor and the slave processor. And the general mode system «when the normal operation, the leakage from the processor
記憶體必職人特定的義程式，才能執行特定㈣能（例如 KVM)，此制程式通常贿在域理器端柯讀寫轉發性記憶 單元m例如Flash或刪0M)内，或者有時因為應用程式太大;; 無法全部赫在域理H端的錄單元18，财能部份或者全部 都存在從處刻·外部記鮮元114(也是·寫鱗發性記憶 體）；因此在執行一般模式的程序時，必須視應用程式所存放的: 置（主處理器侧或從處理器侧），來決定下^|用程式到從處理器 之 SRAM 記憶體（Static Random Access Memory)的路徑。 接著步驟331檢查從處理器是否有外部記憶單元ιΐ4;如果有 則進入步驟333 ;如果沒有則進入步驟332。 進入步驟332’代表應雜式係猶在域驾端的可讀寫非 揮發性記憶單it 18裡’因此必須透過刺傳輸介面，從主處理器 下載應用程式到從處理器的内建SRAM。 口 進入步驟333 ’代表應用程式係預存在從處理器端的可讀寫非 揮發性記憶單元114裡，因此必須透過ft傳輸介面從外部記憶單 12 201030532 元114將應用程式載入到從處理器内建的SRAM記憶體裡。 進入步_ ’代_料_人從___記憶 體=，因此從處理器可以正式執行應用程式。當然:，如果此系統 疋應用在讀’則是執細的應用程式，讓第1的職盤或 USB b鼠及榮幕可以在不同的主機之間切換操作。 另-方面，如果主處理器SPI命令是進行更新模式，則進入 步驟34 ’從瑋，將與其連接主機之最新版程式上傳到主處理 器’或者如果主處理H的記憶單元18不鼓，則部份或者全 到從處理器的記憶單元114。 如果未完成則 進入步驟35，檢錢新版財衫上傳完成 進入驟34，如果完成則回到步驟32。 本案具有下列優點： ❿ 1·本案所提㈣錄處理器之運作，從處判賴執行的程 式亦可存放在主處理H之鋪單元中，並於需要時透過下 載方式執行’可減低從處理器之硬體成本負擔，· 2. 本案所㈣❹處驾記麵更觀運作綠，並不需要 對主處理器及每-個從處理器個別進行更新，可集體快速 的對主處理H及從處·妨程歧本更新； 3. 本案職_錢理H鋪败缺運作方法，以集體方 式進行更新，版本控管十分容易； 13 201030532 4. 本案所提出的多處理器記憶體更新及運作方法，並不一定 需要以燒錄方式更新程式，在生產時進行燒錄即可，毋需 等待燒錄流程，可減少等待時間與燒錄費用，並且具備程 式正確性驗證之機制’不會發生程式錯誤之問題； 5. 本案所提出的多處理器記憶體更新及運作方法，可將程式 皆儲存至主處理器中，當程式發生錯誤時，僅需檢查主處 理器之記憶單元之程式，可快速排除問題； 6. 本案所提出的錢理H纖舰新及運作方法，可將全部 的程式都儲存在主處理騎連接之記憶單元中，若遭遇竊 取時，亦不容易分辨出每—程式區塊是屬於那—個處理器 之程式1 SRAM中的程式拔掉電源㈣失，因而無法被模 擬债測，具備較高之保密性。 7. 以條傳蘭USB線即可在主從二處理H運作時簡單的操 ❹ 作欲修改的程式，節省製作成本與本體之空間利用。 8. 右主處理器（Master pr〇cess〇r)因快閃記憶體或卿職之 "己憶早凡容量不足時，從處理器（SlaveProcessor)亦可輕 易擴充。 练上所述，本案所提之多處理器記憶體更新及運作方法，可 有效避免雜處弱之财程式資㈣儲輕從處理ϋ所連接之 «己隐單7L巾並集體之方式快速更新程式版本，進步新穎且 實用如其I更成叶’例如應用至多從處理器之系統中、改變元 14 201030532 件之間之通訊方式或是制其它_之處理ϋ及記憶單元等，只 要是從處理器能在所連接之記憶單元中不具備所需之程式時，透 t啟動載人器下载域理器上之程式，或是可彻外部主機更新 主處理器及從處理器之記憶單元中之程式者，皆為本案所欲揭露 及保護者。 • 本案所揭露之技術，得由熟習本技術人士據以實施，而其前 參所未有之作法亦具備專利性，爰依法提出專利之申請。惟上述之 實施例尚不足以涵蓋本騎欲倾之專概圍，因此，提出申許 專利範圍如附。 月 鲁 15 201030532 【圖式簡單說明1 第一圖為本案較佳實施例之多處理器記憶體更新及運作方法 之系統架構圖； 第二圖為本案較佳實施例之主處理器記憶體更新及運作流程 圖； ) 第二圖為本案較佳實施例之從處理器記憶體更新及運作流程 圖0 【主要元件符號說明】 VGA溝通控制· . · · • · .......13 USB鍵盤..... ............Π USB滑鼠..... ............15 主處理器..... ............16 主啟動載入器·.. ............17 記憶單元..... ............18 i2c傳輸介面· · · · ............19 USB傳輸介面♦ · · ............110 從處理器..... •...........Hi 從啟動載入器· · · ............Π2 i2c傳輸介面· · · · ............113 記憶單元..... ............114 16 201030532 主機...................115 SRAM記憶體................116The memory must be specific to the program, in order to perform a specific (four) can (such as KVM), this program usually bribes in the domain processor read and write forwarding memory unit m such as Flash or delete 0M), or sometimes because of the application The program is too large;; can not all of the recording unit 18 on the H-side of the domain, the financial part or all of the existence of the external record 114 (also written scaly memory); therefore in the implementation of the general mode The program must be placed in the application (the main processor side or the slave side) to determine the path from the program to the SRAM memory (Static Random Access Memory) of the slave processor. Next, step 331 checks if the slave processor has an external memory unit ι4; if yes, it proceeds to step 333; if not, it proceeds to step 332. Proceeding to step 332' represents the readable and writable non-volatile memory list 18 of the domain driver. Therefore, the application must be downloaded from the host processor to the built-in SRAM of the slave processor through the puncturing interface. The port proceeds to step 333' to represent that the application system is pre-stored in the readable and writable non-volatile memory unit 114 from the processor side, so the application must be loaded into the slave processor from the external memory unit 12 201030532 element 114 through the ft transfer interface. Built in SRAM memory. Go to step _ ‘generation_ material_ people from ___memory=, so the slave can formally execute the application. Of course: if the system is “reading”, it is a fine-grained application, so that the first job or USB b mouse and the screen can be switched between different hosts. On the other hand, if the main processor SPI command is in the update mode, proceed to step 34 'From 玮, upload the latest version of the program connected to the host to the host processor' or if the memory unit 18 of the main processing H does not drum, then Part or all of the memory unit 114 of the slave processor. If not, proceed to step 35, check that the new version of the shirt is uploaded, proceed to step 34, and if it is completed, return to step 32. This case has the following advantages: ❿ 1. The operation of the processor (4) mentioned in this case can be stored in the main processing H shop and executed by downloading. The hardware cost burden of the device, 2. In this case (4), the driving record is more green, and does not need to update the main processor and each slave processor individually, and can collectively and quickly handle the H and the slave. The responsibilities of the stipulations are updated; 3. The _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ It is not necessary to update the program by burning, and it can be burned at the time of production. It does not need to wait for the burning process, which can reduce the waiting time and programming cost, and has the mechanism of program correctness verification. The problem; 5. The multi-processor memory update and operation method proposed in this case can store the program to the main processor. When the program has an error, only the main processor needs to be checked. Recalling the unit's program, it can quickly eliminate the problem; 6. The new method and operation method of the Qianli H-ship ship proposed in this case can store all the programs in the memory unit of the main processing ride connection, and if it is stolen, it will not It is easy to tell that each program block belongs to the program of the processor. The program in the SRAM is unplugged (4), so it cannot be simulated and has high confidentiality. 7. It is easy to operate the program to be modified when the master-slave two processing H operates, and save the production cost and the space utilization of the ontology. 8. The right main processor (Master pr〇cess〇r) can be easily expanded from the processor (SlaveProcessor) due to the flash memory or the secret of the memory. As mentioned above, the multi-processor memory update and operation method mentioned in this case can effectively avoid the miscellaneous wealthy program. (4) The storage system quickly updates the program from the “hidden single 7L towel” connected by the processing unit. Version, new and practical, such as its I become more leafy', for example, in a system that uses at most a processor, change the communication between the elements of the 2010 and 201030532, or make other processing and memory units, as long as it is a slave processor. When the connected memory unit does not have the required program, the program can be downloaded from the carrier to download the program on the local processor, or the external host can update the program in the memory unit of the main processor and the slave processor. All of them are intended to be disclosed and protected by the case. • The technology disclosed in this case can be implemented by people who are familiar with the technology, and the practices of the former participants are also patented, and the application for patents is filed according to law. However, the above embodiments are not sufficient to cover the specific scope of the ride. Therefore, the scope of the patent application is attached. Yue Lu 15 201030532 [Simplified Description of the Drawings 1 The first diagram is a system architecture diagram of a multiprocessor memory update and operation method of the preferred embodiment of the present invention; the second diagram is a main processor memory update of the preferred embodiment of the present invention. And the operation flow chart;) The second figure is the flow chart of the slave processor memory update and operation according to the preferred embodiment of the present invention. [Main component symbol description] VGA communication control · . · · • · . USB keyboard.................ΠUSB mouse.................15 main processor..... ...........16 Main boot loader·..............17 Memory unit................. ..18 i2c transmission interface · · · · ............19 USB transmission interface ♦ · · ............110 slave processor ..... •...........Hi from the boot loader · · ·............Π2 i2c transfer interface · · · · ......... ...113 Memory Unit.................114 16 201030532 Host...................115 SRAM Memory ................116
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