TW201034122A - Integrated circuit micro-module - Google Patents

Abstract

Various apparatuses and methods for forming integrated circuit package are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias.

Description

201034122 > 6. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to the packaging of an integrated circuit (ic). More specifically, the present invention relates to an integrated circuit micromodule. [Prior Art] There are several conventional methods for packaging integrated circuit (Ic) crystal grains. Some packaging technologies create electronic modules for incorporating multiple electronic devices (for example, integrated circuits; passive devices such as inductors, capacitors, resistors, or ferromagnetic materials; etc.) into a single package. Among them. A package incorporating more than one integrated circuit die is often referred to as a multi-wafer module. Some multi-chip modules include a substrate or interposer to support various devices; while other multi-chip modules utilize wire frames, dies, or other structures to support a variety of other packaged devices. Several multi-wafer module packaging techniques have been identified, for example, to integrate a plurality of interconnect layers into a composite I using a plurality of stacked films or multiple stacked wafer carriers. Although there is nothing wrong with the existing method of packaging electronic modules, it is still necessary to continue to develop improved packaging technology to provide a cost-effective way to fill a wide variety of different packaging applications. demand. SUMMARY OF THE INVENTION The present invention describes various devices and methods for forming integrated circuit packages, and the present invention is directed to a wafer level method for packaging microsystems. It will provide a substrate with multiple metal channels. A plurality of microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple planarized, photoimageable epoxy layers, one or more 201034122. Each interconnect layer is embedded in a correlation

There is at least one micro system. Interconnect layers and integrated circuits. Connected inside the epoxy layer. The Lay epoxy layer inside. The 糸 基板 基板 w 基板 基板 基板 基板 基板 基板 基板 w w w w w w w w

A hole is formed by electroplating a conductive material into the holes to form a substrate having a plurality of channels. The holes and channels may or may not pass completely through the substrate. Various embodiments of the invention include the use of a wide variety of processes (e.g., back grinding) to remove a portion of the substrate to expose a portion of the channels. One embodiment of the invention includes etching a bottom surface of the substrate to form a cavity. A sensing element (which may include a wide variety of sensors, such as photovoltaic cells, biosensors, gas sensors, electromagnetic sensors, etc.) may be placed or formed Inside the cavity. A plurality of portions in the substrate are removed to form a plurality of holes in the substrate. Conductor materials are electroplated into the holes to form a plurality of metal channels. At least some of the metal channels are electrically coupled to the sensing element. Another embodiment of the invention includes forming a plurality of microsystems and a plurality of conductor pads over a sacrificial substrate. A conductive material is applied to the top surface of the substrate 5 201034122 to form a plurality of substrate solder contact pads. A plurality of microsystems are formed on the top end surface of the substrate. Each of the microsystems includes a plurality of adjacent stacked planarized, photoimageable epoxy layers, one or more interconnect layers, and one or more integrated circuits. At least one of the interconnect layers is formed to electrically couple one or more of the substrate solder contact pads. A mold material is applied to the top surface of the wafer to form a mold wafer structure to encapsulate each of the microsystems. The mold wafer structure is singulated to form individual integrated circuit packages. Each integrated circuit package includes at least one of the plurality of microsystems. At least some of the substrate is removed to expose the substrate solder contact pads. Various embodiments of the invention pertain to apparatus made by performing some or all of the foregoing methods. For example, one embodiment 2 includes a substrate having a plurality of metal vias and/or conductive solder contact pads on its top end surface. A plurality of microsystems are formed on the top end surface of the substrate. The top end surface of the substrate and the microsystems are covered by a mold material. [Embodiment] Among the aspects, the present invention is generally related to an integrated circuit (IC) package and more specifically, the present invention relates to an IC micromodule technology. This view includes a micromodule composed of a plurality of layers made of a dielectric material, which is preferably photoimageable and easily planarized. The micromodule may contain a wide variety of devices including - or multiple integrated circuits, interconnect layers, heat sinks, conductor vias, passive devices, MEMS devices, sensors, heat pipes, etc. . The various devices can be arranged in a variety of different ways and stacked within the micromodule. The layers and devices of the micromodule can be deposited and processed using various (four) known wafer level processing techniques, such as spin coating techniques, 201034122 spray techniques, lithography, and/or electroplating techniques. Another aspect of the present invention relates to wafer level manufacturing techniques and structures that integrate multiple active and/or passive devices into a single-, low-cost, performance package.

Shown in Figure 1 is a package in accordance with an embodiment of the present invention. In the embodiment shown in the figure, a multi-layer package 10A includes: a substrate i 〇 2, a heat sink 104, a plurality of stacked dielectric layers 106, an integrated circuit ι4, and a passive device (in the figure Not shown), interconnect layer 122, via 125, and external contact pads 120. Heat sinks 1〇4 are formed over the substrate 〇2, and the dielectric layers 〇6 are stacked on top of the heat sink. A plurality of interconnect layers are interposed between adjacent dielectric layers 106 as necessary. The integrated circuits are buried in a stacked dielectric layer 06 and may be electrically connected to other devices by suitable lines among the interconnect layers 122 and 125, for example, Its 匕ic, passive device, external contact pads 12〇, ... and so on. In the embodiment shown in the figure, one of the integrated circuits (n4a) is effectively placed over the heat sink 1〇4 to provide a good heat dissipation effect. The dielectric layers 106 can be made of any suitable dielectric material. In various preferred embodiments, the dielectric layers 1〇6 are made of a material that is easily planarized and/or photoimageable. In a particularly preferred embodiment, the layers are made of photoimageable, planarized su_8, although other suitable materials may be used. For some design towels, for layer 1〇6, the I dielectric is highly viscous when it is just coated, and then partially or fully cured during the photolithography process. The layers 1 〇 6 can be applied using a variety of suitable techniques, including spin coating techniques and spray coating techniques. The thickness of each of these 7 201034122 dielectric layers can vary widely depending on the needs of the particular application' and the different layers need not be of the same thickness (although they may also have the same thickness). The integrated circuitry 114 within the package 100 can be arranged in a wide variety of ways and can be placed at almost any location within the package. For example, different integrated circuits 114 can be disposed in substrate 1 〇 2, in different photoimageable layers, and/or in the same layer. In various embodiments, the integrated circuits Π4 can be stacked, placed side by side, placed closely adjacent one another, and/or separated by a substantial distance based on the overall size of the package 100. The integrated circuits disposed in the different layers may be disposed directly or partially above each other, or they may be separated so that they do not overlap each other. The integrated circuit U4 may also have a variety of different form factors, architectures, and configurations. For example, they may be in the form of relatively bare grains (for example, unpackaged grains, flip-chips, etc.), partially and/or fully encapsulated in the form of grains (for example 'BQa, LGA, QFN, etc.). The electrical interconnects in the package HM) can also be arranged in a variety of different ways. The embodiment shown in i comprises two interconnect (line) layers m. There may be more or fewer interconnect layers in different implementations. Each interconnect layer typically has at least one (but, often there are many) lines & 123, which are used to help transmit electrical signals between different devices in the package. The interconnect layers 122 are typically formed on top of an associated layer of the planarized layers 1〇6. The circuit layer is then buried or covered by another dielectric layer. Thus, the interconnect layers typically extend in a plane parallel to the dielectric layers and embedded in the dielectric layers 201034122. Because the interconnect layers (and other possible devices of the package) are formed on top of a dielectric layer, it may be desirable for the dielectric layers 106 to have a very flat and rigid surface thereon. Other devices (eg, 'line, passive device, ..., etc.) may be formed or discrete devices (eg, 1C) may be placed. SU-8 is particularly suitable for this application because it can be easily automatically planarized when applied by conventional spin and spin coating techniques and will be very stiff after being cured. More specifically, su_8 rotated by © can be used to form a hard, flat surface without any additional planarization prior to forming a high quality interconnect layer thereon using conventional sputtering/electroplating techniques. Role (for example, chemical mechanical polishing). A dielectric material that can be coated in this manner to form a very flat surface is referred to herein as a planarizing dielectric. Conductive vias 125 will be provided to electrically connect devices resident at different layers of the package (for example, 1 (: / line / contact / passive device ... etc.). These channels will be arranged to extend at 5 Passing through an associated dielectric layer 106. For example, the channels 125 can be used to couple lines from two different interconnect layers together to transfer a die or another device to An interconnect layer that couples a contact to a line, die, or other device.. etc. As explained in more detail below, multiple metallization channels can be formed simultaneously, so by filling previously formed in a correlation A channel opening in the dielectric layer 1 〇 6 can deposit an associated interconnect layer 122. The package 1 〇〇 may include many other types of devices than those shown in the figure. In the embodiment, only a few integrated circuits and interconnect layers are shown. However, package 100 may also contain almost any number of active 201034122 and/or passive devices. Examples of such active and/or passive devices include resistors. , capacitor, magnetic core, MEMS device , sensors, batteries (for example 'encapsulated batteries or other batteries), integrated thin film battery structures, inductors, etc. These devices can be placed and/or stacked in a package In various locations, the devices may be in the form of discrete devices fabricated in advance or may be formed in the field. One of the advantages of the lithography-based process for creating packages is that they can be layered. These and other devices are formed in the field during the package. That is, after being fabricated in advance, the discrete devices can be placed almost anywhere in the package. The device can also utilize any suitable technique (eg, The known 贱 key and/or electroplating) are directly fabricated on any photoimageable layer 1 〇 6. Due to the relationship of the process characteristics, better matching effects, accuracy and control can be achieved' and can be used in various A low stress package is achieved on the die and/or substrate dimensions (which include medium and large dies and/or substrates). The substrate 102 may be of any suitable material. Made of: bismuth, glass, steel, quartz, G10-FR4, any other FR4 family epoxy, etc. depending on the needs of the particular application 'The substrate may be electrically conductive, electrically insulating and/or Or light transmissive. In some embodiments, the substrate is only removed as a carrier during fabrication and thus will be removed prior to completion of the package. In other embodiments, the substrate will remain integral to the package. The molded component. If desired, the substrate 102 can be thinned after assembly by back grinding techniques or other suitable techniques. Again, in other embodiments, the substrate may be omitted altogether. In some embodiments 'The substrate 102 may be integrated—or multiple sensors (not shown). This approach achieves the goal of integrating the sensor device 201034122 without having to package and not be exposed to the environment. Reliability issues associated with the necessary conditions in the sensor. The sensor can be placed on either side of the substrate 102 and can be embedded or exposed to the environment via an etched window or microchannel. Examples of suitable sensors include, but are not limited to, biosensors, gas sensors, chemical sensors, electromagnetic sensors, acceleration sensors, vibration sensors, temperature sensors , humidity sensor, ..., etc. One such way is to integrate a sensing element to the back face of the substrate 102. The sensing element can be built into the interior of the deep cavity in the substrate 102 that has been etched away from the back side of the substrate 102. For example, the sensing element can be a capacitor made up of a plurality of electrocluster Cii fingers. The electric device can be connected to the contact pads on the front side of the substrate 1〇 via the microchannel. A package 100 can be formed over the contact pads such that the capacitor is electrically coupled to at least a portion of the electrical devices and interconnect layers within the package 100. The sensing elements inside the cavity created on the back side of the wafer may be filled with Q-filled gas sensitive material and may be automatically exposed to the environment, while the active circuitry on the front side of substrate 102 may utilize conventional encapsulation techniques. (For example: as discussed below in conjunction with Figure 5E) to protect. The package 100 also includes a system for dissipating internally generated heat, which may include a heat pipe and a heat sink, such as a heat sink 1〇4. This system may play an important role in the performance of package 100, as packages with high power density and multiple buried devices may require good heat dissipation for proper operation. The heat transfer tubes and fins are typically formed substantially simultaneously with the interconnect layers 122a through 122b and using the same techniques. The heat transfer tubes are capable of passing through and/or bypassing through - or a plurality of interconnect layers and/or illuminating 11 201034122 image layers. Any single, continuous heat pipe, line, and/or channel can be split into a plurality of other lines and/or channels at almost any point of the location and can extend more than one direction within the package, such as · Horizontal and / or vertical. The heat transfer tubes are in fact capable of thermally coupling any of the devices in the package 1 to one or more heat sink pads and/or heat sinks on the outer portion of the package 100. The heat sink 104 may have a variety of different architectures. In the embodiment shown in the figures, the heat sink 1 4 will constitute a layer that covers a range that substantially matches the coverage of the photoimageable layer of the package 100. Alternatively, package 1 may contain - or multiple heat sinks' whose dimensions at least partially match the dimensions of the upper or lower active device (e.g., integrated circuit). In the embodiment of the figure y, the heat sink may have the form of a layer or sheet 104 formed over the substrate and which will form a dielectric layer 1〇6. If desired, the integrated body $114 can be placed directly above the heat sink layer as shown by integrated circuit 114(a). Alternatively, a thermal path (not shown) may be used to improve the thermal path between the buried integrated circuit and the heat sink, as shown by integrated circuit 114(b). In some embodiments, the heat sink or heat sink layer may be exposed on the top surface or bottom π surface of the package. In other embodiments, a substrate or other layer may cover the heat sink or fin layer such that the heat sink acts as a heat spreader. The fins 1〇4 may be made of a variety of suitable conductor materials (e.g., copper) and may be constructed in the same manner as the interconnect layers. Various embodiments of the package 100 may also be incorporated into the m-hearted saying that the package (10) may be combined with a high voltage 12 201034122

Voltage 'HV' isolation and embedded inductive galvanic capability ^ may be characterized by a wireless interface, for example, RF antenna 10, EM power collection (Em power scavenging), EMI sensitive Shielding of sexual applications, ...etc. In various embodiments, the package 1 may include a power management subsystem, for example, a supercharger, an integrated photovoltaic switch, etc. The package 100 can be formed over a wafer and encapsulated, for example, as shown in Figure 5]. The sensing surface and material can be integrated into the package and other processing steps of the wafer as discussed above and in conjunction with the drawings from 5H, 6-8, and 7 to 7〇. Next, a day and day circle level method 200 for forming an integrated circuit package (10) according to an embodiment of the present invention will be described with reference to FIG. The steps of the method are illustrated in Figures 3-8L. The steps of method 2〇〇 may be performed repeatedly and/or in a different order than shown in the figures. It should be noted that the process illustrated in method 200 can be used to simultaneously construct many other structures than those shown in the figures. Initially, a non-essential conductor layer 104 of FIG. 3A is formed at the top of the substrate 102 by any of a variety of <RTI ID=0.0>> For example, it is often applicable to sputter a seed crystal. Of course, it is also possible to use the electric ore deposit of the —° 非 是 是 是 是 是 是 是 是 。 。 。 。 。 。 。 。 。 。 。 ..., can be made of various materials, such as: copper or its metal or metal layer stack of wafers and can be made up of a variety of people...

Gl〇 FR4, indium, tantalum & 〇 and other materials, such as: 矽, G10-FR4, steel, glass, plastic, and so on. / In Figure 3, a flat 13 201034122, photoimageable epoxy 106 is deposited over the heat sink ^" (step 2 (4) of Figure 2. This can be done using a variety of techniques. For example: spin coating, spray coating or sheet lamination. In the embodiment shown in the figures, the epoxy layer 106a is SU-8, and other suitable dielectric materials may also be used. SU-8 is ideal for applications that utilize conventional spin coating technology. SU-8 has a variety of superior properties. It is a highly viscous, photoimageable, chemical (4) polymer 'for example' It is cured when exposed to UV radiation during the photolithography process. Su_8 provides mechanical strength greater than some other known photoresists, resists excessive grinding, and is mechanically stable and thermally stable at temperatures up to at least 300 C. Relative to certain other photoimageable materials (eg BCB), it can be easily and uniformly planarized by spin coating, which makes it easy to fabricate interconnects or passive II on it. The base of the piece and can be used in it The placement of integrated circuits or other passive devices is readily used for dielectric layers ranging from 1 micron to 250 microns, and thinner or thicker layers can be fabricated. In a particular embodiment A plurality of openings having a large aspect ratio (for example, about 5:1 or more) may be formed in the SU 8, which contributes to forming a device having a large aspect ratio, for example, a conductive channel Or other structures. For example, an aspect ratio of 7:1 can be easily achieved. Compared to many other materials, the SU-8 layer can achieve better control, accuracy, and matching effects, which can cause more High density and improved performance. Other suitable dielectric materials having one or more of the above features may be used in place of SU-8. In step 206 of Figure 2, conventional photolithography techniques are utilized to pattern The epoxy resin layer 106a. In one embodiment, a mask 201034122 is used to selectively expose portions of the epoxy layer 10a, which are baked, and then baked after exposure. Homework. These jobs can make 兮ia #u shout this The exposed portion of the epoxy resin layer 106a produces a cross-linking, epoxy resin. During the photolithography process, the portion is cured (for example, partially modified or hardened, the exposed portion of the layer 106a may be cured). In other words, the B-order) may be relative to the unexposed portion to help remove the unexposed portion of the epoxy resin later.

In step 2, 8 of Figs. 2 and 3C, the portion of the epoxy layer that is not exposed is removed to form - or a plurality of openings 306 in the epoxy layer ride. This removal process can be implemented in a variety of ways. For example, the epoxy layer can be developed in a developer solution to cause dissolution of the unexposed portion of the layer. Hard baking may be performed after the development work. In step 210 of Figs. 2 and 3D, the '-integrated circuit H4a is placed in the opening 306 and placed over the heat sink 1〇4. The integrated circuit 114a can be configured in a wide variety of ways. For example, the integrated circuit 114a may be a bare die or flip chip, or it may have a BGA, LGA, and/or other suitable external pin configuration. In the embodiment shown in the figures, the thickness of the integrated circuit 114a may be greater than the thickness of the epoxy layer 106 in which it is initially embedded; however, in other embodiments, the die may The epoxy layer that is buried therein at the beginning has substantially the same or a thin thickness. The active surface of the integrated circuit can be facing up or down. In a particular embodiment, the integrated circuit n4a can be attached with an adhesive and thermally coupled to the heat sink i 〇4. After the integrated circuit 114a has been disposed in the opening 3〇6 and is attached to the “, sheet, the first epoxy layer 106b is applied to the product 15 201034122 circuit 114a and 4 epoxy resin. Above the layer iQ6a (step 2〇4 of Fig. 2), as shown in Fig. 3E. The same as the first epoxy layer (10), it can be prepared by any method (for example: & coating) To deposit the second ring s ^ 曰 layer 1G6b. In the embodiment shown in the drawing, the epoxy resin layer 6b is located directly above the integrated circuit 114a and the epoxy layer 1〇6a, and is close to the integrated body: the road 114a and the epoxy layer 1〇6a. Adjacent and/or direct contact with the integrated body U4a and the epoxy layer 1〇6a; however, other arrangements may be employed. The epoxy layer may completely or partially cover the active surface of the integrated circuit 114a. ❹ After the epoxy layer 1 () 6b has been applied, it can be patterned and developed using any Q and technology (step 2%), and the techniques are used for patterning. The first epoxy resin layer 16a is the same technique. In the embodiment shown in the figures, a plurality of channel openings M2 are formed over the integrated circuit U4a to expose a solder contact 塾 (not shown) on the active surface of the integrated circuit 114 & The resulting structure is as shown in Figure 3F. After any suitable channel opening σ 312 has been formed, the seed layer 319 is deposited over the opening 312 and the epoxy layer 1 as shown in Figure 3G. The seed layer 319 may be made of any suitable material (which includes a plurality of sub-layers sequentially coated (for example, Ding, Cu, and a stack of Φ) and may utilize various types of Such a process is by deposition, by sputtering a thin metal layer on the exposed surfaces. A feature of the foregoing is that the sputtered seed layer will have a tendency to coat all exposed gauges = (which include the sidewalls and bottom of the passage opening 312). The deposition of the seed layer = may also be limited to a portion of the exposed surface. 16 201034122 - In FIG. 311, a photoresist 315 is applied over the seed layer 319. The photoresist 315 may be either positive or negative, which will cover the seed layer 319 and fill the opening 312. In Fig. 31, the photoresist is patterned and developed to form an open region 317 which exposes the BB seed layer 319. These open areas will be patterned to reflect the desired layout of the interconnect layers, including any desired conductor traces and heat pipes, as well as any desired channels in the underlying epoxy layer 1 〇 6 (b). After the desired open regions have been formed, the exposed portions of the seed layer are then electroplated to form the desired © interconnect layer structure. In some embodiments, a portion of the seed layer (e.g., Ti) is etched prior to performing the clock. During electroplating, a voltage is applied to the seed layer 3 1 9 ' to help electroconduct a conductor material (e.g., copper) into the open regions 317. The photoresist 315 and seed layer 319 in the field will then be stripped after the interconnect layer has been formed. Therefore, the interconnection layer 122a is formed above the epoxy layer 1 〇 6b as shown in Fig. 3J (step 212). The foregoing described electrominening operations for filling the openings of the s-channel with metals thereby forming metal channels 313 in the spaces previously defined by the channel openings. The metal vias 313 can be arranged to electrically couple the I/O pads of the integrated circuit 1丨4a and the corresponding lines 3 16 of the interconnect layer 122a. Since the seed layer 3 19 has been deposited on both the sidewalls and the bottom of the opening 3 12 , the conductor material accumulates substantially simultaneously on the sidewalls and the bottoms, thereby causing the filling of the openings 3 12 . The speed will be faster than the seed layer being applied only to the bottom of the opening 3丨2. Although not shown in the epoxy layers l〇6a and l6b; however, other channels may also be formed through one or more epoxy layers, 17 201034122 for devices (for example , lines, passive devices, external contact pads, ICs, ..., etc.) are coupled together. Moreover, in other arrangement orders, a plurality of conductor paths may be formed between a surface of the bottom (or other) surface of the integrated circuit and the heat sink layer 104 to achieve current carrying even if metallization is not utilized. The load function still provides a good thermal path to the heat sink. In general, interconnect layer 122a will have any number of associated traces and metal vias and will wrap the conductors in any manner suitable for the associated packaged devices used to electrically couple them.

It should be noted that although this article has described a special sputtering/electrodeposition process which is very suitable for forming a line above an associated epoxy layer 1〇6 and forming a channel therein at substantially the same time; however, it should It will be appreciated that a variety of other conventional or newly developed processes can be used to separate or form the channels and lines together. After the interconnect layer 122a has been formed, it is generally suitable to form an additional epoxy layer, an interconnect layer, and a suitable device for placing or embedding a suitable device therein or thereon. Steps 204, 206, 208, 210, and/or 212 are repeated in any order to form a particular package, for example: in the embodiment shown in the figures, overlying layer 106b

The package shown in Figure 3K. For example, the additional epoxy layers 1〇6〇 to l〇6f will be (which will actually repeat step 204 if necessary). The integrated circuits 114b and 114c are buried in the epoxy layers 1〇6d and 16e (steps 2〇6, 2〇8, and 21〇). The other interconnect layer 12 is broken into the top epoxy layer 1〇6f (steps 2〇6, 2〇8, and 2 12), and so on. It should be understood that the integrated circuits and interconnect layers in the package can be arranged in a variety of ways depending on the needs of the particular application. For example, in the embodiment shown in the figure, the active faces of some integrated circuits are stacked directly above each other (for example, integrated power " & 114b). Some integrated circuits Will be embedded in the same epoxy layer or multiple layers of the same epoxy resin (for example, 'integrated circuit 丨i servant and H4c). The integrated circuit may be embedded in and embedded in it The epoxy layer of the interconnect layer is different in the epoxy layer (for example, the interconnect layer 3i8a and the integrated circuits U4a and (10)). ("Different" epoxy layer (4) Each layer and other layers in the multilayer are sequentially deposited in a single, adhesive coating, such as the epoxy layer 1〇6a to 1〇^.) The integrated circuits may be stacked. Above each other and/or close to each other. The integrated circuit can also be electrically coupled through electrical interconnect layers, vias and/or lines that extend substantially to the nearest or outer contour of any single integrated circuit (for example, integrated circuits n4b and 丨14c) . In step 214 of Figures 2 and 3L, optional external contact pads 12A may be added to the top surface of the package. The external contact pads ©120 T are placed over other surfaces and formed in a variety of ways. For example, the top epoxy layer 16f can be patterned and developed using the techniques described above to expose a portion of the electrical interconnect layer 122b. Any suitable metal (eg, copper) can be electrically Mineralized into the holes in the epoxy layer 106f to form the conductor vias and the external contact pads 120. Accordingly, at least some of the external contact pads 12A can be electrically coupled to the electrical interconnect layers 122a-122b and/or the integrated circuits 114& to U4c. The features of package 100 can be modified in a variety of ways. For example, it may contain more or fewer integrated circuits and/or interconnect layers. 201034122 It may also contain additional devices such as sensors, MEMS devices, resistors, capacitors, thin-film cell structures, photovoltaic cells' (10) wireless antennas and/or inductors. In some embodiments, the substrate 1〇2 may be concealed or disposed of. The base S 102 may have any suitable thickness. For example, thicknesses in the range of about 1 GG i 25 Gm are extremely suitable for many applications. The thickness of the package 100 may vary widely. For example, a thickness ranging from about 0.5 to 1 mm is well suited for many applications. The thickness of the electrical interconnect layer and 122b may also vary widely with the needs of a particular application. For example, it is believed that the thickness of about 5 〇 is very suitable for many applications. Figure 4A is a cross-sectional view showing another embodiment of the present invention. Similar to the package 100 of FIG. 1, the package 400 of FIG. 4A includes integrated circuits 4〇1 and 4〇3, an epoxy layer 410, and a plurality of interconnect layers. The package 4 also contains some additional non-essential features not shown in the package 100. For example, the package 400 is characterized in that the integrated circuit 401 is thermally coupled to a heat sink 402. In the embodiment shown in the figures, certain dimensions of the heat sink 4〇2 are substantially the same as those of the thermal handle assembly. In a particular embodiment, the heat sink 402 may be larger or smaller than the device below it. The heat sink 4〇2 may be disposed on the top surface or the bottom surface of the integrated circuit 401 or directly contact the top surface or the bottom surface of the integrated circuit 401, which may be directly adjacent to the seal | 400 #-External watch from ( In the case of the embodiment shown in the figures, it may be connected to the outer surface through one or more hot channels. The heat sink 402 is thermally coupled to a conductor layer, such as layer 1 〇 4 of FIG. The epoxy layer 410 is preferably implemented by SU_8. It is particularly helpful to have a heat sink 4〇2 directly below the integrated circuit 401 because 20 201034122 heat is not completely conducted through the SU-8. The package 400 is also characterized by various passive components such as inductors 4〇6 and 408, resistors 4〇4, and capacitors 4〇6. The passive devices can be located in any epoxy layer or location within the package 400. They can be formed using a variety of appropriate techniques, depending on the needs of the particular application. For example, the inductor winding 4 i 2 and the inductor core 4 and 41 〇b may be formed by depositing a conductor material and a ferromagnetic material respectively over at least one of the epoxy layers. form. The thin film resistor may be coated with any suitable resistive material (for example: tantalum chromium, nickel chromium and/or chromium tantalum carbide) by sputtering f on top of one of the tantalum epoxy layers 4丨〇. ) formed. The capacitor may be formed by sandwiching a thin dielectric layer between metal plates deposited over one or more layers of the moon tree layer. Pre-fabricated resistors, inductors, and capacitors can also be placed over one or more epoxy layers 4 ΐ θ. Conductivity, ferromagnetism, and other materials can be deposited by any convenient method known in the art, such as electroplating or sputtering. The package 400 also includes an optional bga 5 • contact pad 410 located above the front surface 416. The substrate 414 can be made of various materials such as gi〇_fr4, steel, and glass because of the position of the contact pads 41〇. In a particular embodiment where the contact contacts are located on the back surface 418, the substrate 4丨4 may be made of tantalum and characterized by a through passage that is electrically connectable to the touch pads. In another embodiment, the substrate is primarily used as a build platform for forming the package 4 and will eventually be removed. Figure 4A shows another embodiment of the present invention having many of the features of FIG. 4α, 21 201034122 I. This embodiment includes additional devices including: precision adjustable capacitor 430 and resistor 432, micro-relay 434, low-cost configurable precision passive feedback network 436, FR-4 base 438, and photovoltaic cells thorough. The battery yang may be covered by a layer of transparent material (such as a transparent SU-8). In other embodiments, photovoltaic cell 440 can be replaced by a window glass sensor, a wireless phase antenna array, a heat sink, or another suitable device. The package 400 may contain a number of additional structures including an array of power inductors, a functioning antenna, a heat pipe, and a thermal pad for dissipating the interior of the package. Figures 4C and 4D show two additional embodiments with a heat pipe. Figure 4C illustrates a package 479 comprising an integrated circuit that is embedded in a multilayer planarized, photoimageable epoxy resin 48. . The plurality of metal interconnects 484 will consume solder contacts (not shown) on the active surface of the integrated circuit 486. The back side of the integrated circuit 486 is placed over a heat pipe 488 which contains the core of the heat conducting line 4 and the conductive channel yang b. The heat pipe 488 is made of any material that will properly conduct heat. For example, as shown by the dotted line, the heat from the integrated circuit is transmitted through the back side of the integrated circuit, flowing near the 488a and upwards. It leads to the channel 488b' so that the crucible will flow to the outer top surface of the package 479. The examples shown in Figure 可以 can be fabricated using a variety of techniques, such as the techniques discussed in conjunction with Figure 。. Μ Figure 4D shows another embodiment of the present invention. In this embodiment, the integrated circuit n4a has a bottom surface which is thermally connected to the heat transfer tube 47A. Heat pipe 22 201034122 4: Electric (10) a is sent to the external heat transfer portion 472 of the package 100. For integrated circuits and high power density packages, heat dissipation can be a problem. Can (4) inside the package (10) - or more (four): The tube can let the heat generated inside be transmitted to the outer surface of the seal 1〇〇. In FIG. 4C, and in the case of % ^ ^, for example, heat is transmitted away from the integrated body path 114a and flows onto the package 1〇〇07, the bottom surface, and the plurality of side surfaces. Thermal flow location 472. ❹ 多个 Multiple heat sinks may also be placed on the top, bottom, side, and/or almost any exterior surface of the package. In the embodiment shown in the figures, for example, the hot knife plate 102 on the bottom surface of the package 1 is thermally coupled to the heat pipe 47 and dissipates heat to the entire bottom surface area of the package 1〇〇. . In one embodiment, all of the heat pipes in the package 100, which are thermally coupled to a plurality of embedded integrated circuits, are also thermally coupled to the heat spreader plate 102. In a variation of this embodiment, some of the heat pipes are also coupled to heat sinks on the top surface of the package 100. The heat pipe 470 can be formed using a process similar to that used to fabricate the interconnect layer 122. They may couple multiple passive and/or active devices within the package 100 and can extend in almost any direction within the package. In the embodiment shown in the figures, for example, the heat pipe 470 will extend in a direction parallel and perpendicular to certain planes in the plane formed by the photoimageable layers ι6. As shown in FIG. 4C, the heat pipe 470 may include thermally conductive lines 470b and 470d and/or channels 470a and 470c that pass through one or more interconnect layers 122 and/or photoimageable layers 1〇6. The heat pipes 470 are configured to dissipate heat, conduct electrical signals, or both. In 23 201034122, in the embodiment, an interconnect layer for transmitting electrical signals and a « heat pipe which is not suitable for transmitting electrical signals are embedded in the same epoxy layer. Another embodiment of the invention is illustrated in Figure 4B. The package arrangement 450 includes a microsystem 452 formed on the top surface 460 of the substrate 456. The microsystem 452 may include a plurality of dielectric barriers, an interconnect layer, an active layer, and/or a passive device, and may have a package 400 in conjunction with the package 1 and/or FIG. Any of the features of the microsystem (5) and the top surface 460 of the substrate core may be encapsulated in a molding material 464 (which may be made of any material such as: thermoset plastic). Electrically coupled to the bottom of the microsystem 452, the external contact pads (not shown in the figure), and the bottom surface 46 of the substrate 456, the channels 458 are terminated. ^ Non-essential solder balls 462 'The solder balls may be It is made of various conductor materials. For example, solder balls 462 can be placed over a printed circuit board to achieve electrical connections between the microsystem 452 and various external components. _ Figures 5A through 5H show A cross-sectional view of a wafer level process for creating a package of the same arrangement as that of Figure 4D. Figure 5A shows a wafer 5 having a top end surface 502 and a bottom surface 504. Circle 0 - a small part. The virtual vertical line shows The projected cutting line 5〇8: In the embodiment shown in the figure, the 'base 5' may be made of a variety of suitable materials, such as: 矽., in FIG. 5B, 'wafer 500' The top surface 502 is etched away to form the holes 506. This etching process can be performed using a variety of techniques. You can then deposit the metal in the hole. The hole φ , ^ ' is used to open an electrical system. This deposition can be carried out by any method suitable for 24 201034122, for example: electro-mine method ◎ for example, a seed layer (not shown) It may be deposited over the top surface 502 of the wafer 500. The metal layer (e.g., copper) may then be used to plate the seed layer. The plating process produces a metal via 510 on the top surface 502 of the wafer 500. Contact pad 512. ❹ In Fig. 5D, 'microsystem 513 will be formed on top surface 502 of wafer 500 using the same steps as those described in connection with Figs. 2 and 3A through 3L. The embodiment shown in the figure The 'microsystems 513 do not have the top knowledge formed in them The external contact pads on the surface 515 'because the top surface 515 will be overmolded in a later operation. In another embodiment, a plurality of external contact pads will be formed on the top surface 515 for Wafer level functional testing is achieved prior to cladding molding. Microsystems 513 have external contact pads on their bottom surface 517 that align with contact pads 512 on the top surface 502 of wafer 500. Electrical connections between the metal vias 510 and the interconnect layers within the microsystems 513 are facilitated.

In Fig. 5E, a suitable molding material 52 is applied over the microsystems 513 and the top surface 5〇2 of the wafer 500. The molding process can be implemented using a variety of suitable techniques and materials. As a result, a molded wafer structure 522 is formed. In some designs, the molding material 52G will completely cover and encapsulate the microsystem 513 and/or the entire tip surface 502. The additional application of the molding material can provide additional mechanical support to the microsystem 513. This can be quite practical when the microsystem 513 is very large. Figure 5F shows the use of any of a variety of suitable techniques (e.g., back 25 201034122 grinding technique). The molded wafer structure 522 after the bottom surface 5〇4 of the wafer 500 is partially removed. As a result, part of the metal passage 51 will be exposed. In Figure 5G, solder balls 524 are applied to the bare metal channels 51. In Figure 5H, the cast wafer structure 522 is then singulated along the projected cut line 5〇8 to create a plurality of individual package arrangements 526. The singulation process can be carried out using a variety of suitable methods (e.g., cutting or laser cutting). 6A through 6C are cross-sectional views showing a wafer level process for establishing a package in accordance with another embodiment of the present invention. Shown in Fig. 6A is a substrate 6A having a plurality of perforations 602 previously fabricated. Figure 6B shows the deposition of metal in the holes 602 to form a plurality of metal channels 6〇4. The deposition of metal can be carried out using any suitable technique (e.g., electroplating techniques). In some embodiments, the substrate 6() will be fabricated with perforations 6〇2 and/or metal channels 604 in advance, thereby omitting one or more processing steps. In Figure 6C, a plurality of microsystems 6〇6 are formed over the metal vias 604 and the substrate 600 using any of the foregoing techniques. Then, the solder bumping operation and singulation can be performed as shown in Figs. 5G and 5H. The actual embodiment shown in the figure may contain the same various features as those described in connection with Figs. 5 to 5H. 7A through 7C are cross-sectional views showing a wafer leveling process for establishing a package in accordance with another embodiment of the present invention. A substrate 7 is provided first. A plurality of copper contact pads 702 are then formed over the top surface of the substrate 7A. In Figure 7B, a plurality of microsystems 7A4 are formed over the copper contact pads 702 and the substrate 7A using any of the foregoing techniques. The microsystems 7〇4 and the top surface of the substrate 700 are then encapsulated in a suitable mold forming 26 201034122 material 706. Next, in Figure 7C, the substrate 700 will be completely removed or removed. A plurality of solder bumps are then attached to the copper contact pads 702. The embodiment shown in the figures may contain the same various features as those described in connection with Figures 5A through 5H. Additional embodiments of the invention are illustrated in Figures 8 to 1A. These embodiments are directed to integrated circuit packages that embed one or more integrated circuits in a substrate (e.g., a germanium substrate). The buried integrated circuit is covered by a photoimageable epoxy layer. An interconnect layer will be formed over the Epoxy ® layer and electrically coupled to the integrated circuit via one or more of the Epoxy layers. Embedding one or more integrated circuits in a substrate provides a number of advantages. For example, various embodiments of the present invention include a buried integrated circuit that uses the substrate as a heat sink conductor and/or a medium for optical communication. When a stone wafer is used as the substrate, the thermal expansion of the buried integrated circuit and the stone substrate is the same as that which can contribute to the reduction of the delamination. In some implementations, embedding the integrated circuit in the substrate rather than in the epoxy layer can help minimize the thickness of the epoxy layer and reduce the size of the package. Various examples of integrated circuit packages including substrates having one or more buried integrated circuits will now be described with reference to Figs. 8A and 8B. 8 is a circuit package 800 comprising a substrate 8〇4, an integrated circuit 8〇2, an epoxy layer 806, and an interconnect layer 812. The substrate 8〇4 is preferably a enamel dome which is easily handled by existing semiconductor packaging equipment. However, depending on the intended use of the package 800, other suitable materials (e.g., glass, quartz, etc.) may be used. The integrated circuit 8〇2 is disposed inside the cavity/hole in the top surface of the substrate 804. The 27 201034122 and the like: the active surface of the road and the top surface of the substrate 8〇4 are covered by the resin layer 806. The epoxy layer m is made of a planarized, photoimageable epoxy resin (for example, su_8). The interconnect layer m will be formed over the epoxy resin I 806. The interconnect layer 8 ι conductor line 812b and the conductive doping and the conductor channel 812a extend to the opening in the epoxy layer 并且 and electrically connect the active circuits 8 〇 2 !/0 touch pad on the face. In the various implementations where new epoxy layers, integrated circuits, and electrical devices are not considered, the dielectric layer can

It is coated over the interconnect layer 812. Solder contact pads may be formed on the outside of the package 800, which electrically couple the integrated circuits 802 and the interconnect layer 812 via openings in the dielectric layer. Figure 8B shows another embodiment of the present invention comprising the provision of an additional layer of epoxy, integrated circuitry and interconnect layers over substrate 8A4. The integrated circuit package 801 includes a plurality of adjacent epoxy layers 822, interconnect layers 818, and integrated circuits 816 which are stacked on the interconnect layer 8, the epoxy layer 806, the integrated circuit 802, and the substrate. Above 8〇4. Integrated electricity

Each of the ways 816 will be disposed in one of the epoxy layers 822. The interconnect layer 818 is interspersed between the respective integrated circuits and the epoxy layer 822. The interconnect layers 818 electrically connect the respective integrated circuits 802 and 816 to each other and electrically connect the integrated circuits 8〇2 and 816 to the 1/() contact pads 824 formed on the top surface of the integrated circuit package 801. . It should be understood that Figures 8A and 8B represent particular embodiments from which many variations can be made. For example, there may be one or almost any number of integrated circuits disposed on or in the substrate 804. 28 201034122 - The arrangement of the conductor channels and lines, the (four) and dimensions of the material cavities and/or the thickness of the interconnect layers and the epoxy layer may be different. In addition, any of the features and arrangements described in conjunction with Figures i through 7C may be combined with virtually any point of view in Figures 8 and 5 or used to modify almost any of the views in Figures 8B. An exemplary method for forming the integrated circuit package of Figs. 8 and 8B will now be described with reference to Figs. 9A through 9G. In Fig. 9A, a substrate 9〇2 is provided. In a preferred embodiment, the substrate 9〇2 is a lithographic wafer because this can help maximize the operation of Figure 9A to 卯 and the compatibility of existing semiconductor wafer-based processing equipment. . In an alternative embodiment, the substrate 9〇2 can be made of a wide variety of materials (including: tantalum, glass, steel, quartz, etc.) depending on the needs of the particular application. . In the crucible 9B, a plurality of cavities 9〇4 are formed in the substrate 9〇2. Cavity 904 can be formed using wet or plasma etching, although other suitable techniques can be utilized. The chemical used in the etching process and the crystalline structure of the germanium in the germanium substrate 902 can help control the angle of the sidewalls of the cavity 9〇4. For example, it has been discovered that the [矽, 丨, 〇] 矽 crystal structure can help more straight sidewalls and/or help form a sidewall that is approximately perpendicular to the bottom surface of its corresponding cavity. The die attach adhesive 9〇3 is applied to the bottom of the cavity 9〇4 to help adhere the integrated circuit 9〇6 to the bottom surface of the cavity 9〇4 as shown in Fig. 9C. In an alternate embodiment, the die attach adhesive 903 is first applied to the integrated body in an individual manner or in the wafer level prior to placing the integrated circuit 906 in the cavity 904. The back surface of circuit 9〇6. Depending on the needs of the particular application, the die attach adhesive may be electrically conductive or non-conductive. In some embodiments, the adhesives of the two types 29 201034122 are simultaneously used in the phase package, such that one of the integrated circuits is electrically coupled to a conductive substrate via its bottom surface, while another product The body circuit is electrically isolated from the substrate (conductivity applications are discussed below). In Fig. 9D, a planarized, photoimageable epoxy layer _ is deposited over the cavities 9〇4, the substrate 9G2, and the integrated circuits _. The epoxy layer 908 is preferably Su_8, but other suitable materials may also be used. The epoxy layer can extend over the active surface of the integrated circuit 906 and directly contact the active surface of the integrated circuit 〇6 and can be filled into the cavity 904 in the substrate 902. As previously mentioned, one of the advantages of using photoimageable epoxy resins (e.g., SU 8 ) is that it provides better control than photolithography. In Fig. 9E, one or more openings 91A are formed in the epoxy layer 908. These openings 91 can be produced in a variety of ways known to those skilled in the art of semiconductor processing. For example, the epoxy layer 908 may be patterned by photolithography and a portion of the epoxy layer 9〇8 may be dissolved using a developer solution. The openings 91 are capable of exposing I/O pads that are buried on the active surface of the integrated circuit 906 disposed within the epoxy layer 908. Shown in Figure 9F is the formation of interconnect layer 912, which can be implemented using various suitable techniques known in the art. One of the methods similar to the steps described in connection with FIGS. 3F to 3J includes: sinking a seed layer and a photoresist layer; patterning the photoresist layer; and plating a metal to form in the openings 910 Conductor Line 912a and Conductor Channel 9121 In various embodiments, the interconnect layer 912 electrically connects a plurality of 30 201034122 bulk circuit dies 906 embedded in the substrate 902. Then, an additional epoxy layer 918, integrated circuit 922, and/or interconnect layer 916 can be formed over substrate 9, 22, integrated circuit 906, epoxy layer 908, and interconnect layer 912. The layers and devices can be arranged in a wide variety of ways, and any of the permutations and features discussed in connection with Figures 1 through 7C can be utilized to modify any of the aspects of the embodiments shown. For example, the one or more interconnect layers 912 and/or 916 can be used to electrically connect the integrated circuit 906 disposed within the substrate 902 and to be embedded in the epoxy layer 918. Any or all of the integrated circuits 922. A heat pipe suitable or unsuitable for transmitting electrical signals extends from the substrate-based integrated circuit die 906 to any outer surface of the integrated circuit package 921. As described previously, 'various passive devices and active devices, heat pipes, heat sinks, sensors, ... may be formed or placed in almost any position of the integrated circuit package 921 (for example, on a substrate) 902 is embedded on the substrate 902 between the epoxy resin layers 918, etc.). The substrate 902 may also be subjected to back grinding or any other operation suitable for reducing the thickness of the substrate 902. Figure 9G shows Figure 9F after an additional epoxy layer, interconnect layer, and integrated circuitry are applied over substrate 〇2, integrated circuit 906, epoxy layer 908, and interconnect layer 912. An example of an integrated circuit package. Shown in Figures 10A through 10D are additional embodiments of the present invention, each of which also includes a substrate having one or more buried integrated circuits. Figure 10A shows an integrated circuit package ι〇〇〇 comprising: a conductive and thermally conductive substrate 1002' having a buried integrated circuit 1〇〇4; a planarized, photoimageable epoxy layer 1006 And an interconnect layer 1〇〇8. Integrated Circuit Package 31 201034122 The package 1000 can be formed using any of the techniques described in connection with Figures 9A through 9F. The integrated circuit 1004b is placed on the bottom surface of the cavity 1005 in the substrate 1002 using the conductive adhesive 1〇12b. Therefore, the integrated circuit 1〇〇4b can electrically couple the substrate 1002 and/or can utilize the substrate 1〇〇2 to dissipate heat/distribution to the outer surface of the package. Some embodiments also include an integrated circuit 1004a that is electrically isolated from the conductor substrate 1002 by a non-conductor adhesive 1〇12a. In the embodiment shown in the figure, only two integrated circuits are shown; however, it is also possible to provide less or even integrated circuit circuits in the substrate 1〇〇2, each of which is electrically coupled separately. The substrate 1〇〇2 is electrically insulated from the substrate 1002. In various embodiments, substrate 1 可 2 can serve as a conduit for achieving an electrical ground connection. The package 1000 includes a ground interconnection 1 〇 2 〇 which is formed over the epoxy layer 1006 and extends through the epoxy layer 1006 and is electrically coupled to one of the substrates 1 〇〇 2 Ground contact zone 1014. Ground interconnect 1020 is made of a conductive material (e.g., copper) and may have been formed at least partially during formation of interconnect layer 1 08 as previously described in connection with Figure 9F. The ground contact regions 1〇14 and other portions of the substrate 1〇〇2 in the substrate 1002 are made of tantalum and are doped to improve their conductivity. To facilitate electrical connection between the substrate 1002 and the ground interconnect 1020, the doping concentration of the ground contact region 1014 is substantially higher than one or more other portions of the substrate 1〇〇2. In various modes of operation, the substrate is made of a p-type semiconductor material and the ground contact region 1〇14 is a doped region; however, any suitable material known to those skilled in the art and / or concentration to dope the substrate 1002 and the ground contact region 1 〇 14. 32 201034122 Thus, when the ground interconnect 1020 is electrically grounded, the integrated circuit 1004b, the substrate 1002, and the ground contact region 1014 are electrically coupled to the ground interconnect 1020 and are also electrically grounded. Figure 10B provides an enlarged view of region 1010 of Figure 1A, in accordance with one embodiment of the present invention. The figure includes a substrate 1〇〇2 having a lower surface: a ground contact region 1014, an interlayer dielectric 1〇16, a passivation layer 1〇18, a plurality of conductive plugs 1022, electrical interconnects 1〇24 and 1020, and an epoxy. The resin layer 1〇〇6 and the ground interconnection 1 020. Various techniques known to those skilled in the art of semiconductor fabrication can be used to deposit, pattern, and/or develop interlayer dielectric 1016 and passivation layer 1018' and form plugs 1 22 and electrical interconnects 2 024. Plug 1022 and electrical interconnect 1024 may be made of a variety of suitable conductive materials - which comprise tungsten and aluminum, respectively. Epoxy layer 1 与 6 and interconnect 丨〇 2 〇 can be formed using a variety of techniques, which include the techniques described in conjunction with Figures 9F. The technique for forming the interlayer dielectric 1 〇 16 and the passivation layer 1 〇 18 of Fig. 10B is integrated into the technique for forming the cavity 1 〇〇 5 of Fig. 1 . For example, during formation of cavity 1005, interlayer dielectric 1 〇 16 will be deposited across top surface 1 〇〇 3 of substrate 1 〇〇 2 . The interlayer dielectric is patterned and etched, not only to create space for the plugs 1 22, but also to form a mask to form a cavity in the substrate 〇〇2. This approach can help reduce the number of processing steps used to fabricate integrated circuit packages. Another embodiment of the invention is illustrated in Figure 1c. Figure 1〇c includes an integrated circuit package that forms an integrated circuit, a planarized photoimageable epoxy layer, and an interconnect layer on both sides of the substrate. In the embodiment shown in FIG. 33 201034122, the integrated circuit 1036, the epoxy layer 1〇4〇, and the interconnect layer 1038 are formed over the top end surface 1〇34 of the substrate 1032. The integrated circuit 1042, the epoxy layer 1 〇 44, and the interconnect layer 1 〇 46 are formed over the reverse bottom surface 1 〇 46 of the substrate 1032. One way to form the integrated circuit package 1030 is to apply the techniques discussed in connection with Figures 9 through 9F over both the top and bottom surfaces of the substrate 1 〇32. A special implementation of the integrated circuit package 1 〇 3 包含 includes arranging a plurality of integrated circuits for communicating with each other via an optical substrate. In the embodiment shown in the figure, for example, the integrated circuit t 〇3 is aligned with the top and bottom of each other and includes a plurality of optical devices, for example, a laser body, an optical debt detector, ... Etc. (Alternatively, in another embodiment, a plurality of optical devices (example #: optical sensor, optical detector, laser diode, etc.) may be used instead of the integrated circuit 1036a and/or 1042a. ). At least a portion of the substrate between the integrated circuits 1〇36& and 1〇42a is transmissive and arranged to allow optical communication between the integrated circuit and 1042a. The substrate may be made of a variety of materials, including glass and quartz. Some implementations include a substrate 1〇32 made entirely of a single light transmissive material and/or having a uniform composition. The substrate 1032 is formed. The enamel substrate 1032 can electrically insulate the integrated circuits i 〇 36a and i 〇 42a; however, for example, they are made to utilize ultraviolet light (which can travel through the cymbal) optically Further, an embodiment of the present invention is illustrated in FIG. 10D. FIG. 10D shows an integrated circuit package 〇5〇, which has a structure for mitigating being embedded in the 34 201034122 package substrate 1052. A characteristic component of the stress on one or more integrated circuits 1054. The integrated circuit package contains - the following substrate brittle: cavity, integrated circuit 1 〇 54, photoimageable epoxy layer deleted and Interconnect layer 1058. Each one The hole 1 〇 6 〇 is a side wall 1064 of the cavity 1 〇 6 及 and the integrated circuit 1 〇 54 includes an air gap during testing and operation, the integrated circuit 1054 and the package 1 〇 5 〇 The temperature cycling operation is performed. The temperature increase may cause the integrated circuit to be expanded and expanded by other devices in the package 1050. If the integrated circuit is encapsulated in a resilient material, the swelling effect is Additional stress may be imposed on the integrated circuit 1 54. The air gap ι 62 can provide space for the integrated circuit 1 () 54 to expand, and thereby help to reduce this stress. Accordingly, the epoxy resin The layer 1056 covers the cavity 1〇6〇, but does not extend substantially into the cavity 1〇6〇. There are various ways to form the characteristic components of the integrated circuit package 1〇5〇. In this case, the formation of the cavity 1〇6〇 in the substrate 1052 and the placement of the integrated circuit 1〇54 in the cavity 1060 can be carried out as previously described with reference to Figures 9a to %. A layer of pre-manufactured photoimageable epoxy resin (eg SU-8) The cavities 1 〇 6 〇 and the substrate 1052 are covered. In various embodiments, the epoxy layer 1 〇 56 is not sprayed and spin coated over the cavities 1 〇 60, but is instead Lamination on the substrate 1052 facilitates the retention of the air gap 1 〇 62 between each of the integrated circuits 1 〇 54 and the sidewalls 1064 of the corresponding cavity 1060. Next, in the epoxy layer 1056 and the interconnect layer The formation of the opening in 1058 can be performed in a manner similar to that described in connection with Figures 9 to 9F. For example, photolithography can be used to pattern the epoxy layer 1〇56, 35 201034122 can result in curing and/or removal of a portion of the epoxy layer 1056. Although the present invention has been described in detail herein, it is understood that the invention may be embodied in many other forms without departing from the spirit or scope of the invention. For example, the various embodiments described herein sometimes illustrate unique and distinct features; however, the invention encompasses a wide variety of integrated circuit packages, each of which may contain substantially all of the features described herein. Any combination is formed using almost any combination of the processes described herein. Taking the substrate 8〇4 of the integrated circuit package 8A of FIG. 8A including one or more embedded integrated circuits as an example, it is possible to further include a plurality of metal channels which pass through the substrate 8〇4 and The interconnect layer 812 is electrically connected to the contacts on the outer surface of the substrate 8〇4. These metal channels are described in conjunction with Figure 4E. The process for fabricating the metal vias is as described with respect to Figures 5A through 5H and is equally applicable to the substrate 8A of Figure 8A. Therefore, the embodiments of the present invention should be considered as illustrative and not restrictive, and the invention is not limited to the details set forth herein, but also in the accompanying application (4) Correction from the inside ❹ [Simplified description of the drawings] With reference to the above description in conjunction with the accompanying drawings, the present invention and its advantages can be best understood, wherein: Figure 1 shows an implementation in accordance with the present invention. For example, a cross-sectional view of a package containing a plurality of integrated circuits and interconnect layers. 2 is a process flow diagram of a wafer level process for packaging integrated circuits in accordance with an embodiment of the present invention. 3A through 3L are cross-sectional views showing selected steps in the process of Fig. 2. 36 201034122 Figures 4A through 4E are cross-sectional views of the package in accordance with various alternative embodiments of the present invention. 5A through 5H are selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. Figures 6A through 6C illustrate selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. 7A through 7C are diagrams showing selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. 8A through 8B are cross-sectional views of a package in accordance with various embodiments of the present invention - each package includes a substrate having a buried integrated circuit. 9A to 9G are diagrams showing a step in a wafer leveling process for forming a package according to another embodiment of the present invention, each package including a substrate having a buried integrated circuit. 10A through 10D are cross-sectional views of a package arrangement in accordance with various embodiments of the present invention. In the drawings, the same component symbols are sometimes used to indicate the same, . Structure 7C pieces. It should also be understood that the (four) depicted in the figures are only schematic and not drawn to scale. [Main component symbol description] None 37

Claims (1)

201034122 VII. Patent Application Range: ι_ A wafer level method for forming an integrated circuit package, comprising: providing a substrate having a first surface and a reverse second surface, the substrate having the substrate a metal channel extending between the first surface and the second surface; forming a plurality of microsystems on the first surface of the substrate, each microsystem comprising: • a plurality of planarizations of closely adjacent stacks, a photoimageable epoxy layer; ❹ at least one interconnect layer, one interconnect layer is embedded in an associated epoxy layer; and • an integrated circuit disposed at least in association Inside the epoxy layer; forming interconnect layers of the plurality of microsystems, electrically interconnecting the plurality of interconnect layers in the interconnect layers with the plurality of metal vias; Applying over the first surface of the substrate to form a mold structure 'to encapsulate each of the plurality of microsystems; and singulating the mold structure' to form The integrated circuit package, where 'each are an integrated circuit package comprising such a micro system in which at least one. 2. The method of claim 1, wherein the providing the substrate comprises: forming a hole in the substrate; and 38 201034122 plating a conductor material into the holes of the substrate to form the same Metal channel. 3. The method of claim 1, wherein the plurality of epoxy resins are sequentially deposited over the substrate to form the plurality of closely adjacent stacked layers, wherein the epoxy layers are Deposited by spin coating with a topmost layer of epoxy; patterning at least some of these in a photolithographic manner after at least some of the layers of epoxy are deposited and before the next layer of epoxy is deposited An epoxy resin layer; forming a plurality of openings in at least some of the patterned epoxy layers after at least some of the epoxy layers are patterned; and before the next epoxy layer is deposited; A plurality of integrated circuits in the plurality of servo circuits are disposed in the plurality of openings associated with the openings, wherein each integrated circuit has a plurality of I/O solder contact pads and the epoxy At least one of the layers is deposited after each integrated circuit is disposed to cover the integrated circuit; and at least one conductor interconnect layer is formed, wherein each interconnect layer is formed An epoxy layer over associated. 4. The method of claim 1 wherein the method comprises back grinding the substrate to expose portions of the metal channels. 5. The method of claim 1, wherein: each epoxy layer is made of SU-8; each microsystem comprises a plurality of integrated circuits; and the epoxy layers At least one of the cymbals extends over the active surface of each of the integrated circuits 39 201034122. 6. The method of claim 2, wherein the substrate is made of one of the group consisting of Si, g1〇_Fr4, and glass. 7. The method of claim 2, wherein the providing of the substrate comprises: etching the second surface of the substrate to form a cavity in the substrate; forming a sensing element in the cavity Removing a portion of the substrate to form a hole in the substrate; and plating a conductor material into the substrate to form the metal channels, wherein at least some of the metal channels are electrically coupled to the sensing element . 8. The method of claim 7, wherein the sensing element is one of the group consisting of: a photovoltaic cell, a biosensor, a gas sensor, a chemical sensor , electromagnetic sensors, acceleration sensors, vibration sensors, humidity sensors, and wireless phase antennas. 9. A method for forming an integrated circuit package, comprising: providing a substrate having a first surface and a reverse second surface; applying a conductor material to the first surface of the substrate, Forming a substrate soldering contact pad; forming a plurality of microsystems on the first surface of the substrate, each microsystem comprising: a plurality of closely adjacent stacked planarized, photoimageable epoxy resin layers; An interconnect layer, each interconnect layer being embedded in an associated epoxy layer; and '201034122 ❹ Inside; an integrated circuit disposed at least - an associated epoxy layer forming an interconnect layer of the plurality of microsystems, the plurality of interconnect layers electrically contacting the substrate tan contact pads; a plurality of substrate solders in the interconnect layer are coated with a mold material over the first surface of the substrate for: molding the wafer structure 1 to encapsulate the plurality of microsystems Each of the patterned wafer structures for forming individual integrated circuit packages, the second integrated circuit package includes at least one of the plurality of microsystems; and removing at least some of the substrates Ίο· As claimed in the patent range, the resin layers are all made of SU-8 to expose the substrate solder contact pads. The method of claim 9, wherein each of the epoxys 11. The method of forming the microsystem of the method of claim 9 includes: wherein: the plurality of layers are itch-dependent, aTM sequential/integrated multiple layers above the substrate An epoxy resin to form the plurality of closely adjacent stacked layers, wherein the epoxy layer is deposited by spin coating, which has a topmost epoxy layer; Etc. After the deposition of some of the epoxy layers, and prior to the deposition of the next ring of the resin layer, at least some of the epoxy layers are patterned in a lithographic manner; at least some of the epoxy resins Forming a plurality of openings in at least one of the lipid layers before being deposited by the epoxy layer; after patterning and in the next patterned epoxy tree 201034122, a plurality of integrated circuits in the plurality of integrated circuits a circuit is disposed in the plurality of openings associated with the openings, wherein each of the integrated circuits has a plurality of I/O solder contacts and at least one of the epoxy layers is Place each unit of electricity After being deposited so as to cover the integrated circuit; and forming at least one conductive interconnect layer, wherein each interconnect layer are formed over an epoxy layer associated. 12. The method of claim 9, wherein: each of the microsystems comprises a plurality of integrated circuits; and at least one of the S Λ裒 oxygen tree monthly B layers is in each of the integrated circuits The upper surface of the active surface extends. 13. The method of claim 9, wherein the substrate is made of one of the group consisting of: 8 (10)-gang and glass 14. An apparatus comprising: a substrate having a plurality of metal channel top surfaces, a reverse bottom surface, and a plurality of microsystems formed on a top k surface of the substrate π, each microsystem All include; a plurality of closely Φ adjacent stacked planarized, photoimageable epoxy trees • at least one interconnect layer, inside the epoxy layer; and each interconnect layer is embedded in an associated layer An integrated circuit disposed at least in the integrated circuit to electrically couple at least one of the 42 201034122 metal vias via the at least one associated epoxy layer interconnect layer. The top surface of the substrate and the molding material above the plurality of microsystems. 15 _A device as claimed in claim </ RTI> </ RTI> which embeds a plurality of sensing elements embedded in the substrate, wherein each of the sensing elements is one of the group consisting of the following seven : Photovoltaic cells, biosensors, gas sensors, chemical sensors, electromagnetic sensors, acceleration sensors, vibration sensors, humidity sensors, and wireless phase antennas. 16. The device of claim 15 wherein the substrate comprises a plurality of tubes that expose portions of the sensing elements. 17. The integrated circuit package of claim 14, wherein the substrate is made of one of the group consisting of Si, G10-FR4, and glass. 18. The integrated circuit package of claim 14, wherein the metal vias do not completely pass through the substrate and the substrate is made of a sacrificial material. ❾ 19. The integrated circuit package of claim 14 wherein: each epoxy layer is made of SU-8; each microsystem includes a plurality of integrated circuits; and the rings At least one of the oxy-resin layers extends over the active surface of each of the integrated circuits. Eight, the pattern: (such as the next page) 43