[go: up one dir, main page]

TW201020830A - Method to determine process window - Google Patents

Method to determine process window Download PDF

Info

Publication number
TW201020830A
TW201020830A TW97145888A TW97145888A TW201020830A TW 201020830 A TW201020830 A TW 201020830A TW 97145888 A TW97145888 A TW 97145888A TW 97145888 A TW97145888 A TW 97145888A TW 201020830 A TW201020830 A TW 201020830A
Authority
TW
Taiwan
Prior art keywords
rule
contact hole
members
pattern
value
Prior art date
Application number
TW97145888A
Other languages
Chinese (zh)
Other versions
TWI452480B (en
Inventor
Te-Hung Wu
Sheng-Yuan Huang
Cheng-Te Wang
Chia-Wei Huang
Ping-I Hsieh
Po-I Lee
Chuen-Huei Yang
Pei-Ru Tsai
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW097145888A priority Critical patent/TWI452480B/en
Publication of TW201020830A publication Critical patent/TW201020830A/en
Application granted granted Critical
Publication of TWI452480B publication Critical patent/TWI452480B/en

Links

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A method to determine a process window is disclosed. First, a pattern data is provided. Second, a sizing value set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.

Description

201020830 六、發明說明: . 【發明所屬之技術領域】 本發明係關於一種決定製程裕度的方法。特定言之,本 發明係關於一種決定製程裕度的方法,使得圖形資料(Pattern data)中的各個多邊形成員儘量外移,而具有滿足最小間隔規 則之最大可能的面積。 〇 【先前技術】 在半導體元件的製造過程中,經常會使用到微影(photo lithography)及餘刻(etching)等關鍵技術。微影技術包括將一複 雜的積體電路圖形逐次轉移至一半導體晶圓表面,以分別供蝕 刻、摻雜等步驟所用。此等圖形的轉移需要極為準確,俾與之 前與之後之其他製程之轉移圖案相互對應,進而製造出精密的 積體電路。 ❹ 但是在微影步驟中,將光罩(reticle)上的標準圖形轉移至 晶圓表面時’經常會產生各式偏差,進而影響半導體裝置之性 能。此等偏差與被轉移的圖形特性、疏密度、晶圓的尺寸、所 使用的光源種類及種種的製程參數有關。 其中’對於因為光學近接效應、工藝規則、光學規則等 所引起的圖形偏差,已經發展出許多檢驗、修正與補償的方 法,以改善影像轉移後的品質。例如,已知之方法有光學近接 201020830 修正(optical proximity correction ’ OPC)、設計規範檢驗(design rule check,DRC)與光學規則檢驗(lithography rule check,LRC) 等等’並已有許多市售光學近接修正軟體,以供檢測佈局圖形 中的狹小處(pitch)、橋接處(bridge)、關鍵尺寸均勻性(cd uniformity)等等問題。此等光學近接修正軟體可以將光罩的標 準佈局圊形經由理論影像校正,而獲得可於晶圓上正確曝光的 影像圖形。此等方法不但能檢測佈局圖形中的問題,還能經由 ❹理論影像校正光罩的佈局圖形。所得之校正圖形若均正確可 用,則予以輸出製作光罩,進而獲得晶圓上正確的影像圖形。 一般說來,以上檢驗、修正與補償的方法都有已經建立 好了的^示準處理流程步驟可供參考。例如,習知技術中利用光 學近接修正來確認光罩之佈局圖形的流程可以是,首先,輸入 一佈局圖形。然後對此佈局圖形進行光學近接修正的布林 (Boolean)預處理,獲得初步佈局圖形。接著,進行光學近接修 ◎正’以修正較特殊的圖形。然後,個別進行設計規範檢驗(design rule check ’ DRC)與光學規則檢驗(lithography rule check, LRC),然後再進行錯誤過滤及檢查。如果所得之圖形若均正 確可用,則予以輸出。若有錯誤,則反覆進行整修及檢查,無 誤後再予以輸出。 然而’以上檢驗、修正與補償方法的概念都是基於要矯 正光學近接效應(0ptical proximity effect)所帶來影像的扭 4 201020830 曲’而不會實質上影響到佈局圖形面積的大小。目此經過光學 近接修正所得之佈局圖形,實際上其面積並不會有實質上的= 變。 但疋由於某些特定的元件,例如接觸洞或是金屬内連 線,當其面積愈大時愈是能降低電阻而有利於元件的操作性 能,然而,對於此等希望面積愈大愈好的佈局圖形而言,例如 ❹接觸洞圖形或是金屬内連線圖形,光學近接修正的結果僅僅只 能避免掉光學近接效應(optical proximity effect)所產生影像 的扭曲,並不能帶來實質上有利於元件操作性能上的助益。因 此,對於此等希望面積愈大愈好的佈局圖形而言,光學近接修 正的操作並不足以提升元件在操作性能上的改良。 由此可知,目前急需要另一種有別於光學近接修正操作 原理與過程的另一種縮放調校(resizing)方法,使得經此方法調 © 校過的佈局圖形能夠獲得最大的可能面積,於是可以決定更好 的製程裕度(process window)。 【發明内容】 本發明於是提出一種決定製程裕度的方法。當佈局圖形 在使用本發明方法調校過之後,特定的圖形會被盡量放大而得 到最大的適當面積。對於某些特定的元件而言,由於當其面積 較大時有利於元件的操作性能’於是在經過本發明方法調校過 之後’即能為元件的操作性能帶來實質上的助益。 201020830 本發明決定製程裕度的方法。首先,提供一圖形資料, 其可以包含多個多邊形,此多個多邊形各別包含複數個成員, 並各別具有其第一面積。其次,決定一調校值組(bias set), 此調校值組由一系列由大到小之調校值(bias)所組成。繼續, 依據此調校值組’讓圖形資料進行一縮放調校程序,而得到合 用的最終調校圖形’並成為一面積改變之標的圖形(target pattern)。在此縮放調校程序中,所有成員依據一最小間隔規 ❹ 貝|J (minimum spacing rule)先進行一内縮程序,然後所有未内 縮的成員再持續進行外移程序直到通過一最小間隔規則 (mijiimum spacing rule )、一 接觸洞對多晶矽規則(contact to poly rule)與一接觸洞對金屬導線規則(contactt〇metalrule) 檢驗’其修正量依照調校值組中一系列由大到小之調校值,直 至調校值為0而終止並保有其最終值。若進行過縮放調校程序 之多邊形其第二面積不小於第-面積,即進行縮放調校程序, G 而得到面積改變之標的圖形。若進行過縮放調校程序之多邊形 其第二面積小於第一面積,則此多邊形之所有成員即拋^所保 有之調校值。然後輸出此標的圖形。 【實施方式】 本發明在於提供一種決定製程裕度的方法,尤其是一 關於增加高圖案密度區域之製程裕度的方法。當使用本發明 法來調校-佈局圖形之後,特定的圖形,例如接觸洞或是= 6 201020830 内連線,會被盡量放大而得到最大的適當面積。由於某些特定 的元件,其面積較大時元件的操作性能更佳,於是本發明方法 ' 一方面決定了製程裕度,另一方面還能為元件的操作性能帶來 實質上的助益。 第1圖例示本發明決定製程裕度的方法主要流程之流程 圖。本發明決定製程裕度的方法100,包含: 步驟110 : 提供一圖形資料。 步驟120 : 決定一調校值組。 步驟130 : 依據所決定之調校值組,將圖形資料反覆進行一 縮放調校程序,而得到合用的一最終調校圖形。 步驟140 : 對最終調校圖形再進行一面積檢驗,而得到面積 改變之一標的圖形,並輸出此標的圖形。 步驟150 : 對此標的圖形進行一光學近接修正程序(OPC)。 步驟160 : 再進行一光學近接修正檢驗(OPC verification)。 ◎ 首先,在步驟110中,此等圖形資料可以是一種需要轉 移的電路圖形,例如接觸洞圖形資料或是金屬導線圖形資料。 此等圖形資料之特點在於,當其面積較大時有利於元件的操作 性能。例如隨機存取記憶體之接觸洞圖形或是金屬内連線圖形 等之任一階段製程的佈局圖形。在此圖形資料之中,會包含對 應於元件之多邊形。多邊形之形狀可以為矩形或其組合,多邊 形之數量通常為兩個以上。每個多邊形各別包含複數個成員 7 201020830 (members),通常為多邊形之邊。每個多邊形經由複數個成員 的組合而形成第一面積,其即為縮放調校程序之前之原始面 積。 以下將舉例說明一任意包含有多個佈局圖形的圖形資料 中,元件、佈局圖形、多邊形、成員、邊、面積間關係的一較 佳實施例。請參考第2圖,其例示一任意的圖形資料中分佈有 對應於元件之佈局圖形,佈局圖形中包含有多邊形、成員、邊。 ϋ 例如’圖形資料200中,可以視情況需要區分為多個佈局圖形 210、220、230。佈局圖形210、220、230即分別對應相鄰之 三個元件,但不限於此。每個佈局圖形210、220、230即為一 個多邊形(polygon)。每個多邊形210、220、230又由多個成 員,也就是多個邊(edges)所組成。邊211、212、213、214, 即視為成員211、212、213、214,共同組成多邊形210。類似 地,邊221、222、223、224共同組成多邊形220,成員231、 ❹232、233、234共同組成多邊形230。每個成員即可被視為在 本發明決定製程裕度的方法操作下的最小操作單位。 其次,在步驟120中,本發明會先視倩況需要決定一調校 值組(bias set)。調校值組即為用來進行本發明決定製程裕度 的方法之操作參數的集合(aeGlleetive)。在—較佳實施例中, 此調校值組通常係由-系列由大到小之調校值所組成,每個調 校值可為-預定單位值的若干倍,或是調校值組中最小值之若 8 201020830 干倍,並依照軟體模擬出之結果 位值,可以為習用製程技術中=大、二其中’所謂之單 &lt;單位值’例如1奈米 (_mete〇,或公制之單位值或是其他非 ; 此假設,在一實施態樣中,調在 之調校值,其為5奈米、4^值^含—系列依序由大到小 卡、3奈米、2奈米、!奈米。換 句話說,調校值組之成分為5太 、 1奈米。 π y卡、4奈米、3奈米、2奈米、 ❹ 當然,調校值不可能無限制从 、 的大’所以調校值組之範圍可 以利用軟體模擬出一較佳的社里y 1们&amp;果。假設一矩形之原始邊長為70 奈米* 70奈米。如果軟體模擬出 &quot; ^ + 扪'、、σ果最大可以為90奈米* 90 奈米時,調校值組之最大值即為2〇奈米。 在決定好了調校值組之後,就可以進入 決定之調校值組,將圖形資料反覆進行一縮 得到合用賴形為止,此即稱為最終調校“校程序,直至 圖形是經由至少-次的縮放調校程序而得^。,由於最終調校 程序是依據所蚊之調校值組來盡量放大每個備又’縮放調校 圖形資料中的各個佈局圖形,即會因此而局圖形所以 上的增益(gain)。 放大並獲面積 在縮放調校程序中,所有的成員會依掳—: (minimum spacingrule)先進行一内縮程序 最J間隔規貝4 間隔規則的某些弱點(weak point)的成員,^传不滿足最小 因為内縮增加間 201020830 距而暫時符合最小間隔規則,預先避免可能發生的狹小處 (pitch)或是橋接處(bridge)。所有經過内縮的成員不會進行以下 的外移(sizing up)程序。只有不經過内縮程序的成員才會進行 以下的外移(sizing up)程序。 在外移程序中,不經過内縮程序的成員,即依據所決定調 校值組中之調校值,由大到小依次被外移。第一次得到的圖形 稱為第一外移圖形,第二次得到的圖形稱為第二外移圖形,第 〇 三次得到的圖形稱為第三外移圖形……等等,並以此類推。 每次外移完成之後,再分別依據最小間隔規則( minimm spacing rule )、接觸洞對多晶石夕規則(contactto poly rule )與接觸洞對 金屬導線規則(contact to metal rule )檢驗各次外移圖形中所 有的個別成員是否合格(qualified ),藉此來確認當次之外移圖 形是否合用。若是當次外移圖形中所有的個別成員皆為合格, 則判定當次之外移圖形係屬合用,即停止其之縮放調校程序, © 而得到一最終調校圖形。 以下將舉例說明在來自晶片設計公司(design house)圖形 資料中,以調校值組將圖形資料進行一次縮放調校程序的過 程。請參考第3圖,其例示在第2圖的圖形資料中,以調校值 組將圖形資料進行一次縮放調校程序的一實施例。每個佈局圖 形 210、220、230 的所有成員 2n、212、213、214、22卜 222、 223 ' 224 ' 231 ' 232 ' 233、234即依據稍早所預先決定的調校 201020830 值組(5奈米、4奈米、3奈米、2奈米、1奈米)巾之最大調 校值(即5奈米)而被外移,得到第一外移圖形。在被外移前, 佈局圖形210、220、230分別具有原始面積a、B、C。在被外 移時’圖形資料中,還可以進一步形成一輔助圖案(assist feature),以協助縮放調校程序的進行。 假設第 3 圖中,成員 212、213、214,221、224,231、 ❹232在此外移操作(sizing Up 〇perati〇n)下,會同時符合最小 間隔規則、接觸洞對多晶矽規則以及接觸洞對金屬導線規則, 所以判定成員212、213、214,221、224,231、232可以進行 5奈米調校值的外移操作。此時,所有通過檢驗之成員,即212、 213、214 ’ 221、224 ’ 23卜232,會保有當次調校值(即5奈 米),且不再進行任何後續之外移程序。 另一方面,在5奈米調校值的外移操作中,成員211, G 222、223 ’ 233、234就不符合最小間隔規則、接觸洞對多晶矽 規則與接觸洞對金屬導線規則中之至少一者,有可能會發生狹 小處(pitch)、橋接處(bridge)或是瞎窗(blind window)等等狀 況,所以當然要判定成員211,222、223,233、234為落選 (disqualified)。此等成員除了不得進行5奈米調校值的外移 操作外,還必須退回其原始狀態。此時,因為有至少一個成員 未通過檢驗,未通過檢驗之所有成員,即211,222、223,233、 234 ’則成為落選成員(disqualified members ),並準備以進行 201020830 下一次(next) 的外移程序。 P成在單一的外移程序中’所有的成員一次就全部通 過外移操作。此時,&amp; 士 吁’所有通過檢驗之成員除了會保有當次調校 值之外,同時當泠 之外移圖形還會視為合用(usable )。視為合 用之外移圖形即成為所謂之最終調校圖形,並準備進入後續步 驟 140。 ’ 、下將繼續舉例說明圖形資料以調校值組進行下一回合 (r_d)外移程序的過程。請參考第4圖,其例示在第3圖 的圖形資料中’以調校值組將圖形資料進行另—回合外移程序 的一實施例。與第3圖的過程不同之處在於,只有落選成員 (disqualified members)方才需要進行本回合的外移程序,因 為所有通過檢驗之成員,已經保有當次調校值(即5奈米), 且不再進行任何後續之外移程序。 由於調校值組(5奈米、4奈米、3奈米、2奈米、1奈 米)中之最大調校值(即5奈米)已經使用過,所以選用次一 個調校值。每個佈局圖形210、220、230的所有落選成員,即 21卜222、223,233、234將依據調校值組(5奈米、4奈米、 3奈米、2奈米、1奈米)中之次大調校值(即4奈米)被外移。 同樣地,再次被外移時’圖形資料中,還可以進一步形成一輔 助圖案,以協助外移程序的進行。 12 201020830 再次假設第4圖中,僅有成員233在此外移操作下,同 時符合最小間隔規則、接觸洞對多晶矽規則與接觸洞對金屬導 線規則,所以判定成員233可以進行4奈米調校值的外移操 作。此時’所有通過檢驗之成員,即成員233 ’會保有當次調 校值(即4奈米),且會不再進行任何後續之外移程序。 另一方面,如第4圖所示,成員211、222、223,234在 4奈米調校值的外移操作下仍會不符合最小間隔規則、接觸洞 ❹ 對多晶石夕規則與接觸洞對金屬導線規則中之至少一者,有可能 會發生狹小處(pitch)、橋接處(bridge)或是瞎窗(blind window ) 等等狀況’所以當然要再次判定成員211、222、223,234為 落選(disqualified)。此等成員除了不得進行4奈米調校值的 外移操作外,還必須再次退回原始狀態。此時,因為還有至少 一個成員未通過檢驗’未通過檢驗之所有成員,即211、222、 223,234,則又再次成為落選成員,並準備以進行下一回合的 ©外移程序。 在下一回合的外移程序中’即對落選成員Mi、222、, 234再次進行類似先前之過程,但是採用調校值組(5奈米、4 奈米、3奈米、2奈米、1奈米)中之又次一大之調校值(即3 奈米)來外移,如此反覆進行直到調校值為〇為止,於是所有 的落選成員均會通過檢驗。在此假設成員222與成員234可以 進行2奈米調校值的外移操作,但是成員211、成員223只能 13 201020830 進行1奈米調校值的外移操作,其結果例示於第5圖。此時, 所有通過檢驗之成員除了會保有當次調校值之外,同時當次之 外移圖形還會視為合用(usable)。視為合用之外移圖形即為所 謂之最終調校圖形,並準備進入步驟140。 因此,如上所述,201020830 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of determining a process margin. In particular, the present invention relates to a method of determining process margin, such that each polygon member in the pattern data is moved as far as possible, with the largest possible area that satisfies the minimum spacing rule. 〇 [Prior Art] In the manufacturing process of semiconductor components, key technologies such as photo lithography and etching are often used. The lithography technique involves successively transferring a complex integrated circuit pattern to a surface of a semiconductor wafer for use in etching, doping, and the like, respectively. The transfer of these patterns is extremely accurate, and the transfer patterns of the other processes before and after are corresponding to each other, thereby producing a precise integrated circuit. ❹ However, in the lithography step, when the standard pattern on the reticle is transferred to the surface of the wafer, various deviations often occur, which affects the performance of the semiconductor device. These deviations are related to the transferred pattern characteristics, the density, the size of the wafer, the type of source used, and various process parameters. Among them, many methods for inspection, correction and compensation have been developed for pattern deviation caused by optical proximity effects, process rules, optical rules, etc., in order to improve the quality after image transfer. For example, known methods include optical proximity correction 'OPC, design rule check (DRC), and lithography rule check (LRC), etc. and there are many commercially available optical proximity devices. The software is modified to detect problems such as pitch, bridge, cd uniformity, and the like in the layout pattern. These optical proximity correction software can correct the standard layout of the reticle via the theoretical image to obtain an image image that can be properly exposed on the wafer. These methods not only detect problems in the layout pattern, but also correct the layout pattern of the mask via the ❹ theoretical image. If the resulting correction pattern is correct, it will be output to produce a mask to obtain the correct image on the wafer. Generally speaking, the above methods of inspection, correction and compensation have been established. For example, in the prior art, the process of confirming the layout pattern of the reticle by using the optical proximity correction may be, first, inputting a layout pattern. The Boolean pre-processing of the optical close-up correction of this layout pattern is then performed to obtain a preliminary layout pattern. Next, optical proximity is performed to correct the more specific pattern. Then, design rule check (DRC) and lithography rule check (LRC) are performed separately, followed by error filtering and inspection. If the resulting graph is available as it is, it is output. If there is an error, it will be refurbished and inspected repeatedly, and then output after error. However, the concepts of the above test, correction and compensation methods are based on the correction of the image caused by the optical proximity effect without substantially affecting the size of the layout pattern. Therefore, the layout pattern obtained by optical proximity correction does not actually have a substantial change in its area. However, due to certain components, such as contact holes or metal interconnects, the larger the area, the lower the resistance and the better the operational performance of the device. However, the larger the desired area is, the better. In terms of layout patterns, such as contact hole patterns or metal interconnect patterns, the result of optical proximity correction can only avoid the distortion of the image produced by the optical proximity effect, and does not bring about substantial benefits. Benefits of component operation performance. Therefore, for such a layout pattern in which the desired area is larger, the optical proximity correction operation is not sufficient to improve the operational performance of the element. It can be seen that there is an urgent need for another resizing method that is different from the optical proximity correction operation principle and process, so that the layout pattern that has been calibrated by this method can obtain the largest possible area, so that Decide on a better process window. SUMMARY OF THE INVENTION The present invention therefore proposes a method of determining process margin. When the layout pattern is calibrated using the method of the present invention, the particular pattern is enlarged as much as possible to obtain the largest appropriate area. For certain specific components, the operational performance of the component is facilitated by the fact that when it has a large area, and then it can be substantially beneficial to the operational performance of the component after being calibrated by the method of the present invention. 201020830 The present invention determines a method of process margin. First, a graphic material is provided, which may include a plurality of polygons each containing a plurality of members and each having its first area. Second, a bias set is determined. This set of adjustments consists of a series of biases from large to small. Continuing, according to the calibration value group, the graphic data is subjected to a scaling adjustment process to obtain a combined final calibration pattern and becomes a target pattern of the area change. In this scaling adjustment procedure, all members perform a retraction procedure according to a minimum spacing rule |J (minimum spacing rule), and then all non-indented members continue to perform the extrapolation procedure until a minimum interval rule is passed. (mijiimum spacing rule), a contact hole to the contact to poly rule and a contact hole to the metal wire rule (contactt〇 metalrule) test 'the correction amount according to a series of large to small adjustments in the adjustment value group The calibration value is terminated until the adjustment value is 0 and its final value is retained. If the second area of the polygon subjected to the zoom calibration procedure is not less than the first area, the zoom adjustment program is performed, and G is obtained to obtain the image of the area change. If the polygon of the zoom adjustment procedure has a second area smaller than the first area, all members of the polygon are the adjustment values that are retained. Then output the graphic of this target. [Embodiment] The present invention is directed to a method of determining a process margin, and more particularly to a method of increasing a process margin of a high pattern density region. When using the method of the present invention to calibrate-layout graphics, specific graphics, such as contact holes or = 6 201020830 interconnects, are amplified as much as possible to obtain the largest appropriate area. Due to the specific components, the operational performance of the components is greater when the area is larger, so that the method of the present invention determines the process margin on the one hand and substantially contributes to the operational performance of the components on the other hand. Fig. 1 is a flow chart showing the main flow of the method for determining the process margin of the present invention. The method 100 of determining a process margin of the present invention comprises: Step 110: providing a graphic material. Step 120: Determine a calibration value group. Step 130: According to the determined calibration value group, the graphic data is repeatedly subjected to a scaling adjustment process, and a final calibration graphic is obtained. Step 140: Perform an area inspection on the final calibration pattern to obtain a graphic with one of the area changes, and output the graphic of the target. Step 150: Perform an optical proximity correction procedure (OPC) on the target graphic. Step 160: Perform an optical OPC verification. ◎ First, in step 110, the graphics data may be a circuit pattern that needs to be transferred, such as contact hole pattern data or metal wire pattern data. The characteristics of these figures are that they contribute to the operational performance of the component when the area is large. For example, a layout pattern of a process such as a contact hole pattern of a random access memory or a metal interconnect pattern. In this graphic, there will be polygons corresponding to the components. The shape of the polygon may be a rectangle or a combination thereof, and the number of the polygons is usually two or more. Each polygon contains a plurality of members 7 201020830 (members), usually the edge of the polygon. Each polygon forms a first area via a combination of a plurality of members, which is the original area before the scaling adjustment procedure. A preferred embodiment of the relationship between components, layout graphics, polygons, members, edges, and areas in a graphics material arbitrarily including a plurality of layout graphics will be exemplified below. Please refer to FIG. 2, which illustrates an arbitrary graphic material with layout patterns corresponding to components, and the layout graphics include polygons, members, and edges. ϋ For example, in the graphic material 200, it may be divided into a plurality of layout patterns 210, 220, and 230 as occasion demands. The layout patterns 210, 220, and 230 respectively correspond to the adjacent three elements, but are not limited thereto. Each of the layout patterns 210, 220, 230 is a polygon. Each polygon 210, 220, 230 is in turn composed of a plurality of members, that is, a plurality of edges. The edges 211, 212, 213, 214 are considered to be members 211, 212, 213, 214, which together form a polygon 210. Similarly, edges 221, 222, 223, 224 collectively form a polygon 220, and members 231, ❹ 232, 233, 234 collectively form a polygon 230. Each member can be considered as the minimum unit of operation under the method operation of the present invention to determine the process margin. Next, in step 120, the present invention will determine a bias set in advance. The calibration value set is a set of operational parameters (aeGlleetive) used to perform the method of determining the process margin of the present invention. In the preferred embodiment, the adjustment value group is usually composed of a series of adjustment values from large to small, and each adjustment value may be a multiple of a predetermined unit value, or a calibration value group. If the minimum value is 8 201020830 dry times, and according to the result value of the software simulation, it can be used in the conventional process technology = large, two of which 'the so-called single &lt; unit value' such as 1 nanometer (_mete〇, or metric The unit value or other non-this; this assumption, in an embodiment, adjusts the calibration value, which is 5 nm, 4 ^ value ^ contains - series sequentially from large to small, 3 nm, 2 nm, !N. In other words, the composition of the adjustment value group is 5 tera, 1 nm. π y card, 4 nm, 3 nm, 2 nm, ❹ Of course, the adjustment value is impossible Unlimited from the big ', so the range of the tuning value group can use the software to simulate a better social y 1 &amp; fruit. Suppose the original side length of a rectangle is 70 nm * 70 nm. If the software When the maximum value of σ fruit is 90 nm * 90 nm, the maximum value of the calibration value group is 2 〇 nanometer. After the group, you can enter the decision adjustment value group, and then repeat the graphic data to get the total use. This is called the final adjustment of the "school program until the graphics are through at least - times of the scaling adjustment process. ^^, because the final tuning procedure is based on the calibration value set of the mosquitoes to maximize the magnification of each layout and the various layout graphics in the zoom adjustment graphics, that is, the gain on the graphics (gain) Zoom in and get the area in the zoom adjustment program, all members will rely on -: (minimum spacingrule) first to perform a contraction procedure, the most J gap rule, the member of the weak point (weak point), ^ The transmission is not satisfied to the minimum because the indentation increases the interval between 201020830 and temporarily meets the minimum interval rule, avoiding the possible pits or bridges in advance. All the indented members will not perform the following migration ( Sizing up). Only the members who do not go through the indentation program will perform the following sizing up procedure. In the external migration program, the members who do not go through the indentation procedure are determined according to the decision. The adjustment value in the calibration value group is shifted from large to small. The first obtained graphic is called the first externally shifted graphic, and the second obtained graphic is called the second externally shifted graphic. The obtained pattern is called the third externally shifted graph, etc., and so on. After each external shift is completed, according to the minimum interval rule (minimm spacing rule), the contact hole to the polycrystalline stone rule (contactto Poly rule) and the contact to metal rule check whether all individual members in each out-of-plane graphic are qualified, thereby confirming whether the externally shifted graphics are used together. If all the individual members in the externally shifted graph are qualified, it is determined that the externally shifted graphics are used together, that is, the zoom adjustment program is stopped, and a final adjustment pattern is obtained. The following is an example of a process in which a graphic value data is subjected to a scaling adjustment process in a graphic design from a wafer design company. Please refer to FIG. 3, which illustrates an embodiment in which the graphic data is subjected to a scaling adjustment process in the graphic data of FIG. All members 2n, 212, 213, 214, 22 222, 223 ' 224 ' 231 ' 232 ' 233, 234 of each layout pattern 210, 220, 230 are based on a previously determined adjustment of the 201020830 value group (5) The maximum adjustment value (ie, 5 nm) of the towel (4 nm, 3 nm, 2 nm, 1 nm) was moved outward to obtain the first outward shift pattern. Before being moved out, the layout patterns 210, 220, 230 have original areas a, B, and C, respectively. In the graphic data when being moved, an assist feature can be further formed to assist in the scaling adjustment process. Assume that in Figure 3, members 212, 213, 214, 221, 224, 231, ❹ 232 will simultaneously meet the minimum spacing rule, contact hole versus polysilicon rule, and contact hole pair under the sizing up 〇perati〇n The metal wire rules, so the decision members 212, 213, 214, 221, 224, 231, 232 can perform an outward shift operation of the 5 nm adjustment value. At this point, all members passing the inspection, namely 212, 213, 214 '221, 224 ‘ 23 232, will retain the current adjustment value (ie 5 nm) and no further external migration procedures will be performed. On the other hand, in the shifting operation of the 5 nm tuning value, the members 211, G 222, 223 '233, 234 do not meet the minimum spacing rule, the contact hole versus polysilicon rule and the contact hole to the metal wire rule. In one case, there may be a situation such as a pitch, a bridge, or a blind window, so it is of course determined that members 211, 222, 223, 233, and 234 are disqualified. These members must return to their original state in addition to the 5 nm adjustment value. At this time, because at least one member fails the test, all members who fail the test, namely 211, 222, 223, 233, 234 'is become disqualified members, and are prepared to perform 201020830 next (next) Move the program. P is in a single extrapolation procedure. 'All members are all moved out at once. At this time, &amp; 士 吁 ’ 所有 All members who pass the inspection will retain the current adjustment value, and the 之外 external shift graph will be considered as usable. It is considered that the combined external shifting pattern becomes the so-called final adjustment pattern and is ready to proceed to the subsequent step 140. </ br> will continue to illustrate the process of graphical data to adjust the value group for the next round (r_d) extrapolation process. Please refer to Fig. 4, which illustrates an embodiment in which the graphic data is subjected to another-to-round migration procedure in the graphic data of Fig. 3. The difference from the process in Figure 3 is that only the disqualified members need to perform the transfer process of this round, because all members who pass the inspection already have the current adjustment value (ie 5 nm), and No further outbound procedures are performed. Since the maximum adjustment value (ie 5 nm) in the adjustment value group (5 nm, 4 nm, 3 nm, 2 nm, 1 nm) has been used, the next adjustment value is selected. All the missing members of each layout graphic 210, 220, 230, ie 21 222, 223, 233, 234 will be based on the adjustment value group (5 nm, 4 nm, 3 nm, 2 nm, 1 nm) The second major adjustment (ie 4 nm) was moved out. Similarly, when it is moved out again, in the graphic data, an auxiliary pattern can be further formed to assist the process of the shifting process. 12 201020830 Again assume that in Figure 4, only member 233 is in the additional shift operation, while meeting the minimum spacing rule, the contact hole versus polysilicon rule and the contact hole versus metal wire rule, so the decision member 233 can perform a 4 nm calibration value. The move operation. At this point, all members who pass the inspection, member 233 apos, will retain the current adjustment value (ie 4 nm) and will not proceed with any subsequent extrapolation procedures. On the other hand, as shown in Fig. 4, the members 211, 222, 223, 234 will still not meet the minimum interval rule and contact hole under the external shift operation of the 4 nm calibration value. At least one of the hole-to-metal wire rules may have a pitch, a bridge, or a blind window, so of course, the members 211, 222, and 223 are again determined. 234 is disqualified. In addition to the fact that these members are not allowed to perform the external shifting of the 4 nm adjustment value, they must return to the original state again. At this time, because at least one member has failed to pass the test, all members failing to pass the test, namely 211, 222, 223, 234, again become the unsuccessful member, and prepare for the next round of the © external migration procedure. In the next round of the migration process, 'the same as the previous process, but the adjustment value group (5 nm, 4 nm, 3 nm, 2 nm, 1) is used for the unsuccessful members Mi, 222, and 234. The next major adjustment value (ie, 3 nm) in the nanometer is moved outwards, and so on until the adjustment value is 〇, so all the unsuccessful members will pass the test. It is assumed here that the member 222 and the member 234 can perform the shifting operation of the 2 nm adjustment value, but the member 211 and the member 223 can only perform the external shift operation of the 1 nm adjustment value by 13 201020830, and the result is illustrated in FIG. . At this point, all members who pass the inspection will retain the current adjustment value, and the externally shifted graph will be considered as usable. It is considered that the combined external shifting pattern is the so-called final calibration pattern and is ready to proceed to step 140. So, as mentioned above,

步驟130 : 依據所決定之調校值組,將圖形資料反覆進行一 縮放調校程序,而得到合用的一最終調校圖形 還可以分成如第6圖所示之子步驟: 子步驟131 : 所有成員進行一内縮程序。 子步驟132 : 子步驟133 : 依序選擇調校值組之調校值。 依據當次之調校值將未經過内縮的所有成員進 行一外移程序,而得到一當次外移圖形。 子步驟134 : 子步驟135 : 確認當次之外移圖形是否符合最小間隔規則。 確認當次之外移圖形是否符合接觸洞對多晶矽 規則。 子步驟136 : 確認當次之外移圖形是否符合接觸洞對金屬導 線規則。 子步驟137 :若所有成員通過檢驗,則當次之外移圖形即為 合用,並為最終調校圖形準備進入步驟140。 子步驟138 : 若所有成員之至少一個未通過檢驗,通過檢驗 之所有成員即保有當次調校值,且不再進行任 何外移程序,而未通過檢驗之所有成員則成為 14 201020830 落選成員,並進入一次一回合之子步驟i3i外 移程序。 接下來,進行 步驟140:對最終調校圖形再進行_面積檢驗, 變之-標的圖形,並輸出此標的圖形 於疋步驟14〇又還可以分成如第7圖所示之子步驟: 子步驟141 .依據面積檢驗確認是否進行縮放調校程序。Step 130: According to the determined calibration value group, the graphic data is repeatedly subjected to a scaling adjustment process, and the obtained final calibration graphic may be further divided into sub-steps as shown in FIG. 6: Sub-step 131: All members Perform a retraction procedure. Sub-step 132: Sub-step 133: The adjustment values of the calibration value group are selected in sequence. According to the current adjustment value, all members who have not been indented are subjected to an external migration process, and a current externally shifted graph is obtained. Sub-step 134: Sub-step 135: Confirm whether the current externally shifted graph meets the minimum interval rule. Confirm that the externally shifted pattern conforms to the contact hole versus polysilicon rule. Sub-step 136: Confirm that the current externally shifted pattern conforms to the contact hole-to-metal wire rule. Sub-step 137: If all members pass the check, then the out-of-band shifting pattern is used in combination, and the final tuning pattern is ready to proceed to step 140. Sub-step 138: If at least one of all members fails the inspection, all members passing the inspection retain the current adjustment value, and no external migration procedure is performed, and all members who fail the inspection become 14 201020830 unsuccessful members. And enter a sub-step i3i out of the program one round. Next, step 140 is performed: performing a _ area check on the final calibration pattern, changing the label to the target image, and outputting the target graphic at step 14 and further dividing into sub-steps as shown in FIG. 7: sub-step 141 Check whether the zoom adjustment procedure is performed based on the area test.

子步驟I42 ·若不進行縮放調校程序,成員所屬之多邊形之 斤有成員即拋棄所保有之調校值,而不進行縮 放調校操作。 '' 子步驟143.=進行縮放調校程序,所得之結果被視為面積 變之標的囷形(target pattern),根據其所保 有之調校值產生一調校結果,並輸出此標的圖 形。 子步驟141之功用在於確定前述之縮放調校程序是否合 且’以免產生愈調較面積愈小現象。若不合宜則不進行縮放調 校操Ί等縮_校之過程則交由子㈣141之面積檢驗程 序來執行°由於希望元件之面積愈大愈好,所以縮放調校程序 不會使彳于元件之面積變小。換言之,每個多邊形21〇、22〇、23〇 經過調校縮小程序之面積A’、B,、c,必不會小於其原始面積 A、B、C 〇 15 201020830 一例如,假設一矩形之原始邊長為 70nm * 70nm,四邊中 之三邊都可以外移lnm,但是有一邊必需内縮3細才能符合最 小間隔規則。由於原始面積MU⑻〉縮放調校面積 (70+1 + 1) (7〇+1·3) =4896,所以此矩形即放棄外移程 序與其調校值,回復至原始尺寸,即7〇腿*7〇腿。所以有些 多邊形之形狀會改變、面積變大,但是有些多邊形之形狀不會 變面積也不變。然而,不會有多邊形之形狀改變、面積變小。 ❹ 进 8圖例不本發明一特定的圖形資料中分佈有對應於元 件之佈局圖幵/本發明第8圖例示在一圖形資料中,佈局圖形 300以不對稱之形式所構成圖形資料。在第8圖中,佈局圖形 300…著水平方向與垂直方向3〇2分散成一圖形資料。佈 局圖形300分別具有沿著水平方向3〇1的第一邊3ιι與沿著垂 直方向302的第二邊312。從第8圖中可以清楚觀察到佈局 圖开/ 300在水平方向3〇1上的間距,遠小於與垂直方向搬上 〇 的間距。 如果在縮放調校程序中’放大沿著水平方向301上的第 -邊時,會使得水平方向3〇1上已經不充裕的間距更加捉 襟見肘,甚至可能造成狹小處或是橋接處等等贼,反而適得 其反影響佈局圖形的正雜。因此在誠調校㈣巾建議放 大沿著垂直方向302的第二邊312以盡量增加每個元件的面 積。由於與垂直方向302上的間距遠大於水平方向3〇1上的間 201020830 距,有更為充裕的空間可供使用,於是既有利於元件面積的增 加,又可以避免造成狹小處或是橋接處等等瑕庇。 如果本發明來自晶片設計》司的圖形資料是接觸洞圖形 資料時’代表接觸洞圖形的多邊形,即矩形,會希望其具有適 當的較大面積。已知過小的面積會造成曝光能量達不到臨界 值’而導致圖案沒有曝開(瞎窗)。因此,一方面,面積較大時, ❻微影時的曝光強度較大,越容易得到成功的曝光圖案。另一方 面,接觸洞的面積較大,電阻就可以較小,還會有利於元件的 操作性能的提升。還有,接觸洞的面積較大,元件之電接區 (landing area)就可以較寬,也有利於製程裕度。倘若使用本 發明方法即可獲得以上之好處,此為傳統之光學近接修正程序 所不能及之處。 然後,在顧本發·法得到—合㈣標的圖形之後, © 就可以輸出合用的標的圖形。於是可以進入 步驟150:進行-傳統之光學近接修正程序(〇pc),與隨後之 步驟160·再進行一光學近接修正檢驗(〇pCverificati〇n)。 傳統之光學近接修正程序與光學近接修正檢驗可以包含 布林(Boolean)預處理、一設計規範檢驗(design ruie check, DRC)、—光學規則檢驗(lithography rule check, LRC)、一基於 模型之光學近接修正程序(a model-based OPC process)與一 基於規則之光學近接修正程序(a rule-based OPC process )...... 17 201020830 等等。此等傳統之光學近接修正程序與光料祕正檢 為一般技藝人士所熟知,在此不多加贅述。 以上所述僅為本發明之較佳實施例,凡依 做之均等變化與修飾,皆應屬本發明之涵蓋W恢專利範圍所 【圖式簡單說明】 ❹圖。第1_示本發明蚊製贿度的方h要流程之 第2圖例示任意的圖形資料中分佈有對 流程 圖形。 應於元件之佈局 第3圖例示在第2圖的圖形資料中 資料進行-讀㈣值組將圖形 第4圖例示在第3圖的圖形資料中, ❹ 貝料進行另-回合縮放調校程序的—實施例。調校值組將圖形 第5圖例示完成外移操作,其結果 第6圖所示為步驟13〇之子步驟。 施例。 第7圖所示為步驟140之子步驟。 第8圖例示本發明一特定的圖形資 件之佈局_。 h佈有對應於元 【主要元件符號說明】 200圖形資料 21〇、220、23〇、300佈局圖形、多邊形 201020830 2n、212、213、214 成員、邊 221、222、223、224 成員、邊 231、232、233、234 成員、邊 311第一邊 312第二邊Sub-step I42 • If the zoom adjustment procedure is not performed, the member of the polygon to which the member belongs is discarded from the retained calibration value without performing the zoom adjustment operation. '' Sub-step 143.=The scaling adjustment procedure is performed, and the result is regarded as the target pattern of the area change, and a calibration result is generated according to the calibration value retained therein, and the target pattern is output. The function of sub-step 141 is to determine whether the aforementioned scaling adjustment procedure is compliant and to avoid the occurrence of a smaller overshoot area. If it is not suitable, the process of zooming and adjusting is not performed. The process of the calibration is performed by the area inspection program of sub (4) 141. Since the area of the desired component is larger, the scaling adjustment program does not cause the component to be smashed. The area becomes smaller. In other words, the area A', B, and c of each polygon 21〇, 22〇, 23〇 through the calibration reduction procedure must not be smaller than its original area A, B, C 〇 15 201020830. For example, suppose a rectangle The original side length is 70nm * 70nm, and three of the four sides can be moved outward by 1nm, but one side must be retracted by 3 to meet the minimum spacing rule. Since the original area MU(8)> zoom adjustment area (70+1 + 1) (7〇+1·3) = 4896, this rectangle will give up the extrapolation program and its adjustment value, and return to the original size, that is, 7〇* 7 licking legs. Therefore, the shape of some polygons will change and the area will become larger, but the shape of some polygons will not change the area. However, there is no change in the shape of the polygon and the area becomes small. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In Fig. 8, the layout pattern 300 is dispersed into a graphic material in the horizontal direction and the vertical direction 3〇2. The layout pattern 300 has a first side 3ιι along the horizontal direction 3〇1 and a second side 312 along the vertical direction 302, respectively. It can be clearly seen from Fig. 8 that the spacing of the layout opening/300 in the horizontal direction 3〇1 is much smaller than the spacing from the vertical direction. If you zoom in on the first side of the horizontal direction 301 in the zoom calibration procedure, the gaps in the horizontal direction 3〇1 that are already insufficient will be even more stretched, and may even lead to thieves such as small places or bridges. On the contrary, it is counterproductive to influence the layout graphics. Therefore, it is recommended to enlarge the second side 312 along the vertical direction 302 in order to maximize the area of each component. Since the distance from the vertical direction 302 is much larger than the distance between 201020830 in the horizontal direction 3〇1, there is more space available, which is beneficial to the increase of the component area and avoids the narrowness or the bridge. Waiting for the shelter. If the graphic material from the wafer design section of the present invention is a contact polygon pattern, the polygon representing the contact hole pattern, i.e., the rectangle, is expected to have a suitably large area. It is known that an excessively small area causes the exposure energy to fail to reach a critical value&apos; and the pattern is not exposed (the window). Therefore, on the one hand, when the area is large, the exposure intensity at the time of lithography is large, and it is easier to obtain a successful exposure pattern. On the other hand, the contact hole has a large area and the resistance can be small, which also contributes to the improvement of the operational performance of the component. Also, the contact hole has a large area, and the landing area of the component can be wide, which is also advantageous for the process margin. The above benefits can be obtained by using the method of the present invention, which is beyond the reach of conventional optical proximity correction procedures. Then, after the image of the (4) mark is obtained by the Gu Benfa method, © can output the combined target figure. Thus, step 150 can be performed: a conventional optical proximity correction procedure (〇pc), followed by an optical proximity correction test (〇pCverificati〇n). Conventional optical proximity correction procedures and optical proximity correction tests may include Boolean pre-processing, a design ruie check (DRC), a lithography rule check (LRC), a model-based optics. A model-based OPC process and a rule-based OPC process... 17 201020830 and so on. These conventional optical proximity correction procedures and light material corrections are well known to those of ordinary skill in the art and will not be repeated here. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications should be included in the scope of the invention. The first figure shows the flow of the bribes of the mosquitoes of the present invention. Fig. 2 exemplifies the flow pattern of any of the graphic materials. Figure 3 of the layout of the components should be exemplified in the graphic data of Fig. 2. The data is read-read (four) value group. Figure 4 is illustrated in the graphic data of Fig. 3, and the bead material is subjected to another round calibration procedure. - an embodiment. The calibration value group will graphically Fig. 5 illustrates the completion of the extrapolation operation, and the result of Fig. 6 shows the substep of step 13〇. Example. Figure 7 shows the sub-steps of step 140. Figure 8 illustrates the layout of a particular graphics element of the present invention. h cloth has corresponding to element [main component symbol description] 200 graphic data 21〇, 220, 23〇, 300 layout graphic, polygon 201020830 2n, 212, 213, 214 member, edge 221, 222, 223, 224 member, edge 231 , 232, 233, 234 members, side 311 first side 312 second side

❹ 19❹ 19

Claims (1)

201020830 七、申請專利範圍: 1· 一種決定製程裕度(pr〇cesswind〇w)的方法,包含: 挺供—圖形資料(pattern data ); 決定—調校值組(bias set); 依據該調校值組,將該圖形資料進行一縮放調校程序, 而得到合㈣-最終嫩_,並絲—面積改變之標_形(加㈣ pattern)’其中δ亥最終嫩圖形符合一最小間隔規則㈤ ❹rule)、-接觸洞對多晶魏則(e()ntaettopGlyruie)與—接觸洞對金 屬導線規則(contactto metal rule);以及 輸出該標的圖形。 :求項1的方法’其中該圖形資料包含複數個多邊形,該複數個 多邊形各⑺包3複數個成員,各別該複數個多邊形具有一第一面積。 3. 如請求項2的方法,其中該複數個多邊形包含_矩形。 4. 如請求項2的方法,其中該成員_多邊形之一邊。 5.如請求項1的方法,其中該圖形 導線圖形資料所組成之群組。 資料選自由接觸洞圖形資料與金屬 20 201020830 7. 如請求項2的方法,其中該縮放調校程序包含: 將所有該成員進行一内縮(sizing d_)程序; 選擇該調校值組之一最大值; 依據該最大值將所有未内縮之該成員進行一外移(sizing up)程 序,而得到一第一外移圖形;以及 破認該第-外移圖形是否合用,而得到該最終調校圖形。 8. 如請求項7的方法’其中確認該第—外移圖形衫合用包含: 分別以該最小_規則、該接觸洞對多_酬與該接觸洞對金 屬導線規跡檢驗該第-外移_巾所有該成s,以確認該第一外移 圖形是否合用。 9.如請求項8之方法,進一步包含:201020830 VII. The scope of application for patents: 1. A method for determining the process margin (pr〇cesswind〇w), which includes: “supply data”; decision-bias set (bias set); The calibration value group performs a scaling adjustment procedure on the graphic data, and obtains a combination of (4)-final _, and a silk-area change _ shape (plus (four) pattern), wherein the final pattern of δ hai meets a minimum interval rule (5) ❹rule), - contact hole to polycrystalline Wei (e () ntaettop Glyruie) and - contact hole to metal wire rule (contact to metal rule); and output the target graphic. The method of claim 1 wherein the graphic material comprises a plurality of polygons, each of the plurality of polygons (7) comprising a plurality of members, each of the plurality of polygons having a first area. 3. The method of claim 2, wherein the plurality of polygons comprise a _ rectangle. 4. The method of claim 2, wherein the member _ polygon is one side. 5. The method of claim 1, wherein the graphical wire graphic data comprises a group. The data is selected from the contact hole graphic data and metal 20 201020830 7. The method of claim 2, wherein the scaling adjustment program comprises: performing a sizing d_ program for all the members; selecting one of the calibration value groups a maximum value; according to the maximum value, all the members that are not indented are subjected to a sizing up procedure to obtain a first outwardly shifted pattern; and whether the first-outward shifting pattern is used in combination to obtain the final Adjust the graphics. 8. The method of claim 7, wherein the first-outward shifting of the graphic shirt comprises: respectively: detecting the first-outward shift with the minimum-rule, the contact hole pair, and the contact hole-to-metal wire trace _ all the s should be s to confirm whether the first outward shifting pattern is used. 9. The method of claim 8, further comprising: 若所有該成員均通過該最小間隔規則、該接觸洞對多晶石夕規則與 該接觸晴金麟親狀檢驗,職第—外義料為仙,並為 該最終舖妨圖概。 1〇_如請求項8之方法,進一步包含 若該成員至少_縣通賴最小__、 _觸洞形紐關與該_洞對金屬導線規則之 ^ 值且不再進行任何外移程序,而未通過檢驗之該等: 成為洛選成貝以進行一次一(此对)外移程序。 員 21 201020830 11.如請求項10的方法’其中該次一外移程序包含· 提供該調校值組之一次大值; 依據該次大值將所有該落選成員再次進行該外 次一外移圖形;以及 確認所有該落選成員是否通過檢驗。 移程序,而得到— 12.如請求項11之方法,進一步包含: 若有祕職貞it職最小_賴、__對多晶魏則與 該接觸洞對金屬導線規則之檢驗,則通過檢驗之該落選成員即保有S 次大值’且不再進行任何外移程序。 如請求項11之方法,進一步包含: 若有該落選成員未通過該最小間隔規則、該接觸洞對多晶矽規則 與該接觸洞對金屬導線規則之檢驗,未通過該最小間隔規則、該接觸 © 洞對多晶矽規則與該接觸洞對金屬導線規則之檢驗之該落選成員則繼 續進行下一次外移程序直到通過該最小間隔規則、該接觸洞對多晶矽 規則與該接觸洞對金屬導線規則之檢驗,其修正量為該調校值組之一 當次值之一次大值,直至該次大值為〇並保有該次大值;以及 得到該最終調校圖形。 14.如請求項7的方法,其中進行該内縮程序包含: 依據該最小間隔規則來決定所有該成員是否内縮。 22 201020830 15.如請求項Η之方法’進一步包含: 若有該成員符合該最小間隔規則’決定該成員即不内縮。 ^6.如請求項14之方法,進一步包含: 若有該成員不符合該最小間隔規則’該成員即内縮。 17.如請求項16之方法,進一步包含·· 〇 ^ 若進行過該縮放調校程序之一第二面積不小於該第一面積,即進 订該縮放調校程序’而得到該面積改變之標的圖形(targetpattem)。 Μ =項16之方法,進-步包含: 員所屬之放調校程序之H積小於該第面積,則該成 邊形之所有該成員即拋棄所保有之該調校值組之該值。 ❹ 19·如請求们之方法 輪〜圏::::_序_) 2〇’如凊求項 對該樑的八、明式: 19的方法, 圖形進行〜 進一步包含:光學近接修正檢驗(〇PC verification )。 23If all the members pass the minimum interval rule, the contact hole for the polycrystalline stone rule and the contact with the Qingjinlin parental test, the job-foreign material is Xian, and is the final plan. 1 〇 _ the method of claim 8, further comprising if the member at least _ county relies on the minimum __, _ contact hole button and the _ hole to the metal wire rule value and no further migration procedure, Those who have not passed the test: become a one-to-one (this pair) extrapolation procedure. Member 21 201020830 11. The method of claim 10, wherein the one-time one-out-out procedure comprises: providing a large value of the adjusted value group; and all the unsuccessful members are again subjected to the external one-out shift according to the second large value Graphics; and confirm that all of the unsuccessful members passed the test. Move the program and get - 12. The method of claim 11 further comprises: if there is a secret 贞it job minimum _ _, __ for polycrystalline Wei and the contact hole for the metal wire rule test, pass the test The unsuccessful member maintains S times large value' and no further migration procedures are performed. The method of claim 11, further comprising: if the missing member fails the minimum spacing rule, the contact hole versus the polysilicon rule and the contact hole to the metal wire rule, the minimum interval rule, the contact © hole is not passed The missing member of the polysilicon rule and the contact hole to metal wire rule continues to perform the next migration process until the minimum spacing rule, the contact hole versus polysilicon rule and the contact hole to the metal wire rule are tested. The correction amount is a large value of the secondary value of one of the adjustment value groups until the large value is 〇 and the large value is retained; and the final calibration pattern is obtained. 14. The method of claim 7, wherein the performing the indentation procedure comprises: determining whether all of the members are indented based on the minimum spacing rule. 22 201020830 15. The method of claim ‘ further includes: if the member meets the minimum interval rule’, the member is not retracted. ^6. The method of claim 14, further comprising: if the member does not meet the minimum interval rule, the member is indented. 17. The method of claim 16, further comprising: ??? if the second area of the scaling adjustment procedure is not less than the first area, that is, the scaling adjustment program is ordered to obtain the area change The target graphic (targetpattem). Μ = the method of item 16, the step-by-step includes: if the H product of the release program to which the member belongs is smaller than the first area, then all the members of the formed shape discard the value of the adjusted value group retained. ❹ 19·If the request method rounds ~圏::::_序_) 2〇'If the request is for the beam of the eight, the explicit: 19 method, the graphics are carried out ~ Further contains: optical proximity correction test ( 〇PC verification ). twenty three
TW097145888A 2008-11-27 2008-11-27 Method to determine process window TWI452480B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW097145888A TWI452480B (en) 2008-11-27 2008-11-27 Method to determine process window

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW097145888A TWI452480B (en) 2008-11-27 2008-11-27 Method to determine process window

Publications (2)

Publication Number Publication Date
TW201020830A true TW201020830A (en) 2010-06-01
TWI452480B TWI452480B (en) 2014-09-11

Family

ID=44832394

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097145888A TWI452480B (en) 2008-11-27 2008-11-27 Method to determine process window

Country Status (1)

Country Link
TW (1) TWI452480B (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6782517B2 (en) * 2000-08-07 2004-08-24 Dupont Photomasks, Inc. Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block
JP4133047B2 (en) * 2002-07-05 2008-08-13 シャープ株式会社 Correction mask pattern verification apparatus and correction mask pattern verification method
TW200832171A (en) * 2007-01-29 2008-08-01 United Microelectronics Corp Method for correcting photomask pattern

Also Published As

Publication number Publication date
TWI452480B (en) 2014-09-11

Similar Documents

Publication Publication Date Title
US8225237B2 (en) Method to determine process window
CN105425532B (en) Light source mask co-optimization method
TW439113B (en) Mask pattern correction process
CN106777829A (en) A kind of optimization method and computer-readable storage medium of integrated circuit mask design
US8261214B2 (en) Pattern layout creation method, program product, and semiconductor device manufacturing method
Wood et al. Insertion strategy for EUV lithography
KR20120100297A (en) Flare correction method and method for fabricating euv(extreme ultra violet) mask
TW201628112A (en) Method for improving the process of semiconductor components by combining wafer entity measurement results and digital analog data
CN113050363A (en) Method for establishing optical proximity correction model and optical proximity correction method
TW201707060A (en) Apparatus and method for creating a physical non-reproducible function by modifying a photomask of a semiconductor process
CN105824187B (en) Optical proximity correction method
TWI222145B (en) Evaluation method
CN111386500A (en) Method for identifying masks for microlithography
CN109188857B (en) Layout splitting method and splitting system
JP2003255509A (en) Method of manufacturing photomask and method of manufacturing semiconductor device using the photomask
CN106599336A (en) Semiconductor process simulation device and simulation method thereof
KR20080001438A (en) How to Build a Mask Layout
US20060010409A1 (en) Semiconductor integrated circuit design method, design support system for the same, and delay library
TW201020830A (en) Method to determine process window
TWI762216B (en) Method for testing semiconductor pattern
JP2009251500A (en) Method of verifying pattern, method of forming pattern, method of manufacturing semiconductor device, and program
CN102402137B (en) Photoetching method of pores
JP2010122438A (en) Method, program and device for verifying lithographic simulation model
KR100944332B1 (en) Method of manufacturing mask of semiconductor device and method of manufacturing semiconductor device
JP2007156027A (en) LSI mask data correction method and semiconductor manufacturing apparatus