TW201028702A - A parallel test switching device, a parallel test system and a parallel test method - Google Patents

Abstract

The present invention relates to a parallel test switching device, a parallel test system and a parallel test method, and particularly relates to a parallel test switching device, a parallel test system and a parallel test method for an open test system. The present invention provides a simple parallel test switching device to help an open test system to perform parallel test without any complicated pre-compiler. The simple parallel test switching device has a parallel test macro. Therefore, the test cost can be reduced and test efficiency can be improved substantially.

Description

201028702 VI. Description of the Invention: [Technical Field] The present invention provides a parallel test conversion device, a flat test and a parallel test method, in particular, a parallel test conversion and a parallel test method for parallel testing of a test system . , ^ set flat test 忒 [previous technology] system and test system used by the test system, the user can not modify or write it, that is, seal, test system; the other is open To the user. Test the system written in the firmware code, and then use the open test system to test or test the firmware to the semiconductor component.叮 忒 忒 即 即 ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ Test program. Therefore, a closed system using a circular interface is obviously not suitable for use, and the specific gravity of the open test system is increasing. However, most of the test systems of the drop-off type can only provide testing of a single semiconductor component. Only one semiconductor component can be tested in two or two times. Before the semiconductor component is tested, the next semiconductor element is processed. The test, the so-called Serial Test, but puts the simultaneous testing of multiple semiconductor components at the same time, that is, the parallel test (Parallel Test). Therefore, the general use of the open g test 3 201028702 t ί to carry out the # sequence test, but can not be like the closed test two s can (3) multiple semiconductor components caused by the system compared to the closed test system, if forced to the current The open system implementation of the parallel test i plus a pre-compiler (pre-compiler) to deal with the simultaneous data and signal transmission of the parallel test of more than 70? Test process. However, in order to be able to cope with the various test programs written by Ο or to test the firmware code, and test the test process and state, the required pre-compiler is very large. And the burden of maintenance is large. Therefore, the entire open test system is equally 'and complicated and not easy to maintain', so the overall test cost is greatly increased. And, secondly, the open test system of the pre-compiler, when the line test is performed, each semiconductor component is recorded between a semiconductor device pin and a device channel. The correspondence tables of the correspondences are all the same and fixed, so the design of the traces on the test board and the probe card used by the test machine is limited, and thus cannot be The shortest and best data and signal transmission path is obtained for each semiconductor component in the parallel test, resulting in poor signal quality of the open test system. For example, it is flat in an open test system using a pre-compiler. When testing, each test area (site) corresponds to and uses a fixed test channel, for example, the first test area uses the test channel numbered 1-10, and the second test area uses the test channel numbered 11-20. Since each test area uses the same correspondence table, when the pins of the conductor elements in the first test area correspond to the test channels numbered 1-4, respectively, the test area is performed ^ 4 201028702 The pins of the semiconductor components can only be tested according to the test channel of the rhyme J: 2 9^, but cannot be changed according to the design of the traces on the different test boards or the probe cards, and it is impossible to make each test. The semiconductor components in the area correspond to different test channels, and the short and optimal data and signal transmission paths are known.

Therefore, you need a parallel test system, parallel test conversion device and parallel test method to enable the open test system to switch between test mode and g test, and provide test and parallel test in the same test system. 'And without the use of a large and complex front ^ Zeyi', the pins of each semiconductor component in the parallel test can be matched to the optimal test channel, so that the shortest and best data and signal transmission are obtained. The reduction of the cost of the trial and the increase of the test effect. SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel test conversion device that can be applied to various open test systems, and is used as a simple device for switching between test modes such as sequential test and parallel test, and is made open.开放 The open test system in which the user writes the test program can perform the switching between the sequential test and the parallel test by a simple device, and provides the best data and signal transmission path for each semiconductor component in the parallel test. , thereby reducing the cost of testing and increasing the performance of the test. Another object of the present invention is to provide a parallel test system capable of parallel testing of test programs written by users without using a large and complicated pre-compiler and providing parallel testing. The best data and signal transmission path for each semiconductor component in the middle, which reduces the cost of testing and increases test efficiency. 201028702 #—The purpose is to provide a parallel method, which can be changed to ί ϋ ΐ ' 将 将 将 将 将 将 将 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 使用者 对 对 对 对 对 si si si si si si si si si si The best information and signal transmission of a semiconductor component reduces the cost of testing and increases job efficiency. For the purpose of the present invention, the present invention provides a parallel test conversion device, a test execution and end control unit, a parallel test: '#枓, a storage soap element, and a sequential test execution and end control el. In the parallel test execution and end control unit, the parallel test is performed to convert the test process into parallel and the parallel test of the plurality of half (four) components is performed and the start, execution and end of the parallel test are controlled, and the test is performed. The storage unit is used to capture and store the blood 5 obtained after the parallel test, and the subsequent test is used to calculate the data. Secondly, the sequential test execution and end control unit is used to test the parallel process from parallel test to sequential test, and to start, execute and end the sequence test. This parallel test turns into two: it is constructed with simple components, and provides switching between the open test system and the parallel test. In the open test, the test can be performed in both the sequential test and the parallel test. The problem of material and signal transmission generated when parallel testing of a plurality of semiconductor components is simultaneously performed, and the optimal material and signal transmission path of each semiconductor component is provided, thereby reducing the test cost and increasing the test dual energy. According to the above object, the present invention provides a parallel test system, which can perform parallel test, and can perform parallel test, which includes = test control for controlling the flow and operation of semiconductor components, and one for judging A test conversion device for switching between the sequence test and the parallel test, and a test execution _ for performing the test by the test command provided by the test control device 6 201028702 and the mode of the parallel test conversion device. This - flat; ^ ^ by - simple parallel test conversion device, for example - macro refers to the test program written by the user or test the firmware test process while measuring several semiconductor components ·" The best data for a semiconductor component and the mg ^ ' ', the test cost, and the increase of the test performance and the urban transfer path are reduced. According to the above object, the present invention provides a parallel test program for parallel testing by a user. It seems that the user writes the test program, and then:: test, then 'convert this test process into one-to-many' and collect the data measured by the parallel test; after all, test all semiconductor components After the completion, the company will simply step the 'example' φ material and signal transmission path, and reduce the test cost to apply = the effect of the release is to provide a translator, that is, you can replace the huge complex with 5 to 曰7 The pre-coding is converted into parallel test by a 'differential test (4), or by means of a device, such as a macro-instruction step, etc., which replaces the complex and magical and developmental tricks.訧,, now will reduce the cost of testing and increase the test efficiency. " 7 201028702 In addition, the present invention compares another effect of the prior art, two iic devices, parallel test systems and parallel test t ί ' The position and state provide the same as the corresponding it conductor component pin corresponds to the best test channel, thereby providing the best information due to the test carrier or probe card, and reducing the test or probe card Wiring set

[Embodiment] Detailed: The t embodiment is described in detail below. However, except for the line. That is, the present invention may be widely practiced in other embodiments without being limited by the embodiments, and the various elements or structures in the drawings should not be This is a limited cognition, that is, the following description can be used to limit the number of restrictions. The spirit and scope of the present invention is the structure and method in which a plurality of elements or structures coexist. In addition, the various parts of the 'in the specification' are not in full accordance with the size ', and some of the dimensions are exaggerated or simplified compared to other related dimensions to provide a clearer description to enhance the understanding of the present invention. The prior art, which is used in the present invention, is only referred to herein by reference to the accompanying drawings. Referring to FIG. 1A, a simplified schematic diagram of a parallel test system 10 according to an embodiment of the present invention, the parallel test system 10 includes a test control device for controlling the flow and operation of semiconductor component testing, and A parallel test 30 for switching between sequential testing and parallel testing, and a test execution module 40 for performing semiconductor component testing. The test execution device 40 tests the semiconductor components according to the test command and test program provided by the test control device 20 and the test mode provided by the parallel test conversion 8 201028702 device 30. Show), use the two-two test program platform (not in the middle of the test, or: written, but not the use of the helmet ^ 驭疋 from the C programming language t test machine type. Appropriate:: The requirements or on-stage programming conforms to the test procedure written by this test program. Secondly: ί is in the test program level (or test established - in accordance with this test and „ 3 (four) provides financial test (Serial T (10) = i: = r) = test mode And providing the two sets of 30 series by a flat, first map, parallel test conversion device 甘 甘 甘 33 and a sequential test execution and end Ο unit 1. Among them, parallel test execution and end control: then 1 The test control device 20 converts into a parallel test that can simultaneously test the number + and the body 7 according to the test flow established by the user. The parallel test data is released and the mi test is stored and stored in each parallel test. —Semiconductor ί No. Based on the judgment of 5. Sequential test execution and end; i – dark pa is used to convert the test process from parallel test to test sequence test in the same two semiconductor components, and the beginning of the sequential test , execution and end. The 'parallel test conversion package s 30 has a synchronous test flag 35, which is used to set the synchronization test flag for one or more semiconductor components according to the current test state, test flow or test 9 201028702 results, and mark and determine those The semiconductor component is subjected to synchronous testing, that is, marking and determining the semiconductor component to be subjected to the sequential test or the parallel test. Next, the 'parallel test conversion device 30 further has a test channel automatic extension unit 36 for demonstrating the test project in the test flow. The test channel corresponding to all the semiconductor components set with the synchronous test flag is extended for parallel testing, wherein the test channel automatic extension unit 36 includes several different correspondence tables, each of which corresponds to Correspondence between each pin of a semiconductor component and each device channel, and the correspondence relationship recorded in each correspondence table is different, so that each semiconductor component is found according to its position and state. A suitable correspondence table allows each pin to form the most with the corresponding test channel Or the shortest signal transmission path, which can be used in conjunction with the test carrier or the probe card used to reduce the restrictions on the test carrier or the design of the trace on the probe card. The conversion device 3〇 also has a measurement data storage soap 7G 37 for use in parallel testing,

Ϊί ί* Two packs, 3 data access areas (not shown), per-data measurement data and job results. The + conductor read conversion secret time corresponding to the deposit, the test flow established by the parallel test test execution device 40 and the parallel test conversion device 3 in the 201028702 test system 10 are the test control device 2' A part of it is provided in the test control device 20. The foregoing parallel test systems 10 and 10 operate in the following manner: after the test device 20 or 20 is programmed, the test control device 20 or 20 is prepared, and the control device 20 or 20 is Test program or test firmware code to establish a pair of single semiconductor components for testing the measured turbulence f, and transfer it to the parallel test conversion device 3, and the test control device 2 or 2 〇 will directly The test execution device 40 or 疋 executes the test command to the test execution device 4 via the parallel test conversion device. The last name is followed by the parallel test execution in the parallel test conversion device 30. The control unit 32 automatically converts this test flow into a parallel f test, and the synchronous test flag unit 35 sets the synchronous test flag to the mother-semiconductor. The component is either set to the conductor component that needs to be tested in parallel, and is used as a mark for the semiconductor to be tested synchronously. The test execution and end control unit 32 selects and tests those semiconductor components to be tested in parallel by the setting of the synchronization test flag. Then, the test channel automatic extension unit 36 will automatically extend the test process = test items, and each test channel of the half-body component set with the synchronous test flag corresponds to the test items, and each set $ synchronization test The semiconductor components of the flag are corresponding to each different pin, and each pin can be matched with the test carrier or the device to obtain the shortest and best signal transmission path. Therefore, the parallel test system of the present invention 10盥1〇, ΐΓίΐΓί test the routing design on the carrier board or the probe card, or the design of the scale on the Μ 歧 歧 骑 , , , The 201028702 is suitable for a variety of test carrier boards and probe cards, and even flexibly uses each test channel to match the traces on the test carrier board and the probe card, thereby obtaining a transmission path for short test signals, thereby obtaining better signal quality. Then, the test execution device 4 〇 according to the test command provided by the test control device 2 〇 20 ′ and the parallel test conversion device 3 〇 模 模 , , , , , , , , , , 测试 测试 测试 测试 测试 测试 测试 测试 测试 测试 测试 测试 测试Passing a number of semiconductor elements that have a synchronous test flag set to the same as '昧进ϋ Ξ ϊ' and the semiconductor test without the synchronization test flag = 乂7=2 at the same time as or after the parallel test, the measurement data The measurement data of each semiconductor element is stored in the data access area of each of the semiconductor elements corresponding to the 'hidden' p-semi-semiconductor element. i. Calculate the measurement data of the phantom age and the lead component and the test results. For example, if the measurement component of the semiconductor component is tested, or if the test result is determined by the test result, the semiconductor component knows the V. Follow-up testing process or test project. The pieces are - after the test is completed, etc. * If you need to perform a sequential test conversion device 30 5 20' then pass the sequential test command to the flat i 20 or 20, receive the j test and play 5 40 ° in the test control襄After the transfer command, the synchronous test flag unit 7^ re-sets a synchronous test flag, but $12 201028702 sets the synchronous test flag for only one semiconductor component at the same time', that is, the test is completed in one semiconductor component. Previously, the synchronous test flag was not set to another semiconductor component. Therefore, the test actuator 4〇 will only test the same semiconductor component at the same time. Of course, the parallel test systems 10 and 10' of the present invention can also perform the above-described sequential test at the beginning of the test in accordance with the test requirements.

In addition, the parallel test execution and end control unit 32 of the present invention may include a simple parallel measurement macro instruction to control the start, execution, and end of the parallel test, and collect the measurement data and test results of the parallel test. For example: //parallel test start / / user's test program / / get information

MacroParallelTestStart() //User’s Test Item 1

MacroGetTestData_l () //User’s Test Item 2 "user test program

MacroGetTestData_2 () / / Get the data MacroParallelTestEndQ / / Parallel test end Ϊ 6 Γ, δ ^ ItCm 1 ^ User, s Item 2 Write the test program in the different test items side of the example, although there are only two items, one 1 - Increase or decrease the demand for testing. Q is not called a domain, but is W, and can also be used to control the start, execution, and end instructions of the control unit, and the operations of the control unit, for example: and the measurement of the sequential test: 201028702

MacroSerialTestStart〇//Sequential test start //User's Operation //Get the data after the operation MacroSerial TestEnd〇//Sequence test ends Therefore, according to the above embodiment, the parallel test system of the present invention can not only sequence the test program written by the user Testing, but also 'for parallel testing', with a simple parallel test conversion device, a complex compiler that is difficult to develop and maintain, and provides the best data and signal transmission for each semiconductor component in parallel measurement. Path, use ^ to reduce test costs and increase test performance. In addition, the present invention further provides a parallel test conversion device which can be used for various open test systems, and performs switching between sequential test and parallel test, and enables various open test systems to not only perform 2 sequential tests. Parallel testing can be performed to reduce test time and increase test performance. The composition of the parallel test conversion device is as shown in the second figure, which has been described above, and therefore will not be described herein. Secondly, the present invention further provides a parallel test method, which can perform parallel test in an open test system without any magic big

And complex pre-compiler. Referring to the third figure, it is a flow chart of a parallel test method of an embodiment of the present invention. First, after the user writes the second test program or tests the firmware code on the test machine, the test machine will open # execute the test program or test the firmware code (step 300). ^中:^ Test program or test firmware code is written in C programming language, but not limited to it, but can be used in the appropriate programming language according to the requirements of the test program or the type of test machine. Written, and this ancient program contains several test items. 'W 201028702 Then 'the test machine will establish the test flow of the test according to this test type (step move), and this parallel test flow is correct;: j body: the amount of semiconductor components is strictly enforced ^ ', ,, The fruit is fruited (step 308), and then, after each test, the end of the parallel test procedure (step 31). ΡComplete the measurement ^The second method includes a synchronization test flag set to 2 in the i conversion to parallel test flow step ((4) 鹌〇 4), and further includes a synchronous test flag setting step, and set the same test flag to be performed. Synchronously testing the semiconductor components, thereby marking or determining the semiconductor components for the flat test. Furthermore, the conversion of the test flow into the parallel test flow step (step 3〇4) further includes a test channel extension step for extending each test item and corresponding to all semiconductor components set with the synchronous test flag test. The test device (device Carmel), and each semiconductor component set with the synchronous test flag test can perform various test items corresponding to the parallel test. ^ The test channel extension step includes a step of providing a correspondence table, so that the semiconductor components with the synchronous test flag are set according to different, corresponding tables, so that each pin corresponds to one can cooperate with the test carrier or < The traces on the pin card are set to § 10 and the test channel for the shortest and best signal transmission path is obtained. Each correspondence table records the correspondence between each pin of each semiconductor component and each test channel, and provides parallel testing of the shortest and best test signal transmission path for each semiconductor component. Therefore, the parallel test method of the present invention is not limited to 15 201028702 being limited to the test carrier or the trace design on the probe card, and the routing design on the carrier board or the probe card is limited or even flexible; 1 Use the test channels to match the traces on the test carrier and the probe card. The cost of the test signal can be shortened, and the better signal is obtained. In addition, the measurement data of each semiconductor component participating in the parallel test is collected. The step of testing the result (step 3 08) further comprises providing a data storage area step for providing each data storage area corresponding to the synchronous test flag and the semiconductor component, that is, providing each semiconductor for parallel testing. Individual data storage areas for components. Secondly, the measurement data of each semiconductor component collected and parallelly tested and the less steps of the ( (step 308) further comprise a data storage step, and the measurement data and the test result of each semiconductor component are stored to the corresponding data. The parallel test method of the present invention further includes an operation and determination step of calculating and judging the measurement data and the test result of the semiconductor component by the exclusive data storage/area corresponding to each semiconductor component. According to the specifications provided by the test program written by the user, the test state of each/semiconductor component is judged, and it is determined whether each semiconductor component is to be subjected to subsequent testing or test branching, and the parallel test method of the present invention includes A step of resetting the synchronization test flag is performed, and the semiconductor component that needs to be subjected to subsequent testing or test branching is re-synchronized to test the flag setting, and the semiconductor component that needs to be subjected to subsequent testing or test branching is selected. In addition, the parallel test method can control the start, execution, and end of the parallel test by a simple parallel test macro instruction 'and collect the measurement data and test results of the parallel test'. This 16 201028702 +仃The Test Giant # instruction has been described above and, therefore, will not be described here. The line is followed by the job, and then the test is carried out, and the test step is also included - for the sequential measurement - time, only the - Feng ^ test flag setting step ' is used to test the sequential conductor elements. The end of the measurement data of this test, as well as the follow-up test, the description of the sequence test macro instruction has been tested in the previous article ^ = the open test system provided by the invention, parallel g, the scent device, The parallel test system and the flat Si are written by the latter (4) into (4) or the job code or the device or the step, for example, the macro instruction is difficult to replace, and the complex is huge and the development process is difficult, ^ ^ ' Convert the #序 test flow into a parallel test flow. (4) Add the test rate. Section, this publication, and ί mother ^in set the state with a different corresponding board or probe card to provide the most ΐ ΐ 的 、 、 、 : : : : : : 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 洛 ^ ^ ^ ^ ^ Figure 2 is a simple diagram of a parallel test system of the present invention. The single figure is a simple schematic view of another embodiment of the present invention. Ten _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The fourth diagram of the 4th Η 辏 辏 辏 复 为本 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉 泉〇Parallel test conversion device 4〇Test execution device 32 Parallel test execution and end control unit 33 Parallel test data capture storage unit 34 Sequential test execution and end control unit 35 Synchronization test flag unit Ref. Data storage unit: Start the execution of the user-written test 2 Build according to the test program - Test flow step: Step, ΐ Test flow is converted into parallel test flow Step 306 Perform parallel test flow step == = ; = Test data and test result steps 18

Claims (1)

201028702 VII. Patent application scope: 1. A parallel test conversion device for converting between sequential test and parallel test, comprising: a parallel test execution and end control unit for converting the test flow into parallel test Parallel testing of a plurality of semiconductor components, and controlling the start, execution, and end of the parallel test; a parallel test data capture storage unit for capturing and storing the data obtained after the parallel test for subsequent The test process performs calculation and judgment of the data; and a sequential test execution and end control unit for testing the test process from the parallel test to the sequential test, and controlling the start, execution and end of the sequential test. 2. The parallel test conversion device according to claim 1, wherein φ further comprises a synchronous test flag unit for setting a synchronous test flag according to the current test state, test flow or test result, and determining those to be The semiconductor components are tested synchronously. 3. The parallel test conversion device of claim 2, wherein the parallel test execution and end control unit selects for synchronous testing of those semiconductor components by the synchronization test flag. 201028702 4. The parallel test conversion device according to claim 2, wherein the synchronous test flag 7L is subjected to a parallel test or when a sequential test of the semiconductor 7G component is required, depending on the test flow or result. At the same time, the synchronous test flag is set only for the semiconductor component, and the sequential test execution and end control unit controls the execution of the sequential test according to the synchronous test flag. ❿S. For the towel, please refer to the parallel test conversion device mentioned in Item 2, which also includes a test channel automatic extension unit to extend the test items in the test process and corresponding to all the tests with the synchronous test flag. The device channel of the semiconductor component is tested for parallel. 6_ The parallel test conversion device according to claim 5, wherein the test channel automatic extension unit further comprises a plurality of correspondence tables, each of which records a pin of a semiconductor component. Correspondence with each test channel. 7. The parallel test conversion device according to claim 5, further comprising a measurement data storage unit for storing the test result and the measurement data of each semiconductor component after the parallel test. 8. The parallel test conversion device according to claim 7, wherein the 201028702 measurement data further comprises a plurality of data access areas, wherein each data access area corresponds to a semiconductor component for storing The test result of the corresponding semiconductor component is the parallel test conversion device according to claim 8, wherein the parallel test data capture unit is tested by taking in the individual data storage area of each semiconductor component. Data and results, through operations and = = = to determine those semiconductor components need to carry out subsequent tests or test branches, and 10. Parallel test conversion device as described in claim 1, wherein the parallel test execution and The end control unit also contains the following parallel test giant instructions: " m MacroParallelTestStart 〇 / / parallel test start / / User's Test Item 1 / / user's test program ❹ MacroGetTestData a 1 () / / get the data / / User's Test Item 2 MacroGetTestData_2 () / / user's test program / / get the information MacroParallelTestEndQ / / parallel test ends. 11. The parallel test conversion device according to claim 1, wherein the sequential test execution and end control unit further comprises the following test: 2 sets 21 201028702 instructions: MacroS erialTestStart() //Sequential test start // User's Operation //The operation after obtaining the data MacroSerialTestEndQ //The end of the sequential test. 12.-Parallel test system for performing the sequential test and the parallel test, including: • A test control device for controlling the test of the semiconductor component a process and operation; a parallel test conversion device for switching between the sequential test and the parallel test; and - a test execution device for accepting the test command provided by the test and the parallel device Job mode, and perform tests according to the test command and the test mode. Test program or firmware code (c〇de) 13. As described in the patent application scope 12, the parallel system, in which: the material device is more Includes a test program platform for users to write 14. Parallel testing as described in claim 13 The test program platform is a C language test n,,, which is a dynamic code _6) a C language program or 22 201028702 15. The parallel test system as described in claim 12, wherein the parallel test system A test conversion device is interposed between the test control device and the test execution device. 16. The parallel test system of claim 12, wherein the parallel test conversion device and the test control device are separate devices. 17. The parallel test system of claim 12, wherein the parallel test conversion device is disposed in the test control device. 18. The parallel test system of claim 12, wherein the parallel test conversion device provides a test mode comprising a sequential test mode and a parallel test mode. The parallel test system of claim 13, wherein the parallel test conversion device comprises: a parallel test execution and end control unit for using the test program written by the user or the firmware The test flow established by the code is converted into parallel test to perform parallel test on a plurality of semiconductor components, and controls the start, execution and end of the parallel test; a parallel test data capture storage unit for parallel test The obtained data is retrieved and stored for the subsequent test process to perform the calculation and judgment of the data 23 201028702; and a sequential test execution and end control unit for converting the test process from the parallel test to the sequential test for testing And control the start, execution, and end of the sequential test. 20. The parallel test system according to claim 19, further comprising a synchronous test flag unit for setting a synchronous test flag according to the current test state, the test φ process or the test result, and determining the semiconductor to be determined. The components are tested synchronously. 21. The parallel test system of claim 20, wherein the parallel test execution and end control unit selects a synchronization test for those semiconductor components by the synchronization test flag, and notifies the test execution device that the settings are The semiconductor components of the synchronous test flag are tested in parallel. ❿ 22. The parallel test system of claim 20, wherein the synchronous test flag unit performs the parallel test after the parallel test or the sequential test of the semiconductor component, at the same time according to the test process or the result The synchronization test flag is set only for a semiconductor component, and the sequential test execution and termination control unit controls the execution of the sequential test according to the synchronization test flag, and notifies the test execution device to perform the sequential test. 24 201028702 23. Parallel test system as described in claim 20, further comprising a test channel automatic extension unit for extending the test items in the test flow and corresponding to all set synchronization test flags Test the semiconductor device's device channel for parallel testing. 24. The parallel test system of claim 23, wherein the test channel automatic extension unit further comprises a plurality of correspondence tables, each of which corresponds to a pin of a semiconductor component and Correspondence between each test channel. 25. The parallel test system of claim 23, further comprising a measurement data storage unit </ RTI> for storing the test results and measurement data of each semiconductor component after the parallel test. G 26. The parallel test system of claim 25, further comprising a plurality of data access areas, wherein each of the data access areas corresponds to a semiconductor component for storing the corresponding semiconductor component Test results and measurement data. If you apply for the parallel job secrets mentioned in item 26, the flat test data capture unit will determine the test data and results in the individual data storage area of each semiconductor component by using the calculation disk. 25 201028702 It is determined that those semiconductor components need to be tested or tested for branching. 28. The parallel test system of claim 19, wherein the parallel test execution and end control unit further comprises the following parallel test macro instructions: MacroParallelTestStart() //parallel test start //User's Test Item 1 // The user's test program MacroGetTestData_l () / / get the data / / User's Test Item 2 / / user's test program / / get the data &quot; parallel test is over. MacroGetTestData_2() MacroParallelTestEndQ 29. Parallel test system as described in claim 9, wherein the Φ sequential test execution and end control unit further includes the following sequential test macro instructions: MacroSerialTestStart〇//User's Operation MacroSerialTestEndQ //De The sequence test starts//the operation after obtaining the data&quot; the sequential test ends. The 30-parallel lining method can convert the test mode between the financial and the ping (four) test, including: 26 201028702 Start executing a test program; establish a test flow according to the test program; convert the test flow into a pair of multiple semiconductors Parallel testing process for components to perform synchronous testing; performing the parallel testing process; collecting data and test results measured by the parallel testing process; and ending the parallel testing process. 31. The parallel test method described in claim 30, which further includes a step of writing the test program on the test machine. 32. The parallel test method as described in claim 31, wherein the test program is written in C language. ❹ 33. The parallel stripping method according to claim 30, further comprising a synchronization test flag setting step for setting a synchronous test flag to the semiconductor component that needs to be synchronously tested, thereby marking or selecting to perform the flat Tested semiconductor components. 34. The parallel test method of claim 33, wherein the test process further comprises various test items. 27 201028702 35 · As in the parallel test method described in claim 34, Lizhong also includes a test channel extension step for extending the test items and corresponding to all semiconductors set with the synchronous test flag test. The component's test channel is tested in parallel. 36. The parallel test method of claim 35, wherein the 誃 test channel extension step further comprises a correspondence table step for providing a corresponding table corresponding to the semiconductor components of the parallel test. 37. The parallel test method according to claim 36, wherein the one of the correspondence tables records a test channel corresponding to a pin of each of the semiconductor components, and provides the shortest and the best of each of the semiconductor components. The test signal transmission method is parallel test. ❿ 38. The parallel test method according to claim 35, further comprising a data storage area step for providing data storage corresponding to each of the semiconductor elements Area. 39. The parallel test method of claim 38, further comprising a data storage step for storing the measured data and test results of each of the semiconductor components in the corresponding data storage area. 28 201028702 40. The parallel test method as described in claim 39, further comprising an operation and a judgment step for extracting the measurement data and the test result of each of the data storage areas for calculation and judgment, and It is determined whether each of the semiconductor elements is subjected to subsequent testing or test branching. 41. The parallel test method as described in claim 4, further comprising the step of resetting the synchronous test flag, re-synchronizing each of the semiconductor components requiring a subsequent ® test or test branching Test flag setting. 42. The parallel test method as described in claim 4, wherein the parallel test method can be completed by the following parallel test macro instruction: MacroParallelTestStart〇&quot;parallel test start //User's Test Item 1 &quot; The test program Q MacroGetTestDatal 〇 / / get the data / / User's Test Item 2 / / user's test program MacroGetTestData a 2 () / / get the information MacroParallelTestEnd () / / parallel test end. 43. The parallel test method of claim 30, further comprising a sequential test step for performing a sequential test. 29 201028702 44. The parallel test method of claim 43, wherein the sequential test step comprises a single synchronous test flag setting step for setting a synchronization test flag for only one semiconductor component at the same time, and Label or select semiconductor components for sequential testing. 45. The parallel test method of claim 44, wherein the sequential test step can be completed by the following sequential test macro instruction: 10 MacroSerialTestStart() //Sequential test start //User's Operation //Get data Post-operation MacroSerialTestEndQ //Sequential test ends. 30