201027914 六、發明說明： 【發明所屬之技術領域】 本發明係關於放大器。 【先前技術】 本發明應用於具南阻抗輸出的一類放大器（ainpiifier class) ’該類放大器將電流提供至一外部負載電阻器以設 定放大器輸出電壓。本發明可應用於（但不限於）高增益精 確度及低偏移係重要的精密放大器。本發明在由許多放大 器輸出共用一外部單負載電阻器的多工輸出應用中亦係有 益的’其中對於以多種供應電壓供電給放大器或使一些多 工放大器電力斷開係便利的。 存在一第一組應用，其中對於放大器而言，具有零值等 於接近Vcc/2(供應電壓除以2)之一外部參考電壓Vref的一 雙向輸出係有益的。在此等應用中，外部負載電阻器係繫 於Vref。大部分正輸出接近Vcc，且大部分負輸出接近 G(接地）。存在單向的一第二組應用，其中零輸出精確地 在G處。在此等應用中，負載電阻器係繫於G，且大部分 正輪出接近Vcc。此二組應用在放大器輸出結構上設置不 同的需求，且該等需求在單型、單片放大器IC中通常係不 可能的（將在後文中描述）。 在精密應用中具有一外部負載電阻器的一個動機係為移 除歸因於介於放大器與感測該放大器輸出之裝置間的較小 接地偏移而否則可能引入的誤差。在此等應用之多者中， 在二個1C之間可有一大距離且正接地偏移及負接地偏移明 143694.doc 201027914 顯與系統之誤差預篡右關 預算有關。在此等應用中，當使用G作為 參考電壓時，輸出必需能夠低於本端ic接地。 另—組問題（尤其就具有單向輸出的放大器）為正在接近 ， 纟輸出的同時維持但定的增益且達成一絕對零輸出，此需 — 要能够完全關閉正流至外部負載電阻器的電流。 具有-外部負載電阻器的一個額外動機係多個放大器可 。。夕m用-單負載電阻器，在該多工組態中啟用 ❿ 單個放大器’同時停用所有其他放大器。此在由一單個 類比轉數位轉換器（ADC)讀取許多放大器之輸出的一應用 中係有益的。在此情形中的一問題係，在多工系統中的所 • #放大器必須始終保持受相同供應電壓供電。若一單個放 . A器被斷開電力（電力供應終端係低於正常系統供應電廢 或接近G)，則將透過該電力斷開的放大器之輸出驅動器之 本體-極體使多工輸出短路。雖然在業界通信及介面產品 中防此問題的保護係普遍的，然而在精密放大器中係不普 ❹ 遍的。Thurber，Jr.讓與給本發明之受讓人的美國專利第 5,414,314號涵蓋一高侧（1^〇8)連接及一低侧（NM〇s)連 接，其之二者提供用於使一輸出隔離於供應且隔離於接地 的構件。Boucher讓與給本發明之受讓人的美國專利第 5,963,067號提供用於主動整流之構件並使用Thurber Jr所 涵蓋之連接。 【發明内容】 本發明係關於一種用於自一正軌道及一放大器地軌道操 作的放大器輸出級’該放大器輸出級包括：第一上拉電路 143694.doc 201027914 及第二下拉電路，該第一上拉電路及該第二下拉電路耦接 至一輸出級輸出；該第一上拉電路經由第三電路而耦接至 該正軌道，及該第二下拉電路經由第四電路而耦接至該放 大器接地軌道；該第四電路經組態用以當該輸出級輸出從 相對於該放大器接地軌道的一正電壓接近該放大器接地執 道的一電壓時，逐漸關閉至該下拉電路的電流，且在該輸 出級輸出到達該放大器接地軌道的一電壓之前，關閉至該 下拉電路的電流；包含放大作用的該第三電路被耦接至該 下拉電路以回應於到該輸出級的一輸入而逐漸地關閉至該 上拉電路之電流’用以隨著該輸出級輸出正在接近接地參 考電壓時，維持於越來越低的輸出級輸出處的輸出級增 益’並回應於到該輸出級的一對應輸入而關閉至該上拉電 路之電流，以容許一輸出級輸出電壓等於比該放大器接地 軌道更小的一接地參考之電壓；其中該放大器具有一自組 態輸出級，該自組態輸出級可搭配一中軌或可低於該放大 器接地軌道的接地參考而操作。 【實施方式】 圖1展示從差動輸入INP-INN至差動輸出VOUT-VREF的 一完整先前技術放大器系統。未含於積體電路（1C)中的圖1 之放大器系統之僅部分係外部電阻器RLOAD。在外部設 定電壓VREF。此ic係一跨導放大器。輸出為電流「][」， 其與差動輸入INP-INN成比例。當電流「I」流經Rl〇aD 時該電流建立差動電壓VOUT-REF。 圖2a係包括本發明之全部態樣的一例示性ab類放大器 143694.doc 201027914 輸出結構的原理圖。此輸出結構代表在圖1之GM3中之輸 出級。 以下討論將關於圖2a且將頻繁引用放大器輸出作為輸出 >級°如先前所述，電壓VREF#_外部設定電壓。該電壓 :REF通常係一標稱電壓(即介於供應電壓與接地之間的中 段（中軌））或在接地處。當VREF為中軌時，相對於vref， 輸出（VWT)可為正或負，且稱此為—雙向操作。”咖 瘳 A接地時’僅正輸出係可能的且稱此為單向操作。電阻器 RLOA^D係在IC之外部以藉由消除歸因於接地偏移的誤差 而獲得充分的精密性；並容許靈活獲得雙向操作及單向操 作二者。 ’、 料論的輸出級有時稱為—軌道至軌道㈣_t()_rail)輸出 本發明之應用一般可將輸出級組態為高阻抗疊接式 電流鏡輸 iii (eaSe〇de-eurrent mirrGr Gutput)、單電晶體反相 增益級或AB類輸出。討論之剩餘部分將主要限於Μ類輸 ❿ *丄因為本發明之實施大部分係無需考量額外電路來維持 精在！ 生的直觀AB類輸出。另外，此討論將僅考量靜態操 作或DC操作。當提及一轉變時，應解釋為靜態情況的一 漸進序列。 在AB類輸出t，將用多種形式的AB類偏壓電路（先前 的圖之一種來控制閘極電壓PGATE及NGATE。除在一 類輸出中輪出驅動II從未完全斷電的事實外，操作Μ 類偏Μ電路的細節可從技術文獻中獲得且將與此討論無 關取而代之，當接合一驅動器時，互補驅動器具有剩餘 143694.doc 201027914 的一小偏壓電流。電容器CM1及電容器CM2稱為Miller電 容器，且雖然與本發明無關，對於一 AB類電路中的穩定 性，通常需要該等電容器。此類行為之全部係充分記述在 文獻中。 在正常操作期間（非極端情況），PMOS-DRIVER_2及 NMOS-DRIVER—2將為全開，同時閘極電壓PGMOD在 G_AMP處且輔助閘極電壓NGMOD在V—AMP處》為獲得跨 RLOAD的一正電壓，使閘極電壓PGATE低於PMOS臨限值 以開啟PMOS_DRIVER_l。在此時，NGATE約保持在 NMOS的臨限值處，且NMOS—DRIVER_1維持在偏壓電流 位準。為獲得跨RLOAD的一負電壓，使閘極電壓NGATE 高於NMOS臨限值以開啟NMOS_DRIVER_l。在此時， PGATE約保持在PMOS臨限值處，且PMOS_DRIVER_l維持 在偏壓電流位準。 在圖 2a 中，展示 PMOS_DRIVER_l、PMOS_DRIVER_2、 NMOS_DRIVER—1、NMOS一DRIVER_2 二極體對。此等二極體 對係存在於所有MOS裝置中的寄生本體二極體，且此等二 極體對在所有MOS裝置的源極與本體、汲極與本體之間隱 蔽性地連接。僅在輔助此討論時才將此等二極體對展示在 圖式之特定裝置中。當有足夠的正向電壓偏壓（通常大於 3 00 mV)時，該等二極體對指入正電流的方向。在具有正 向偏壓的情況下，電流從P型材料流至N型材料。在一 PMOS裝置中，源極及汲極係P型且本體係N型。相反，對 於一NMOS裝置，源極及汲極係N型，且本體係P型。圖2a 143694.doc 201027914 明確展示各MOS本體之連接，此將有利於後續討論。 當VREF等於G_AMP±l〇〇mV時，獲得一零輸出 此討論將藉由參考放大器尋求之輸出電壓而避免該放大 器輸入偏移的問題，考慮放大器增益及輸入偏移並假定該 放大器輸入適於獲得該輸出。運用低輸入偏移電壓（小於 100 μν)並組合高增益（大於5〇 v/V)，吾人所關注之獲得極 低輸出電壓在精密系統中係可行的。 再次’ VREF為參考電壓，其配合VOUT有差別地使用以 獲得該系統的輸出。VREF精確等於G_AMP的操作情況係 從VREF大於G—AMP至VREF小於G—AMP之連續轉變的一 單一情況。為此原因，此討論將首先包含VREF大於 G_AMP的情況，接著討論VREF小於G_AMP的情況。 圖3展示一典型的軌道至軌道輸出級，圖中僅展示對此 討論為基本的組件。第一操作情況係VREF大於G_AMP的 情況。假定VREF為高於G_AMP達100 mV。當所要差動輸 φ 出VOUT-VREF極小（例如，±10 mV或更小）或為零時，放 大器可保持線性及適當的PGATE及NGATE相位控制，因為 在保持比G—AMP更高之一電壓的同時，VFB及VOUT可在 VREF處上下擺動，此導致一正輸出或一負輸出。在此操 作情況中，PM0S驅動器及NMOS驅動器二者使正常偏壓 電流通過，且另外，可上調該等驅動器之一者而下調另一 者以得到適當的輸出電流，以獲得所要的跨外部電阻器 RLOAD的輸出差動電壓。 第二操作情況係VREF小於G_AMP的情況。在此情況 143694.doc 201027914 中，假定VREF低於G_AMP達100 mV。因為輸出級無法拉 低VFB低於G_AMP，所以當所要的差動輸出VOUT-VREF 極小（例如，±10 mV或更小）或為零時，放大器將不保持線 性。當需要VFB低於G_AMP以獲得正確輸出時，NMOS驅 動器將變成反相，即當放大器欲減少差動輸出時，其將增 加閘極驅動NGATE的電壓。此將更難以開啟NMOS驅動 器，將VFB及VOUT拉至G_AMP(其為錯誤方向），最終以 最大強度開啟該NMOS驅動器，同時輸出處於飽和，且在 該輸出處有一明顯電壓誤差。 在上述情況中，必需防止電流流過NMOS_DRIVER_l以 防止此種飽和情況及所得的誤差。此係圖2a中驅動閘極電 壓NGMOD之放大器A1的用途。在以上實例中，可設定高 於G_AMP的一任意電壓臨限值（假設150 mV)，以使當 VOUT下降低於該臨限值時，NMOS—DRIVER—2關閉。在 圖2a中，VOUT—REF係該臨限值電壓。A1係一線性放大 器，而非一比較器，使得NMOS驅動器被慢慢地而非突然 地關閉。電容器CM4稱為Miller電容器，且雖然其與此討 論無關，但是為穩定性，通常需要該電容器。201027914 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an amplifier. [Prior Art] The present invention is applied to an ainpiifier class having a south impedance output. This type of amplifier supplies current to an external load resistor to set an amplifier output voltage. The present invention is applicable to, but not limited to, precision amplifiers where high gain accuracy and low offset are important. The present invention is also advantageous in multiplex output applications where a plurality of amplifier outputs share an external single load resistor, where it is convenient for powering the amplifier with multiple supply voltages or for some power amplifiers to be disconnected. There is a first set of applications in which a bidirectional output having an external reference voltage Vref that is zero equal to one of Vcc/2 (supply voltage divided by 2) is beneficial for the amplifier. In these applications, the external load resistor is tied to Vref. Most of the positive output is close to Vcc and most of the negative output is close to G (ground). There is a second set of applications that are unidirectional, where the zero output is exactly at G. In these applications, the load resistor is tied to G and most of the positive turns are close to Vcc. These two sets of applications set different requirements on the amplifier output structure, and such requirements are generally not possible in single-mode, monolithic amplifier ICs (described later). One motivation for having an external load resistor in precision applications is to remove errors that may otherwise be introduced due to the small ground offset between the amplifier and the device sensing the output of the amplifier. In many of these applications, there is a large distance between the two 1Cs and the positive ground offset and negative ground offset. 143694.doc 201027914 The system error is related to the budget. In these applications, when G is used as the reference voltage, the output must be lower than the local ic ground. Another set of problems (especially for amplifiers with unidirectional outputs) is approaching, 纟 output while maintaining a fixed gain and achieving an absolute zero output, which is required - to be able to completely shut down the current flowing to the external load resistor . An additional motivation with an external load resistor is available for multiple amplifiers. . With a single-load resistor, enable 单个 a single amplifier' in this multiplex configuration while deactivating all other amplifiers. This is beneficial in an application where the output of many amplifiers is read by a single analog-to-digital converter (ADC). One problem in this situation is that the # amps in a multiplexed system must always be powered by the same supply voltage. If a single amplifier is disconnected from the power supply (the power supply terminal is lower than the normal system supply or close to G), the multiplex output is shorted by the body-pole of the output driver of the amplifier that is disconnected through the power. . Although the protection against this problem is common in industry communication and interface products, it is not a good choice in precision amplifiers. U.S. Patent No. 5,414,314 to the assignee of the present disclosure, which is incorporated herein by reference in its entirety, in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all each The output is isolated from the component that is supplied and isolated from ground. U.S. Patent No. 5,963,067 to the assignee of U.S. Pat. SUMMARY OF THE INVENTION The present invention is directed to an amplifier output stage for operation from a positive track and an amplifier ground track. The amplifier output stage includes: a first pull-up circuit 143694.doc 201027914 and a second pull-down circuit, the first The pull-up circuit and the second pull-down circuit are coupled to an output stage output; the first pull-up circuit is coupled to the positive track via a third circuit, and the second pull-down circuit is coupled to the fourth pull-down circuit via the fourth circuit An amplifier ground track; the fourth circuit configured to gradually turn off current to the pull-down circuit when the output stage output approaches a voltage from the amplifier ground path relative to a positive voltage of the amplifier ground track, and Closing the current to the pull-down circuit before the output stage outputs a voltage to the amplifier ground track; the third circuit including the amplification is coupled to the pull-down circuit in response to an input to the output stage The ground current to the pull-up circuit is used to maintain a lower and lower output stage as the output stage output is approaching the ground reference voltage. The output stage gain of the source's and the current to the pull-up circuit is turned off in response to a corresponding input to the output stage to allow an output stage output voltage to be equal to a ground reference voltage that is less than the amplifier ground track; The amplifier has a self-configuring output stage that can be operated with a neutral rail or a ground reference that can be below the ground rail of the amplifier. [Embodiment] Figure 1 shows a complete prior art amplifier system from a differential input INP-INN to a differential output VOUT-VREF. The only part of the amplifier system of Figure 1 that is not included in the integrated circuit (1C) is the external resistor RLOAD. Set the voltage VREF externally. This ic is a transconductance amplifier. The output is current "][", which is proportional to the differential input INP-INN. This current establishes the differential voltage VOUT-REF when current "I" flows through R1〇aD. Figure 2a is a schematic diagram of an exemplary ab-type amplifier including all aspects of the present invention 143694.doc 201027914 output structure. This output structure represents the output stage in GM3 of Figure 1. The following discussion will be related to Figure 2a and will frequently reference the amplifier output as an output > stage ° as previously described, voltage VREF #_ external set voltage. This voltage: REF is usually a nominal voltage (ie, the middle section (middle rail) between the supply voltage and ground) or at ground. When VREF is the middle rail, the output (VWT) can be positive or negative relative to vref, and is referred to as - bidirectional operation. "Curry A is grounded" only positive output is possible and is referred to as unidirectional operation. Resistor RLOA^D is external to the IC to achieve sufficient precision by eliminating errors due to ground offset; It also allows flexible access to both bidirectional and unidirectional operations. ', the output stage of the material theory is sometimes called - orbit to track (four) _t () _ rail) output The application of the invention can generally configure the output stage as a high impedance splicing Current mirror output iii (eaSe〇de-eurrent mirrGr Gutput), single crystal inverting gain stage or class AB output. The remainder of the discussion will be mainly limited to Μ type ❿ *丄 because most of the implementation of the present invention is not considered Additional circuitry to maintain the precision! Raw intuitive Class AB output. In addition, this discussion will only consider static operations or DC operations. When referring to a transition, it should be interpreted as a progressive sequence of static conditions. A variety of Type AB bias circuits (one of the previous figures will be used to control the gate voltages PGATE and NGATE. Except for the fact that the drive II is never completely powered down in one type of output, the operation of the Μ type bias circuit Details can be learned from Nothing is obtained in the literature and will be irrelevant to this discussion. When a driver is bonded, the complementary driver has a small bias current remaining 143694.doc 201027914. Capacitor CM1 and capacitor CM2 are referred to as Miller capacitors, and although not relevant to the present invention, These capacitors are usually required for stability in a Class AB circuit. All of these behaviors are well documented in the literature. During normal operation (non-extreme), PMOS-DRIVER_2 and NMOS-DRIVER-2 will be fully open. At the same time, the gate voltage PGMOD is at G_AMP and the auxiliary gate voltage NGMOD is at V-AMP" to obtain a positive voltage across RLOAD, so that the gate voltage PGATE is lower than the PMOS threshold to turn on PMOS_DRIVER_l. At this time, NGATE is about Keep at the threshold of the NMOS, and NMOS-DRIVER_1 is maintained at the bias current level. To obtain a negative voltage across RLOAD, the gate voltage NGATE is higher than the NMOS threshold to turn on NMOS_DRIVER_l. At this time, PGATE It remains at the PMOS threshold and PMOS_DRIVER_l is maintained at the bias current level. In Figure 2a, PMOS_DRIVER_l, PMOS_DRIVER_2, NMOS_DRIVER-1 are shown. NMOS-DRIVER_2 diode pair. These diode pairs are parasitic body diodes present in all MOS devices, and these diode pairs are in the source and body, the drain and the body of all MOS devices. Concealed connections are made. These diode pairs are only shown in the particular device of the diagram when assisted in this discussion. When there is sufficient forward voltage bias (usually greater than 300 mV), the pair of diodes are pointing in the direction of the positive current. In the case of a forward bias, current flows from the P-type material to the N-type material. In a PMOS device, the source and drain are P-type and the present system is N-type. In contrast, for an NMOS device, the source and drain are N-type, and the system is P-type. Figure 2a 143694.doc 201027914 clearly shows the connections of the various MOS bodies, which will facilitate subsequent discussion. When VREF is equal to G_AMP±l〇〇mV, a zero output is obtained. This discussion will avoid the input offset of the amplifier by the output voltage sought by the reference amplifier, taking into account the amplifier gain and input offset and assuming that the amplifier input is suitable. Get the output. Using a low input offset voltage (less than 100 μν) combined with a high gain (greater than 5 〇 v/V), the very low output voltage that we are interested in is very viable in precision systems. Again 'VREF is the reference voltage, which is used differentially with VOUT to obtain the output of the system. The operation of VREF exactly equal to G_AMP is a single case from a continuous transition in which VREF is greater than G-AMP to VREF less than G-AMP. For this reason, this discussion will first include the case where VREF is greater than G_AMP, and then discuss the case where VREF is less than G_AMP. Figure 3 shows a typical track-to-rail output stage, only the components discussed in this figure are shown. The first operating condition is when VREF is greater than G_AMP. Assume that VREF is higher than G_AMP by 100 mV. When the desired differential output φ out of VOUT-VREF is extremely small (for example, ±10 mV or less) or zero, the amplifier can maintain linearity and proper PGATE and NGATE phase control because it remains one of the higher than G-AMP. At the same time as the voltage, VFB and VOUT can swing up and down at VREF, which results in a positive output or a negative output. In this operation, both the PMOS driver and the NMOS driver pass the normal bias current, and in addition, one of the drivers can be up-regulated and the other can be down-regulated to obtain the appropriate output current to achieve the desired cross-resistance The output differential voltage of RLOAD. The second operational situation is when VREF is less than G_AMP. In this case 143694.doc 201027914, it is assumed that VREF is lower than G_AMP by 100 mV. Because the output stage cannot pull VFB below G_AMP, the amplifier will not remain linear when the desired differential output, VOUT-VREF, is extremely small (for example, ±10 mV or less) or zero. When VFB is required to be lower than G_AMP to obtain the correct output, the NMOS driver will become inverting, that is, when the amplifier wants to reduce the differential output, it will increase the voltage of the gate drive NGATE. This makes it more difficult to turn on the NMOS driver, pull VFB and VOUT to G_AMP (which is the wrong direction), and finally turn on the NMOS driver with maximum intensity while the output is saturated and there is a significant voltage error at that output. In the above case, it is necessary to prevent current from flowing through NMOS_DRIVER_1 to prevent such saturation and the resulting error. This is the use of amplifier A1 that drives gate voltage NGMOD in Figure 2a. In the above example, an arbitrary voltage threshold (assuming 150 mV) above G_AMP can be set so that NMOS-DRIVER-2 turns off when VOUT falls below the threshold. In Figure 2a, VOUT-REF is the threshold voltage. A1 is a linear amplifier instead of a comparator, causing the NMOS driver to be turned off slowly rather than abruptly. Capacitor CM4 is called a Miller capacitor, and although it is not relevant to this discussion, it is often required for stability.
考慮乂1^卩在G_AMP 土 100 mV範圍内的情況。當VOUT 充分高於VOUT_REF時，閘極電壓NGMOD在V_AMP且非 常難以開啟NMOS—DRIVER—2，同時串聯電阻極低。 NGATE係在NMOS臨限值，且NMOS_DRIVER_l僅傳導AB 類偏壓電流。隨著放大器差動輸出VOUT-VREF朝零降 低，VOUT最終遞減直達電壓VOUT_REF。此刻，NGMOD 143694.doc -10· 201027914 從電壓V_AMP被拉至NMOS臨限值電壓，其以線性方式逐 漸地關閉 NMOS_DRIVER_2。當關閉 NMOS_DRIVER_2 時，亦關閉正常流入NMOS_DRIVER_l中的偏壓電流。當 此發生時，電流流動係從PMOS驅動器通過電阻器RGAIN 及RLOAD進入VREF。放大器將此偵測為VOUT中之一微 正擾動，且憑藉透過圖1之GM2的反饋，藉由充分提高 PGATE以相同量地減少PMOS駆動器中之電流而補償該放 大器。雖然閘極電壓NGATE維持偏壓電流通過該等NMOS 驅動器，然而在此全部過程中，閘極電壓NGATE實質上保 持不變。此係因為放大器無指示將NMOS驅動器關閉的資 訊。 在以上若干段落之討論中，圖3係用於展示第一操作情 況（VREF高於G_AMP)非為典型軌道至軌道輸出級的難 點，而第二操作情況（VREF低於G_AMP)導致相位反轉並 且是一問題，所以此討論之其餘内容將參閱圖2a而考量 VREF低於G_AMP，並論證本發明如何解決相位反轉問 題。因此，現有之情勢為VREF低於G—AMP達100 mV、 VOUT 低於 VOUT REF、NGMOD 低（大體上在 G_AMP)、 NMOS_DRIVER_2關閉、NGATE在NMOS臨限值電壓及 NMOS_DRIVER_l開啟但無電流通過。隨著要求差動輸出 降低，VOUT將進一步降低，且VFB及VOUT將變得低於 G_AMP。VOUT降低係由於電流路徑通過外部電阻器 RLOAD，且因為PMOS驅動器供應越來越少的電流。在 NMOS_DRIVER_l開啟的情况下，在節點PWELL處的電壓 143694.doc 201027914 將跟隨VFB而低於G_AMP，但因為NMOS_DRIVER—2係關 閉的，將無電流流動且PWELL容易跟隨VFB。NGMOD係 ，但應值得重視的是隨著PWELL持續跟隨VFB而 低於G_AMP，因為NMOS_DRIVER_2之閘極係在G_AMP且 源極被拉低至低於G_AMP，所以閘極源極電壓正在遞增’ 然而仍剩餘許多次臨限值（Sub-threshold)。由於在電流位 準成為一問題之前，閘極源極電壓需要超過500 mV’ 100 mV之接地彈跳目標有大體上裕度。注意到由於本體二極 體之方向，PWELL可持續低於G_AMP真電流將不在 NMOS_DRIVER_2周圍流動。提供封鎖的二極體係在 NMOS_DRIVER_2上之較低的二極體，其指向G-AMP。總 而言之，無電流流經NMOS驅動器且此系疵僅使用PGATE 來控制 VOUT-VREF。 無需一主動下拉裝置而獲得一零輸出 獲得極少量（次毫伏）或零輸出係無需一彡動不拉裝置的 一接地參考放大器之一極端情況。在此情況中’不能以線 性方式完全關閉典型軌道至軌道接地參考輸出驅動器（如 圖4中所繪示）。控制PGATE的電路變得飽和且增益迅速降 低。此係在典型AB類輸出及高阻抗疊接電流鏡構造中的 情形，因為在各情形中，輸出試圖提供具棰少量電流的鏡 像版本。甚至當電流基本上變到零且裝置氐配實質上降級 時，控制裝置仍處於一逐漸較低臨限值情况而決不會元全 關閉，且雖然輸出驅動器設法將此種情況成鏡像’然而增 益基本上為零，回應時間極長且洩漏佔優勢。單電晶體反 143694.doc -12· 201027914 轉增益級構造能夠避免此問題。此問題係PMOS驅動器進 入PMOS驅動器幾乎關閉但持續洩漏少量電流的弱反轉情 況。在此情沉中，由於輸出級中缺少增益，放大器之有效 增益降低至不再回應於輸出誤差的點。 因為漏電流不能被控制，且其漸漸佔優勢，放大器增益 變成零且輸出電流及由此之輸出電壓不再變成零。此情況 係極端過程且依溫度而定，即漏電流之量值將依批次之不 同而變化，且將總是隨著溫度增加而明顯增加。 圖2a之輸出級使用附加之放大器A2及參考電壓 NGATE—REF以校正此問題。對應於在NMOS_DRIVER_l中 之最高有用操作電流情況，NGATE_REF係高於NGATE之 正常操作電壓的一任意電壓，但其亦便利性地低於 V—AMP。放大器A2之正常狀態係隨著輸入NGATE低於 NGATE—REF，輸出PGMOD係在G—AMP。此引起極難以開 啟PMOS_DRIVER_2且提供及小的串聯電阻。類似電容器 CM4，電容器CM3係一 Miller電容器，且通常為了穩定 性，而需要該電容器。為簡短總結該電路之較低部分的狀 態，VOUT係低於VOUT—REF，因此閘極驅動NGMOD係偏 低的且NMOS_DRIVER_2係斷開的。在進入相對於上述 PGATE之控制的飽和情況之前，閘極驅動PGATE仍在接近 NMOS臨限值的一電壓位準。NMOS_DRIVER_2係關閉 的，因此NMOS驅動器不使電流通過。當該系統試圖得到 更低輸出電流及更低輸出電壓時，其試圖拉高閘驅動 PGATE高於PMOS臨限值，但當PMOS_DRIVER_H4始進入 143694.doc 13 201027914 弱反轉時控制PGATE之電路開始飽和且損失增益。為作補 償，該系統將促使NGATE開始上升以更難以開啟 NMOS_DRIVER_l，但因為 NMOS_DRIVER_2係斷開的， 無電流流入任一驅動器。該放大器之回應係進一步增加 NGATE，但是仍無電流流動，但當NGATE上升至高於由 NGATE_REF設定的臨限電壓時，閘極驅動PGMOD將開始 從G—AMP跨過PMOS_DRIVER_2之PMOS臨限值而上升， 如此將開始使PMOS—DRIVER_2進入弱反轉。此後因為控 制PGATE之電路飽和，PMOS_DRIVER_l保持於弱反轉 中，所以PGATE保持實質上靜態。但是NGATE未飽和且閘 極驅動PGMOD使放大器A2之增益升壓以在低輸出電流情 況期間維持系統的總增益。此增加之增益對在控制次毫伏 輸出的同時維持系統增益並維持該系統的線性係有益的。 PGMOD使相對於PGATE或NGATE的增益增加，但此外其 可在充分高於PMOS臨限電壓擺動，以將PMOS_DRIVER_2 線性驅動至更低位準的弱反轉中，並用以完全關閉 PMOS_DRIVER_2。此給予該系統以極低電流維持系統增 益及調變差動輸出的能力，及不依賴於過程變化或溫度將 PMOS—DRIVER一2完全關閉而獲得一零輸出的能力。 在圖2a之敘述中，其指出放大器A1係一放大器而非一比 較器。實際上放大器A1及放大器A2二者應係放大器而非 比較器。特定言之，當VOUT從正側接近G_AMP時’放大 器A1關閉NMOS_DRIVER_2以防止難以開啟NMOS_DRIVER_2 (其將繼而防止VOUT始終低於G_AMP)。由一比較器提供 143694.doc • 14· 201027914 的放大器A1之一開關信號將得到相同的結果，但在該放大 器中加進一瞬變。另一方面，當回應於該放大器的一輸入 時’放大器A2控制PMOS_DRIVER_l漏電流之流動，且基 本上控制通過輸出級並維持系統之增益及線性的電流，當 該輸入如此指示時完全關閉上拉電路。 當輸出停用且輸出電壓高於供應電壓或供應器被關閉電力 時’獲得高輸出阻抗 φ 有將多級放大器輸出繫於一單負載電阻器而將其作為進 入一單接收電路的多工構件的應用^此類接收電路將通常 為一類比轉數位轉換器（ADC)，但其很可能為其他裝置。 在此一系統中’當所有其他部分停用時啟用一單多工輸出 以驅動負載電阻器。當停用時，此等輸出必需係高阻抗， 即此等輸出既不將電流汲入至該負載電阻器也不提供電流 至該負載電阻器。在某些情形中有可能的是，在多工組態 中的一或多個電路將具有比其他電路更低電壓位準的供應 • 電壓。亦有可能的是，在其他裝置保持被供電且輸出被停 用的同時，該等多工裝置之一或多者將被關閉電力。在所 有此等情況中，當停用或關閉電力時’該等輸出必需能夠 對高於本端供應電壓的輸出電壓維持高阻抗。 MOS裝置在半導體摻雜密度上及形狀上經常係對稱的， 但非總是如此。在正常操作期間，通常將一pM〇s裝置之 源極辨別為更高電壓的P+端子，除非將本體連接至該等端 子之一者，則在此情形中該端子稱為源極）^在當電流從 PMOS汲極流入源極的情況中，稱裝置為反向連接。在一 143694.doc 201027914 非對稱裝置中，通常將汲極辨別為較輕度摻雜端子且電流 仍可在任一方向中流動。PMOS臨限值係當該裝置開始開 啟時閘極源極電壓及閘極本體電壓的函數。雖然稱該臨限 值為閘源電壓，但是事實上，介於該閘極與該端子之間的 電壓係在更高電壓。 當將該PMOS裝置之本體連接至源極時，源極本體二極 體經由該連接而被分流（旁路）。當將汲極拉低至相對於源 極更低的電壓時，汲極本體二極體被反向偏壓且封鎖電流 在MOS裝置周圍流動，容許裝置電流受控於由源極閘極電 壓。 圖5係與圖3相同，惟在輸出驅動器上展現寄生MOS本體 二極體且增添MOS裝置PMOS_l及NMOS_l用以停用輸出 級除外。在 PMOS_DRIVER_l 及 NMOS_DRIVER_l 二者 中，本體連接係繫於裝置之源極。通常在等輸出驅動器處 的電壓偏壓以使寄生二極體封鎖電流流動且MOS裝置能夠 控制電流流經電路。當跨MOS本體二極體之電壓偏壓充分 反向（>300 mV)時，電流將流經該本體二極體並環繞該 MOS裝置。 在圖5中，在正常操作期間，VFB係介於V_AMP與 G_AMP之間，且閘極電壓PGATE及閘極電壓NGATE控制 該等驅動器的電流之流動。為停用驅動器，拉低CS_AMP 並拉高CSB_AMP。如此，PGATE經由PMOS_l而上拉至 V_AMP，且NGATE經由NMOS_l而下拉至G_AMP，藉此 關閉對應的驅動器。只要在此停用情況期間VFB保持介於 143694.doc -16- 201027914 V—AMP與G_AMP之間，將無電流流至該外部負載電阻 器，或無自該外部負載電阻器流動之電流。通常起始流經 一本體二極體之漏電流所需的正向偏壓為約300 mV，由此 若VFB經拉至高於V_AMP且大於300 mV時，漏電流將開 始流入V_AMP中。在更大正向偏壓電壓處’將流動指數性 地更高位準電流。在電力斷開裝置的情況中’若V_AMP待 下降至相對於G_AMP的0 V，顯著電流可流動且VFB將被 箝位在高於G—AMP的600 mV至800 mV。 如同在圖5中，圖2a之CS_AMP被拉低且CSB—AMP被拉 高以停用驅動器。如此，PGATE經由PMOS_l而上拉至 V_AMP，且NGATE經由NMOS_l而下拉至G—AMP，藉此 關閉對應的驅動器。不同的是，在圖2a中增加與 PMOS_DRIVER_l 的 PMOSJDRIVER_2，及增加PMOS_2。 在正常操作期間，當啟用輸出時，PMOS_2之閘極係在 V—AMP，且由此關閉PMOS—2。容許放大器A2之輸出 PGMOD(由CS一AMP啟用）如早先所述擺動以控制 PMOS_DRIVER_2。當由於CS_AMP低而停用驅動器及放 大器A2輸出時，關閉PMOS_2且將PGMOD 、 PMOS—DRIVER 2 之閘極繫於 PAB_POC。PAB_POC 係連接 至 PMOS—DRIVER—1、PMOS_DRIVER_2及 PMOS—2之源極 及本體的共同節點。 圖6係放大器A2之輸出停用電路。當CS_AMP為低時， 停用圖2a之輸出驅動器，且藉由直接NMOS_2及透過反相 器INV1關閉PMOS_3，亦停用放大器A2之輸出。INV1係在 143694.doc •17- 201027914 改變狀態後不汲取電流的一簡單邏輯反相器。INV1係由 PAB—POC供應，其引起PMOS—3之閘極上升至PAB一POC並 維持在使PMOS_3維持關閉狀態的電壓。在放大器A2之輸 出停用的情況下，PGMOD可從G_AMP上至PAB_POC變動 而無需提供或没入電流。 回到圖2a，在PMOS_DRIVER_l關閉且VFB上升高於 V_AMP之300 mV的反向偏壓情況中，VFB加正向偏壓於 PMOS_DRIVER_l之本體二極體且將引起PAB_POC隨其上 升，滯後約300 mV。PAB—POC將上升至高於V—AMP但電 流將不流經PMOS_DRIVER_2，因為其之閘極由PMOS_2連 接至其之源極（更高電壓）。電流亦未繞過PMOS_DRIVER_2， 因為其被從V_AMP指出的上部本體二極體封鎖。在此情況 中，V_AMP可在相對於G_AMP的0 V處，且仍無電流將流 經PMOS驅動器。 總結，在圖2a中，拉低CS_AMP並拉高CSB—AMP以停用 驅動器，並停用A2之輸出，其容許與 PAB—POC之間浮動，且藉由PMOS_2將PGMOD繫於 PAB—POC。此連接導致PMOS_DRIVER_2未被連接、 PAB_POC 在 VFB ±300 mV以内、V_AMP 可在從 G_AMP 至 高於VFB的的任意安全電壓位準處且無電流將流動的一狀 態。因為CS_AMP及CSB_AMP係產生於由V_AMP供應的 系統中，所以其等將被約束為介於V_AMP與G_AMP之 間。在當電力斷開該裝置且V_AMP係在0 V或接近0 V時， CS—AMP及CSB_AMP亦將接近0 V，且輸出驅動器將保持 143694.doc -18- 201027914 於上述之高阻抗狀態，此容許VFB及VOUT上拉至未超過 過程限制的任意安全電壓位準。 如先前所述，可將輸出級組態為ΑΒ類輸出、高阻抗疊 接式電流鏡輸出、單電晶體反轉增益級。使用根據本發明 之高阻抗疊接式電流鏡輸出的一輸出級亦繪示於圖2b中。 在此圖式中，PC AS及NC AS係疊接偏壓電壓，PGATE及 NGATE係輸入信號且PMOD及NMOD係等效於圖2a之 PMOD及NMOD。類似圖2a之AB類輸出級，該疊接式電流 鏡級亦提供一上拉輸出能力及一下拉輸出能力。 在一單電晶體反相增益級中（若輸出級僅需要提供電 流、不需要提供電流及汲入電流，則可使用該單電晶體反 相增益級），由於缺少一 NMOS下拉裝置而將不需要NGATE 信號，但仍然提供NGATE信號用於控制以低輸出電流位準 及接近0 V輸出電壓位準維持系統增益及線性所需的虛擬 交越網路（virtual crossover network)，且當輸入如此指示 時，完全關閉上拉電路。圖2a之停用電路除了應用至圖式 之上拉部外，亦應用至單電晶體反相增益級，以當停用時 維持在輸出處的高阻抗，容許輸出拉升至V_AMP以上，且 容許V_AMP變成0 V。 由此，在具有上拉電路及下拉電路二者的放大器中，當 輸出級輸出從相對於放大器接地軌道的一正電壓接近放大 器接地軌道的一電壓時，至下拉電路的電流被逐漸地關 閉，且在輸出級輸出到達該放大器接地軌道的一電壓時， 關閉至該下拉電路的電流。此防止下拉電路供應電流至一 143694.doc -19- 201027914 輸出負載，其將防止當輸出負載參考小於放大器接地的一 接地電位時，跨輸出負載的電壓到達零。同時，耦接至該 上拉電路的電路回應於至該輸出級之一輸入而逐漸關閉至 上拉電路的電流’且回應於至該輸出級之一對應輸入而關 閉至上拉電路的電流，以容許一輸出級輸出電壓等於一接 地參考（小於放大器接地軌道）。此外，當未選擇放大器 時，一極佳的信號保證將至上拉電路的電流關閉，使得當 未選擇放大器時（即使該放大器電力斷開時）放大器輸出將 為和ifj阻抗 極佳的g號亦關閉下拉電路以容許該放大 _ 斋輸出至少某種程度上更低於放大器接地參考而無需供應 電流至該放大器輸出。此容許直接多工放大器輸出諸如 用於至ADC的輸入。 由此本發明具有多個項樣，可以所要之多種組合或次組 «單獨地實踐該等態樣。雖然本文出於說明性而非限制性 目的揭示並論述了本發明之較佳實施例’然而熟悉此項技 術者應理解多種形式及細節的變化可在不脫離以下請求項 之全廣度所界定的本發明之精神及範疇下在本發明之實施@ 例中進行。 【圖式簡單說明】 . 圖1繪示從差動輸入ΙΝΡ_ΙΝΝ至差動輸出v〇ut_vref的 一完整先前技術放大器系統。 圖2係匕括本發明的全部態樣的一例示性ab類放大器 輸出結構的原理圖。 圖2b繪不使用根據本發明的高阻抗疊接式電流鏡輸出的 143694.doc •20. 201027914 輸出級。 圖3繪示一部分典型軌道至軌道輸出級。 圖4繪示一典型軌道至轨道接地參考的輸出驅動器。 圖5係與圖3相同，惟在輸出驅動器上展現寄生MOS本體 二極體且提供用於停用該輸出驅動器的一構件除外。 圖6繪示用於圖2a之放大器A2的輸出停用電路。 【主要元件符號說明】Consider the case where 乂1^卩 is in the range of 100 mV of G_AMP soil. When VOUT is sufficiently higher than VOUT_REF, the gate voltage NGMOD is at V_AMP and it is very difficult to turn on NMOS-DRIVER-2, while the series resistance is extremely low. NGATE is at the NMOS threshold and NMOS_DRIVER_l only conducts Class AB bias current. As the amplifier's differential output, VOUT-VREF, goes low, VOUT eventually decrements the direct voltage, VOUT_REF. At this moment, NGMOD 143694.doc -10· 201027914 is pulled from the voltage V_AMP to the NMOS threshold voltage, which gradually turns off NMOS_DRIVER_2 in a linear manner. When NMOS_DRIVER_2 is turned off, the bias current flowing into NMOS_DRIVER_1 is also turned off. When this occurs, current flow enters VREF from the PMOS driver through resistors RGAIN and RLOAD. The amplifier detects this as a positive perturbation in VOUT and compensates for the amplifier by substantially increasing PGATE by reducing the current in the PMOS actuator by substantially increasing the PGATE feedback through GM2 of Figure 1. Although the gate voltage NGATE maintains a bias current through the NMOS drivers, the gate voltage NGATE remains substantially unchanged throughout this process. This is because the amplifier has no indication that the NMOS driver is turned off. In the discussion of the above paragraphs, Figure 3 is used to show that the first operating condition (VREF is higher than G_AMP) is not a typical rail-to-track output stage, while the second operating condition (VREF is lower than G_AMP) results in phase reversal. And it is a problem, so the rest of this discussion will refer to Figure 2a and consider VREF below G_AMP and demonstrate how the invention solves the phase reversal problem. Therefore, the current situation is that VREF is lower than G-AMP up to 100 mV, VOUT is lower than VOUT REF, NGMOD is low (generally at G_AMP), NMOS_DRIVER_2 is off, NGATE is on NMOS threshold voltage, and NMOS_DRIVER_l is on but no current is passed. As the differential output is required to decrease, VOUT will decrease further and VFB and VOUT will become lower than G_AMP. The VOUT reduction is due to the current path through the external resistor RLOAD, and because the PMOS driver supplies less and less current. With NMOS_DRIVER_l turned on, the voltage 143694.doc 201027914 at node PWELL will follow VFB and be lower than G_AMP, but since NMOS_DRIVER-2 is off, no current will flow and PWELL will easily follow VFB. NGMOD system, but it should be worth noting that as PWELL continues to follow VFB and is lower than G_AMP, because the gate of NMOS_DRIVER_2 is at G_AMP and the source is pulled low below G_AMP, the gate source voltage is increasing'. There are many sub-thresholds remaining. The ground bounce target with a gate source voltage of more than 500 mV' 100 mV has a general margin before the current level becomes a problem. Note that due to the orientation of the body diode, PWELL can continue to flow below the NMOS_DRIVER_2 for less than the true current of G_AMP. Provides a lower diode of the blocked two-pole system on NMOS_DRIVER_2, which points to the G-AMP. In summary, no current flows through the NMOS driver and this system uses only PGATE to control VOUT-VREF. A zero output is obtained without an active pull-down device. Extremely small (next millivolts) or zero output is an extreme case of a grounded reference amplifier that does not require a swaying device. In this case, the typical track to track ground reference output driver (as shown in Figure 4) cannot be completely turned off in a linear manner. The circuit that controls PGATE becomes saturated and the gain is rapidly reduced. This is the case in a typical Class AB output and high impedance spliced current mirror configuration because in each case the output attempts to provide a mirrored version with a small amount of current. Even when the current substantially changes to zero and the device is substantially degraded, the control device is still in a gradually lower threshold condition and never turns off completely, and although the output driver tries to mirror this situation, however The gain is essentially zero, the response time is extremely long and the leakage dominates. Single transistor anti-143694.doc -12· 201027914 Rotary gain stage construction can avoid this problem. This problem is a weak reversal of the PMOS driver entering the PMOS driver that is almost turned off but continues to leak a small amount of current. In this case, due to the lack of gain in the output stage, the effective gain of the amplifier is reduced to a point that no longer responds to the output error. Because the leakage current cannot be controlled and it gradually dominates, the amplifier gain becomes zero and the output current and thus the output voltage no longer becomes zero. This condition is an extreme process and depends on the temperature, ie the magnitude of the leakage current will vary from batch to batch and will always increase significantly with increasing temperature. The output stage of Figure 2a uses an additional amplifier A2 and a reference voltage NGATE_REF to correct this problem. Corresponding to the highest useful operating current condition in NMOS_DRIVER_1, NGATE_REF is an arbitrary voltage higher than the normal operating voltage of NGATE, but it is also conveniently lower than V-AMP. The normal state of amplifier A2 is that the input NGATE is lower than NGATE-REF, and the output PGMOD is at G-AMP. This makes it extremely difficult to turn on PMOS_DRIVER_2 and provide a small series resistance. Like capacitor CM4, capacitor CM3 is a Miller capacitor and is typically required for stability. To briefly summarize the state of the lower part of the circuit, VOUT is lower than VOUT-REF, so the gate drive NGMOD is low and NMOS_DRIVER_2 is off. The gate drive PGATE is still near a voltage level of the NMOS threshold before entering saturation with respect to the control of PGATE described above. NMOS_DRIVER_2 is off, so the NMOS driver does not pass current. When the system tries to get lower output current and lower output voltage, it tries to pull the gate drive PGATE higher than the PMOS threshold, but when PMOS_DRIVER_H4 starts to enter 143694.doc 13 201027914 weak reversal, the circuit controlling PGATE begins to saturate. And loss gain. To compensate, the system will cause NGATE to start rising to make it more difficult to turn on NMOS_DRIVER_l, but because NMOS_DRIVER_2 is off, no current flows into either driver. The amplifier's response further increases NGATE, but there is still no current flowing, but when NGATE rises above the threshold voltage set by NGATE_REF, the gate drive PGMOD will start rising from G-AMP across the PMOS threshold of PMOS_DRIVER_2. This will start to make PMOS-DRIVER_2 into a weak inversion. Thereafter, since the circuit controlling PGATE is saturated, PMOS_DRIVER_l remains in the weak inversion, so PGATE remains substantially static. However, NGATE is not saturated and the gate drive PGMOD boosts the gain of amplifier A2 to maintain the overall gain of the system during low output current conditions. This increased gain is beneficial for maintaining the system gain while maintaining the linearity of the system while controlling the secondary millivolt output. PGMOD increases the gain relative to PGATE or NGATE, but it can also be driven above the PMOS threshold voltage swing to linearly drive PMOS_DRIVER_2 to a lower level of weak inversion and to completely turn off PMOS_DRIVER_2. This gives the system the ability to maintain system gain and modulate differential output with very low current, and the ability to achieve a zero output without shutting down PMOS-DRIVER-2 completely independent of process variations or temperatures. In the description of Figure 2a, it is indicated that amplifier A1 is an amplifier rather than a comparator. In fact, both amplifier A1 and amplifier A2 should be amplifiers rather than comparators. Specifically, when VOUT approaches G_AMP from the positive side, amplifier A1 turns off NMOS_DRIVER_2 to prevent NMOS_DRIVER_2 from being turned on (which will in turn prevent VOUT from being always below G_AMP). Provided by a comparator 143694.doc • 14· 201027914 A switching signal from amplifier A1 will give the same result, but a transient is added to the amplifier. On the other hand, when responding to an input of the amplifier, 'amplifier A2 controls the flow of PMOS_DRIVER_l leakage current, and basically controls the current through the output stage and maintains the gain and linearity of the system. When the input is so indicated, the pull-up is completely turned off. Circuit. When the output is deactivated and the output voltage is higher than the supply voltage or the supply is turned off, the 'high output impedance φ is obtained. The multi-stage amplifier output is tied to a single load resistor as a multiplexed component into a single receiving circuit. Applications ^ Such receiving circuits will typically be an analog-to-digital converter (ADC), but it is likely to be other devices. In this system, a single multiplex output is enabled to drive the load resistor when all other parts are deactivated. When deactivated, these outputs must be high impedance, ie, these outputs neither sink current into the load resistor nor supply current to the load resistor. In some cases it is possible that one or more circuits in a multiplexed configuration will have a lower voltage level of supply than other circuits. It is also possible that one or more of the multiplex devices will be powered down while other devices remain powered and the output is deactivated. In all such cases, when the power is deactivated or turned off, the outputs must be capable of maintaining a high impedance to the output voltage above the supply voltage of the local terminal. MOS devices are often symmetrical in terms of semiconductor doping density and shape, but this is not always the case. During normal operation, the source of a pM〇s device is typically identified as a higher voltage P+ terminal, unless the body is connected to one of the terminals, in which case the terminal is referred to as the source) In the case where current flows from the PMOS drain to the source, the device is referred to as a reverse connection. In a symmetrical device, the drain is usually identified as a lightly doped terminal and the current can still flow in either direction. The PMOS threshold is a function of the gate source voltage and the gate body voltage when the device begins to turn on. Although the threshold value is referred to as the gate voltage, in reality, the voltage between the gate and the terminal is at a higher voltage. When the body of the PMOS device is connected to the source, the source body diode is shunted (bypassed) via the connection. When the drain is pulled low to a lower voltage relative to the source, the drain body diode is reverse biased and the blocking current flows around the MOS device, allowing the device current to be controlled by the source gate voltage. Figure 5 is the same as Figure 3 except that the parasitic MOS body diode is shown on the output driver and the MOS devices PMOS_1 and NMOS_1 are added to disable the output stage. In both PMOS_DRIVER_l and NMOS_DRIVER_l, the body connection is tied to the source of the device. The voltage bias is typically at the output driver to cause the parasitic diode to block current flow and the MOS device is capable of controlling current flow through the circuit. When the voltage bias across the MOS body diode is sufficiently reversed (> 300 mV), current will flow through the body diode and surround the MOS device. In Figure 5, during normal operation, the VFB is between V_AMP and G_AMP, and the gate voltage PGATE and the gate voltage NGATE control the flow of current to the drivers. To disable the drive, pull CS_AMP low and pull CSB_AMP high. Thus, PGATE is pulled up to V_AMP via PMOS_1, and NGATE is pulled down to G_AMP via NMOS_1, thereby turning off the corresponding driver. As long as VFB remains between 143694.doc -16- 201027914 V-AMP and G_AMP during this deactivation, no current will flow to the external load resistor or there will be no current flowing from the external load resistor. The forward bias required to initially initiate leakage current through a body diode is about 300 mV, whereby if VFB is pulled above V_AMP and greater than 300 mV, leakage current will begin to flow into V_AMP. The flow will exponentially be a higher level current at a larger forward bias voltage. In the case of a power disconnect device, 'if V_AMP is to fall to 0 V relative to G_AMP, significant current can flow and VFB will be clamped at 600 mV to 800 mV above G-AMP. As in Figure 5, CS_AMP of Figure 2a is pulled low and CSB-AMP is pulled high to disable the driver. Thus, PGATE is pulled up to V_AMP via PMOS_1, and NGATE is pulled down to G_AMP via NMOS_1, thereby turning off the corresponding driver. The difference is that PMOSJDRIVER_2 with PMOS_DRIVER_1 is added in Figure 2a, and PMOS_2 is added. During normal operation, when the output is enabled, the gate of PMOS_2 is tied to V-AMP, and thus PMOS-2 is turned off. Allow the output of amplifier A2, PGMOD (enabled by CS-AMP), to swing as described earlier to control PMOS_DRIVER_2. When the driver and amplifier A2 outputs are disabled due to the low CS_AMP, PMOS_2 is turned off and the gates of PGMOD and PMOS-DRIVER 2 are tied to PAB_POC. PAB_POC is connected to the common node of the source and body of PMOS-DRIVER-1, PMOS_DRIVER_2 and PMOS-2. Figure 6 shows the output disable circuit of amplifier A2. When CS_AMP is low, the output driver of Figure 2a is disabled, and PMOS_3 is turned off by direct NMOS_2 and by inverter INV1, and the output of amplifier A2 is also disabled. INV1 is a simple logic inverter that does not draw current after changing state in 143694.doc •17- 201027914. INV1 is supplied by PAB-POC, which causes the gate of PMOS-3 to rise to PAB-POC and maintain the voltage at which PMOS_3 is maintained in the off state. In the event that the output of amplifier A2 is disabled, PGMOD can be varied from G_AMP to PAB_POC without the need to supply or sink current. Returning to Figure 2a, in the reverse bias case where PMOS_DRIVER_l is turned off and VFB rises above 300 mV of V_AMP, VFB is forward biased to the body diode of PMOS_DRIVER_1 and will cause PAB_POC to rise with it, with a hysteresis of approximately 300 mV. . The PAB-POC will rise above V-AMP but the current will not flow through PMOS_DRIVER_2 because its gate is connected by PMOS_2 to its source (higher voltage). The current also does not bypass PMOS_DRIVER_2 because it is blocked by the upper body diode indicated by V_AMP. In this case, V_AMP can be at 0 V relative to G_AMP and no current will flow through the PMOS driver. In summary, in Figure 2a, CS_AMP is pulled low and CSB-AMP is pulled high to disable the driver, and the output of A2 is disabled, allowing for floating between PAB and POC, and PGMOD is tied to PAB-POC by PMOS_2. This connection causes PMOS_DRIVER_2 to be unconnected, PAB_POC to be within VFB ±300 mV, and V_AMP to be at any safe voltage level from G_AMP to above VFB and no current will flow. Since CS_AMP and CSB_AMP are generated in the system supplied by V_AMP, they will be constrained to be between V_AMP and G_AMP. When the power is disconnected and the V_AMP is at 0 V or close to 0 V, CS-AMP and CSB_AMP will also be close to 0 V, and the output driver will remain 143694.doc -18- 201027914 in the high impedance state described above. Allow VFB and VOUT to pull up to any safe voltage level that does not exceed the process limit. As previously described, the output stage can be configured as a ΑΒ-type output, a high-impedance spliced current mirror output, and a single transistor inversion gain stage. An output stage using the high impedance spliced current mirror output in accordance with the present invention is also illustrated in Figure 2b. In this figure, PC AS and NC AS are stacked with bias voltage, PGATE and NGATE are input signals and PMOD and NMOD are equivalent to PMOD and NMOD of Figure 2a. Similar to the Class AB output stage of Figure 2a, the stacked current mirror stage also provides a pull-up output capability and a pull-down output capability. In a single transistor inverting gain stage (if the output stage only needs to supply current, no need to supply current and sink current, the single transistor inverting gain stage can be used), due to the lack of an NMOS pull-down device The NGATE signal is required, but the NGATE signal is still provided to control the virtual crossover network required to maintain system gain and linearity at low output current levels and near 0 V output voltage levels, and when input is so indicated When the pull-up circuit is completely turned off. The disable circuit of Figure 2a is applied to the single transistor inverting gain stage in addition to the pull-up on the pattern to maintain the high impedance at the output when disabled, allowing the output to rise above V_AMP, and Allow V_AMP to become 0 V. Thus, in an amplifier having both a pull-up circuit and a pull-down circuit, when the output stage output approaches a voltage from the amplifier ground track relative to a positive voltage of the amplifier ground track, the current to the pull-down circuit is gradually turned off. And when the output stage outputs a voltage that reaches the ground track of the amplifier, the current to the pull-down circuit is turned off. This prevents the pull-down circuit from supplying current to a 143694.doc -19- 201027914 output load that will prevent the voltage across the output load from reaching zero when the output load reference is less than a ground potential at the amplifier ground. At the same time, the circuit coupled to the pull-up circuit responds to the input to one of the output stages to gradually turn off the current to the pull-up circuit and responds to the current to the pull-up circuit in response to a corresponding input to the output stage to allow An output stage output voltage is equal to a ground reference (less than the amplifier ground track). In addition, when the amplifier is not selected, an excellent signal ensures that the current to the pull-up circuit is turned off, so that when the amplifier is not selected (even when the amplifier is powered off), the amplifier output will be the g-number with the ifj impedance. The pull-down circuit is turned off to allow the amplification_fast output to be at least somewhat lower than the amplifier ground reference without supplying current to the amplifier output. This allows direct multiplexer output such as for input to the ADC. Thus, the invention has a plurality of items that can be practiced in various combinations or subgroups. The present invention has been disclosed and described herein for purposes of illustration and description of the preferred embodiments The spirit and scope of the present invention are carried out in the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a complete prior art amplifier system from a differential input ΙΝΡ_ΙΝΝ to a differential output v〇ut_vref. Fig. 2 is a schematic diagram showing an exemplary output structure of an exemplary ab-type amplifier of all aspects of the present invention. Figure 2b depicts the 143694.doc •20.201027914 output stage without the use of a high impedance spliced current mirror output in accordance with the present invention. Figure 3 depicts a portion of a typical track-to-track output stage. Figure 4 illustrates an exemplary track-to-rail ground reference output driver. Figure 5 is the same as Figure 3 except that a parasitic MOS body diode is shown on the output driver and a component is provided for deactivating the output driver. Figure 6 illustrates the output disable circuit for amplifier A2 of Figure 2a. [Main component symbol description]
A1 放大器 A2 放大器 CM1 Miller電容 1 CM2 Miller 電容 2 CM3 Miller 電容 3 CM4 Miller 電容 4 INV1 反相器 NMOS_ _DRIVER_ 一 1 NMOS一 _DRIVER_ _2 PMOS_ 1 PMOS_ DRIVER_ .1 PMOS_ DRIVER_ 2 PWELL 143694.doc - 21 -A1 amplifier A2 amplifier CM1 Miller capacitor 1 CM2 Miller capacitor 2 CM3 Miller capacitor 3 CM4 Miller capacitor 4 INV1 inverter NMOS_ _DRIVER_ 1 NMOS_ _DRIVER_ _2 PMOS_ 1 PMOS_