TW201013400A - Memory control system, data recovery method and date reading method thereof - Google Patents

Abstract

The present invention discloses a memory control system, data recovery method and date reading method thereof, whose feature is to define a memory as a plurality of virtual disks, use the said virtual disks to form a disk array, and to store data into these virtual disks in array form. When an error correction procedure is proceeded to the data stored in the memory by error correction code (ECC) but fails, data saved in those virtual disks can be used to recover and correct the failed data. Thereby, the correctness of memory data saving is increased by the combined complementary properties between the ECC correction procedure and disk array.

Description

201013400 IX. Description of the Invention: [Technical Field] The present invention relates to a memory controller, and more particularly to a memory control system incorporating a error correction code and a disk array, a data recovery method thereof, and the like Reading method [Prior technology] At present, 'flash memory, flash memory is a very popular portable data storage device. However, since the cells (cdl) in the flash memory are accessed, it may cause a secret cell that affects the side-by-side control, resulting in incorrect data stored in the next wall, causing the wrong bit to occur. -— ^ To ensure the correctness of the information stored in the Flash, in the traditional technique, the 'every-poor page is divided into data error areas and alternate positive: 造m ί code (_ G. (10)峋code) & 'Generate a poor material, fault-tolerant data is stored in the spare area. Apricot reading ginseng = ^ 里! ^Growth, but the negative impact caused by the physical limit is also caused by the misplacement of the element, causing the interference between the electrons to be intensified, making the above-mentioned faults depend on the W machine & The error correction code of the test will confirm the data storage with the fault-tolerant data in the system. _ The data = the progress of the conductor process, the wafer size of the flash memory is continuously reduced and the data is correct. [28/丨1 The number of errors in the number of errors in the rough-cutting code is greater. *·", the more bits read, the more fault-tolerant resources are changed π.. and also need In addition, if the data page exceeds the maximum number of error correction codes used, the number of corrections can not be recovered. Therefore, how to ensure the validity of the age data is more effective. - The problem to be solved. > In addition, the disk array is a common data backup technology, but the disk array thermal method actively detects the error bit, and for the uniform sentence error bit, the disk array The data recovery effect is not good. [Summary of the Invention]

In view of the above-mentioned problems of the prior art, the object of the present invention is to provide a/hidden body control method for its bribe and its resource acquisition method, so as to solve the problem that the error correction error code is also caused by the error in the green body. The problem of the above 4 knowledge techniques cannot be replied to, and the object of the present invention is to provide an integrated control system, a method, and a method for taking the same. , positive code and the complementarity of the disk array, improve the correct memory storage data! = day, purpose, propose a memory control system, for the host control # ° (10), sub-take 'the memory control system contains - Host interface unit, one brother into = 泽泽单凡, - second address translation unit, - memory interface unit, unit and - error correction codec single-core host interface unit is electrically connected to the host as data transmission The '--logical address is mapped to - virtual magnetic area == the virtual magnetic area address of the bit dish. The second trait is mapped to the physical address of the memory. 5 隐 隐 ” ” ” ” 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 2010 The interface is stored as a virtual disk. Error correction is performed on the codec. The stored data is corrected for errors. When the data error is corrected, the disk array ^ is used 7L early. Save the information in response to: Lost information.

According to the purpose of the present day and the month, the method of returning to the body, the method for responding to the data includes the following steps. First, the memory is compared to a plurality of virtual disks ’ and the virtual disks are formed into a disk _, and the data is stored in an array to the virtual disks. Next, the asset error correction code (ECC) stored in the ship is corrected. When the ECC correction procedure fails, the virtual disk age information is used to correct the error and correct the failed data. According to the purpose of the present invention, a dragon reading method is further proposed. The memory-memory system is defined as a plurality of virtual disks, and the virtual disks are formed into a disk_' and the memory_data The data is stored in the array to the virtual disks separately. The data reading method includes the following steps. #—When the host reads the target (4) to the record, it determines whether the target f_ is stored in the virtual disk. If the scale is returned to the virtual reality, it is still unable to respond, using the storage ς f his virtual disk towel rib to reconstruct the target data - redundant data and related information to generate the reconstructed target data, and transmit the reconstruction Target data to the main embodiment [Embodiment] FIG. 1 is a block diagram of the memory control system of the present invention. 201013400 - In the figure, the memory control system 1 is used for a host 19 to control the storage of a memory π. The acquisition includes a host interface unit 11, a first address translation unit 12, and a second address. The translation unit 13, a memory interface unit, a disk array control unit 15, and an error correction codec unit 16. The plurality of physical addresses 181 of the memory 18 are defined as virtual domain addresses 174 of the plurality of virtual disks 171 173 173. Memory 18 can be a non-volatile memory such as a flash memory. The host interface unit 11 is electrically connected to the host 19 as a data transmission interface, and receives an instruction 190 from the host unit 9, such as a read command or a write command. The host interface unit π can be a parallel advanced technology addition (ΡΑΤΑ), an additional peak) interface, a SAS interface, a coffee interface, a C interface, and the like. After the host interface unit 11 receives the instruction 19G, the logical address 191 of the data to be accessed by the instruction 19() is transmitted to the first address translation unit 12, and the logic is transferred from the first address to the unit 12 Address 191 is mapped to a virtual sector address 174. If the instruction is to write private $, the host interface unit 11 transmits the negative material 192 of the instruction 19 to be written to the memory to the error correction codec unit 16 and the disk array_control unit 15, respectively. The error correction codec unit 16 encodes the data 192 to generate an error correction code 161 corresponding to the material 192 and transmits it to the memory interface unit. After receiving the data 192 and the virtual magnetic zone address 174, the magnetic control unit 15 generates a redundant data 151 corresponding to the data 192 according to the m, and transmits it to the memorandum τ. The techniques for generating error correction codes and generating redundant data are well known to those skilled in the art and will not be described here. The first address transfer unit 13 maps the virtual magnetic domain address 174 into a memory 201013400 ^ body, __ control fresh element 15 (four) slimming interface single / MM car, the style will be 192, error correction code 161 and redundancy The data 151 stores two or two tf 171~173' and the memory interface unit 14 is based on the physical address 181 - magnetic: _丨nl writes the action. Where the 'disk array unit 15 is set to

(t!〇^ 〇)^" ' 1 (RAID (RAID 4) disk array 3 (RAID 3) mode, a disk array 4 IS Γ: _ array 5 _ 5) mode or - magnetic object i magnetic ^ When using different modes, the memory 18 will be defined as a different number of virtual = discs ^ redundant data (5) will also be unique, f in the current day _ protection range ^ for example, if the disk array control unit 15 is set to a RAID ! mode, then at least ^ 2 virtual disks need to be defined, and the redundant data is the data of the data 192; if the disk array control unit 15 is set to the -RAID 5 mode, the gate 18 needs to be defined at least 3 virtual disks, and redundant resources. (Parity). If the 190 is a read command, then the command 19〇 wants to read f! 12 and the second address translation unit ι^ = virtual secret 174 and real address 181. The (four) interface unit 根 root entity address 181 reads the data m from the memory 18 and its corresponding error correction code ^, and The error is sent to the error correction codec unit 16. Since some memory, such as the fast eight-hearted hidden body, may have a data error during access, the data is transmitted to the second machine 19刖, the error correction codec unit 16 corrects the data error according to the error correction code 161. If the number of error bits is within the range of the error correction code, the error correction codec unit 16 may correct the data. Then, the correct material 192 is transmitted to the host computer 19 through the host interface unit u. If the number of error bits exceeds the allowable range of the error correction code 161, the error 201013400 indicates that the codec unit 16 outputs a trigger signal to start. Magnetic / early 70 15 use virtual 191 ~ 173 stored information to reply to the error = 192, _ _ _ _ through k host; 早 face 7 〇 11 transmitted to the host 19.

The Φ shirt/1 嘀 address translation unit 12 performs address mapping according to the first mapping table, and the address translation unit 13 performs address mapping according to the second mapping table. 1 = system 1 further includes - storage list S to store the first mapping table and or 'the first mapping table and the second mapping table are stored in the memory 18, w remembrance control system, system 1 start 'first place The address translation unit 12 and the second address translation unit 13 respectively read the first mapping table and the second mapping table from the memory 18. The second address translation unit 13 can have various implementations to implement mapping between the virtual magnetic domain address 174 and the physical address (8) of the hidden body 18. In the case of flash memory, for example, the same or different flash memories. The f-pages of the body wafer can be mapped to the same or different virtual disks. For example, 'map-flash memory is mapped to L virtual disks VDon 'SX, Y represents the γth of the Xth virtual disk Section (sect〇r), χ is an integer to L-1; this flash memory has one block (bl〇ck), each block has ν data pages, Pl, J ' indicates the first The Jth data page of a block, where I is an integer from M_;1, and J is an integer from 〇4 to 4, the mapping method can be as follows:

S χ, γ

Pr

Y + Y- Table 1 indicates that the flash memory has 3 blocks (ie, M=3), and each block has 9 poor pages (ie, n=:9). This flash memory system is defined as 3 One virtual disk VD0~VD2' is l=3. N/L calculates the number of data pages that each block can allocate to each virtual disk. And [G] takes the integer value of G. For example, if 〇^Yg2, and 201013400 -, M==3 ' then [Y/[N/L]H), if, you are Chen]]=1, if • y ~8 then [丫/[^/ 1]]-2, indicating that in each virtual disk, the second to the second extents ^ map the data page of the Gth block' and the third to fifth extents map the data pages of the third block. The 6th to 8th sections map the data pages of the 2nd block.

Xx[N/L] indicates which data page the virtual disk is mapped from. For example, for a virtual disk, Xx[N/L]=〇, from the first data page of each block. Start mapping. For virtual disk 1, Xx[N/L]=3 'from the third data page of each block = start mapping; for virtual disk 2, Χχ[Ν/^= 6. Start mapping from the 6th data page of each block. After confirming the map start value, calculate the map offset (offset) corresponding to each Υ value by Υ—[Υ/_]]χ[Ν/£], so when γ==0, 3, 6, The mapping offset # is 0; when Y=1, 4, and 7, the mapping offset is 1; when m and 8 are, the mapping offset is 2. Taking S0, 2 as an example 'X=0' Y=2, which maps the data page of the third block, the mapping start value is 0' and the mapping offset is 2', so SG, 2 map pQ, 2 is obtained. Taking S24 as an example, Χ=2 ′ γ=4, which maps the data page of the first block, the mapping start value is 6, and the mapping partial shift amount is 1, so that S2,4 maps Ρι,7. As an example, χ=ι, γ=8, which maps the data page of the second block, the mapping start value is 3, and the mapping offset is 2, so the mapping Ρ2, 5 is obtained. γ~表一S〇,〇--- S〇,l S〇,2 S〇,3 So, 4 S〇,5 S〇,6 S〇,7 S〇(8 VD0~~~~| Si, ! Si,2 Sl,3 Si,4 _Sl^ Sl.7 s18 VD1 S2.1 S2.2 S2l3 S2.4 S2,5 ^2,6 S2.7 s2.8 VD2~~~~~ —- Map 1 '----- Ρ〇·1 Ρ〇'2 Ρΐ,Ο Pu _ϋ〇_ P.1 P2.2 fast ifs memory Ρ〇·4 Ρ〇.5 Pl,3 Ρΐ,4 _PlsJ 1*2.3 P2 .4 PS Ρ〇·7 Ρ〇·8 Ρΐ,6 Ρΐ,7 P2.7 P2.8

U 201013400 » . According to the same principle, the data blocks of the same or different flash memory chips can be mapped to the same or different virtual disks. Table 2 shows that three flash memories are defined as three virtual disks, the first flash memory has six blocks, and the other two flash memories have three blocks, and each block can be A section mapped into one virtual disk VD0 to VD2. Where ' Βχ, γ denotes the γth block of the Xth flash memory. Table 2 sector-0~99 sector-100 ~199 sector-200~299 sector-300~399 VDO sector-Ο~99 sector-100-199 Sector-200~299 sector-300~399 VDl sector-Ο ~99 sector -100—199 Sector-200~299 sector-300~399 VD2 mapping Β〇·〇B〇3 — Bl Λ r> , Β〇ι -B〇.,_ B〇.4 •^1.0 Bl 1 -B2_i B2 .2 flash memory B〇.5 Bl,2 sub-, other Wei methods still include @鲁体芯片 mapping-virtual disk, or mix the above three mapping implementations: 隐Use hidden elements, body Control (4) system 1 can be included as needed - dynamic mapping generation list = from this virtual disk - the amount of out of the county exceeds, earlier virtual disk. Lift the block to the P27, h shell page (Pl, 6, Pl, 7, P, S, Pi, ', 8), so that the disk is lit out, and the 6-disk touch capacity is reduced. The disc array can be effectively executed to generate a new second mapping table, and the loss=dynamic mapping generating unit is remapped as shown in Table 4. After remapping, the damaged area, n is scattered with other virtual disks, and ~ Remap to ^ and 12 201013400, Sq, 8 'damaged sections Pl, 7 and 卩 2, 7 remapped to Si, ? and su, damaged section p - P2, 8 remapped to and heart, 8, so The memory damage can be reduced and the effect of the capacity of the disk array can be performed. 77 ’. effective

201013400 , , , , 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 重新 重新 重新 上述 重新 重新 重新 重新 重新 重新 重新 重新 重新 重新 重新 重新 重新 重新

S〇,〇S〇, l Si,〇Su ^2,0 ---w__ ^2,1 S ,〇,2 2,2 S〇,3 S〇>4 S,,3 Si,4 S2, 3 S2,4

Pi,〇 Pu Pu” Pl,3 Pm ΡιΓ p2;1 ^2,2 ρ2,Γ

The first address translation unit 12, the one-to-one memory media unit 14, the _ _ partial solution unit 13, the code unit mapping generation unit, and the arranging unit perform a software mode processing state of the related program or Microcontroller. The horse block diagram " reference to the second ®, which is the ghost diagram of the embodiment of the memory of the invention. In this embodiment, the first bit: bit, the element 13, the disk array control unit 15 or a wrong = editing surface software = is shown in the figure. The memory controller 2 includes a host device, a brother memory interface unit 14, a processing unit 221, and a storage unit. The storage unit 222 stores a first mapping table 23, a program 25, an error correction codec 26, a: = column 271 and an address translation program 272. 14 201013400 - The first mapping table 231 records the mapping relationship between the logical address of the data provided by the host 19 and the virtual magnetic domain address of the virtual disks 171 to 173, and the second mapping table 232 records the virtual magnetic domain address and The mapping relationship between the physical addresses of the memory 18, therefore, the processing unit τ 221 reads the address translation program 272, the first mapping table 231, and the second mapping table 232 from the storage unit 222 and executes, when the processing unit works according to The first mapping table 231 performs the address translation program 272 to generate the function of the first address translation unit 12. When the processing unit 221 performs the address translation program 2=2' in accordance with the second mapping table 232, the first bit can be generated. The function of the address translation unit 13. The first mapping table and the second mapping table 232 may also be stored in the memory 18, and after the memory control system 2 is activated, the processing unit 22! reads the first mapping table 231 and the second mapping table from the memory 18 again. The processing unit 221 reads the disk array control program 25, the error correction codec program %, the _ mapping raw silk type π, and the disk_control solution element 15 and the error correction codec unit 16 are respectively read from the storage unit 222. Dynamic mapping generates a single Wei. These Weis have been engraved in the paragraphs and are not mentioned here.

FIG. 3 is a flow chart showing the steps of the data recovery method of the present invention. In the figure, this _ bait recovery method is used for the memory, and includes the following steps. In step 31, it is defined as a complex number, and the city_physical address is divided into a plurality of groups, and the 'each group' can be regarded as a virtual disk. In the step magic, make = these virtual lions constitute - and _ financial storage data to the virtual disk. Among them, the disk array is set to - disk: ', array 2_ job, = disk_DH type, - disk array 4 (RAiD 4) mode, a disk array 5 (RAID 5) pull or a magnetic Disk array 6 (RAID sentence mode. 15 201013400 For example, if the disk array is set to a RAID mode, at least 2 virtual disks must be defined in the memory, and the backup data and the backup data are stored in the array separately. Some virtual disks; if the disk array is set to a 5 mode, the memory needs at least 3 smart disks, and the transfer type stores Wei and its corresponding parity data on these virtual disks respectively. Ο In step 33, an error correction code (EC.) correction procedure is performed on the data stored in the 5 memory. The ECC correction program uses an error correction code to decode, if the number of error bits in the data is in the error correction code. Allowance _, then ecc correction procedure 2 - Bay = * Step 34 'When the ECC correction program fails ' indicates that the number of errors in the data exceeds the allowable range of the error correction code, then use the virtual disk storage material to reply (recoveiy) This error corrects the failed data. = read 4, which shows the step of the embodiment of the data recovery method of the present invention 'This data recovery method is based on the number of virtual disks formed by a virtual disk in the domain - _ material. 'Material 疋 No error. If not, the process ends. If the forward process repeats this item, the second is executed in step 492 by the coffee - the disk array does not correct the error in the target data, then in the step 44 other virtual disk read ^ build this ° in step 45 from the material, and in step 4_== the material of the material and its related errors. If the recovery of the rebuilt household p hanging redundant lean and this Whether the relevant information is wrong step 彳7 execution ^-H Yu (four) material (four) please correct the error, then in the positive process, and judge whether it can be repaired. If the ECC correction 16 201013400 - the program can not be repaired 'then the data can not be repaired, and then end _. In the middle, if the disk array of the virtual disk is set to - RAm !, then the number of pieces required for this reconstruction is the backup data of the target data. The disk array of these virtual disks is set to -05 mode, then the capital record 2 and related materials required for this reconstruction are The target (4) of the same material and the data of other virtual disks are stored. 0. If the error in the redundant data or related data required for the reconstruction is judged, the error can be repaired. Step 48 is repaired by the ECC correction procedure, followed by steps. 491 uses the redundant data and related materials to reply to the data. Please refer to FIG. 5, which is a flow chart showing the steps of the data reading method of the present invention, wherein the data reading method is turned over. The memory is defined as a plurality of virtual disks, and the virtual disks are formed into a disk array, and the body in the memory is separately stored in the array to the virtual disks. The soil contains the following steps. At step 51, the finger 7 of the read-target data from the host is received, and then the virtual disk storing the target data in step 52 is unable to return to % j. If so, it indicates that the virtual disk performs a wear leveling process (wear leveling). ), - blockmanagement program, bl〇ckerase program, garbage collection (garbage c〇Uection) program, etc., so that the access command cannot be responded to 'use the storage in step 53 The redundant data and related data required for reconstructing the target resource in the other virtual thorns are used to generate a reconstructed target data, and the reconstructed target data is transmitted to the host in step 54. The above is based on the ‘those’. Any and all equivalent modifications made by the spirit and scope of the present invention, and (4) shall be included in the scope of the appended patent application. 201013400 [Simplified description of the drawings] Fig. 1 is a block diagram of a memory control system of the present invention; Fig. 2 is a block diagram of an embodiment of a memory control (four) system of the present invention; FIG. 4 is a flow chart of steps of an embodiment of the data recovery method of the present invention, and FIG. 5 is a flow chart of the data reading method of the present invention. Description] I: memory control system; II: host interface unit; 12: first address translation unit; 13: second address translation unit, · 14: memory interface unit; 15: disk array control unit; : redundant data; φ 16 : error correction codec unit; 161: error correction code; 171~173: virtual disk; 174. virtual area address; 18: memory; 181: physical address; 19: host; ''Command; £9$: Logical Address; 192: Data; 2 · Memory Control System; 221: Processing Unit; 222: Storage Unit; 231: First Mapping Table; 232: Second Mapping Table; Disk array control program; 26: error N codec programs; 271: dynamically map generation programs; 272: Address Translator; ~34,41 ~48,491,492 and 31, 51~54: step process. 18

Claims (1)

201013400 Patent application scope: - Memory control system, for - host control - access to the title, the memory control system includes: face; host interface unit, electrically connected to the host as a means of data transmission 2 3. The first address is transferred to a logical address received from the host into a virtual domain address, wherein the plurality of physical addresses of the memory are defined as a plurality of virtual disks. The virtual magnetic zone address; - the second position of the sub-scientific element, the miscellaneous _ secret memory of the physical address; the 戏 theater; the I-side single 70' is based on the entity bit received from the second address translation unit Addressing the data to the memory; a disk_control unit, based on the virtual address received from the first address translation unit, the control-memory interface unit storing data to the virtual disks; and J The correct type of codec is stored in the memory, and the data stored in the memory is 兮'when the error is corrected, the township _ control solution uses =^ 崎 她 鸣 鸣 备 备 备 备 备 备 第 第 第 第 第 第 第 第(4) System 'where the memory system is one Flash memory. ~ The memory control system according to claim 1, wherein when the main 19 201013400 2 receives and writes the material, the error correction codec unit encodes the ««, the input material. To generate a erroneous positive code corresponding to the data to be written, and the disk array control unit generates the virtual magnetic domain address from the first address to generate a redundant resource corresponding to the input data. The disk array is controlled by the element (4) interface unit to array ==, the wrong code is 峨 _ _ ^ 4 4 ^ 4. ^ The memory control system described in claim 3, wherein the disk is early The system uses at least the redundant material to reply to the error correction 5_ as in the memory control system described in claim 3, the "host", the memory reads - the target data, when the memory is introduced Judgment = f Haimu The virtual _ disc can not _, __ array = send the reconstructed target data to the host. Heart Beike, and pass .t apply for the scope of patents! According to the item, the military system is set to a disk array mode: ::, , m type, disk array, 4 mode:, —: array 5 (face 5) mode or a disk Array 6_D6) mode disk, such as the memory control address transfer field described in item 1 of the claim (4), according to the -first mapping silk into the hiding;: address translation unit residual data - the second mapping table Address ^ brother - 20 7. 201013400 8 · 2! Please delete the memory control system described in item f, and further include a storage 7G to store the first mapping table and the second mapping table. 9 i is the memory control secret described in item 7 of the patent scope, wherein the first, the ejaculation table and the second mapping table are stored in the draping towel, and when the commemorative system activates the first-to-the-key translation unit And the second address translation 7 reads the first mapping table and the second mapping table from the memory. ', 10 ΐ ΐ 记忆 记忆 之 之 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆The second is updated to spread the damaged block to the virtual disks. , 11. 4 data back and method; for - memory, the f material recovery method private: the definition of the billion body into a plurality of virtual disks; data into a - do _, and the scale of the financial health The data stored in the narration library is subjected to an error correction code (ECC) correction procedure; and when the ECC is corrected, the ship uses virtual magnetic data to reply (recoveiy) the error to correct the failed data. △ The data recovery method system described in item u of the patent application scope is a flash memory. Hai & R has the data recovery method described in claim n, wherein the magnetic array is set to a disk array (RAID _, (RAID 1) mode, a disk array 2 (RAiD2) Mode, - Disk array 3 21 201013400 (5) mode or a disk array 6 (RAID 6) mode. 14. The data recovery method described in the application of the patent (4) u, further includes: Record-table and - "Saki, township-mapping table system - the logical address and the virtual disk: =, ' and the second mapping table records the virtual disk address: the 5 own, think The physical-physical address mapping relationship; and the Φ Φ virtual shot table and the second mapping table are arrayed to the 15: the range of information described in item 14 of the method, when the virtual, heart, - When a damaged block with a capacity exceeding the gated value occurs, the person mapping table is regenerated to damage the block to the virtual ones in May. 16.; the seed reading method is used for a memory, the memory The second virtual disk is defined as a plurality of virtual disks, and the virtual disks constitute a disk array, and the memory is The data is stored in the array to the virtual disks. The data reading method includes: when the factory host reads a target data into the memory, the virtual disk that stores the data is unable to respond. If the virtual disk storing the target data cannot respond, use one of the redundant data and related data stored in the other virtual disk to reconstruct the target data to generate a reconstructed target data; and transmit the target data; Reconstruction of the target data to the host. 17. The method of reading data as described in claim 16 wherein the memory 22 201013400 system is a flash memory. 18. If the patent application scope, the The data reading method, wherein storing the undesired ίhai virtual disk system performs a wear averaging process, a blockmanagement program, and a block erase process. The program or a garbage collection collecti〇n) program, so that it can not respond. ❹ 23