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TW201012976A - Method for substantially uniform copper deposition onto semiconductor wafer - Google Patents

Method for substantially uniform copper deposition onto semiconductor wafer Download PDF

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TW201012976A
TW201012976A TW097135668A TW97135668A TW201012976A TW 201012976 A TW201012976 A TW 201012976A TW 097135668 A TW097135668 A TW 097135668A TW 97135668 A TW97135668 A TW 97135668A TW 201012976 A TW201012976 A TW 201012976A
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electrode
wafer
current density
voltage
electrolyte
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TW097135668A
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TWI425122B (en
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Yue Ma
Xi Wang
Chuan He
Hui Wu
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Acm Research Shanghai Inc
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Abstract

The methods practiced in an electrochemical deposition apparatus with two or more electrodes, described in earlier inventions, are disclosed. The methods produce uniform copper films with WFNU less than 2.5% on semiconductor wafers bearing a resistive copper seed layer with a thickness ranging from 50 to 900 Å in a copper sulfate based electrolyte whose conductivity is between 0.02 to 0.8S/cm.

Description

201012976 六、發明說明: 【相關專利引用】 本專利申請爲1999年1月15曰提交的美國專利(專 利申請號爲09/232,864’現專利號爲6391 166)的延續部 分。美國專利6391 166聲明了 1998年2月12日提交的美 國臨時申請號爲60/074,466的美國專利與1998年7月 27日提交的美國臨時申請號爲6〇/〇94 215的美國專利的 ❹ 利益。同時本申請也聲明了 2007年11月2日提交的國際 專利號爲PCT/CN2007/071008的國際專利的利益。上述專 利的所有内容引用於本專利中。 【發明所屬之技術領域】 本發明一般而言關於一種在超大型積體電路製造中 採用電化學沈積的方法,在超薄大阻抗籽晶層半導體工件 上製備均勻銅膜。 【先前技術】 在半導體晶片上使用多個不同的處理步驟製造電晶 體和互連元件。在形成互連元件的過程中,半導體晶片可 能、左過例如·掩臈,蝕刻和沈積等處理,從而形成半導體 電晶趙和所需要的電子電路,來連接這些電晶料端。具 體而。,可執行多次掩膜、離子植入退火和等離子蝕刻、 以及化學以及物理氣相沈積步驟來形成窄溝槽、電晶體 阱柵極、多晶矽線路以及互連線路結構,如通孔和溝槽。 3 201012976 • 如通孔和溝槽形成以後’在這些結構中沈積電導物質 來連接底部的電晶體。除去多餘的電導物質,使此電導結 構形成所需電路。在超大型積體電路製造中,採用在超薄 的大抗阻籽晶層上電化學沈積一層金屬膜層來形成電導 線路,該金屬膜層通常是銅膜。這種沈積工藝可填充通孔 結構’溝槽結構或兩種結構的混合結構。當這些結構被填 充時,銅連續地沈積並在半導體晶片表面上形成一層膜。 φ 最終形成的銅膜均勻度至關重要,這是由於後續的用來去 除多餘銅的工藝步驟(通常是平坦化步驟CMP)要求很高 的均勻度,從而使最終産出的器件與器件之間獲得相同的 電性能。先進的工藝技術一般可將膜内不均勻度(wFNU, 爲膜厚標準偏差與膜厚平均值的比值)控制在2·5%以内。 大的WFNU對後續CMP工藝步驟有負面影響,將引起 銅局部殘留或過多電介質材料在抛銅過程損失。如拋光過 程將晶片上的銅等量地去除,晶片邊緣最初的銅膜相對較 ® 厚,從而導致銅或阻擋層在該處殘餘,這種非完全去除工 藝將引起器件短路。如果大幅度地採用過抛光來清除晶片 邊緣的銅和阻擋層,晶片中心附近區域的電介質材料則過 度損失’使溝槽和通孔的高度降低,晶片上互連線間的電 阻産生差異》這兩種影響都對器件的良率有很大損害。 爲滿足製造技術的更新換代’不斷發展,晶片尺寸從 20 0mm轉變爲300ram,籽晶層厚度持續降低,從而使半導 體晶片上的籽晶層歐姆電阻顯著增加。在傳統電化學沈積 工藝中(一般指電鍍),電源向單一的工作電極與具籽晶 201012976 層的晶片基材提供電流或電壓。晶片基材、工作電極、電 源及電解液形成一個電解池。由於一種叫做“邊緣效應” 的現象,超薄大阻抗晶片上的電流密度是不均勻的,在邊 緣相對較高。該電流不均勻性使電鍍速率在晶片邊緣高, 晶片中心低,進而使晶片表面上的銅膜沈積厚度不均勺。 當籽晶層厚度減小,晶片尺寸增大後,邊緣效應更加顯 著。在最嚴重的情況中,沈積僅發生在晶片邊緣。 ❿ 邊緣效應可藉由採用相對低酸的電解質得到改善,如 圖3a-3d所示。但是,隨著技術發展,僅採用低酸電解液 仍無法解決由邊緣效應産生的電鍍不均勻。通常,這種不 均勻性可藉由提高鍍膜厚度來改善,如圖3c_3d所示。但 這將嚴重限制工藝設備的產能,並大大增加後續平坦化工 藝去除多餘材料的成本。 在現有的專利中,已有諸多設計應用於工藝設備中以 解決邊緣效應產生的不均勻性問題。美國專利6391166 ❹ (1999.1.15)揭示了電鍍設備與方法,採用獨立電源控 制電極系統,以克服在半導體晶片超薄籽晶層上電鍍速率 不均勻的問題。美國專利6755954(2004· 6. 29)揭示了 一 種電鍍設備與方法電沈積銅膜,可得到相對較小的膜厚偏 差,在其中的一個實施例中’在具400A籽晶層的300mm 晶片上沈積〇.6um (6000A)銅膜’得到的銅膜厚度偏差爲 394A。 5 201012976 【發明内容】 本發明揭示了用於一種具有多電極與一個電源控制 系統的電化學沈積設備的方法。在本發明的文本與圖示 中’稱該設備爲所述設備。在美國專利6391166與全球專 利PCT/CN2007/071 008中曾描述該設備的實施例。 所揭示方法應用於籽晶層厚度爲5〇A至900A的晶片 電鍍,所採用電解液的電導率爲〇.〇2至0.8s/cm。 _ 所揭示方法可在具35〇A籽晶層的晶片上製備出晶片 内不均勻度僅爲0.33%(厚度偏差爲42A)的電化學鐘銅 膜,比以往專利揭示方法所得不均勻度小數倍。 【實施方式】 本發明的揭示了用於一種具有多電極與一個電源控 制系統的電化學沈積設備的方法。所揭示方法應用於軒晶 層厚度爲5 0A至90 0A的晶片電鍍,所採用電解液的電導 9 率爲0·〇2至〇·8 S/cm。該方法將在美國專利6391166 所揭示的設備中實施。 本發明方法包括以下步驟: 將電解液注入所述設備,電解液流速在1至20LPM範 圍内; 將晶片傳送到晶片固持裝置上’該裝置與晶片間可導 電; 對晶片施加一個小的偏壓; 將晶片送到電解液中’並使晶片的前表面與電解液完 6 201012976 全接觸; 向每個電極提供電流;與各電極相連的各電源可在要 求的時刻從電壓模式切換到電流模式; 向每個電極提供一個相對較小的電流或電壓,總電流 以2A至10A爲宜,電極之間的電流密度比爲〇. 5:丨至 300:1 ; 向每個電極提供一個相對較大的電流或電壓,總電流 φ 以10A至40A爲宜’電極之間的電流密度比爲0. 5:1至 300:1 ; 切換到一個小的偏壓模式施加在所述半導體晶片上; 將晶片自電解液取出; 停止電源供應’並清除晶片表面殘留電解液。 在上述第6步驟與第7步驟中,根據使用的電極數 量、電解液電導率’使每個電極上電流分佈和電極之間電 流密度比在小範圍内變化。在以下實施例中,將針對特定 © 電極數量與電解液電導率對這些範圍作具體說明。 在一個實施例中’揭示了一種應用於所述兩電極設備 的方法’其中所採用電解液電導率爲0.0 2-0. 2S/cm。 在一個實施例中,揭示了一種應用於所述兩電極設備 的方法’其中所採用電解液電導率爲0.2-0. 8S//Cm。 在一個實施例中,揭示了一種應用於所述三電極設備 的方法’其中所採用電解液電導率爲002_0· 2s/cm。 , 在一個實施例中,揭示了一種應用於所述三電極設備 . 决’其中所採用電解液電導率爲0.2-0. 8S//Cm。 7 201012976 . 在—個實施例中,揭示了一種應用於所述四電極設備 的方法’其中所採用電解液電導率爲0.0 2-0. 2S/cm。 在一個實施例中,揭示了 一種應用於所述四電極設備 的方法’其中所採用電解液電導率爲0.2-0. 8S//cm。 在一個實施例中’揭示了 一種應用於所述十電極設備 的方法’其中所採用電解液電導率爲〇〇2_〇 2s/cjn。 在一個實施例中,揭示了一種應用於所述十電極設備 φ 的方法’其中所採用電解液電導率爲0. 2-0. 8S//cni。 圖2繪示了一個具有單個電極2〇1的傳統電鍍設備。 圖3a-3d爲採用該單電極電鍍設備在3〇〇mm半導體晶片表 面上得到的沈積曲線。具體而言,圖3a-3b繪示了具厚度 爲350A到900A籽晶層的在半導體晶片上沈積3〇〇〇A厚銅 膜的沈積曲線,分別採用了低電導率和高電導率電解液。 圖3c-3d繪示了在具350A籽晶層的半導體晶片上沈積爲 3000A至6000A厚銅膜的沈積曲線,分別採用了低電導率 參 和高電導率電解液》 由圖3a-3b中的厚度曲線計算得到的WFNU值列於表 1。WFNU值隨籽晶層厚度的減小而增大,說明了,當軒晶 層很薄,很難在半導體晶片表面均勻地沈積銅膜。當軒晶 層厚度小於700A時,採用傳統單電極電鍍設備無法使 WFNU值小於2. 5%。當電解液電導率增加時,情況更差。 201012976 表 1 籽晶層厚度 低電導率電解液 高電導率電解液 -WFNU -WFNU 350A 3. 72% 13.91% 550A 2. 95% 11.45% 700A 2. 58% 10.19% 900A 2.21% 8. 94% 參 如圖3c-3d所示,在相同的350A籽晶層上,WFNU隨 電鍍膜層厚度增加而改善。相應值列於表2。這種現象是 由於沈積過程中增厚的膜層歐姆電阻降低,從而減小了邊 緣效應。在電鍍厚度小於5000A的情況下,WFNU值大於 2.5%,當電解液的電導率高的情況下,WFNU值遠大於 2. 5%。雖然增加電鍍厚度可改善WFNU,但是由於1C工藝 流程中的後續CMP步驟需要高成本來去除多餘的銅膜,因 〇 而不允許沈積膜層過厚。 表 2 沈積厚度 低電導率電解液 高電導率電解液 -WFNU -WFNU 3000A 3. 72% 13·91% 4000A 2. 98% 11.25% 5000A 2. 48% 9. 93% 6000A 2. 12% 8. 83% 9 201012976 本發明的所有分析都基於更薄的籽晶層(35〇A)與電 鍍厚度(3000A),這樣的組合使得揭示的方法具有很高的 敏感性。 ' 實施例1 在本發明的一個實施例中,揭示了一種應用於圖4所 示設備的半導體晶片上均勾沈積銅膜的方法。該設備爲圖201012976 VI. INSTRUCTIONS: [Related patent citation] This patent application is a continuation of the U.S. patent filed on Jan. 15, 1999 (patent application number 09/232,864, patent number 6391 166). U.S. Patent No. 6,391,166 issued to U.S. Patent Application Serial No. 60/074,466, filed on Feb. 12, 1998, and U.S. Patent Application Serial No. interest. At the same time, this application also declares the benefits of the international patent number PCT/CN2007/071008 filed on November 2, 2007. All of the above patents are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of electrochemical deposition in the fabrication of ultra-large integrated circuits to produce a uniform copper film on an ultra-thin, large-impedance seed layer semiconductor workpiece. [Prior Art] Electro-crystals and interconnect elements are fabricated using a number of different processing steps on a semiconductor wafer. In the process of forming the interconnection elements, the semiconductor wafer may be subjected to treatment such as, for example, masking, etching, and deposition to form a semiconductor transistor and a desired electronic circuit to connect the terminals. Specifically. Multiple masks, ion implantation annealing and plasma etching, and chemical and physical vapor deposition steps can be performed to form narrow trenches, transistor well gates, polysilicon lines, and interconnect structures such as vias and trenches. . 3 201012976 • After the formation of vias and trenches, a conductive material is deposited in these structures to connect the transistors at the bottom. Excess conductive material is removed to form the conductive structure to form the desired circuitry. In the manufacture of ultra-large integrated circuits, a metal film layer is electrochemically deposited on an ultra-thin large resist seed layer to form a conductive line, which is usually a copper film. This deposition process can fill the via structure' trench structure or a hybrid structure of the two structures. When these structures are filled, copper is continuously deposited and a film is formed on the surface of the semiconductor wafer. The uniformity of the copper film that is ultimately formed by φ is critical because the subsequent process steps to remove excess copper (usually the planarization step CMP) require high uniformity, resulting in a final output between the device and the device. Get the same electrical performance. Advanced process technology generally controls the in-film heterogeneity (wFNU, which is the ratio of the film thickness standard deviation to the average film thickness) within 2.5%. The large WFNU has a negative impact on subsequent CMP process steps and will cause localized copper residues or excessive dielectric material loss during the copper throwing process. If the polishing process removes the copper on the wafer an equal amount, the original copper film at the edge of the wafer is relatively thicker than ®, causing copper or barrier layers to remain there. This incomplete removal process will cause the device to be shorted. If the polishing is used to remove the copper and barrier layers at the edge of the wafer, the dielectric material in the vicinity of the center of the wafer is excessively lost 'the height of the trenches and vias is lowered, and the resistance between the interconnects on the wafer is different. Both effects are very detrimental to the yield of the device. In order to meet the ever-increasing development of manufacturing technology, the wafer size has changed from 200 mm to 300 ram, and the thickness of the seed layer has continued to decrease, so that the ohmic resistance of the seed layer on the semiconductor wafer is significantly increased. In conventional electrochemical deposition processes (generally referred to as electroplating), the power supply supplies current or voltage to a single working electrode and a wafer substrate with a seed layer of 201012976. The wafer substrate, working electrode, power source and electrolyte form an electrolytic cell. Due to a phenomenon called "edge effect", the current density on an ultra-thin large-impedance wafer is not uniform and is relatively high at the edges. This current non-uniformity causes the plating rate to be high at the edge of the wafer and the center of the wafer to be low, thereby causing uneven thickness of the copper film deposited on the surface of the wafer. When the seed layer thickness is reduced and the wafer size is increased, the edge effect is more pronounced. In the most severe cases, deposition occurs only at the edge of the wafer.边缘 Edge effects can be improved by using a relatively low acid electrolyte, as shown in Figures 3a-3d. However, with the development of technology, it is still impossible to solve the uneven plating caused by the edge effect by using only a low acid electrolyte. Generally, this non-uniformity can be improved by increasing the thickness of the coating, as shown in Figures 3c-3d. However, this will severely limit the capacity of process equipment and greatly increase the cost of removing excess material from subsequent flat chemicals. In the existing patents, many designs have been applied to process equipment to solve the problem of unevenness caused by edge effects. U.S. Patent No. 6,391,166 (1999.1.15) discloses an electroplating apparatus and method that employs an independent power supply control electrode system to overcome the problem of uneven plating rates on the ultrathin seed layer of semiconductor wafers. U.S. Patent 6,575,954 (2004, 2.9) discloses an electroplating apparatus and method for electrodepositing a copper film which provides a relatively small film thickness deviation, in one of the embodiments 'on a 300 mm wafer having a 400A seed layer The thickness deviation of the copper film obtained by depositing 〇.6um (6000A) copper film was 394A. 5 201012976 SUMMARY OF THE INVENTION The present invention discloses a method for an electrochemical deposition apparatus having multiple electrodes and a power supply control system. In the text and illustration of the present invention, the device is referred to as the device. An embodiment of the apparatus is described in U.S. Patent No. 6,391,166 and the entire disclosure of PCT/CN2007/071 008. The disclosed method is applied to wafer plating having a seed layer thickness of 5 Å to 900 Å, and the conductivity of the electrolyte used is 〇 2 0.8 2 to 0.8 s / cm. _ The disclosed method can prepare an electrochemical clock copper film with a wafer inhomogeneity of only 0.33% (thickness deviation of 42A) on a wafer having a 35〇A seed layer, which is less uneven than the method disclosed in the prior patent. Several times. [Embodiment] The present invention discloses a method for an electrochemical deposition apparatus having a multi-electrode and a power supply control system. The disclosed method is applied to wafer plating having a thickness of 50 ° to 90 0 A, and the conductivity of the electrolyte used is 0·〇2 to 〇·8 S/cm. This method will be implemented in the apparatus disclosed in U.S. Patent No. 6,391,166. The method of the present invention comprises the steps of: injecting an electrolyte into the apparatus at a flow rate in the range of 1 to 20 LPM; transferring the wafer to the wafer holding device - the device is electrically conductive from the wafer; applying a small bias to the wafer The wafer is sent to the electrolyte 'and the front surface of the wafer is in full contact with the electrolyte 6 201012976; current is supplied to each electrode; each power source connected to each electrode can be switched from voltage mode to current mode at the required time Provide a relatively small current or voltage to each electrode, the total current is preferably 2A to 10A, and the current density ratio between the electrodes is 〇. 5: 丨 to 300:1; provide a relative to each electrode a large current or voltage, the total current φ is preferably 10A to 40A, and the current density ratio between the electrodes is 0.5:1 to 300:1; switching to a small bias mode is applied to the semiconductor wafer; Take the wafer out of the electrolyte; stop the power supply' and remove residual electrolyte from the wafer surface. In the sixth step and the seventh step described above, the current distribution on each electrode and the current density ratio between the electrodes were varied within a small range depending on the number of electrodes used and the electrolyte conductivity. In the following examples, these ranges will be specifically described for the specific number of electrodes and electrolyte conductivity. In one embodiment, a method of applying the two-electrode device is disclosed, wherein the electrolyte conductivity is 0.0 2-0. 2 S/cm. </ RTI> In one embodiment, a method of applying the two-electrode device is disclosed. In one embodiment, a method of applying to the three-electrode device is disclosed wherein the electrolyte conductivity employed is 002_0·2 s/cm. </ RTI> In one embodiment, an electrolyte is used in the three-electrode device. In an embodiment, a method of applying the electrolyte to the four-electrode device is disclosed in which the conductivity of the electrolyte is 0.0 2-0. 2 S/cm. In one embodiment, a method of applying the electrolyte to the four-electrode device is disclosed in which the electrolyte conductivity is 0.2-0. 8 S/cm. In one embodiment, 'a method of applying to the ten-electrode device' is disclosed in which the electrolyte conductivity is 〇〇2_〇 2s/cjn. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> Figure 2 depicts a conventional electroplating apparatus having a single electrode 2〇1. Figures 3a-3d show the deposition curves obtained on the surface of a 3 mm semiconductor wafer using this single electrode plating apparatus. Specifically, Figures 3a-3b illustrate deposition curves of a 3〇〇〇A thick copper film deposited on a semiconductor wafer having a thickness of 350A to 900A, using low conductivity and high conductivity electrolytes, respectively. . Figures 3c-3d illustrate the deposition curves of a 3000A to 6000A thick copper film deposited on a semiconductor wafer with a 350A seed layer, using a low conductivity and high conductivity electrolyte, respectively, as shown in Figures 3a-3b The WFNU values calculated from the thickness curves are listed in Table 1. The WFNU value increases as the thickness of the seed layer decreases, indicating that it is difficult to uniformly deposit a copper film on the surface of the semiconductor wafer when the enamel layer is thin. The WFNU value is less than 2.5% when the thickness of the enamel layer is less than 700 Å. The situation is even worse when the electrolyte conductivity increases. 201012976 Table 1 Seed layer thickness Low conductivity Electrolyte high conductivity electrolyte - WFNU -WFNU 350A 3. 72% 13.91% 550A 2. 95% 11.45% 700A 2. 58% 10.19% 900A 2.21% 8. 94% As shown in Figures 3c-3d, WFNU is improved as the thickness of the plated layer increases over the same 350A seed layer. The corresponding values are listed in Table 2. This phenomenon is due to the reduced ohmic resistance of the thickened film during deposition, which reduces the edge effect. In the case where the plating thickness is less than 5000 A, the WFNU value is more than 2.5%, and when the conductivity of the electrolyte is high, the WFNU value is much larger than 2.5%. Although increasing the plating thickness improves WFNU, the subsequent CMP steps in the 1C process require high cost to remove excess copper film, which does not allow the deposited film to be too thick. Table 2 Deposition Thickness Low Conductivity Electrolyte High Conductivity Electrolyte - WFNU -WFNU 3000A 3. 72% 13·91% 4000A 2. 98% 11.25% 5000A 2. 48% 9. 93% 6000A 2. 12% 8. 83% 9 201012976 All analyses of the present invention are based on a thinner seed layer (35〇A) and a plating thickness (3000A), such a combination making the disclosed method highly sensitive. [Embodiment 1] In one embodiment of the present invention, a method of depositing a copper film on a semiconductor wafer applied to the apparatus shown in Fig. 4 is disclosed. The device is a diagram

1發明的一個實施例,它包含第一電極401a和第二電極 4〇lb,其中第一電極面積爲總電極面積的50%-90%,所有 電極面積總和與半導體晶片面積之比大於〇85。該方法 包括以下步驟: 步驟1 :打開流體控制裝置4233和423b,以控制每 個電極工作區域的流速’在第一電極4Gla的工作區域 内’流速爲5到20LPM,在第二電極4()11)的工作區域内, 流速爲1至H5 LPM。在本發明的一個實施 制裝置423a和423b同睹升胡μ找 趙控 门時打開,在本發明的另一個實施 ,流鳢控制裝置423a和423b在不同的時間打開. 二Γ:傳送具有杆晶層的半導體晶片到設財的晶 爲其導電; 平導體日曰片籽晶層相接觸可 步驟3:對所述半導趙晶片施加一個 圍在0.01-10V ; 幻侷歷其範 步帮4 :用晶片固持裝置 曰&amp; 发罝將日日片送到電解液中,並4 日曰片的前表面完全浸入電解液; 亚4 步驟5:向電極4〇la盥 〃 401b &amp;供電流,並保持^ 10 201012976 極40 la上電壓爲正,電極40 lb上電壓爲正或負(本文中 電壓的正負號相對晶片而言);電極401 a的工作電流爲5 至20A,電極401b的工作電流爲0.01至10A。電極401a 與401b上的電流密度比爲1:1至300:1。此步驟持續5 至30秒,填充半導體晶片422表面的通孔與溝槽。在本 發明的一個實施例中,與電極4 01 a和4 01 b相連的電源同 時從電壓模式切換到電流模式;在本發明的另一個實施例 ❹ 中’與電極401a和401b相連的電源在不同的時間從電壓 模式切換到電流模式; 步驟6:向電極401a與40 lb提供電流,並保持電 極401a上電壓爲正,4〇lb上電壓爲正或負;電極4〇1&amp; 的工作電流爲15至40A,電極401b的工作電流爲on 至20A。電極401a與401b上的電流密度比爲ι:1至 300:1。此步驟在電極4〇la和4〇11}上施加相對較大的電 流,從而提高電化學沈積的效率。當沈積得到要求的厚 〇 膜,終止此步驟。 步驟7·在所述半導體晶片上施加一個小的偏壓。在 本發明的一個實施例中,電極401a和401b同時從電流模 式切換到電壓模式,在本發明的另一個實施例中電極 401a和40lb在不同的時間從電流模式切換到電壓模式; 步驟8·將晶片自電解液取出,旋轉清除晶片表面殘 留電解液; 述的步驟5與步驟6中,電極401b電壓的正負 符號由電化學妙接处^ ^ • 積條件決定。例如’當電解液的電導率 201012976 低,半導體晶片表面電導層厚,對電極401a和401b同時 施加正電壓,如圖5a所示;當電解液的電導率高,半導 體晶片表面電導層薄,對電極401a施加正電壓,對電極 40 lb施加負電壓,如圖5b所示. 步驟5中’在籽晶層爲200至2000A的300 mm半導體 晶片上均勻電鍍銅膜所採用的電流密度比與每個電極電 壓正負符號,具體設置如表3,所採用的電解液電導率分 _ 別爲 0. 02-0· 2S/cm 與 0. 2-0. 8S/cm : 表3 .....-—---- 電極401a符號 電極401b 符號 電流密度比 (401a : 401b) 電導率 0. 02-0. 2S/cm + + 1:1-30:1 + — 15:1-30:1 -—2:1 二 15_______ ❹ ---厂 0. 2-0. 8S/cm 當沈積的銅膜厚度達到1500A後,開始步驟6。在籽 晶層爲200至2000A的300mm半導體晶片上均勻電鍍銅膜 所採用的電流密度比與每個電極電壓正負符號,具體設置 如表4,所採用的電解液電導率分別爲〇. 0 2-0. 2S/cm與 〇.2-0.8S/cm : 12 201012976 表4 電極401a符號 電極401b符號 電流密度比 (401a : 401b) 電導率 + + 1:1-30:1 0. 02-0. 2S/cm + 一 15:1-30:1 電導率 0. 2-0.8S/cm + 一 10:1-20:1An embodiment of the invention comprising a first electrode 401a and a second electrode 4〇1b, wherein the first electrode area is 50%-90% of the total electrode area, and the ratio of the total electrode area to the semiconductor wafer area is greater than 〇85 . The method comprises the following steps: Step 1: Opening the fluid control devices 4233 and 423b to control the flow rate of each electrode working region 'in the working region of the first electrode 4Gla' flow rate is 5 to 20 LPM, at the second electrode 4 () In the working area of 11), the flow rate is 1 to H5 LPM. In one embodiment of the present invention, the devices 423a and 423b are opened when the door is raised, and in another embodiment of the invention, the flow control devices 423a and 423b are opened at different times. The semiconductor wafer of the crystal layer is electrically conductive to the crystal of the wealth; the seed layer of the flat conductor is contacted by the seed layer: step 3: applying a 0.01-10V to the semiconductor wafer of the semiconductor wafer; 4: using the wafer holding device 曰&amp; hair to send the sun piece to the electrolyte, and the front surface of the ruthenium film is completely immersed in the electrolyte on the 4th; sub 4 step 5: to the electrode 4〇la盥〃 401b &amp; Current, and keep ^ 10 201012976 The voltage on the pole 40 la is positive, the voltage on the electrode 40 lb is positive or negative (the sign of the voltage in this paper is relative to the wafer); the working current of the electrode 401 a is 5 to 20A, the electrode 401b The operating current is 0.01 to 10A. The current density ratio on the electrodes 401a and 401b is 1:1 to 300:1. This step lasts 5 to 30 seconds to fill the vias and trenches on the surface of the semiconductor wafer 422. In one embodiment of the invention, the power supplies connected to electrodes 401a and 401b are simultaneously switched from voltage mode to current mode; in another embodiment of the invention, 'the power source connected to electrodes 401a and 401b is Switching from voltage mode to current mode at different times; Step 6: Supply current to electrodes 401a and 40 lb, and keep the voltage on electrode 401a positive, the voltage on 4〇lb is positive or negative; the operating current of electrode 4〇1&amp; For 15 to 40 A, the operating current of the electrode 401b is from on to 20A. The current density ratio on the electrodes 401a and 401b is ι:1 to 300:1. This step exerts a relatively large current on the electrodes 4〇1a and 4〇11}, thereby increasing the efficiency of electrochemical deposition. This step is terminated when the desired thick ruthenium film is deposited. Step 7 - Apply a small bias voltage to the semiconductor wafer. In one embodiment of the invention, electrodes 401a and 401b are simultaneously switched from a current mode to a voltage mode, and in another embodiment of the invention electrodes 401a and 40bb are switched from a current mode to a voltage mode at different times; The wafer is taken out from the electrolyte and rotated to remove residual electrolyte on the surface of the wafer. In steps 5 and 6, the positive and negative signs of the voltage of the electrode 401b are determined by the electrochemical connection. For example, when the conductivity of the electrolyte is low, the conductivity of the semiconductor wafer is low, the surface of the semiconductor wafer is thick, and the electrodes 401a and 401b are simultaneously applied with a positive voltage, as shown in FIG. 5a. When the conductivity of the electrolyte is high, the surface of the semiconductor wafer is thin, A positive voltage is applied to the electrode 401a, and a negative voltage is applied to the electrode 40 lb as shown in FIG. 5b. In step 5, the current density ratio and uniformity of each of the copper films are uniformly plated on a 300 mm semiconductor wafer having a seed layer of 200 to 2000 Å. The positive and negative sign of the electrode voltage, as shown in Table 3, the conductivity of the electrolyte used is 0. 02-0· 2S/cm and 0. 2-0. 8S/cm : Table 3 ..... - - - - - electrode 401a symbol electrode 401b symbol current density ratio (401a: 401b) conductivity 0. 02-0. 2S / cm + + 1:1-30:1 + - 15:1-30:1 - —2:1 二15_______ ❹ --- Plant 0. 2-0. 8S/cm After the thickness of the deposited copper film reaches 1500A, start step 6. The current density ratio and the positive and negative sign of each electrode voltage are uniformly plated on a 300 mm semiconductor wafer with a seed layer of 200 to 2000 A. The specific settings are as shown in Table 4. The conductivity of the electrolyte used is 〇. 0 2 -0. 2S/cm and 〇.2-0.8S/cm : 12 201012976 Table 4 Symbol 401b symbol current density ratio of electrode 401a (401a: 401b) Conductivity + + 1:1-30:1 0. 02-0 2S/cm + a 15:1-30:1 Conductivity 0. 2-0.8S/cm + a 10:1-20:1

圖6a與6b繪示了在350A籽晶層上電鍍3000A厚鋼 膜的沈積曲線,所採用的電解液分別爲低電導率與高電導 率電解液。其中,方法1的曲線爲採用表3與表4中的工 藝參數所得,方法2的曲線爲採用表3與表4所述範圍外 中。如圖6a-6b與表5 的工藝參數所得。WFNU值列於表 所示,所揭示的方法使採用高電導率與低電導率電解液沈 積3_A膜層的麵均得到很大程度的改善。所述3〇〇㈣ 半導體晶片上沈積曲線的 域,這比通常工業中採用的 算嚴格很多。 WFNU計算排除邊緣2 3mm區 排除邊緣3. 0到6· 5nm區域計Figures 6a and 6b illustrate the deposition curves of a 3000A thick steel film deposited on a 350A seed layer, using electrolytes of low conductivity and high conductivity, respectively. Among them, the curve of Method 1 is obtained by using the process parameters in Tables 3 and 4, and the curve of Method 2 is outside the range described in Tables 3 and 4. Obtained in the process parameters of Figures 6a-6b and Table 5. The WFNU values are shown in the table, and the disclosed method provides a large improvement in the surface of the 3_A film deposited by the high conductivity and low conductivity electrolyte. The field of the curve is deposited on the 3 〇〇 (4) semiconductor wafer, which is much more stringent than that used in the general industry. WFNU calculation excludes edge 2 3mm area excludes edge 3. 0 to 6· 5nm area meter

方法1 (揭示的)- ___WFNU 低電導率電解液 高電導率電解液Method 1 (Revelation) - ___WFNU Low Conductivity Electrolyte High Conductivity Electrolyte

方法2 (傳統的)-WFNU 3. 65% 12.94% 13 201012976 才木用局電導率與低電導率電解液的情況下,揭示方法 (方法D較傳統方法(方法2)而言,均使WFNU得以顯 对 Ml. 上 。尤其在採用低電導率電解液的情況下,得到的 WFNU 小於 2. 5%。 實施例2 在本發明的一個實施例中,揭示了 一種應用於圖7所 ❹ 不6又備的半導趙晶片上均勻沈積銅膜的方法。該設備爲圖 1發明的—個實施例,它包含第一電極7〇la、第二電極 701b,和第三電極7〇lc,其中第一電極面積爲總電極面 積的40%-60%’所有電極面積總和與半導體晶片面積之比 大於0.85。該方法包括以下步驟: 步驟1 :打開流體控制裝置723a、723b和723c,以 控制母個電極工作區域的流速’在第一電極的工作 區域内,流速爲5到20 LPM,在第二電極701b的工作區 ® 域内’流速爲5到20 LPM,在第三電極701c的工作區域 内’流速爲1到15 LPM。在本發明的一個實施例中,流 體控制裝置723a、723b和723c同時打開,在本發明的另 一個實施例中’流體控制裝置723a、723b和723c在不同 的時間打開; 步驟2:傳送具有籽晶層的半導體晶片到設備中的晶 片固持裝置721上’該裝置與半導體晶片籽晶層相接觸可 爲其導電; 步驟3 :對所述半導體晶片施加一個小的偏壓,其範 14 201012976 圍在 0. 01-10V ; 步驟4 :用晶片固持裝置將晶片送到電解液中,並使 晶片的前表面完全浸入電解液; 步驟5:向電極701a 、7〇lb與7〇lc提供電流,並 保持電極701a和701b上電壓爲正,電極7〇ic上電壓爲 正或負;電極701a的工作電流爲2至20A,電極701b 的工作電流爲〇·〇1至2〇A,電極的工作電流爲on φ 至20A。電極701a與7〇lb上的電流密度比爲1 :ι至 50:1,電極70 la與701c上的電流密度比爲1:1至3〇〇:1。 此步称持續5至30秒,填充半導體晶片722表面的通孔 與溝槽。在本發明的一個實施例中,與電極7〇1&amp;、701b 和701c相連的電源同時從電壓模式切換到電流模式;在 本發明的另一個實施例中,與電極7〇la、701b和701c相 連的電源在不同的時間從電壓模式切換到電流模式; 步驟6 :向電極701a、701b與701c提供電流,並保 ® 持電極7〇la和701b上電壓爲正,電極701c上電壓爲正 或負;電極701a的工作電流爲4至30A,電極701b的工 作電流爲4至30A,電極701c的工作電流爲〇. 1至20A。 電極701a與701b上的電流密度比爲1:1至50:1,電極 7〇la與701b上的電流密度比爲1:1至300:1。此步驟在 電極701a、701b和701c上施加相對較大的電流,從而提 高電化學沈積的效率。當沈積得到要求的厚膜,終止此步 驟0 步驟7:在所述半導體晶片上施加一個小的偏壓。在 15 201012976 ,電極701a、7〇lb和701c同時從 气在本發明的另一個實施例中, c在不同的時間從電流模式切換到 步驟8:將晶片自電解液取出,旋轉清除晶片表面殘 留電解液;Method 2 (traditional) - WFNU 3. 65% 12.94% 13 201012976 In the case of the use of local conductivity and low conductivity electrolyte, the method is disclosed (method D is more traditional than method (method 2), making WFNU In the case of using a low conductivity electrolyte, the WFNU obtained is less than 2.5%. Embodiment 2 In one embodiment of the present invention, one is disclosed for use in FIG. 6 is a method for uniformly depositing a copper film on a semiconductor wafer. The device is an embodiment of the invention of FIG. 1, which comprises a first electrode 7a, a second electrode 701b, and a third electrode 7?lc, Wherein the first electrode area is 40%-60% of the total electrode area' ratio of the total electrode area to the semiconductor wafer area is greater than 0.85. The method comprises the following steps: Step 1: opening the fluid control devices 723a, 723b and 723c to control The flow rate of the working area of the parent electrode is 'in the working area of the first electrode, the flow rate is 5 to 20 LPM, and the flow rate in the working area® of the second electrode 701b is 5 to 20 LPM, in the working area of the third electrode 701c. Internal 'flow rate is 1 to 15 LPM. In this In one embodiment of the invention, the fluid control devices 723a, 723b and 723c are simultaneously opened, in another embodiment of the invention the 'fluid control devices 723a, 723b and 723c are opened at different times; Step 2: the transfer has a seed layer The semiconductor wafer is transferred to the wafer holding device 721 in the device. The device is in contact with the seed layer of the semiconductor wafer to conduct electricity. Step 3: Apply a small bias voltage to the semiconductor wafer, and the radius 14 201012976 is around 0. 01-10V; Step 4: Using a wafer holding device to send the wafer into the electrolyte and completely immersing the front surface of the wafer into the electrolyte; Step 5: supplying current to the electrodes 701a, 7〇lb and 7〇lc, and maintaining The voltages on the electrodes 701a and 701b are positive, the voltage on the electrode 7〇ic is positive or negative; the operating current of the electrode 701a is 2 to 20A, and the operating current of the electrode 701b is 〇·〇1 to 2〇A, and the operating current of the electrode is On φ to 20 A. The current density ratio on the electrodes 701a and 7〇lb is 1:1 to 50:1, and the current density ratio on the electrodes 70la and 701c is 1:1 to 3〇〇:1. 5 to 30 seconds, a through hole filling the surface of the semiconductor wafer 722 And a trench. In one embodiment of the invention, the power supply connected to the electrodes 7〇1 &amp; 701b and 701c is simultaneously switched from a voltage mode to a current mode; in another embodiment of the invention, the electrode 7〇la The power supplies connected to 701b and 701c are switched from the voltage mode to the current mode at different times; Step 6: supplying current to the electrodes 701a, 701b, and 701c, and maintaining the voltage on the electrodes 7〇la and 701b as positive, on the electrode 701c The voltage is positive or negative; the operating current of the electrode 701a is 4 to 30 A, the operating current of the electrode 701b is 4 to 30 A, and the operating current of the electrode 701c is 0.1 to 20 A. The current density ratio on the electrodes 701a and 701b is 1:1 to 50:1, and the current density ratio on the electrodes 7〇la and 701b is 1:1 to 300:1. This step applies a relatively large current to the electrodes 701a, 701b, and 701c, thereby improving the efficiency of electrochemical deposition. When the desired thick film is deposited, this step is terminated. Step 7: Apply a small bias voltage to the semiconductor wafer. At 15 201012976, electrodes 701a, 7〇lb, and 701c are simultaneously gas-extracted. In another embodiment of the invention, c is switched from current mode to step 8 at different times: the wafer is removed from the electrolyte, and the wafer surface remains removed by rotation. Electrolyte

在上述的步驟5與步驟6中,電極7〇lc電壓的正負 符號由電化學沈積條件決定 '例如,當電解液的電導率 低,半導體晶片表面電導層厚,對電極7〇la、7〇lb* 7〇ic 同時施加正電壓,如圖8a所示;當電解液的電導率高, 半導體晶片表面電導層薄,對電極7〇1&amp;和7〇lb施加正電 壓’對電極701c施加負電壓,如圖8b所示. 步驟5中,在籽晶層爲150至2000A的3 00mm半導體 晶片上均勻電鍍銅膜所採用的電流密度比與每個電極電 壓正負符號,具體設置如表6,所採用的電解液電導率分 ❷ 本發明的一個實施例中 電流模式切換到電壓模 電極 701a、701b 和 701 電壓模式; 別爲 0. 02-0. 2S/cm 與 〇· 2-0. 8S/cm : 表6 電極 電極 電極 電流密度比 701a 的 701b 的 701c 的 (701a : (701a : 符號 符號 符號 701b) 701c) 電導率 + + + 1:1-2:1 1:1-300:1 0.02-0.2S/cm + + — 1:1-2:1 10:1-40:1 電導率 + + - 5:1-20:1 2:1-10:1 0.2-0. 8S/cm 16 201012976 當沈積的銅膜厚度達到1500A後,開始步驟6。在軒 晶層爲50至2000A·的300mm半導體晶片上均勻電鑛銅膜 所採用的電流密度比與每個電極電壓正負符號,具體設置 如表7,所採用的電解液電導率分別爲0. 0 2-0. 2S/cm與 0.2-0.8S/cm : 電極 電極 電極 —--- 電流密度比 701a 的 符號 701b 的 符號 701c 的 符號 (701a : 701b) (701a : 701c) 電導率 + + + 1:1-2:1 1:1-300:1 0. 02-0. 2S/cm + + 一 1:1-2:1 50.1-300.1 電導率 0.2-〇. 8S/cm + + 一 1:1-2:1 ~~------ 20:1-80:1In the above steps 5 and 6, the positive and negative signs of the voltage of the electrode 7〇lc are determined by the electrochemical deposition conditions. For example, when the conductivity of the electrolyte is low, the surface of the semiconductor wafer is electrically conductive, and the counter electrode 7〇la, 7〇 Lb* 7〇ic applies a positive voltage at the same time, as shown in Figure 8a; when the conductivity of the electrolyte is high, the conductive layer on the surface of the semiconductor wafer is thin, and a positive voltage is applied to the electrodes 7〇1 &amp; and 7〇lb, which is negative to the electrode 701c. The voltage is as shown in Fig. 8b. In step 5, the current density ratio and the positive and negative sign of each electrode voltage are uniformly plated on the 300 mm 2000 semiconductor wafer with a seed layer of 150 to 2000 A, as shown in Table 6. The electrolyte mode conductivity is used in one embodiment of the present invention. The current mode is switched to the voltage mode electrodes 701a, 701b, and 701. The voltage mode is 0. 02-0. 2S/cm and 〇·2-0. 8S /cm : Table 6 Electrode electrode current density ratio 701a of 701b of 701c (701a : (701a : symbol symbol 701b) 701c) Conductivity + + + 1:1-2:1 1:1-300:1 0.02 -0.2S/cm + + — 1:1-2:1 10:1-40:1 Conductivity + + - 5:1-20:1 2:1- 10:1 0.2-0. 8S/cm 16 201012976 When the thickness of the deposited copper film reaches 1500A, start step 6. The current density ratio and the positive and negative sign of the voltage of each electrode on the 300 mm semiconductor wafer of 50 to 2000 A· on the Xuan crystal layer are set as shown in Table 7. The conductivity of the electrolyte used is 0. 0 2-0. 2S/cm and 0.2-0.8S/cm : Electrode electrode electrode—symbol of symbol 701c of symbol 701b of current density ratio 701a (701a : 701b) (701a : 701c) Conductivity + + + 1:1-2:1 1:1-300:1 0. 02-0. 2S/cm + + a 1:1-2:1 50.1-300.1 Conductivity 0.2-〇. 8S/cm + + a 1: 1-2:1 ~~------ 20:1-80:1

圖9a與9b繪示了在350A籽晶層上電鍍3〇〇〇A厚銅 膜的沈積曲線,所採㈣電解液分別爲低電導率與高電導 率電解液。其中’方法1的曲線爲採用表6與表7中的工 所得方法2的曲線爲採用表6與表7所述範圍外 . 數所侍。WFNU值列於表8中。如圖9a-9b與表8 二所揭示的方法使採用高電導率與低電導率電解液沈 ::膜層的w剛均得到很大程度的改善。所述刪職 導體晶片上沈積曲線的WFNU計算排除邊緣2 3ffim區 17 201012976 域’這比通常工業中 算嚴格很多 、 用的排除邊緣3. 0到6. 5mm區域計 ❹Figures 9a and 9b illustrate the deposition curves of a 3〇〇〇A thick copper film deposited on a 350A seed layer. The (4) electrolytes are low conductivity and high conductivity electrolytes, respectively. The curve of Method 1 is that the curve of Method 2 in Table 6 and Table 7 is taken as the range outside the range described in Tables 6 and 7. The WFNU values are listed in Table 8. The method disclosed in Figures 9a-9b and Table 8 provides a significant improvement in the use of high conductivity and low conductivity electrolytes. The WFNU calculation of the deposition curve on the erased conductor wafer excludes the edge 2 3ffim area 17 201012976 domain ' This is much stricter than the usual industry, and the exclusion edge is used 3. 0 to 6. 5 mm area meter ❹

低電導率電解液 高電導率電解液Low conductivity electrolyte high conductivity electrolyte

2. 81% 8. 55% 採用间電導率與低電導率電解液的情況下,揭示方法 、、)較傳統方法(方法2)而言,均使wFNU得以顯 著文善尤其在採用低電導率電解液的情況下,得到的 WFNU 小於 2. 5%。 實施例3 在本發明的-個實施例中,揭示了 一種應用於圖1〇 所示設備的半導體晶片上均勾沈積銅膜的方法。該設備爲 圖1發明的-個實施例,它包含第-電極1001a、第二電 極1001b、第二電極i〇〇lc、和第四電極其中第 一電極面積爲總電極面積的30%-50%,所有電極面積總和 與半導體晶片面積之比大於0.85。該方法包括以下步驟: 步驟1 :打開流體控制裝置l〇23a、l〇23b、1023c和 10 2 3d以控制每個電極工作區域的流速,在電極i〇〇ia、 l〇〇lb和i〇01c的工作區域内,流速爲5到2〇 lpm,在電 18 201012976 極1 〇 01 d的工作區域内,流速爲1到1 5 LPM。在本發明 的個實施例中’流體控制裝置i〇23a、1 023b、1 023c和 1 023d同時打開,在本發明的另一個實施例中,流體控制 裝置1023a、l〇23b、1023c和l〇23d在不同的時間打開; 步驟2.傳送具有軒晶層的半導體晶片到設備中的晶 片固持裝置1021上,該裝置與半導體晶片籽晶層相接觸 可爲其導電; φ 步驟3 :.對所述半導體晶片施加一個小的偏壓,其範 圍在 0.01-10V ; 步驟4:用晶片固持裝置將晶片送到電解液中,並使 晶片的前表面完全浸入電解液; 步驟 5:向電極 i〇01a 、i〇olb 、i〇〇ic 與 l〇〇ld 提 供電流,並保持電極1〇〇la、1〇〇113和1〇〇lc上電壓爲正, lOOld上電麼爲正或負;電極iQoia的工作電流爲1至 15A’電極i〇〇ib的工作電流爲〇 5至1〇A,電極i〇〇lc ❹ 與的工作電流爲〇 〇1至i〇A。電極i〇〇ia與i〇〇ib 上的電流密度比爲0.5:1至1〇:1,電極1〇〇1&amp;與i〇〇lc 上的電流密度比爲〇.5:1至50:1,電極1〇〇1&amp;與1〇〇ld 上的電流密度比爲1 :1至300 :卜此步驟持續5至3〇秒, 填充半導體晶片1 022表面的通孔與溝槽。在本發明的一 個實施例中,與電極l〇〇la、1001b、1〇01〇和1001(1相連 的電源同時從電壓模式切換到電流模式;在本發明的另一 個實施例中’與電極l〇01a、1001b、1〇〇1(:和1001(1相連 的電源在不同的時間從電壓模式切換到電流模式; 19 201012976 步驟 6:向電極 l〇〇la 、l〇〇lb 、1001c 與 l〇〇ld 提 供電流,並保持電極1001a、1001b和1001c上電壓爲正, 電極1001d上電壓爲正或負;電極1001a的工作電流爲2 至30A,電極l〇〇lb的工作電流爲1至30A,電極1001c 的工作電流爲1至30A,電極100Id的工作電流爲〇. 01 至2(^。電極1〇〇1&amp;與1〇〇1!3上的電流密度比爲〇.5:1至 10:1,電極l〇〇la與1001c上的電流密度比爲0 5:1至 ❹ 50 :卜電極1001a與1001d上的電流密度比爲1:1至 300:1。此步驟在電極 1001a、i〇〇lb、1〇〇1(:和 1〇〇1(1 上 施加相對較大的電流,從而提高電化學沈積的效率。當沈 積得到要求的厚膜,終止此步驟。 步驟7 :在所述半導體晶片上施加一個小的偏壓。在 本發明的一個實施例中,電極1〇〇la、i〇〇ib、i〇01c和 1001d同時從電流模式切換到電壓模式;在本發明的另一 個實施例中’電極l〇〇la、l001b、1001c* i001(i在不同 〇 的時間從電流模式切換到電壓模式; 步驟8:將晶片自電解液取出,旋轉清除晶片表面殘 留電解液; 在上述的步驟5與步驟6中,電極l〇〇ld電壓的正負 符號由電化學沈積條件決定。例如,當電解液的電導率 低’半導體晶片表面電導層厚,對電極l〇〇la、l〇〇lb、 1001c和looid同時施加正電壓,如圖lla所示;當電解 液的電導率高,半導體晶片表面電導層薄,對電極l〇〇la、 1001b和looic施加正電壓,對電極1〇〇ld施加負電壓, 20 201012976 如圖lib所示。 步驟5中,在籽晶層爲50至2000Α的30 0mm半導體 晶片上均勻電鍍銅膜所採用的電流密度比與每個電極電 壓正負符號,具體設置如表9,所採用的電解液電導率分 別爲 0. 0 2-0. 2S/cm 與 0_ 2-0· 8S/cm : 表9 電極 1001a 的符號 電極 1001b 的符號 電極 1001c 的符號 電極 1001d 的符號 電流密度比 (1001a : 1001b) (1001a : 1001c) (1001a : 1001d) 電導率 0. 02-0. 2 S/cm + + + + 0.5:1-2: 1 0.5:1-10 :1 1:1-300: 1 + + + - 0.5:1-2: 1 0.5:1-3: 1 10:1-100 :1 電導率 0. 2-0.8S /cm + + + 1:1-2:1 4:1-30:1 2:1-20:1 參 參 當沈積的銅膜厚度達到1500A後,開始步驟6。在籽 晶層爲.50至2000A的300mm半導體晶片上均勻電鍍铜膜 所採用的電流密度比與每個電極電壓正負符號’具體設置 如表10,所採用的電解液電導率分別爲0.02-0.2S/cm與 〇.2-0.8S/cm : 21 201012976 表ίο 電極 1001a 的符號 電極 1001b 的符號 電極 1001c 的符號 電極 1001d 的符號 電流密度比 (1001a : 1001b) (1001a : 1001c) (1001a : 1001d) 電導率 0. 02-0. 2 S/cm + + + + 1:1-2:1 1:1-10: 1 1:1-300 :1 + + + 一 0.5:1-2 :1 0.5:1-1 0:1 10:1-30 0:1 電導率 0. 2-0. 8S /cm + + + 1:1-2:1 1:1-2:1 1:1-250 :1 圖12a與12b繪示了在35 0A籽晶層上電鍍300 0A厚 銅膜的沈積曲線,所採用的電解液分別爲低電導率與高電 導率電解液。其中’方法1的曲線爲採用表9與表10中 ❷ 的工藝參數所得,方法2的曲線爲採用表9與表10所述 範圍外的工藝參數所得。WFNU值列於表11中。如圖 1 2 a-1 2b與表11所示’所揭示的方法使採用高電導率與 低電導率電解液沈積3000A膜層的WFNU均得到很大程度 的改善。所述300mm半導體晶片上沈積曲線的WFNU計算 排除邊緣2. 3mm區域,這比通常工業中採用的排除邊緣 3. 0到6. 5mm區域計算嚴格很多。 22 201012976 低電導率電解液 高電導率電解液 方法1 (揭示的= 〇· 33¾ λ 66% 方法2 (傳統的)_2. 81% 8. 55% using inter-conductivity and low-conductivity electrolytes, revealing methods, and more than traditional methods (method 2), make wFNU significantly good, especially in low conductivity 5%。 The WFNU is less than 2.5%. [Embodiment 3] In one embodiment of the present invention, a method of depositing a copper film on a semiconductor wafer applied to the apparatus shown in Fig. 1A is disclosed. The device is an embodiment of the invention of FIG. 1 and includes a first electrode 1001a, a second electrode 1001b, a second electrode i〇〇lc, and a fourth electrode, wherein the first electrode area is 30% of the total electrode area - 50 %, the ratio of the sum of all electrode areas to the area of the semiconductor wafer is greater than 0.85. The method comprises the following steps: Step 1: Opening the fluid control devices 13a, 23b, 1023c and 10 2 3d to control the flow rate of each electrode working region at the electrodes i〇〇ia, l〇〇lb and i〇 In the working area of 01c, the flow rate is 5 to 2 〇 lpm, and the flow rate is 1 to 15 LPM in the working area of the electric 18 201012976 pole 1 〇 01 d. In one embodiment of the invention, the 'fluid control devices i〇23a, 1 023b, 1 023c and 1 023d are simultaneously opened. In another embodiment of the invention, the fluid control devices 1023a, l23b, 1023c and l〇 23d is opened at different times; Step 2. Transfer the semiconductor wafer having the enamel layer to the wafer holding device 1021 in the device, and the device is in contact with the seed layer of the semiconductor wafer to conduct electricity; φ Step 3: The semiconductor wafer is applied with a small bias voltage ranging from 0.01 to 10 V. Step 4: The wafer holding device is used to send the wafer to the electrolyte, and the front surface of the wafer is completely immersed in the electrolyte; Step 5: To the electrode i 01a, i〇olb, i〇〇ic, and l〇〇ld provide current, and keep the voltages on electrodes 1〇〇la, 1〇〇113, and 1〇〇lc positive, and lOOld is positive or negative when energized; The operating current of iQoia is 1 to 15A'. The operating current of the electrode i〇〇ib is 〇5 to 1〇A, and the operating current of the electrode i〇〇lc ❹ is 〇〇1 to i〇A. The current density ratio of the electrodes i〇〇ia and i〇〇ib is 0.5:1 to 1〇:1, and the current density ratio of the electrodes 1〇〇1&amp; and i〇〇lc is 〇.5:1 to 50: 1. The current density ratio of the electrodes 1〇〇1&amp; and 1〇〇ld is 1:1 to 300: this step lasts 5 to 3 seconds, filling the vias and trenches of the surface of the semiconductor wafer 1 022. In one embodiment of the invention, the power supplies connected to the electrodes 10a, 1001b, 1〇01, and 1001 (1 are simultaneously switched from voltage mode to current mode; in another embodiment of the invention 'with electrodes L〇01a, 1001b, 1〇〇1 (: and 1001 (1 connected power supply switches from voltage mode to current mode at different times; 19 201012976 Step 6: To the electrodes l〇〇la, l〇〇lb, 1001c and L〇〇ld provides current and keeps the voltage on electrodes 1001a, 1001b and 1001c positive, the voltage on electrode 1001d is positive or negative; the operating current of electrode 1001a is 2 to 30A, and the operating current of electrode l〇〇lb is 1 to 30A, the operating current of the electrode 1001c is 1 to 30A, and the operating current of the electrode 100Id is 〇. 01 to 2 (^. The current density ratio of the electrode 1〇〇1&amp; and 1〇〇1!3 is 〇.5:1 To 10:1, the current density ratio on the electrodes l〇〇la and 1001c is from 0:5 to ❹50: the current density ratio on the electrodes 1001a and 1001d is 1:1 to 300:1. This step is at the electrode 1001a. , i〇〇lb, 1〇〇1 (: and 1〇〇1 (1 applies a relatively large current, thereby improving the efficiency of electrochemical deposition. This step is terminated by depositing the desired thick film. Step 7: Apply a small bias voltage to the semiconductor wafer. In one embodiment of the invention, the electrodes 1〇〇la, i〇〇ib, i〇01c Switching from current mode to voltage mode simultaneously with 1001d; in another embodiment of the invention 'electrode l〇〇la, l001b, 1001c* i001 (i switches from current mode to voltage mode at different times; step 8: The wafer is taken out from the electrolyte and rotated to remove residual electrolyte on the surface of the wafer; in the above steps 5 and 6, the positive and negative signs of the voltage of the electrode lld are determined by electrochemical deposition conditions. For example, when the conductivity of the electrolyte is low 'The surface of the semiconductor wafer is electrically conductive, and the electrodes l〇〇la, l〇〇lb, 1001c and looid are simultaneously applied with a positive voltage, as shown in FIG. 11a; when the conductivity of the electrolyte is high, the surface of the semiconductor wafer is thin, The electrodes l〇〇la, 1001b, and looic apply a positive voltage, and a negative voltage is applied to the electrode 1〇〇ld, 20 201012976 as shown in lib. In step 5, uniform on the 30 mm semiconductor wafer with a seed layer of 50 to 2000 Å. The current density ratio of the copper plating film and the positive and negative sign of each electrode voltage are set as shown in Table 9. The conductivity of the electrolyte used is 0. 0 2-0. 2S/cm and 0_ 2-0· 8S/ Cm : Table 9 Symbolic current density ratio of the symbol electrode 1001c of the symbol electrode 1001b of the electrode 1001a (1001a: 1001b) (1001a: 1001c) (1001a: 1001d) Conductivity 0. 02-0. 2 S/cm + + + + 0.5:1-2: 1 0.5:1-10 :1 1:1-300: 1 + + + - 0.5:1-2: 1 0.5:1-3: 1 10:1-100 :1 Conductivity 0. 2-0.8S /cm + + + 1:1-2:1 4:1-30:1 2:1-20:1 Reference Step When the thickness of the deposited copper film reaches 1500A, start step 6. The current density ratio and the positive and negative sign of each electrode voltage on the 300mm semiconductor wafer with a seed layer of .50 to 2000A are set as shown in Table 10. The conductivity of the electrolyte used is 0.02-0.2. S/cm and 〇.2-0.8S/cm : 21 201012976 Table ί The symbol current density ratio of the symbol electrode 1001d of the symbol electrode 1001b of the electrode 1001a of the electrode 1001a (1001a: 1001b) (1001a: 1001c) (1001a: 1001d) The conductivity is 0. 02-0. 2 S/cm + + + + 1:1-2:1 1:1-10: 1 1:1-300 :1 + + + a 0.5:1-2 :1 0.5 :1-1 0:1 10:1-30 0:1 Conductivity 0. 2-0. 8S /cm + + + 1:1-2:1 1:1-2:1 1:1-250 :1 Figures 12a and 12b illustrate the deposition curves of a 300 0A thick copper film deposited on a 35 0A seed layer, using electrolytes of low conductivity and high conductivity, respectively. The curve of Method 1 is obtained by using the process parameters of Table 9 and Table 10, and the curve of Method 2 is obtained by using the process parameters outside the range described in Table 9 and Table 10. The WFNU values are listed in Table 11. The method disclosed in Figures 1 2 a-1 2b and Table 11 provides a significant improvement in the deposition of the 3000A film layer with high conductivity and low conductivity electrolyte. The WFNU calculation of the deposition curve on the 300 mm semiconductor wafer excludes the edge 2. 3 mm area, which is much stricter than the exclusion edge used in the usual industry 3. 0 to 6. 5 mm area. 22 201012976 Low conductivity electrolyte High conductivity electrolyte Method 1 (disclosed = 〇 · 333⁄4 λ 66% Method 2 (conventional) _

WFNUWFNU

採用高電導率與低電導 (方法1)較傳統方法(方法 的情況下,揭示方法 著改善。尤其在採用彻世《 2)而言,均使WFNU得以顯 六·你休用低電導 WFNU小於2. 5%。 液的情況下,得到的 例4 本發明的上述方法用於 用於美國專利6391 1 66揭示的簡 單電極結構設備中,本發 个赞月揭不方法也按類似地方案設 參 計’應用於具有多於四個電極的電極結構的設備中,其 中該結構的第一電極面積爲總電極面積# 5%一3〇%,所 有電極面積總和與半導體晶片面積之比大於。85。 在軒晶層爲50至2000A的300mm半導體晶片上均勻 電鍛10 0A至1500A厚銅膜所採用的電流密度比與每個電 極電壓正負符號,具體設置如表12,所採用的電解液電 導率分別爲0· 02-0. 2S/cm與〇. 2-0. 8S/cm。在此情況下, 電鑛設備具有N個電極,N可在5至15之間變化。 23 201012976 表 12 第一 第二至第 第N-1 第N電 電流密度比 電極 N-2電極 電極符 極符號 El : E2… (El : (El : 符號 符號 號 En-2 En-1) En) 電導率 + + + + 0.8:1-2: 0.5:1-10 1:1-30 0. 02-0. 2 1 :1 0:1 S/cra + + + - 0.5:1-2: 0.5:1-3: 10:1-1 1 1 00:1 電導率 + + + - 1:1-2:1 4:1-40:1 2:1-10 0. 2-0.8S 0:1 /cm 之後,在籽晶層爲50至2000A的300mm半導體晶片 上均勻電鍍剩餘部分銅膜所採用的電流密度比與每個電 極電壓正負符號,具體設置如表13,所採用的電解液電 參 導率分別爲 0. 02-0. 2S/cm 與 0. 2-0. 8S/cm : 24 201012976 表13 第一 第二至 第N-1 第N電 -----^ 電流密度tl* -- 電極 第N-2 電極 極符 El : -----(E1 : ------- (E1 : 符號 電極符 符號 號 E2… En-l) En) 號 En-2 電導率 + + + + 1:1-2:1 --—-. 1:1-10 ------- 1:1-30 0.02-0. :1 0:1 2S/cm + + + - 0.5:1-2 1 — 一 0.5:1- 10:1-3 :1 10:1 00.1 電導率 + + + 一 1:1-2:1 1:1-2: —— 1:1-30 0. 2-0. 8 1 0:1 S/cm ❹ 表13繪示了在分別採用低電導率電解液1與高電導 率電解液2的情況下,用所述設備在350A籽晶層上電鑛 β 300 0Α厚銅膜的沈積曲線《其中,所述實施例設備具有十 個獨立可控電極。用本發明方法得到的WFNU值大大低於 2. 5%,分別爲電解液i中爲〇 26%,電解液2中爲〇. 59%。 在本發明揭示的方法的基礎上,得到的WFNU可隨電 極數量N增加而改善。當採用電極數量大於J的設備時, 用這些方法在具350A籽晶層晶片上電鍍銅膜可得到小於 ·. 2.5%的WFNU。當N增加到4,在同樣的晶片與籽晶層上電 鑛得到的WFNU降至〇,33%。 25 201012976 將本發明揭示的方法與美國專利6755954揭示的方 法進仃對比1持所有條件㈣·⑴多電極 解液電料=〇.5 s/Cffi,⑻軒晶層厚度= 400A⑷ 二,度=6_,以及⑸排除晶片邊緣2n s 爲了直接比較,使用厚度均勻範圍取代WFNU。 圖Η綠示了用本發明揭示的方法計算出的沈積曲線。厚 度均勻範圍的對比值列於表14 e 表14The use of high conductivity and low conductance (method 1) is more traditional than the method (method of the method, revealing the improvement of the method. Especially in the case of the use of the world "2), both make WFNU visible. You use low conductance WFNU is less than 2. 5%. In the case of a liquid, the obtained example 4 of the present invention is used in a simple electrode structure apparatus disclosed in U.S. Patent No. 6,391,166, and the method of the present invention is applied to a similar method. In an apparatus having an electrode structure of more than four electrodes, wherein the first electrode area of the structure is the total electrode area #5% to 3%, and the ratio of the sum of all the electrode areas to the area of the semiconductor wafer is larger than. 85. The current density ratio and the positive and negative sign of each electrode voltage are uniformly electric forged on a 300 mm semiconductor wafer of 50 to 2000 A in a layer of 50 to 2000 A. The specific setting is as shown in Table 12, and the electrolyte conductivity used is as shown in Table 12. 2·0-0. 2S/cm and 〇. 2-0. 8S/cm. In this case, the electrominening device has N electrodes and N can vary between 5 and 15. 23 201012976 Table 12 First to Nth N-1 Nth electric current density ratio electrode N-2 electrode electrode polarity symbol El : E2... (El : (El : symbol symbol En-2 En-1) En Conductivity + + + + 0.8:1-2: 0.5:1-10 1:1-30 0. 02-0. 2 1 :1 0:1 S/cra + + + - 0.5:1-2: 0.5 :1-3: 10:1-1 1 1 00:1 Conductivity + + + - 1:1-2:1 4:1-40:1 2:1-10 0. 2-0.8S 0:1 / After cm, the current density ratio and the positive and negative sign of each electrode voltage are uniformly plated on a 300 mm semiconductor wafer with a seed layer of 50 to 2000 A. The specific settings are as shown in Table 13, and the electrolyte is used. The rate is 0. 02-0. 2S/cm and 0. 2-0. 8S/cm : 24 201012976 Table 13 First second to N-1 Nth electric -----^ Current density tl* - - Electrode No. N-2 Electrode is El: -----(E1 : ------- (E1 : symbol electrode symbol No. E2... En-l) En) No. En-2 Conductivity + + + + 1:1-2:1 ----. 1:1-10 ------- 1:1-30 0.02-0. :1 0:1 2S/cm + + + - 0.5:1 -2 1 — A 0.5:1- 10:1-3 :1 10:1 00.1 Conductivity + + + A 1:1-2:1 1:1-2: —— 1:1-30 0. 2-0. 8 1 0:1 S/cm ❹ Table 13 shows the use of low conductivity electrolyte 1 and high conductivity electrolyte 2 respectively. In the case of the apparatus, a deposition curve of a beta 300 0 thick copper film on a 350A seed layer is used, wherein the apparatus of the embodiment has ten independently controllable electrodes. The WFNU value obtained by the method of the present invention is much lower than 2.5%, which is 〇26% in the electrolyte i and 〇.59% in the electrolyte 2. Based on the method disclosed in the present invention, the obtained WFNU can be improved as the number of electrodes N increases. When a device having a larger number of electrodes than J is used, the copper film is plated on a 350A seed layer wafer by these methods to obtain less than 2. 2.5% of WFNU. When N is increased to 4, the WFNU obtained by electrowinning on the same wafer and seed layer is reduced to 〇, 33%. 25 201012976 The method disclosed in the present invention is compared with the method disclosed in U.S. Patent No. 6,755,954. All conditions are met (4)·(1) Multi-electrode liquid-repellent electric material=〇.5 s/Cffi, (8) Xuanjing layer thickness=400A(4) Second, degree= 6_, and (5) exclude the edge of the wafer 2n s For direct comparison, replace the WFNU with a uniform thickness range. The green color shows the deposition curve calculated by the method disclosed in the present invention. Contrast values for the uniform range of thickness are listed in Table 14 e Table 14

均勻範圍 240A 揭示方法的厚度均勻範圍Uniform range 240A reveals the uniform thickness range of the method

138. 4A 本發明揭示方法得到的沈積銅膜的WFNu爲0.72%, 厚度均勻範圍爲138.4A,與美國專利6?55954揭示方法 相比改善了 2倍。 【圖式簡單說明】 圖1繪示本方法採用的已有發明中所述設備的示意 圖; 圖2繪示單一電極電鍍設備的局部示意圖; 圖3a-3d繪示採用單一電極電鍍設備獲得的沈積曲 線; 圖4繪示具有兩個電極電鍍設備的局部示意圖; 圖5a和5b繪示兩電極設備所採用的波形圖; 26 201012976 圖6a和6b _示採用兩電極設備獲得的沈積曲線; 圖7繪示具有三個t極電鍍設備的局部示意圖; 圖8a和8b、繪示三電極設備所採用的波形圖; 圖9a和9b冑示採用三電極設備獲得的沈積曲線; 圖10料具有四個電極電鍛設備的局部示意圖; 圖11a和lib繪示四電極設備所採用的波形圖; 圖12a和12b繪示採用四電極設備獲得的沈積曲線; ❹ 圖13繪示採用十電極設備獲得的沈積曲線; 圖14緣示計算得到的沈積曲線; 【主要元件符號說明】 401a、701a、1001a :第—電極 401b、701b、1001b :第二電極 701c、1001c :電三電極 1001d :第四電極 ❹ 421、721、1021 :晶片固持裝置 422、722、1022 :半導體晶片 423a、 423b、 723a、 723b' 723c、 1023a、 1023b、 1023c、 1023d :流體控制裝置 27138. 4A The deposited copper film obtained by the method of the present invention has a WFNu of 0.72% and a uniform thickness range of 138.4 A, which is 2 times better than the method disclosed in U.S. Patent No. 6,555,954. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing the apparatus of the prior invention used in the method; FIG. 2 is a partial schematic view showing a single electrode plating apparatus; and FIGS. 3a-3d are diagrams showing deposition by a single electrode plating apparatus. Figure 4 is a partial schematic view of a two-electrode plating apparatus; Figures 5a and 5b show waveform diagrams used in a two-electrode device; 26 201012976 Figures 6a and 6b show the deposition curves obtained using a two-electrode device; A partial schematic diagram of a three-electrode plating apparatus is shown; Figures 8a and 8b show waveform diagrams used in a three-electrode apparatus; Figures 9a and 9b show deposition curves obtained using a three-electrode apparatus; FIG. 11a and lib show waveform diagrams used in a four-electrode device; FIGS. 12a and 12b show deposition curves obtained using a four-electrode device; ❹ FIG. 13 depicts deposition obtained using a ten-electrode device Fig. 14 shows the calculated deposition curve; [Major component symbol description] 401a, 701a, 1001a: first electrode 401b, 701b, 1001b: second electrode 701c, 1001c: electric three Electrode 1001d: fourth electrode 421 421, 721, 1021: wafer holding device 422, 722, 1022: semiconductor wafer 423a, 423b, 723a, 723b' 723c, 1023a, 1023b, 1023c, 1023d: fluid control device 27

Claims (1)

201012976 七 、申請專利範圍 1 一種用於具有二個電極的電化學沈積均勻銅膜設 備的方法,包括以下步驟,其中第—電極面積爲總電極面 積的 50%-9〇% : 將硫酸鋼電解液注入所述設備,流量爲1至2〇LpM; 將半導體晶片傳送到晶片固持裝置上,使該裝置與晶 片電導層有導電接觸; ❹ 參 打開電源,爲半導體晶g1 τ守疲日日月徒供最大可至1〇v的偏壓; 將半導體晶片送到電解液中與之相接觸;: 保持第一電極電壓相對晶片爲正; 進行第一步電鍍工藝,向各雷 门合冤極鉸供和爲2A至10A 的總電流’當第二電極 罨壓相對晶片爲正時,第一電極與 第一電極電流密度比爲 a u ^ 场川.1,當第二電極電壓相對 日日片爲負時’第一電極與第— 征兴弟一電極電流密度比爲 2:1-3〇:1 ; ^ 進行第一步電鍍工藝,向各雷 λα减α 口合冤極扣供和爲10Α至40Λ 的總電流,當第二電極電壓相對 T曰曰乃舄正時,第一電極與 第一電極電流密度比爲1 1-3 曰κ &amp; 6 ± 利.1,*第二電極電壓相對 曰日片爲負時’第一電極與 10:1-30:!; ㈣電流密度比爲 切換電源向半導體晶片提供最大 崁供被大可至ιον的偏壓; 將半導體晶片自電解液取出。 如申請專利範圍第1項所述的方法,丨中所有電 28 201012976 極的總面積與晶片面積之比大於〇85。 3·如申請專利範圍第丨項所述的方法, 穴T延行繁 —步電鍍工费時,當第二電極的電壓相對晶片爲負,在 導率爲0.02至〇. 2S/cm電解液中,第—電極與第_ 電流密度比爲15:1-30:1。 —電極 〇 4.如申請專利範圍第1項所述的方法,其中進行第 -步電鐘卫藝時,當第二電極的電壓相對晶片爲負, 導率爲0.2至0.8s/cmf:解液中,第—電極與第二 電流密度比爲2:1-15:1。 5·如中請專利範圍第!項所述的方法,其中進行第 二步電鍍工藝時,當第二電極的電壓相對晶片爲負,在電 導率爲0.02至〇.2s/cm電解液中,第—電極與第二電極 ❷ 電流密度比爲15: 1-30:1。 6.如申睛專利範圍第1項所述的方法,其中進行第 二步電鐘工藝時,當第二電極的電壓相對晶片爲負,在電 導率爲〇·2至〇.8^電解液中,第—電極與第:電極 電流密度比爲1〇:卜2〇.1。 , 7.如申請專利範圍第1項所述的方法,其中半導體 晶片軒晶層厚度爲5〇至9〇〇A。 29 201012976 曰Η 申凊專利範圍第1項所述的方法,其中半導體 曰曰片電趟鋼膜的_調節到〇.2%至2 5%範圍内。 9· 4請專利範園第i項所述的方法,其中各電極 置於同1向高度。 電極 如申請專利範圍第1項所述的方法,苴 置於不同縱向高度。 U.-種用於具有三個電極的電化學沈積均勾銅膜設 備的方法,包括以下步驟’其中[電極面積爲總電極面 積的 40%-6〇% : 將硫酸銅電解液注入所述設備,流量爲!至2〇LpM; 將半導趙晶片#送到晶片固持裝置上,使該裝置與晶 片電導層有導電接觸; ❹ 打開電源,爲半導體晶片提供最大可至1〇v的偏壓. 將半導體晶片送到電解液中與之相接觸; 保持第一電極電壓相對晶片爲正; 進行第一步電鍍工藝’向各電極提供和爲2A至1〇八 的總電流,當第三電極電壓相對晶片爲正時,笛 ^ 4 弟一電極與 第二電極電流密度比爲,第一電極與第三電極電 流密度比爲1:1-300:1’當第三電極電壓相對晶片爲負 時,第一電極與第二電極電流密度比爲11—20^,第一 電極與第三電極電流密度比爲2:1-40:1 ; 201012976 進行第二步電鍍工藝,向各電極提供和爲1〇A至4〇A - 的總電流,當第三電極電壓相對晶片爲正時,第一電極與 第二電極電流密度比爲1:卜2:1,第一電極與第三電極電 流密度比爲1 : 1 -300: 1,當第三電極電壓相對晶片爲負 時,第一電極與第二電極電流密度比爲1:卜2:1,第一電 極與第三電極電流密度比爲20:卜300: 1 ; 切換電源向半導體晶片提供最大可至1〇v的偏塵; 將半導體晶片自電解液取出。 12·如申請專利範圍第丨丨項所述的方法其中所有 電極的總面積與晶片面積之比大於〇 85。 13·如申請專利範圍第u項所述的方法其中進行 第一步電鍍工藝時,當第三電極的電壓相對晶片爲負,在 電導率爲0. 02至〇. 2S/cm電解液中,第一電極與第_ 極電流密度比爲1:卜2:1,第一電極與第=雷搞蕾 。一电極電流密度 比爲 10:1-40: 1。 14·如申請專利範圍第11項所述的方法, 第一步電鍍工藝時,當第三電極的電壓相對晶片爲負, 電導率爲〇. 2至〇. 8s/cm電解液中’第一電極與第一在 極電流密度比爲5: 1-20:1,第一電極與第_發&amp; &amp;電 —冤極電流密 度比爲 2:1-10:1。 Φ 31 201012976 15·如申請專利範圍第u項所述的方 忠,具中進行 第二步電鍍工藝時,當第三電極的電壓相對晶片爲負, 電導率爲0_ 02至〇. 2S/CID電解液中,第一 命、在 电極興第二雷 極電流密度比冑1:卜2:1,,第—電極與第三電 度比爲50··卜300:1。 ;11达 16.如申請專利範園第11項所述的方法,並… 第二步電鍵工藝時,當第三電極的電屢相對晶片爲負,: 電導率爲0.2S 〇.8S/cm電解液中’第_電極虚第二電 極電流密度比爲,第一電極與第三電極電流密度 比爲20:卜80:1。 其中半導 17.如申請專利範圍第U項所述的方法 體晶片籽晶層厚度爲50至900A。 Φ I8·如申請專利範圍第1項所述的方法,其中半導體 晶片上電鍵銅膜的WFNU調節到〇. 2%至2. 5%範圍内。 19.如申請專利範圍第U項所述的方法,其中各電 極置於同一縱向高度。 20 ·如申請專利範圍第 極置於不同縱向高度。 11項所述的方法, 其中各電 32 201012976 21. —種用於具有四個或四個以上電極的電化學沈積 • 均勻銅膜設備的方法,包括以下步驟,其中第一電極面積 爲總電極面積的5%至50%, 將硫酸銅電解液注入所述設備,流量爲丨至2〇LpM ; 將半導體晶片傳送到晶片固持裝置上,使該裝置與晶 片電導層有導電接觸; 打開電源,爲半導體晶片提供最大可至丨〇v的偏壓; _ 將半導體晶片送到電解液中與之相接觸; 保持第一電極電壓相對晶片爲正; 進行第一步電鍍工藝,向各電極提供和爲以至 的總電流,當第末個電極電壓相對晶片爲正時,第一電極 與第二電極電流密度比爲0.5:1-10:1,第一電極與第末 個電極電流密度比爲i :卜300:卜第一電極與其他電極電 流密度比爲0.5:1-2:卜當第末個電極電壓相對晶片爲負 時,第一電極與第二電極電流密度比爲〇 5:12:1,第二 φ 電極與第末個電極電流密度比爲Id-300:1,第一電極與 其他電極電流密度比爲0.5:卜30:1; 進行第二步電鍵工藝,向各電極提供和爲1〇A至4〇a 的總電流,當第末個電極電壓相對晶片爲正時第一電極 與第二電極電流密度比爲〇.5:1-1〇:1,第一電極與第末 個電極電流密度比爲1:1 -300:1,第一電極與其他電極電 流密度比爲0.8:卜2:卜當第末個電極電壓相對晶片爲負 時,第一電極與第二電極電流密度比爲〇5:1_2:1,第— • 電極與第末個電極電流密度比爲1 : 1-300: 1,第一電極與 33 201012976 其他電極電流密度比爲〇. 5 : 1 __丨〇 .夏,· 1 的偏壓; 切換電源向半導體晶片提供最大可至 將半導體晶片取出電解液。 22·如中請專利錢第21項所述的方法,其 電極的總面積與晶片面積之比大於〇 85。201012976 VII. Patent Application No. 1 A method for electrochemically depositing a uniform copper film device having two electrodes, comprising the following steps, wherein the first electrode area is 50%-9% of the total electrode area: electrolysis of sulfuric acid steel The liquid is injected into the apparatus at a flow rate of 1 to 2 〇LpM; the semiconductor wafer is transferred to the wafer holding device to make the device electrically contact with the wafer conducting layer; the 参 打开 opens the power source, and the semiconductor crystal g1 τ is kept weak. A bias voltage of up to 1 〇V is supplied; the semiconductor wafer is brought into contact with the electrolyte; the first electrode voltage is kept positive with respect to the wafer; and the first electroplating process is performed to the respective gates of the thunder The total current of the hinge is 2A to 10A. When the second electrode is positive with respect to the wafer, the current density ratio of the first electrode to the first electrode is au ^ field.1, when the second electrode voltage is relative to the day slice When it is negative, the ratio of the current density of the first electrode to the first electrode is 2:1-3〇:1; ^ The first step of the electroplating process is performed, and the supply of each of the λα minus α 10 to 40 总 total electricity Flow, when the second electrode voltage is relatively positive with respect to T曰曰, the current density ratio of the first electrode to the first electrode is 1 1-3 曰 κ &amp; 6 ± . .1, * the second electrode voltage is relative to the 曰 片When negative, the first electrode and 10:1-30:!; (4) current density ratio for the switching power supply to the semiconductor wafer to provide the maximum 崁 to the bias of ιον; the semiconductor wafer is taken out of the electrolyte. As in the method described in claim 1, the ratio of the total area of the electrodes to the wafer area is greater than 〇85. 3. If the method described in the third paragraph of the patent application is applied, the hole T is extended to the step-by-step plating time, when the voltage of the second electrode is negative with respect to the wafer, the conductivity is 0.02 to 2 S/cm electrolyte. The ratio of the first electrode to the _th current density is 15:1-30:1. The method of claim 1, wherein when the first step clock is performed, when the voltage of the second electrode is negative with respect to the wafer, the conductivity is 0.2 to 0.8 s/cmf: in the solution The ratio of the first electrode to the second current density is 2:1-15:1. 5. Please ask for the scope of patents! The method according to the item, wherein, when the second step of the electroplating process is performed, when the voltage of the second electrode is negative with respect to the wafer, in the electrolyte having an electric conductivity of 0.02 to 2.2 s/cm, the first electrode and the second electrode ❷ current The density ratio is 15: 1-30:1. 6. The method according to claim 1, wherein in the second step of the electric clock process, when the voltage of the second electrode is negative with respect to the wafer, the conductivity is 〇·2 to 〇.8^ electrolyte The ratio of the current density of the first electrode to the first electrode is 1 〇: 卜2〇.1. 7. The method of claim 1, wherein the semiconductor wafer layer has a thickness of 5 Å to 9 Å. 29 201012976 凊 The method of claim 1, wherein the semiconductor 趟 趟 趟 steel film is adjusted to within 2 2% to 2 5%. 9·4 Please refer to the method described in item i of the patent garden, in which the electrodes are placed at the same 1-direction height. Electrode The method described in claim 1 is placed at different longitudinal heights. U.- A method for an electrochemical deposition uniform copper film apparatus having three electrodes, comprising the following steps 'where [electrode area is 40%-6% of total electrode area: copper sulfate electrolyte is injected into the Equipment, traffic is! Up to 2〇LpM; send the semi-conductive wafer to the wafer holding device, so that the device has conductive contact with the wafer conducting layer; ❹ turn on the power supply to provide the semiconductor wafer with a bias voltage of up to 1〇V. Sending to the electrolyte to be in contact with it; maintaining the first electrode voltage positive with respect to the wafer; performing the first step of the plating process 'providing a total current of 2A to 1-8 to each electrode, when the third electrode voltage is relative to the wafer Timing, the ratio of the current density of the electrode to the second electrode of the flute is 4: the current density ratio of the first electrode to the third electrode is 1:1-300:1', when the third electrode voltage is negative relative to the wafer, the first The current density ratio of the electrode to the second electrode is 11-20^, and the current density ratio of the first electrode to the third electrode is 2:1-40:1; 201012976 performs the second step electroplating process, providing a sum of 1 〇A to each electrode The total current to 4〇A -, when the third electrode voltage is positive with respect to the wafer, the current density ratio of the first electrode to the second electrode is 1: 2:1, and the current density ratio of the first electrode to the third electrode is 1 : 1 -300: 1. When the third electrode voltage is negative relative to the wafer, The current density ratio of the first electrode to the second electrode is 1: 2:1, and the current density ratio of the first electrode to the third electrode is 20: 300: 1; the switching power supply provides a maximum of 1 〇v to the semiconductor wafer. Dust; The semiconductor wafer is taken out of the electrolyte. 12. The method of claim 2, wherein the ratio of the total area of all of the electrodes to the area of the wafer is greater than 〇85. The electrolyte is 0. 02至〇. 2S/cm electrolyte, when the first electrode is subjected to the first step of the electroplating process, when the voltage of the third electrode is negative with respect to the wafer, in the conductivity of 0. 02 to 2. 2S / cm electrolyte, The ratio of the first electrode to the _ pole current density is 1: Bu 2:1, and the first electrode and the first electrode are buds. The current density ratio of one electrode is 10:1-40:1. 14. The method of claim 11, wherein in the first step of the electroplating process, when the voltage of the third electrode is negative relative to the wafer, the conductivity is 〇. 2 to 8. 8s/cm in the electrolyte 'first The ratio of the electrode to the first in-phase current density is 5:1-20:1, and the ratio of the first electrode to the first electrode &amp;&amp; electro-deuterium current density is 2:1-10:1. Φ 31 201012976 15·Fangzhong, as described in the scope of patent application, in the second step of the plating process, when the voltage of the third electrode is negative relative to the wafer, the conductivity is 0_ 02 to 〇. 2S/CID In the electrolyte, the first life, the second lightning current density ratio in the electrode is 胄1: 2:1, and the ratio of the first electrode to the third power is 50·· 300:1. ; 11 up to 16. As described in the patent application, the method described in item 11, and... In the second step of the keying process, when the third electrode is negatively opposite to the wafer, the conductivity is 0.2S 〇.8S/cm. In the electrolyte, the _th electrode virtual second electrode current density ratio is, the first electrode and the third electrode current density ratio is 20: Bu 80:1. Wherein the semiconductor substrate has a seed layer thickness of 50 to 900 Å as described in claim U. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. 19. The method of claim U, wherein each electrode is placed at the same longitudinal height. 20 · If the pole of the patent application is placed at a different vertical height. The method of claim 11, wherein each of the electricity 32 201012976 21. A method for an electrochemical deposition uniform copper film apparatus having four or more electrodes, comprising the steps of: wherein the first electrode area is a total electrode 5% to 50% of the area, the copper sulfate electrolyte is injected into the apparatus at a flow rate of 2 〇LpM; the semiconductor wafer is transferred to the wafer holding device to make the device in conductive contact with the wafer conducting layer; Providing a semiconductor wafer with a bias voltage up to 丨〇v; _ bringing the semiconductor wafer into contact with the electrolyte; maintaining the first electrode voltage positive with respect to the wafer; performing a first step of electroplating to provide a sum to each electrode For the total current, when the first electrode voltage is positive with respect to the wafer, the current density ratio of the first electrode to the second electrode is 0.5:1-10:1, and the current density ratio of the first electrode to the last electrode is i : Bu 300: Bu current electrode and other electrode current density ratio of 0.5: 1-2: When the first electrode voltage is negative relative to the wafer, the first electrode and the second electrode current density ratio is 〇 5:12: 1, second The current density ratio of the φ electrode to the first electrode is Id-300:1, and the current density ratio of the first electrode to the other electrode is 0.5: Bu 30:1; the second step of the key bonding process is performed, and the sum of the electrodes is 1 〇A The total current to 4〇a, when the first electrode voltage is positive with respect to the wafer, the first electrode and the second electrode current density ratio is 〇.5:1-1〇:1, the first electrode and the last electrode current The density ratio is 1:1 -300:1, and the current density ratio of the first electrode to the other electrode is 0.8: 2: When the first electrode voltage is negative relative to the wafer, the current density ratio of the first electrode to the second electrode is 〇5:1_2:1, the first – the current density ratio of the electrode to the last electrode is 1: 1-300: 1, the first electrode and 33 201012976 other electrode current density ratio is 〇. 5 : 1 __丨〇. Summer, · 1 bias; switching power supply to the semiconductor wafer to the maximum to remove the electrolyte from the semiconductor wafer. 22. The method of claim 21, wherein the ratio of the total area of the electrodes to the area of the wafer is greater than 〇85. 23.如申請專利範圍第21項所述的方法, 具中進行 第一步電鍍工藝時’當第末個電極的電壓相曰 J曰曰月舄負, 在電導率爲0. 02至〇. 2S/cm電解液中,第—费杜加被 要極與第二 電極電流密度比爲0.5M-3:卜第一電極與第束個電極電 流密度比爲10:1-100:1,第一電極與其他電極電流密度 比爲 0. 5: 1-2: 1» 24.如申請專利範圍第21項所述的方法,其中進行 ❹ 第一步電鍵工藝時,當第末個電極的電壓相對晶片爲負, 在電導率爲0.2至〇. 8S/cm電解液中,第一電極與第二 電極電流密度比爲4:1-40:1,,第一電極與第末個電極電 流密度比爲2: 1-100: 1,第一電極與其他電極電流密度比 爲1:卜2:1。 25.如申請專利範圍第21項所述的方法,其中進行 第二步電鍍工藝時,當第末個電極的電壓相對晶片爲負, 在電導率爲0.02至〇.2S/cm電解液中’第一電極與第二 34 第一電極與第末個電極 電極與其他電極電流密 ❹ ❹ 201012976 電極電流密度比爲〇. 5:卜10:丨 電流密度比爲1(^ 1 — 200:1,第 度比爲 0.5:1-2:1。 當請專利錢第“所述时法,其令進行 第二步電鑛工藝時,當第末個片仃 在電導率爲0.2至〇.8s/c 相對曰曰片爲負, 電極電流密度比爲m — H,第 -電極與第二 流密度比爲第電極與,末個電極電 爲1:1-2:1。 極與其他電極電流密度比 27 .如申請專利範圍第21 體晶片籽晶層厚度爲5〇至9〇〇a。 ^ '法,其中半導 28 .如申請專利範圍第21 I* a LJ L Φ 方法》其中丰实 體晶片上電鍍鋼膜的WFNU調 、+導 0. 2%至2. 5%範圍内。 29·如申請專利範圍第21項冲 極置於同一縱向高度。 a的方法’其中各電 3〇 .如申請專利範圍第21項 極置於不同縱向高度。 L的方法’其中各電 3523. The method of claim 21, when the first step of the electroplating process is carried out, when the voltage of the first electrode is 曰J曰曰月舄, the conductivity is 0. 02至〇. In the 2S/cm electrolyte, the current-density ratio of the first electrode to the second electrode is 0.5M-3: the current density ratio of the first electrode to the first electrode is 10:1-100:1, The current density ratio of one electrode to the other electrode is 0. 5: 1-2: 1» 24. The method according to claim 21, wherein the voltage of the first electrode is performed when the first step of the key process is performed. The relative density of the first electrode and the second electrode is 4:1-40:1, and the current density of the first electrode and the second electrode is negative in the electrolyte of 0.2 to 8 S/cm. The ratio is 2: 1-100: 1. The current density ratio of the first electrode to the other electrodes is 1: Bu 2:1. 25. The method of claim 21, wherein when the second step of the electroplating process is performed, when the voltage of the first electrode is negative relative to the wafer, in an electrolyte having a conductivity of 0.02 to 2.2 S/cm. The first electrode and the second electrode 34 and the first electrode electrode are in close contact with the other electrodes. ❹ 201012976 The electrode current density ratio is 〇. 5: 卜10: 丨 current density ratio is 1 (^ 1 - 200:1, The first ratio is 0.5:1-2:1. When the patent method is mentioned, the method is to make the second film in the second step of the electric ore process, when the last film is in the conductivity of 0.2 to 〇.8s/ c is negative with respect to the cymbal, the electrode current density ratio is m - H, the ratio of the first electrode to the second flow is the first electrode and the last electrode is 1:1 - 2: 1. The polarity of the electrode and other electrodes Ratio 27. The thickness of the seed layer of the 21st body wafer is 5 〇 to 9 〇〇 a. ^ 'Method, where the semi-guide 28. As claimed in the scope of the 21st I* a LJ L Φ method, which is rich The WFNU of the galvanized steel film on the body wafer is in the range of 0.2% to 2.5%. 29. If the scope of the application is in the 21st paragraph, the punch is placed in the same longitudinal direction. Height. A method 'wherein each electrically 3〇. Patent application range as item 21 placed at different longitudinal height of the pole. Method L' wherein each electrically 35
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US6815336B1 (en) * 1998-09-25 2004-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing
US6551484B2 (en) * 1999-04-08 2003-04-22 Applied Materials, Inc. Reverse voltage bias for electro-chemical plating system and method
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