〜-059 28185twf.doc/n 201011914 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電晶體結構，且特別是有關於— 種功率電晶體的結構。 ' 【先前技術】 參 ❹ 隨著電子技術的進步，以及人們對於電子產品依賴声 ^增加’-個具有多合—功能的電子產品才有可能成為 %真正的主流。也因此，將多個不同功能的電路加以整合 的技術，也成為近代電子工程師的一個很重要的課題。 在進行上述的電路整合工作時，最先會碰到的就 謂^組電源供應的問題。傳統上，這些不同功能的電路， 都由其專屬的電源供應系統來產生其所彡貞的電源隹 ^成本無積財量之下，這種枝勢必紐被實行^ 於此’業界提出了許多不同麵的電源產生裝置( =轉直流電源轉換器(DC DC p。爾_e㈣及交流 =源轉換H(AC DC p_咖讀朔，轉決前述的 巧’這些電源轉翻為了產生足夠大的神，通常 曰固有強大電流驅動能力的功率電晶體，這種功率雷 ί雷積魔大的問題外，尚有電流密度、散熱度、導 2 i均句度等多個在電路佈局上所會面臨的多： 和的6 μ此，習知的電晶體佈局技術中來處理大面積電曰曰 謂多指狀(mu财mger)結構的佈局方式，也無法‘ 效的完整克服上述的多個問題。 有 4 【發明内容】 以節積種電㈣單元環雜構來構成， 電二：=_構成的 參 極提供—種電晶體單元，包括L閘 本、第-參雜區以及第二參雜區。其中的閘極以第— 結構來構成，其第-參雜區’配置在該上述的第 構的内侧1其第二參雜區則是圍繞在第—環狀結構的= 側’形成第n賴。第二_則是嶋在第二 的外侧並形成第三環狀結構。 …k 本發明提供—種功率電晶體，包括多個電晶體單元。 、中的各電晶體單元包括第―閘極、第二閘極、第— 雜區。其中的第-閑極以第-環狀結構來構 =^繞在上述環狀結構的外側，形成第二環狀結I第 „圍繞在第二參雜區的外側並 第二參雜區與相鄰的各電匕 極與相鄰的電晶體單元的第元的第-閘 電性的第—參雜區相互以第一導線 採祕有環狀結構的電晶體單 辜電晶體，因此在當需要多個電晶體單元排列在 201011914 ^-059 28185twf.doc/n 可以有效的減低電晶體在晶片上所佔去的面積，除有效降 低成本外，還具有降低導通電阻以及提升功率電晶體的電 流密度、電流均勻度、散熱度及對抗電致遷移等能力。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例’並配合所附圖式，作詳細說明如下。 【實施方式】 _ 以下將針對本發明的電晶體單元及功率電晶體提出 多個實施例來加以說明，並佐以圖示，以期本領域據通常 知識者更能了解’並得據以實施。 首先請參照圖1Α，圖1Α繪示本發明的電晶體單元的 -實施例的不意圖。在本實施例中，電晶體單元則為一 個金氧半場效電晶體(MeW-Oxide-SemicDiKluctoi* Field Effete Transistor，_ΕΤ)。電晶體單元 ι〇〇 呈有一個 所構成的閘極U〇，而這個環狀結構的閉極110 :斤=住的區域，就是電晶體單元1〇〇的第-參雜區120。 H在間極110外圈的另一個環狀結構的區域， 早元100的第二參雜區130，而在第二參雜區 的外圍則醜著_環狀結構㈣極140。 如同本領域具通常知識者的 ==區，及極及源極，二= :極。相對的，當第-參雜請為電 、;及極時’帛二參雜區13GW為電晶體單元 201011914 χί ν i-^ww-059 28185twf.doc/n 100的源極。另外，當電晶體單元100單獨被使用時，閘 極110、120可以利用閘極導線LG相互連接，以形成電晶 體單元100的共同閘極。 值知注意的是’電晶體單元中的環形結構(不管是 閘極110、150或是第一、第二參雜區120、130)，不但可 以是如同圖1A繪示為正圓形外，也可以如同圖1B繪示的 本發明的電晶體單元的另一實施例的示意圖的橢圓形結 φ 構。 為更仔細說明這種環狀結構的電晶體單元，請參照圖 2繪示的本發明的實施例的電晶體單元1〇〇的立體剖面 圖。由圖2的繪示可以清楚看見，環狀結構的閘極n〇、 140为別覆盍在基底140上的閘極氧化層（gate oxide) 1H、141上，而基底上另形成兩個區域分別為第—參雜區 120及第二參雜區13〇。若電晶體單元1〇〇為一個p型的 金氧半場效電晶體，則第一參雜區12〇及第二參雜區13〇 分別為P極性的參雜區，而若是電晶體單元100為一個N 型的金氧半場效電晶體，則第一參雜區12〇及第二參雜區 130分別為N極性的參雜區。 而被環狀結構的閘極110覆蓋在基底14〇上，並同時 為第一參雜區120及第二參雜區13〇所包圍的部分，在當 環狀結構的閘極11〇受到了適當的偏壓時，即會對應產生 通道150。上述所謂適當的偏壓即為對的金氧半場效 電晶體的閘極及基底間加上正極性的偏壓，而針對p塑的 金氧半場效電晶體的閘極及基底間加上負極性的偏壓。~-059 28185twf.doc/n 201011914 IX. Description of the Invention: [Technical Field] The present invention relates to a crystal structure, and more particularly to a structure of a power transistor. '[Prior Art] Participation ❹ With the advancement of electronic technology and the reliance on electronic products to increase the number of electronic products that have multiple functions, it is likely to become the true mainstream of %. Therefore, the technology of integrating multiple circuits with different functions has become an important issue for modern electronic engineers. When performing the above-mentioned circuit integration work, the first thing that will be encountered is the problem of the power supply of the group. Traditionally, these different functional circuits have their own power supply system to generate their own power supply. The cost is not under the accumulated amount of money. Different power generation devices (=DC-DC power converter (DC DC p. er_e(4) and AC=source conversion H (AC DC p_咖读朔, turn the aforementioned smart) These power turns to generate enough The god, usually the power transistor with inherently strong current drive capability. In addition to the problem of power, the current density, heat dissipation, and the degree of conduction are many in the circuit layout. Will face more: and 6 μ this, the conventional transistor layout technology to deal with large-area electric 曰曰 多 multi-finger (mu money mger) structure layout, can not be 'effectively complete to overcome the above There are 4 [Summary of the invention] Constitutive electric (4) unit ring hybrid structure, electric 2: = _ formed by the pole provides a kind of transistor unit, including L gate, the first - doping area and Two noisy areas. The gates are composed of the first structure. The first-doping region 'is disposed on the inner side of the first configuration 1 and the second impurity region thereof is formed around the = side of the first-ring structure to form a nth ryth. The second _ is 嶋 in the second The outer side forms a third annular structure. The present invention provides a power transistor including a plurality of transistor units. Each of the transistor units includes a first gate, a second gate, and a first impurity region. Wherein the first-idle pole is configured by a first-ring structure to be wound around the outer side of the annular structure, and a second annular junction I is formed to surround the outer side of the second doping region and the second doping region and The adjacent electric dipoles and the first-gate electrical first-doping regions of the adjacent transistor units are mutually etched with a first-conductor transistor monolayer transistor having a ring structure, thus When a plurality of transistor units are arranged at 201011914^-059 28185twf.doc/n, the area occupied by the transistor on the wafer can be effectively reduced, and in addition to effectively reducing the cost, the on-resistance and the power transistor are reduced. Current density, current uniformity, heat dissipation and resistance to electromigration. The above features and advantages of the invention will be more apparent and understood. The preferred embodiments of the invention will be described in detail below with reference to the accompanying drawings, and the following description will be described below. [Embodiment] _ The following will be directed to the transistor unit and power transistor of the present invention. A number of embodiments are provided to illustrate and be illustrated in the drawings, in the hope that those skilled in the art will be able to understand and implement the same. First, please refer to FIG. 1A, which illustrates the transistor unit of the present invention- The embodiment is not intended. In this embodiment, the transistor unit is a metal oxide half field effect transistor (MeW-Oxide-SemicDiKluctoi* Field Effete Transistor, _ΕΤ). The transistor unit ι〇〇 is composed of one. The gate U 〇, and the closed pole 110 of this annular structure: the area where the jin = live, is the first-doping region 120 of the transistor unit 1 。. H is in the region of the other annular structure of the outer ring 110, the second doping region 130 of the early element 100, and the ugly_ring structure (four) pole 140 at the periphery of the second doping region. As in the field of the general knowledge of the == area, and the pole and source, two =: pole. In contrast, when the first-parameter is electricity, and the extreme time, the 13GW of the second impurity region is the source of the transistor unit 201011914 χί ν i-^ww-059 28185twf.doc/n 100. In addition, when the transistor unit 100 is used alone, the gates 110, 120 may be connected to each other by a gate wire LG to form a common gate of the transistor unit 100. It is worth noting that the ring structure in the transistor unit (whether the gates 110, 150 or the first and second doping regions 120, 130) may be not only a circle as shown in FIG. 1A, but also An elliptical junction φ configuration of a schematic view of another embodiment of the transistor unit of the present invention, as illustrated in FIG. 1B, may also be used. For a more detailed description of the transistor unit of such a ring structure, please refer to the perspective view of the transistor unit 1A of the embodiment of the present invention shown in FIG. As can be clearly seen from the depiction of FIG. 2, the gates n〇, 140 of the ring structure are covered on the gate oxides 1H, 141 on the substrate 140, and two regions are formed on the substrate. The first is the first doping zone 120 and the second doping zone is 13〇. If the transistor unit 1 is a p-type MOS field effect transistor, the first doping region 12 〇 and the second doping region 13 〇 are respectively P-polar doping regions, and if it is the transistor cell 100 For an N-type metal oxide half field effect transistor, the first doping region 12〇 and the second doping region 130 are respectively N-polar doped regions. And the gate 110 of the ring structure covers the substrate 14〇, and at the same time, the portion surrounded by the first doping region 120 and the second doping region 13〇, when the gate 11〇 of the ring structure is received When a suitable bias voltage is applied, the channel 150 is correspondingly produced. The so-called appropriate bias voltage is a positive polarity bias between the gate and the substrate of the pair of gold oxide half field effect transistors, and a negative electrode is applied between the gate and the substrate of the p-type gold oxide half field effect transistor. Sexual bias.
201011914 r x ^^^-059 28185twf.doc/n _抑⑽霸I日日體早元⑽在其閉極n〇 甘下方形成通道150 ’此通道15G同樣為環狀結構，因此 其通道150的寬度(width)可以其閘極11〇的内環半徑r2及 外環半徑的d的平均值為半徑，所計#出的關^而其 通道150的長度(length)則為閘極11〇的内環半徑 環半徑的rl的差。 在此請特別注意，上述關於圖2中繪示的電晶體單元 100的層次關係僅只是一個實施例，並不以此限制本發 明。例如圖2繪示的閘極11〇、140不一定要直接覆蓋在基 底no上，也可以覆蓋在所謂的井區(wellX未繪示)上，而 關於金氧半％效電晶體的製程結構是為本領域具通常知識 者所能知道的，並不是本發明的重點，在此不多詳述。 關於利用上述實施例的電晶體單元1〇〇所建構出的功 率電晶體的實施例則請參照圖3，其中圖3繪示本發明之 功率電晶體300的一實施例的示意圖。在本實施中，功率 電晶體300包括有七個電晶體單元，這些電晶體分別包栝 閘極3101〜3107、閘極3401〜3407、第一參雜區.3201〜3207 及第二參雜區3301〜3307。其中，六個電晶體單元環繞住 —個電晶體單元，位於中央的電晶體單元的第二參雜區 33〇1與周圍的電晶體的第二參雜區3302〜3307部份重疊。 另外’關於功率電晶體300的配線方式則請參照圖4， 圖4緣示本發明之功率電晶體3〇〇實施例的一配線實施方 式。由於圖4中的七個電晶體單元是為建構出一個功率電 晶體300。因此’所有的電晶體單元的每一個汲極都必需 8 --U59 28185twf.doc/n 201011914 被電性連接起來’在此’以各電晶體單元的第—參雜區作 為汲極為例子，在對應要被連接的各電晶體單元的汲極上 先形成連接點com〜CON3，再利用連接點上方的導線層 形成導線L1通過各連接的CON1〜CON3的上方，即可二 將作為汲極的第一參雜區3201〜3207連接起來，並形成— 個共同没極。 在上述的說明中，連接點可以形成在半導體製程中用 ❹ 來作為導線連接的contact層或VIA層中，而導線層則可 選用對應到連接點CON1〜CON3所連接的導電層（一般為 金屬層）來形成。相同的，各電晶體單元的源極同樣也可二 猎由上述方式來完成電性連接。以連接作為源極的第二來 雜區3304、3305為例’連接點CON4、CON5分別形成在 第二參雜區3304、3305上，導線L2則通過連接點c〇N4、 CON5並元成苐一參雜區3304、3305的電性連接，形成功 率電晶體300的共同源極。 另外，關於各電晶體單元的閘極電性連接的方式，由 於母一個電晶體單元内圈的閘極都與相鄰的電晶體單元外 區的閘極電性連接，因此，功率電晶體3〇〇中的所有電晶 體單元的閘極都是直接電性連接在一起。也因此，並不需 要另外的導線來做連接。 特別值得一提的是，上述的導線連接方式，是在半導 體製程中為該領域具通常知識者都可以輕易實施的。而上 述的說明僅只是針對本發明實施例的導線連接方式提出一 個範例，並不限制本發明的功率電晶體的導線連接方式的 u59 28185twf.doc/n 201011914 範圍。 再者，本發明實施例中的功率電晶體300並不一定要 如圖示中的以七個電晶體單元的排列方式，也有其他不同 數目或不同方向的排列方式。請參照圖5A〜圖5E，圖5A〜 圖5E分別緣示本發明實施例中的功率電晶體3〇〇不同電 晶體早元排列方式的示意圖。若以各電晶體單元的環狀結 構的中心點（第一參雜區的中心點)連線的形狀來說明，則 可以如圖5A〜圖5C排列成直線的結構，也可以如同圖5D 或圖5E纷示的網狀的結構。然而’為使每一個電晶體單 元在製造時彼此間不會發生過大的變異，每個電晶體單元 可以對稱性方式排列。 另外’功率電晶體300的通道寬度長度計算方式，則 參考上^又關於電晶體单元的通道寬度長度計算方式，再將 單一電晶體單元的通道寬度乘以功率電晶體300中的電晶 體單元的個數’即可算出功率電晶體300的通道總寬度。 在此補充說明，為使功率電晶體所佔的面積減小，在 此提出一個實施例來說明電晶體單元排列的方式。請參照 圖6 ’圖6繪示本發明的功率電晶體中的電晶體單元排列 的實施方式。在圖6的繪不中’各電晶體单元的中心點 Α1〜Α5彼此間的距離都是相等的，這種排列方式可以緊密 的結合各電晶體單元，以節省電路面積。 綜上所述’本發明利用具有環狀結構的電晶體單元， 來排列組合出功率電晶體，有效的緊密排列電晶體單元。 進而減低功率電晶體在晶片上所佔去的面積，除有效降低 •u59 28185twf.doc/n 201011914 ^外，還具有降低導通電阻以及提升功率電日日日體的電流 禮度、電流均勻度、散熱度及對抗電致遷移等能力。 雖然本發明已以較佳實施例揭露如上，麩^ =本發明，任何所屬技術領域中具有通常;:識^ =離本發明之精神和範_，當可作些許之更動與潤飾， =本發明之保護範圍#視後附之帽專利範圍所界定者 【圖式簡單說明】 圖。圖1A繪示本發明的電晶體單元的一實施例的示意 圖繪示的本發明的電晶體單元的另一實施例的示 愚圖。 圖2綠示的本發明的實施例的電晶體單元1〇〇的立體 剖面圖。 魯 圖3綠示本發明之功率電晶體300的一實施例的示意 w 圖。 圖4繪示本發明之功率電晶體300實施例的一配線實 施方式。 圖5A〜圖5E分別繪示本發明實施例中的功率電晶體 300不同電晶體單元排列方式的示意圖。 圖6繪示本發明的功率電晶體中的電晶體單元排列的 —實施方式。 11 201011914 -kj59 28185twf.doc/n 【主要元件符號說明】 100:電晶體單元 110、140、3101-3107、3401 〜3407 :閘極 120、3201〜3207 :第一參雜區 130、3301〜3307 :第二參雜區 170 :基底 150 :通道 141、111 :閘極氧化層 300 :功率電晶體 rl、r2 :半徑 CON1〜CON3 :連接點 L卜L2、LG :導線 A1〜A5 :中心點201011914 rx ^^^-059 28185twf.doc/n _ (10) typhoon I day body early element (10) forms a channel 150 under its closed pole 〇 ' 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此(width) may be the radius of the inner ring radius r2 of the gate 11〇 and the average of the outer ring radius d, and the length of the channel 150 is the inside of the gate 11〇. The difference in rl of the radius of the ring radius. It should be noted here that the hierarchical relationship described above with respect to the transistor unit 100 illustrated in FIG. 2 is merely an embodiment and is not intended to limit the present invention. For example, the gate electrodes 11 and 140 shown in FIG. 2 do not have to be directly covered on the substrate no, and may be covered on a so-called well region (wellX not shown), and the process structure of the gold oxide half-effect transistor. It is known to those of ordinary skill in the art and is not the focus of the present invention and will not be described in detail herein. Referring to Figure 3 for an embodiment of a power transistor constructed using the transistor unit 1 of the above embodiment, Figure 3 is a schematic diagram of an embodiment of a power transistor 300 of the present invention. In the present embodiment, the power transistor 300 includes seven transistor units, which respectively encapsulate the gates 3101 to 3107, the gates 3401 to 3407, the first doping region .3201 to 3207, and the second doping region. 3301~3307. Wherein, the six transistor units surround a transistor unit, and the second doping region 33〇1 of the central transistor unit partially overlaps the second doping regions 3302~3307 of the surrounding transistor. Please refer to Fig. 4 for the wiring pattern of the power transistor 300. Fig. 4 shows a wiring embodiment of the power transistor 3' of the present invention. Since the seven transistor units in Fig. 4 are constructed to construct a power transistor 300. Therefore, 'each of the bucks of all the crystal cells must be 8 --U59 28185twf.doc/n 201011914 is electrically connected 'here' with the first doping region of each transistor unit as an example, The connection points com~CON3 are formed on the drains of the respective transistor units to be connected, and the wire L1 is formed by the wire layers above the connection points through the upper portions of the CON1 to CON3 of the respective connections, so that the second A doping zone 3201~3207 is connected and forms a common dipole. In the above description, the connection point may be formed in a contact layer or a VIA layer using ❹ as a wire connection in a semiconductor process, and the wire layer may be selected as a conductive layer (generally a metal) connected to the connection points CON1 to CON3. Layer) to form. Similarly, the sources of the respective transistor units can also be electrically connected in the manner described above. Taking the second interleaved regions 3304 and 3305 as the source as an example, the connection points CON4 and CON5 are respectively formed on the second doping regions 3304 and 3305, and the wires L2 are connected to each other through the connection points c〇N4 and CON5. The electrical connections of a doped region 3304, 3305 form a common source of power transistors 300. In addition, regarding the manner in which the gates of the respective transistor units are electrically connected, since the gates of the inner ring of the mother transistor unit are electrically connected to the gates of the outer regions of the adjacent transistor units, the power transistor 3 is The gates of all the transistor units in the crucible are directly electrically connected together. Therefore, no additional wires are needed for the connection. It is particularly worth mentioning that the above-mentioned wire connection method can be easily implemented by a person with ordinary knowledge in the field in the semi-conducting process. The above description is merely an example for the wire connection method of the embodiment of the present invention, and does not limit the range of the wire connection mode of the power transistor of the present invention to u59 28185 twf.doc/n 201011914. Furthermore, the power transistor 300 in the embodiment of the present invention does not necessarily have to be arranged in seven different crystal units as shown in the figure, and there are other different numbers or different directions. Referring to FIG. 5A to FIG. 5E, FIG. 5A to FIG. 5E respectively show schematic diagrams of the arrangement of different transistors in the power transistor 3〇〇 in the embodiment of the present invention. If the shape of the center point of the annular structure of each transistor unit (the center point of the first doping area) is described, the structure may be arranged in a straight line as shown in FIG. 5A to FIG. 5C, or may be as shown in FIG. 5D or Figure 5E shows the structure of the mesh. However, each transistor unit can be arranged in a symmetrical manner so that each of the transistor units does not undergo excessive variation from each other during manufacture. In addition, the calculation method of the channel width length of the power transistor 300 refers to the calculation method of the channel width length of the transistor unit, and multiplies the channel width of the single transistor unit by the transistor unit in the power transistor 300. The total number of channels of the power transistor 300 can be calculated by the number '. In addition, in order to reduce the area occupied by the power transistor, an embodiment is proposed to explain the arrangement of the transistor unit. Referring to Figure 6', Figure 6 illustrates an embodiment of an arrangement of transistor cells in a power transistor of the present invention. In the drawing of Fig. 6, the center points Α1 to Α5 of the respective transistor units are equidistant from each other, and this arrangement can closely combine the respective transistor units to save circuit area. In summary, the present invention utilizes a transistor unit having a ring structure to arrange and combine power transistors to effectively closely arrange the transistor units. In turn, the area occupied by the power transistor on the wafer is reduced, in addition to effectively reducing the on-resistance and the current uniformity and current uniformity of the power-on-day body. Ability to dissipate heat and resist electromigration. Although the present invention has been disclosed in the preferred embodiments as above, the present invention is generally in the art; the knowledge and the spirit of the present invention, when some modifications and refinements can be made, = the present invention The scope of protection # is defined by the patent scope of the attached cap [simplified description of the figure]. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a schematic illustration of another embodiment of an electro-optical unit of the present invention, schematically depicted in an embodiment of an electro-optic unit of the present invention. Fig. 2 is a perspective cross-sectional view showing the transistor unit 1A of the embodiment of the present invention. Lutu 3 Green shows a schematic w diagram of an embodiment of the power transistor 300 of the present invention. 4 illustrates a wiring implementation of an embodiment of a power transistor 300 of the present invention. 5A to 5E are schematic views respectively showing the arrangement of different transistor units of the power transistor 300 in the embodiment of the present invention. Figure 6 illustrates an embodiment of an arrangement of transistor cells in a power transistor of the present invention. 11 201011914 -kj59 28185twf.doc/n [Description of main component symbols] 100: transistor unit 110, 140, 3101-3107, 3401 to 3407: gate 120, 3201 to 3207: first doping region 130, 3301 to 3307 : second doping region 170: substrate 150: channel 141, 111: gate oxide layer 300: power transistor rl, r2: radius CON1 ~ CON3: connection point L Bu L2, LG: wire A1 ~ A5: center point
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