201011898 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種nor型快閃記憶體結構及其製造 方法’更特別的是關於一種具有高摻雜汲極區的N〇R型快 閃記憶體（flash memory)結構及其製造方法。 【先前技術】 快閃記憶體是一種非揮發性(n〇n_v〇latile)的記憶體， ^ g卩在無外部電源供電時’也能夠保存資訊内容’這使得襄 置本身不需要浪費電力在資料的記憶上，再加上快閃記憶 ，也具備重複讀寫、體積小、容量高及便於機帶的特性， 這使得快閃記憶體特別適合使用在攜帶式的裝置上。目矿 NQR型快閃記憶體應用的範圍’除了個人電腦上的主柄 會利用NOR型快閃記憶體儲存BI〇s資料夕卜，手機、 裝置也會使用NOR型快,閃記憶體來存放系統資料，装 鲁叫㈣取速度，滿足特&置_健求。 、201011898 IX. Description of the Invention: [Technical Field] The present invention relates to a nor-type flash memory structure and a method of fabricating the same, and more particularly to an N〇R-type flash with a highly doped drain region A flash memory structure and a method of manufacturing the same. [Prior Art] Flash memory is a non-volatile (n〇n_v〇latile) memory, ^ g卩 can also save information content when there is no external power supply. This makes the device itself do not need to waste power. The memory of the data, together with the flash memory, also has the characteristics of repeated reading and writing, small size, high capacity and easy to belt, which makes the flash memory particularly suitable for use on portable devices. The scope of the NQR-type flash memory application of the mine is 'in addition to the main handle on the personal computer, the NOR-type flash memory is used to store the BI〇s data. The mobile phone and the device will also use the NOR-type fast flash memory to store. System data, installed Lu called (four) to take the speed, meet the special & ,
^軋化層厚度的微縮是必然的趨勢。微縮 隨著科技的進步，快閃記憶體的數程枯m奈米 « "〜Π~叩顶罘度，和 ’ τη徠閘極的通道長度 。微縮元件尺寸不僅可 么尺）縮減到現在的奈米 ，亦可同時提升元件本身的 ’然而事實上並非如此。 及閘極線寬的縮短卻使得短通 提高單位面積的積體電路密度，' 電流驅動能力，可謂一舉兩得，； 件閘極線寬已從以往的微米（10-6 (1(r9公尺），隨著元件的微縮及闡 201011898 道效應（Short Channel Effect)越來越嚴重，而為避免短通道 效應對元件造成影響，其中之一解決方法即是降低源極/ 汲極的接面深度來達成。 以輕摻雜汲極（Lightly Doped Drain，LDD)而言，可 提高元件的崩潰電壓（Breakdown Voltage )、改善臨界電壓 的特性、降低熱載子效應（Hot Carrier Effect)。雖然輕摻 雜沒極降低了汲極接面的高電場，有效的提升元件的可靠 度’然而輕摻雜汲極造成的淺接面深度卻容易在進行接觸 孔#刻時’造成汲極被挖穿的現象，而破壞了記憶體的結 構。 因此’如何改良該汲極區以避免蝕刻該接觸孔時所造 成的挖穿現象就變的相當重要。 【發明内容】 本發明的主要目的在提供一種具高摻雜汲極區之 NOR型快閃記憶體’使汲極區接面深度降低以改善短通道 效應的同時，亦能避免蝕刻該接觸孔時，對該輕摻雜汲極 區造成挖穿的現象。 為達上述目的，本發明係提供一種具高摻雜汲極區 NOR型快閃記憶體結構，其包含：—半導體基底，於其上 具有-閘極結構；—第—汲極區’係為_輕摻雜區位於 該二閘極結構之間的該半導體基底中；—第—源極區係 位於該二閘極結構之二外側的該半導鱧基底中；其中，該 第一源極區於該半導體基底t之接面深度較該第 一汲極區 201011898 深；-高摻雜汲極區，係位於該二閘極結構間的該半導體 基底中，並與該第-汲極區重4，且該高捧雜汲極區於該 半導體基底中的接面深度較該第一汲極區深；二自動對^ 金屬砍化物層’係分別為於該二閘極結構上方；及一位障 插塞，係分隔該二閘極結構。 料上述目的，本發_提供—種具高摻雜汲極區之 NOR型快閃記憶體結構的製造方法，其包含：提供一半導 J 體基底；於該半導體基底上方形成二閘極結構；於該二閘 -© 極結構之間_半導縣底中騎-輕摻_子佈植製程 以形成輕摻雜的一第一汲極區，於該二閘極結構之二外側 的該半導體基底中分別形成一輕摻雜源極區，再進行一源 極離子佈植製程，於該二閘極結構之二外側的該半導體基 底中分別形成一第一源極區，其中該第一源極區於該半導 體基底中之接面深度較該第一汲極區深；於該二閘極結構 之間分別形成一 L形間隙壁，該二L形間隙壁係位於該第 ❹一汲極區上方，進行一高摻雜離子佈植製程以於該二閘極 結構間形成-高摻雜汲極區，其中該高摻雜汲極區與該第 • 一汲極區重疊，且該高摻雜汲極區於該半導體基底中的接 :㈣度較該第-汲極於該二閘極結構間形成一 插检。 藉此’本發明之NOR型快閃記憶體結構及其製造方法 能避免餘刻該接觸孔時，對該輕摻雜汲極區造成挖穿 象。 201011898 【實施方式】 為充分瞭解本發明之目的、特徵及功效，茲藉由下述 具體之實施例’並配合所附之圖式，對本發明做一詳細說 明，說明於後。在這些不同的圖式與實施例中，相同的元 件將使用相同的符號。 首先參照第一圖，係本發明快閃記憶體結構的部分剖 面圖。圖中顯示於一半導想基底100上形成有二閘極結構 102，該些閘極結構102分別包含：穿隧氧化層1〇2a (tunneling oxide layer)、浮動閘 1〇2b ( fl〇ating gate)、介 電層102c、控制閘102d( control gate)及形成一區域i〇3。 該半導體基底100材料可為矽、SiGe、絕緣層上覆矽（siiicon on insulator, SOI)、絕緣層上覆矽鍺（smc〇n germanium ⑽ insulator, SGOI)、絕緣層上覆鍺（germanium 〇n insul_， GOI);於本實施例中，該半導體基底1〇〇係為一矽基底。 接著請參照第二圖，進行一輕摻雜離子佈植製程2〇1， 於該二閘極結構102之半導體基底1〇〇中利用輕摻雜汲極 (Lightly Doped Dram, LDD)佈植形成二輕摻雜源極區2〇2 及一第一汲極區204。於本發明實施例中該半導體結構為 一 p型半導體結構中，該輕摻雜離子佈植製程2〇1中使用 的離子為砷，劑量約為1X10M〜7xl〇M(i〇n/cm2)，能量約為 10〜30(KeV)。其中該二輕摻雜源極區2〇2及該第一汲極區 204係為一 N摻雜區域，於該半導體基底1〇〇中之 度約為200 A。 接著請同時參照第三圖及第二圖，於該半導體基底1〇〇 201011898 上形成一光罩302，該第一汲極區204會被該光罩302所 涵蓋。進行一源極離子佈植製程301，加深該二輕掺雜源 極區202於該半導髏基底100内的離子佈植深度而成為二 第一源極區304’該些第一源極區304與該第一汲極區204 呈不對稱狀。相同地，於該P型半導體結構中，該源極離 子佈植製程301中使用的離子為砷，劑量約為ΐχΐ〇14〜 7xl015(ion/cm2)，能量約為10〜3〇(Kev)。其中該第一源極 區係為一 N摻雜源極區’於該半導體基底1〇〇中之接面深 ❹ 度約為200 A。 接著請參照第四圖’形成一第一氧化層壁401及一第 二氧化層402，再利用一習知的沉積技術，如：來源氣體 包含NH3及SiH4的化學氣相沉積法（CVD)、快速熱退火 化學氣相沉積（rapid thermal chemical vapor deposition, RTCVD)、原子層沉積（atomic layer deposition, ALD)，沉 積一氧化層404。該氧化層404的厚度可介於20〇A至15Q0. & A’在本實施例中約為75〇A。 接著請同時參照第四圖及第五圖，利用乾式或濕式蝕 刻進行一蝕刻製程將該氧化層404蝕刻成複數個氧化層間 隔物（Oxide spacer) 502a〜d。再進行另一蝕刻製程，將 該第一氧化層402姓刻成二l形間隙壁（L-shape) 504a、 5〇4b及蝕刻該第一氧化層壁4〇1。最後經一高摻雜汲極離 子佈植製程506於該二閘極結構1〇2之間形成一高摻雜汲 極區508。其中該高摻雜汲極區508與該第一汲極區204 重疊，且該高摻雜汲極區508於該半導體基底10〇中的接 201011898 面深度較該第一汲極區204深。該高摻雜汲極離子佈植製 程506中使用的離子為砷，劑量約為5xl014〜 8xl015(ion/cm2)，能量約為20〜55(Kev)，該高摻雜汲極區 508於該半導體基底100中之接面深度約為600 A。該第一 汲極區204與該高摻雜汲極區508的接面外觀（junction profile)是陡峭的，且與該些第一源極區304的平滑接面 外觀不同。其中該高摻雜汲汲區係為一 N摻雜。如此，由 於該高摻雜汲極區508的植入，當該輕摻雜的第一汲極區 204於接觸孔蝕刻時，就算較淺的接面深度造成該第一汲 極區204被挖穿的現象，也不會破壞記憶體的結構。 接著請參閱第六圖，於表面形成一由銘（cobalt，Co)、 鈦（titanium，Ti)、鎳（nickel，Ni)或鉬（molybdenum，Mo ) 所構成之金屬矽化物層，並且進行一快速熱退火處理製 程’以形成一自動對準金屬矽化物層602a、602b與602c (salicide layer)，用以降低寄生電阻提昇元件驅動力β 接著請參閱第七圖，接續上述步驟，於該半導體基底 100上沉積一接觸孔蝕刻停止層70¾ contact etch stop layer， CESL)’其可為SiN、氮氧化發（oxynitride)、氧化石夕（oxide) 等’在本實施例中為SiN。該接觸孔蝕刻停止層702的沉 積厚度為100至1500 A。接著，一層間介電質層704 (inter-layer dielectric，ILD) ’ 如：二氧化矽 si〇2，沉積在 該接觸孔蝕刻停止層702之上。 最後請參閱第八圖’利用習知的光阻光罩製程，將一 接觸孔802從該層間介電質層704非均向性地餘刻到該接 201011898 觸蚀刻停止層702。再丨儿積一位障插检804 ( barrier plug) 形成一如第八圖所示之具高摻雜汲極區的NOR型快閃記 憶體結構。 本發明在上文中已以較佳實施例揭露，然熟習本項技 術者應理解的是，該實施例僅用於描繪本發明中記憶體單 元的一部分結構，而不應解讀為限制本發明之範園。應注 意的是，舉凡與該實施例等效之變化與置換，均應設為涵 -蓋於本發明之範_内。因此，本發明之保護範圍當以下文 0 之申請專利範圍所界定者為準。 【圓式簡單說明】 第一圖到第八圖係顯示在不同製程步驟時，本發明實施例 的快閃記憶體結構剖面圖。 【主要元件符號說明】 100 半導體基底 102 閘極結構 102a 穿隧氧化層 102b 浮動閘 102c 介電層 l〇2d 控制閘 103 區域 201 輕摻雜離子佈植製程 202 輕摻雜源極區The miniaturization of the thickness of the rolled layer is an inevitable trend. Miniaturization With the advancement of technology, the flash memory's number of steps is negligible « "~Π~ dome top, and the channel length of the 'τη徕 gate. The size of the miniature component can be reduced not only to the current nanometer, but also to the component itself. However, this is not the case. And the shortening of the gate line width makes the short-pass increase the density of the integrated circuit per unit area, 'the current drive capability can be described as two things at a time; the gate width of the gate has been from the previous micron (10-6 (1 (r9 m)) As the component shrinks and the 201011898 Short Channel Effect becomes more and more serious, and one of the solutions is to reduce the source/drain junction depth to avoid the short channel effect on the component. In the case of Lightly Doped Drain (LDD), it can improve the component's Breakdown Voltage, improve the threshold voltage characteristics, and reduce the Hot Carrier Effect. The high electric field of the bungee junction is not reduced, and the reliability of the component is effectively improved. However, the shallow junction depth caused by the lightly doped bungee is easy to cause the bungee to be punctured when the contact hole is inscribed. Therefore, the structure of the memory is destroyed. Therefore, how to improve the drain region to avoid the phenomenon of the tunneling caused by etching the contact hole becomes very important. Providing a NOR-type flash memory with a highly doped drain region reduces the junction depth of the drain region to improve the short channel effect, and also avoids etching the contact hole when the lightly doped drain is In order to achieve the above object, the present invention provides a highly doped bungee region NOR type flash memory structure, comprising: a semiconductor substrate having a gate structure thereon; a drain region is a lightly doped region in the semiconductor substrate between the two gate structures; a first source region is located in the semiconductor substrate outside the two gate structures; Wherein the first source region is deeper than the first drain region 201011898 at the junction of the semiconductor substrate t; the high doped drain region is located in the semiconductor substrate between the two gate structures, and And the first-dippole region is heavier than 4, and the junction depth of the high-polythorium-pole region in the semiconductor substrate is deeper than the first-pole region; the second automatic metal-deposited layer is respectively Above the two gate structure; and a barrier plug that separates the two gate structures. The above object, the present invention provides a method for fabricating a NOR-type flash memory structure having a highly doped drain region, comprising: providing a half-conducting J-body substrate; forming a two-gate structure over the semiconductor substrate; The two gates are separated from the pole structure by a semi-conducting-light-doped _ sub-distribution process to form a lightly doped first drain region, the semiconductor substrate outside the two gate structures Forming a lightly doped source region, and performing a source ion implantation process, respectively forming a first source region in the semiconductor substrate outside the two gate structures, wherein the first source region The junction depth in the semiconductor substrate is deeper than the first drain region; an L-shaped spacer is formed between the two gate structures, and the two L-shaped spacers are located in the first-pole region Above, a highly doped ion implantation process is performed to form a high-doped drain region between the two gate structures, wherein the highly doped drain region overlaps with the first drain region, and the high doping The junction of the dopant region in the semiconductor substrate: (four) degrees compared to the first-pole pole at the two gate junction Is formed between a plug detection. Thus, the NOR type flash memory structure of the present invention and the method of fabricating the same can avoid the occurrence of cross-cutting of the lightly doped drain region when the contact hole is left. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the accompanying claims. In these different figures and embodiments, the same elements will use the same symbols. Referring first to the first drawing, a partial cross-sectional view of the flash memory structure of the present invention is shown. The figure shows that a two-gate structure 102 is formed on one half of the substrate 100, and the gate structures 102 respectively include: a tunneling oxide layer 1 〇 2a (tunneling oxide layer), a floating gate 1 〇 2b (f〇ating gate) ), a dielectric layer 102c, a control gate 102d (control gate), and an area i〇3. The semiconductor substrate 100 may be made of germanium, SiGe, siiicon on insulator (SOI), smc〇n germanium (10) insulator (SGOI), and overlying insulating layer (germanium 〇n). Insul_, GOI); In this embodiment, the semiconductor substrate 1 is a germanium substrate. Then, referring to the second figure, a lightly doped ion implantation process 2〇1 is performed, and light-doped Dram (LDD) is implanted in the semiconductor substrate 1〇〇 of the two-gate structure 102. The second lightly doped source region 2〇2 and a first drain region 204. In the embodiment of the present invention, the semiconductor structure is a p-type semiconductor structure, and the ion used in the lightly doped ion implantation process 2〇1 is arsenic, and the dose is about 1×10M~7×1〇M(i〇n/cm2). The energy is about 10~30 (KeV). The two lightly doped source regions 2〇2 and the first drain regions 204 are an N-doped region having a thickness of about 200 A in the semiconductor substrate. Then, referring to the third and second figures, a reticle 302 is formed on the semiconductor substrate 1 〇〇 201011898, and the first drain region 204 is covered by the reticle 302. Performing a source ion implantation process 301 to deepen the ion implantation depth of the two lightly doped source regions 202 in the semiconductor substrate 100 to become the first source regions 304' 304 is asymmetric with the first drain region 204. Similarly, in the P-type semiconductor structure, the ions used in the source ion implantation process 301 are arsenic, and the dose is about 〜14~7xl015 (ion/cm2), and the energy is about 10~3〇(Kev). . The first source region is an N-doped source region' having a junction depth of about 200 A in the semiconductor substrate. Next, please refer to the fourth figure 'forming a first oxide layer wall 401 and a second oxide layer 402, and then using a conventional deposition technique, such as chemical vapor deposition (CVD), where the source gas contains NH3 and SiH4, Rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (ALD), deposition of an oxide layer 404. The oxide layer 404 may have a thickness of between 20 A and 15 Q0. & A' is about 75 A in this embodiment. Next, referring to the fourth and fifth figures, the oxide layer 404 is etched into a plurality of oxide spacers 502a-d by an etching process using dry or wet etching. Another etching process is performed to pattern the first oxide layer 402 into L-shapes 504a, 5〇4b and etch the first oxide layer wall 〇1. Finally, a highly doped ytterbium region 508 is formed between the two gate structures 1 〇 2 via a highly doped yttrium ion implantation process 506. The highly doped drain region 508 overlaps the first drain region 204, and the highly doped drain region 508 is deeper than the first drain region 204 in the semiconductor substrate 10A. The ion used in the highly doped drain ion implantation process 506 is arsenic, the dose is about 5xl014~8xl015 (ion/cm2), and the energy is about 20~55 (Kev), and the highly doped drain region 508 is The junction depth in the semiconductor substrate 100 is about 600 Å. The junction profile of the first drain region 204 and the highly doped drain region 508 is steep and is different from the smooth junction of the first source regions 304. Wherein the highly doped germanium region is an N doping. Thus, due to the implantation of the highly doped drain region 508, when the lightly doped first drain region 204 is etched in the contact hole, the shallower junction depth causes the first drain region 204 to be dug. The phenomenon of wearing does not destroy the structure of the memory. Next, referring to the sixth figure, a metal telluride layer composed of cobalt (Co), titanium (titanium, Ti), nickel (nickel, Ni) or molybdenum (Mo) is formed on the surface, and a a rapid thermal annealing process 'to form an auto-alignment metallization layer 602a, 602b and 602c (salicide layer) for reducing the parasitic resistance boosting element driving force β. Referring to the seventh figure, the above steps are performed on the semiconductor. A contact hole etch stop layer 703⁄4 is deposited on the substrate 100. It may be SiN, oxynitride, oxide, etc., which is SiN in this embodiment. The contact hole etch stop layer 702 has a deposition thickness of 100 to 1500 Å. Next, an inter-layer dielectric (IGD) such as cerium oxide si〇2 is deposited on the contact hole etch stop layer 702. Finally, referring to the eighth figure, a contact hole 802 is non-uniformly engraved from the interlayer dielectric layer 704 to the contact etch stop layer 702 by a conventional photoresist mask process. A barrier plug 804 is formed to form a NOR flash memory structure having a highly doped drain region as shown in FIG. The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that this embodiment is only used to describe a part of the structure of the memory unit in the present invention, and should not be construed as limiting the present invention. Fan Yuan. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be within the scope of the invention. Therefore, the scope of the present invention is defined by the scope of the patent application of the following 0. [Circular Simple Description] The first to eighth drawings show cross-sectional views of the flash memory structure of the embodiment of the present invention at different process steps. [Main component symbol description] 100 Semiconductor substrate 102 Gate structure 102a Tunneling oxide layer 102b Floating gate 102c Dielectric layer l〇2d Control gate 103 Region 201 Lightly doped ion implantation process 202 Lightly doped source region
201011898 . 204 第一没極區 301 源極離子佈植製程 302 光罩 304 第一源極區 401 第一氧化層壁 402 第二氧化層 404 氧化層 502a〜d 氧化層間隔物 504a〜b 506 L形間隙壁 ❿ 高摻雜汲極離子佈植製程 508 南換雜汲極區 602a〜c 自動對準金屬矽化物層 702 接觸孔蝕刻停止層 704 層間介電質層 802 接觸孔 804 位障插栓 Q 12201011898 . 204 first non-polar region 301 source ion implantation process 302 photomask 304 first source region 401 first oxide layer wall 402 second oxide layer 404 oxide layer 502a~d oxide layer spacers 504a~b 506 L Shaped gap ❿ Highly doped 汲 离子 508 508 South 508 〜 602 602 602 602 602 602 602 602 602 自动 702 702 702 702 702 704 704 704 704 704 704 704 704 704 704 704 704 804 804 804 804 Q 12