201011837 九、發明說明： ^明所屬之技術領域】 本發明是揭靈 ι鄕作料^_之以雜的方法； 【先前技術j 在半導體產業中，夕日 在裂作典型金屬 於夕日日矽材料具有抗熱性質因此 〇 ❹ 多晶石夕材料來製化物半導體(MC)S)電晶體時通常會使用 域得以在高溫下〜電晶_閘極電極，使其雜與波極區 擋以離子佈植軸^進行退火。其次’由於多晶魏夠阻 案化之後能容易地=原子進人通道區域，因此在閘極圖 地形成自行對準的源極與汲極區域。 材料相比，多晶許多缺點。首先’與大多數金屬 成。曰間極疋以高電阻值的半導體材料所形 强你&夕阳⑦閘極是以比金屬導線為低的傳導速率在 刼作。為了彌補高電阻鱼甘： 龟卩與其相應之較低操作速率，多晶矽 〆吊 里與昂責的矽化金屬處理，使其操作速率 可提升至可接受的範圍。 ββ其人夕日日夕閘極容易產生空乏效應（depletion effect)。 嚴格來說目刚夕晶石夕的摻雜濃度只能達到約WO'm3 到約3xlG /em的範圍。在閘極材料中的摻雜濃度需要至 少達到如心⑽3的條件下，由於雜濃度上的限制，因 7 201011837 此當多晶石夕閘極受到偏麗時’便會發生缺乏載子的現象， -使得靠近多晶石夕閘極與閘極介電層的介面上就容易產生介 乏區。而此空乏效應除了會使等效的閘極介電層厚度= 加，又同時造成閘極電容值下降鱼 Γ ^進而導致兀件驅動能力 衰退等困境。 故目前便有新的閘極材料被研製生產，例如利用具特定 〇 功函數(work function)之金屬間極來取代傳統的多晶石夕閑 極。然而，製做金屬閘極時，一方面需要與醒〇s元件搭 配’另一方面則又需與PMOS元件相匹配，以符合醒〇s 電晶體與PMOS電晶體的需求，而分別形成功函數的費米 能階(Fermi level)接近 N 型石夕(N_type Si)與 p 型矽(p_typeSi) 的準費米能階(Quasi Fermi level)的金屬，因此使得相關元 件的整合技術以及製程控制更形複雜，且各材料的厚度與 成分控制要求亦更形嚴苛。需注意的是，目前製作金屬閘 極所廣泛採用的方法是先掏空虛置（dummy)閘極中的多晶 矽材料，然後再依序填入所需的N型金屬與P型金屬。 然而’這種作法雖可同時製作出具有兩種功函數的金屬 閘極’但在填入低電阻材料的時候時常會因空間的不足(例 如N型金屬層佔據了閘極侧壁的大部分空間）而提高閘極 . 的電阻值，使兩邊的電晶體區無法獲得平均的電阻值，嚴 重影響電晶體的效能。因此，如何改良目前製作雙功能函 8 201011837 數金屬開極的製程 力產品的作法即為 而能同時達到降低成本與完成具有 一重要課題。 競爭 【發明内容】 的是揭露一種製作具有金屬閘極之電 本發明之主要目 晶體的方法。 ❹：發曰明之方法主要是先提供一基底，且基底上定義有一 第*電阳體區與一第二電晶體區。然後形成一堆疊薄膜並 覆蓋基底，且堆叠薄膜包含一高介電常數介電層與一第一 金屬層。接著圖案化堆叠薄膜，以分別於第-電晶體區與 第-電晶體區形成-閘極。然後形成一介電層並覆蓋該等 Ά極再進行平坦化製程以去除部分介電層直至各閉極 頂4。然後去除第二電晶體區之閘極内的第一金屬層，並 》形成一第二金屬層於介電層及閘極表面，以於第一電晶體 區及第二電晶體區分別形成一金屬閘極。 本發明的另一實施例是揭露一種具有金屬閘極之電晶 體，包含有一基底，基底上定義有一第一電晶體區及一第 二電晶體區以及一金屬閘極設於第一電晶體區。其中，金 屬閘極另包含一高介電常數介電層設於金屬閘極的底部， 一第一金屬層設於高介電常數介電層表面且不延伸至金屬 閘極之侧壁，以及一第二金屬層設於第一金屬層上並同時 9 201011837 覆蓋金屬閘極之側壁。 【實施方式】 凊參照·第1圖至第9圖’第1圖至第9圖為本發明較佳 實施例製作一具有金屬閘極之電晶體示意圖。如第1圖所 示，首先提供一基底12，例如一矽基底或一絕緣層上覆矽 (silicon-on-insulator; SOI)基底等。然後在基底12中定義 ❹ 至少一 NM0S電晶體區14以及一 PM0S電晶體區16，並 形成複數個隔離兩個電晶體區14、16的淺溝隔離 構 18。 。 接著形成一由氧化物、氮化物等之介電材料所構成的閘 極絕緣層20在基底12表面，並形成一由高介電常數介電 層22、一選擇性之遮蓋層24、一 N型金屬層26、一客曰 矽層28以及一遮罩層30所構成的堆疊薄膜在閘極絕緣層 ❹ 20上。其中，選擇性之遮蓋層24僅覆蓋於NM0S電晶體 區14上或省略此層，且多晶矽層28係用來做為一犧牲層， 其亦可由非晶石夕或其他材料所構成。 在本較佳實施例中，高介電常數介電層22是由矽酸铪 氧化合物（HfSiO)、矽酸铪氮氧化合物（HfSi〇N)、氧化銓 (Hf0)、氧化鑭(La〇)、鋁酸鑭(LaAlO)、氧化锆(Zr0)、矽酸 锆氧化合物（ZrSiO)或锆酸銓(HfZr0)，或其組合所構成；遮 201011837 蓋層24是由氧化鑭(La〇)或氧化鋼(Dy2〇3)，或其組合所構 成，N型金屬層26是由氮化鈦(TiN)、碳化钽(TaC)、氮化 组(TaN)、氛化碎紐(TaSiN)或鋁，或其組合所構成；多晶矽 層28可由不具有任何摻質（undoped)的多晶矽材料或由具 有N+推質的多晶矽材料所構成；而遮罩層3〇則是由二氧 化矽（SiOJ、氮化矽（SiN)、碳化矽（siC)或氮氧化矽（si〇N) 所構成。 ❹ 接著如第2圖所示，形成一圖案化光阻層（圖未示）在遮 罩層30上，並利用圖案化光阻層當作遮罩進行一圖案轉移 製程，以單次蝕刻或逐次蝕刻步驟，去除部分的遮罩層3〇、 多晶矽層28、N型金屬層26、遮蓋層24、高介電常數介電 層22及閘極絕緣層2〇，並剝除此圖案化光阻層，以於 NMOS電晶體區14以及PM〇s電晶體16區各形成一閘極 32 ° 如第3圖所示，然後在nm〇s電晶體區14及PM0S電 晶體區16各選擇性進行一淺摻雜製程，以形成所需的輕摻 雜源與汲極。舉例來說，本發明可先覆蓋一圖案化光阻層 (圖未示）在NMOS電晶體區14以外的區域，然後利用該圖 案化光阻層當作遮罩進行一離子佈植，將N型摻質植入 • NMOS電晶體區14之閘極32兩側的基底12中，以kNM〇s 電晶體區14形成一輕摻雜源與汲極％。接著去除上述的 201011837 圖案化光阻層’再覆蓋另一圖案化光阻層在PMOS電晶體 區16以外的區域，並利用該圖案化光阻層當作遮罩進行另 一離子佈植，將P型摻質植入PMOS電晶體區16之閘極 32兩侧的基底12中’以於PMOS電晶體區16形成一輕摻 雜源與汲極36。 隨後進行第一階段的側壁子製程，例如先氧化多晶矽層 28的表面或以沈積的方式形成一氧化矽層38,接著再沈積 一氮化矽層40並利用蝕刻方式形成由氧化矽層38與氮化 矽層40所構成的側壁子在NMOS電晶體區14與PMOS電 晶體區16之閘極32的周圍侧壁。 如第4圖所示’先覆蓋一由氮化矽所構成的保護層42 於氮化矽層40表面，然後進行一選擇性磊晶成長(selective epitaxial growth，SEG)製程，以於NMOS電晶體區14或 PMOS電晶體區16之基底12中形成應變珍（strained Si)。 例如可先於PMOS電晶體區16之閘極32兩側的基底12 中形成二凹槽，再利用選擇性磊晶成長製程實質上 (substantially)填滿這兩個凹槽而形成石夕鍺層44。此石夕鍺層 44可對PMOS電晶體區16的通道區域施加一壓縮應力 (compressive strain)’進而提升PMOS電晶體的電洞遷移 率。除此之外’也可依據製程的需求在NMOS電晶體區14 之閘極32兩侧的基底12中形成碳化石夕（sic)層（圖未示）， 12 201011837 並以此碳化石夕層對NMOS電晶體區14的通道區域施加一 拉伸應力（tensile strain)，以提升NMOS電晶體的電子遷移 率。 接著進行第二階段的側壁子製程，例如可在NMOS電晶 體區14與PMOS電晶體區16的保護層42側壁上再形成一 由氧化石夕所形成的侧壁子46。 〇 隨後在NMOS電晶體區14及PMOS電晶體區16各進 行一重摻雜離子佈植製程，以分別形成所需的源極/汲極區 域。如同上述形成輕摻雜没極的作法，本發明可先覆蓋一 圖案化光阻層（圖未示）在NMOS電晶體區14以外的區域， 然後利用該圖案化光阻層當作遮罩進行一離子佈植製程， 將N型摻質植入側壁子46兩侧的基底12中，以於NM〇s 電晶體區14形成一源極/汲極區域48。接著去除上述的圖 案化光阻層’再覆蓋另一圖案化光阻層在PMOS電晶體區 16以外的區域，姐利用該圖案化光阻層當作遮罩進行另一 離子佈植，將P蜇摻質植入PMOS電晶體區16側壁子46 兩側的基底12中’以形成另一源極/汲極區域5〇。 另需注意的是，上述源極/沒極區域的製程可利用選擇性 蟲晶成長製程來遠成、這些製程的進行順序可依製程需求 改變或調整、且側壁子的數目並不限於此。舉例來說，在 201011837 進行第一階段的側壁子製程時可省略氧化矽層38或氮化 石夕層40的其中一者’且在形成氮化石夕所構成的保護層μ 及側壁子46時可省略其中-者。除此之外，由氧化石夕層 38及氮切層4G所構成駐側壁子可在形成輕摻雜源^ 汲，34、36之前或之後才製作；可先形成由氧化矽層％ 及氮化矽層40所構成的主侧壁子及源極/汲極區域，然後 去除侧壁子之後再形成輕摻雜源極汲極；可於形成複數個 © 侧壁子後先在半導體基底中蝕刻出凹槽並形成磊晶層然 後去除最外層的側壁子後再進行源極/汲極區域製程；可於 輕換雜源極汲極製程後先於半導體基底中蝕刻出凹槽以形 成蟲晶層’然後形成侧壁子後再進行源極/汲極區域的製 程。上述關於輕摻雜源極汲極、侧壁子以及源極/汲極區域 等製程順序都屬本發明所涵蓋的範圍。 然後在形成源極/;及極區域48、50後，進行一個自行對 ❹準矽化金屬（self-aligned silicide，Salicide)製程。例如先形 成一由鈷、鈦、鎳、鉑、鈀或鉬等所構成的金屬層（圖未示） 在基底12表面並覆蓋側壁子46，並進行一快速升溫退火 製程，利用高溫使金屬層與侧壁子46兩側的基底12表面 反應為一矽化金屬層52。最後再去除未反應的金屬層。 接著形成一氮化矽層54在各閘極32、各侧壁子46與基 底12表面。在本較佳實施例中，氮化矽層54的厚度約為 201011837 100埃，其主要做為後續進行平坦化時之一钱刻停止層。 又’亦可在NMOS電晶體區14與PMOS電晶體區分別形 成具有拉伸應力與收縮應力的較厚氮化矽層作為應力層， 此應力層兼具有提供應力及作為钱刻停止層的功用。然後 形成一主要由氧化物所構成的層間介電層（interlayer dielectric)56並覆蓋NMOS電晶體區14與PMOS電晶體區 16的氮化矽層54。此層間介電層可包含氮化物、氧化物、 碳化物、低介電係數材料中之一或多者。 如第5圖所示，進行一化學機械研磨（chemical mechanical polishing，CMP)製程或一乾蝕刻製程，以去除部 分的層間介電層56、氮化矽層54及遮罩層30，並使多晶 矽層28頂部約略切齊於層間介電層56表面而受到裸露。 如第6圖所示’接著進行一選擇性之乾蝕刻或濕蝕刻製 程，例如利用氨水(ammonium hydroxide，NH4〇H)或氫氧化 四甲銨(Tetramethylammonium Hydroxide，TMAH)等 ϋ 刻溶 液來去除NMOS電晶體區14及PMOS電晶體區16中的多 晶石夕層28但不#刻層間介電層56，以在各電晶體區14、 16形成一開口 58。需注意的是’在形成開口 58時會同時 暴露出設於各開口 58底部的N型金屬層26。 如第7圖所示，先形成一圖案化光阻層60在NMOS電 15 201011837 晶體區14，然後進行一乾蝕刻或濕蝕刻製程，以去除設置 在PMOS電晶體區16的N型金屬層26。根據本發明之較 佳實施例，如採用濕蝕刻製程，所使用的飯刻劑玎選自由 氨水(ammonium hydroxide，NH4OH)、過氧化氫(hydrogen peroxide，H2〇2)、硫酸(H2S〇4)及鹽酸與去離子水所組成的 混合溶液。如採用乾蝕刻製程，所使用的蝕刻氣體則可選 自由三氯化硼（BC13)、氣氣(Cl2)、六氟化硫(SF6)、氮氣及 氬氣所構成的群組。需注意的是，無論是採用何種蝕刻製 程’本發明都是在不損害高介電常數介電層22的情況下來 去除設置在PMOS電晶體區16的N型金屬層26，並暴露 出南介電常數介電層22。 如第8圖所示，在除圖案化光阻層6〇之後，先沈積一 p 型金屬層62在層間介電層56上並同時覆蓋NMOS電晶體 區14的開口 58側壁及n型金屬層26，以及PMOS電晶體 區的開口 58側壁及高介電常數介電層22。在本實施例 中’ P型金屬層62是由氮化鈦(TiN)、鎢(W)、氮化鶴(WN)、 銘（pt)、鎳（Ni)、釕(Ru)、碳氮化组（TaCN)或碳氮氧化钽 (TaCNO)所構成。 接著填入一由低電阻材料所構成的導電層64在NMOS 電晶體區14與PMOS電晶體區16的1>变金屬層62上並填 滿開口 58。在本實施例中，導電層64町由鋁、鎢、鈦鋁 16 201011837 合金（TiAl)或銘鶴鱗化物（c〇balt tungsten phosphide，CoWP) 專低電阻材料所構成。 最後如第9 ϋ所示，進行另一化學機械研磨製程，去除 ^刀的導電層64及Ρ型金屬層62，以同時於1SHV10S電晶 體區14 & PM〇S電晶體區16分別形成—具有金屬閉極 66、68的電晶體。 再如第9圖所示，本發明依據上述製程另揭露一種具有 金屬閘極66、68 @ CMOS電晶體結構，其主要包含有一 基底12、兩個金屬閘極66、68分別設置於基底12上的 NMOS電晶體區14及pM〇s電晶體區16以及兩個源極/ 及極區域48、50分別^於金屬閘極66、68兩側的基底12 中。其中’丽〇S t晶體區14的金屬閉極66包含有一閘 極絕緣層20設於金屬閘極66的底部、一高介電常數介電 層22設於閘極絕緣層20上、一遮蓋層24設於高介電常數 介電層22上、一 N型金屬層26設於遮蓋層24表面且不向 上延伸成金屬閘極66的側壁、一 U型之p型金屬層62設 於N型金屬層26上並向上延伸成金屬閘極66的侧壁以及 一導電層64設於？型金屬層62上並填滿NMOS電晶體區 14原本的開口 58。在本實施例中，高介電常數介電層22、 遮蓋層24以及N型金廣層26都是設置在金屬閉極的的相 對底部且不延伸成金屬閘極66的侧壁。 17 201011837 * PMOS電晶體區16 $金屬閘極68貝丨i包含有-閘極絕緣 層20設於金屬閘極66的底部、一高介電常數介電層22設 於閘極絕緣層.20上、一 U型之P型金屬層62設於高介電 常數介電層22上並同時向上延伸成金屬閘極68的侧壁以 及-導電層64 β又於P型金屬層62上並填滿pM〇s電晶體 區16原本的開口 58。 ❹ 綜上所述’本發明主要是先全面性沈積一由高介電常數 介電層、N型金屬層及多晶矽材料所構成的多層堆疊薄膜 在基底上，然後再圖案化此堆疊薄膜以形成所須之閘極。 接著形成一平坦化之層間介電層，再去除閘極中的多晶矽 材料，並依序填入所需的P型金屬與低電阻材料。由於N 型金屬層在去除多晶石夕材料之前就已經設置在金屬閘極的 底部’因此後續填入低電阻材料至Nm〇s電晶體區的時候 不致因N型金屬佔據閘極的侧壁而縮減了低電阻材料可 置的空間。藉由上述作法’本發明可使兩邊的電晶體區獲 得更平均的電阻值’進而提升CM〇s電晶體的整體效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍0 18 201011837 ' 【圖式簡單說明】 * 第1圖至第9圖為本發明較佳實施例製作一具有金屬閘極 之電晶體不意圖。201011837 IX. Invention Description: The technical field of the invention belongs to the present invention. The present invention is a method for unifying the 鄕 鄕 鄕 ; ; ; ; ; ; ; ; 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The heat-resistance property of the polycrystalline stone material is usually used to form a semiconductor (MC) S) transistor. The domain is usually used at a high temperature ~ electro-ceramic _ gate electrode, so that the impurity and the wave region block the ion cloth The implant shaft ^ is annealed. Secondly, since the polycrystalline Wei can be easily resisted and then the atom can enter the channel region, a self-aligned source and drain region is formed in the gate pattern. Compared to materials, polycrystalline has many disadvantages. First of all, with most metals. The dipoles are shaped by high-resistance semiconductor materials. You & sunset 7 gates are at a lower conduction rate than metal wires. In order to compensate for the high-resistance fish: the turtles and their corresponding lower operating rates, the polycrystalline crucibles and the ridiculous deuterated metal treatments allow the operating rate to be increased to an acceptable range. The ββ is very prone to depletion effect. Strictly speaking, the doping concentration of the ceramsite can only reach a range of about WO'm3 to about 3xlG /em. The doping concentration in the gate material needs to be at least as high as (10) 3, due to the limitation of the impurity concentration, because 7 201011837, when the polycrystalline stone gate is extremely biased, the phenomenon of lack of carriers will occur. - It is easy to create a depletion zone on the interface close to the polycrystalline silicon gate and the gate dielectric layer. In addition to the depletion effect, the thickness of the equivalent gate dielectric layer is increased, and at the same time, the value of the gate capacitance decreases, which leads to the decline of the driving ability of the component. Therefore, new gate materials have been developed and produced, for example, by replacing the conventional polycrystalline litter with an intermetallic pole having a specific work function. However, when making a metal gate, on the one hand, it needs to be matched with the awake s component. On the other hand, it needs to be matched with the PMOS device to meet the requirements of the 〇 s transistor and the PMOS transistor, and the success function is separately formed. The Fermi level is close to the N-type Si and the pasi-type (p_typeSi) quasi-fermi level metal, thus making the integration of the related components and process control more The shape is complex, and the thickness and composition control requirements of each material are also more stringent. It should be noted that the current widely used method for fabricating metal gates is to first hollow out the polysilicon material in the dummy gate and then fill in the required N-type metal and P-type metal in sequence. However, 'this method can simultaneously produce metal gates with two work functions' but often fills in low-resistance materials due to lack of space (for example, the N-type metal layer occupies most of the gate sidewalls) Space) increases the resistance of the gate. The transistor area on both sides cannot obtain the average resistance value, which seriously affects the performance of the transistor. Therefore, how to improve the current process of manufacturing dual-function 8 201011837 metal-opening process products is an important issue to achieve both cost reduction and completion. COMPETITIVE A method of fabricating a primary crystal of the invention having a metal gate is disclosed. ❹: The method of the invention is mainly to provide a substrate, and the substrate defines a first electro-positive body region and a second electro-optic region. A stacked film is then formed and covers the substrate, and the stacked film comprises a high-k dielectric layer and a first metal layer. The stacked film is then patterned to form a gate between the first transistor region and the first transistor region, respectively. A dielectric layer is then formed and the drain is covered and a planarization process is performed to remove portions of the dielectric layer up to each of the closed tops 4. And removing a first metal layer in the gate of the second transistor region, and forming a second metal layer on the dielectric layer and the gate surface to form a first transistor region and a second transistor region respectively Metal gate. Another embodiment of the invention discloses a transistor having a metal gate, comprising a substrate having a first transistor region and a second transistor region defined thereon, and a metal gate disposed in the first transistor region . Wherein, the metal gate further comprises a high-k dielectric layer disposed at the bottom of the metal gate, a first metal layer disposed on the surface of the high-k dielectric layer and not extending to the sidewall of the metal gate, and A second metal layer is disposed on the first metal layer and at the same time 9 201011837 covers the sidewall of the metal gate. [Embodiment] FIG. 1 to FIG. 9 are a schematic view showing a transistor having a metal gate according to a preferred embodiment of the present invention. As shown in Fig. 1, a substrate 12 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. At least one NMOS transistor region 14 and a PMOS transistor region 16 are then defined in the substrate 12 and a plurality of shallow trench isolations 18 are provided which isolate the two transistor regions 14, 16. . Then, a gate insulating layer 20 made of a dielectric material such as an oxide or a nitride is formed on the surface of the substrate 12, and a high-k dielectric layer 22, a selective mask layer 24, and a N are formed. A stacked film of a metal layer 26, a guest layer 28, and a mask layer 30 is formed on the gate insulating layer 20 . The selective mask layer 24 covers only the NMOS transistor region 14 or omits the layer, and the polysilicon layer 28 is used as a sacrificial layer, which may also be composed of amorphous or other materials. In the preferred embodiment, the high-k dielectric layer 22 is composed of a hafnium oxynitride (HfSiO), a niobium oxynitride (HfSi〇N), a hafnium oxide (Hf0), or a hafnium oxide (La〇). ), lanthanum aluminate (LaAlO), zirconia (Zr0), zirconium oxynitride (ZrSiO) or yttrium zirconate (HfZr0), or a combination thereof; cover 201011837 cover layer 24 is made of lanthanum oxide (La〇) Or oxidized steel (Dy2〇3), or a combination thereof, the N-type metal layer 26 is made of titanium nitride (TiN), tantalum carbide (TaC), nitrided group (TaN), catalyzed broken (TaSiN) or Aluminum, or a combination thereof; the polysilicon layer 28 may be composed of a polycrystalline germanium material having no undoped or a polycrystalline germanium material having an N+ push; and the mask layer 3 is made of cerium oxide (SiOJ, It is composed of tantalum nitride (SiN), tantalum carbide (siC) or niobium oxynitride (si〇N). ❹ Next, as shown in FIG. 2, a patterned photoresist layer (not shown) is formed on the mask layer 30. And performing a pattern transfer process using the patterned photoresist layer as a mask, and removing a part of the mask layer 3, the polysilicon layer 28, and the N type by a single etching or successive etching step a layer 26, a cap layer 24, a high-k dielectric layer 22 and a gate insulating layer 2, and stripping the patterned photoresist layer for each of the NMOS transistor region 14 and the PM 〇s transistor region 16 Forming a gate 32 ° as shown in FIG. 3, and then selectively performing a shallow doping process in the nm〇s transistor region 14 and the PMOS transistor region 16 to form a desired lightly doped source and drain For example, the present invention may first cover a region of a patterned photoresist layer (not shown) outside the NMOS transistor region 14, and then use the patterned photoresist layer as a mask for ion implantation. N-type dopant implantation • In the substrate 12 on both sides of the gate 32 of the NMOS transistor region 14, a lightly doped source and a drain % are formed by the kNM〇s transistor region 14. Then, the above-mentioned 201011837 patterned light is removed. The resist layer 'overlaps another patterned photoresist layer in a region other than the PMOS transistor region 16, and uses the patterned photoresist layer as a mask for another ion implantation, and implants the P-type dopant into the PMOS battery. The substrate 12 on both sides of the gate 32 of the crystal region 16 is formed in the PMOS transistor region 16 to form a lightly doped source and a drain 36. A stage of the sidewall process, such as first oxidizing the surface of the polysilicon layer 28 or depositing a tantalum oxide layer 38, followed by depositing a tantalum nitride layer 40 and forming an oxide layer 38 and tantalum nitride by etching. The sidewalls formed by the layer 40 are on the sidewalls of the NMOS transistor region 14 and the gate 32 of the PMOS transistor region 16. As shown in Fig. 4, a protective layer 42 made of tantalum nitride is first covered with nitrogen. The surface of the germanium layer 40 is then subjected to a selective epitaxial growth (SEG) process to form strained Si in the substrate 12 of the NMOS transistor region 14 or the PMOS transistor region 16. For example, two grooves may be formed in the substrate 12 on both sides of the gate 32 of the PMOS transistor region 16, and then the selective epitaxial growth process is used to substantially fill the two grooves to form a stone layer. 44. This shovel layer 44 can apply a compressive strain on the channel region of the PMOS transistor region 16 to increase the hole mobility of the PMOS transistor. In addition, a carbon sic layer (not shown) may be formed in the substrate 12 on both sides of the gate 32 of the NMOS transistor region 14 according to the requirements of the process, 12 201011837 and the carbonized stone layer A tensile strain is applied to the channel region of the NMOS transistor region 14 to increase the electron mobility of the NMOS transistor. Then, the second stage of the sidewall process is performed. For example, a sidewall 46 formed of oxidized oxide can be formed on the sidewalls of the protective layer 42 of the NMOS transistor region 14 and the PMOS transistor region 16.一 A heavily doped ion implantation process is then performed in each of the NMOS transistor region 14 and the PMOS transistor region 16 to form the desired source/drain regions, respectively. As described above, the method of forming a lightly doped immersion electrode may first cover a region of a patterned photoresist layer (not shown) outside the NMOS transistor region 14, and then use the patterned photoresist layer as a mask. An ion implantation process implants an N-type dopant into the substrate 12 on either side of the sidewall 46 to form a source/drain region 48 in the NM〇s transistor region 14. Then, the patterned photoresist layer is removed to cover another region of the patterned photoresist layer outside the PMOS transistor region 16, and the patterned photoresist layer is used as a mask for another ion implantation. The erbium dopant is implanted in the substrate 12 on both sides of the sidewalls 46 of the PMOS transistor region 16 to form another source/drain region 5 〇. It should also be noted that the above-mentioned source/drainage region process can be made by the selective insect crystal growth process, and the order of the processes can be changed or adjusted according to the process requirements, and the number of the sidewalls is not limited thereto. For example, in the first stage of the sidewall process in 201011837, one of the yttrium oxide layer 38 or the nitride layer 40 may be omitted and the protective layer μ and the sidewall 46 formed by the formation of the nitrite may be omitted. Omit one of them. In addition, the sidewalls formed by the oxidized stone layer 38 and the nitrogen-cut layer 4G may be formed before or after the formation of the lightly doped source, 34, 36; the yttrium oxide layer and the nitrogen may be formed first. The main sidewall and the source/drain region formed by the germanium layer 40, and then the light-doped source drain is formed after removing the sidewall; the plurality of sidewalls may be formed in the semiconductor substrate after forming a plurality of sidewalls Etching the trench and forming an epitaxial layer and then removing the outermost sidewalls before performing the source/drain region process; etching the trenches in the semiconductor substrate to form the pests after the light source switching process The seed layer' then forms a sidewall and then performs a source/drain region process. The above described process sequences for lightly doped source drains, sidewalls, and source/drain regions are within the scope of the present invention. Then, after forming the source/; and the polar regions 48, 50, a self-aligned silicide (Salicide) process is performed. For example, a metal layer (not shown) made of cobalt, titanium, nickel, platinum, palladium or molybdenum is formed on the surface of the substrate 12 and covers the sidewalls 46, and a rapid temperature annealing process is performed to make the metal layer high. The surface of the substrate 12 on both sides of the side wall 46 is reacted as a deuterated metal layer 52. Finally, the unreacted metal layer is removed. A tantalum nitride layer 54 is then formed on each of the gates 32, the side walls 46, and the surface of the substrate 12. In the preferred embodiment, the tantalum nitride layer 54 has a thickness of about 201011837 100 angstroms, which is mainly used as a stop layer for subsequent planarization. Moreover, a thicker tantalum nitride layer having tensile stress and contraction stress can be formed as a stress layer in the NMOS transistor region 14 and the PMOS transistor region, respectively, and the stress layer also provides stress and serves as a stop layer for the stop. function. Then, an interlayer dielectric 56 mainly composed of an oxide is formed and covers the NMOS transistor region 14 and the tantalum nitride layer 54 of the PMOS transistor region 16. The interlayer dielectric layer may comprise one or more of a nitride, an oxide, a carbide, and a low-k material. As shown in FIG. 5, a chemical mechanical polishing (CMP) process or a dry etching process is performed to remove portions of the interlayer dielectric layer 56, the tantalum nitride layer 54 and the mask layer 30, and the polysilicon layer is formed. The top of 28 is approximately flush with the surface of the interlayer dielectric layer 56 and is exposed. As shown in Fig. 6, 'subsequently performing a selective dry etching or wet etching process, for example, using an ammonia hydroxide (NH4〇H) or a tetramethylammonium hydroxide (TMAH) etching solution to remove the NMOS. The polycrystalline layer 28 in the transistor region 14 and the PMOS transistor region 16 but not the interlayer dielectric layer 56 forms an opening 58 in each of the transistor regions 14, 16. It should be noted that the N-type metal layer 26 provided at the bottom of each opening 58 is simultaneously exposed when the opening 58 is formed. As shown in Fig. 7, a patterned photoresist layer 60 is first formed in the NMOS region 15 201011837, and then subjected to a dry etching or wet etching process to remove the N-type metal layer 26 disposed in the PMOS transistor region 16. According to a preferred embodiment of the present invention, if a wet etching process is employed, the rice cooker used is selected from the group consisting of ammonia hydroxide (NH4OH), hydrogen peroxide (H2〇2), and sulfuric acid (H2S〇4). And a mixed solution of hydrochloric acid and deionized water. For the dry etching process, the etching gas used may be selected from the group consisting of boron trichloride (BC13), gas (Cl2), sulfur hexafluoride (SF6), nitrogen and argon. It should be noted that, regardless of the etching process used, the present invention removes the N-type metal layer 26 disposed in the PMOS transistor region 16 without damaging the high-k dielectric layer 22, and exposes the south. Dielectric constant dielectric layer 22. As shown in FIG. 8, after the patterned photoresist layer 6 is formed, a p-type metal layer 62 is deposited on the interlayer dielectric layer 56 while covering the opening 58 sidewall and the n-type metal layer of the NMOS transistor region 14. 26, and the opening 58 sidewall of the PMOS transistor region and the high-k dielectric layer 22. In the present embodiment, the 'P-type metal layer 62 is made of titanium nitride (TiN), tungsten (W), nitrided crane (WN), 铭 (pt), nickel (Ni), ruthenium (Ru), carbonitriding. Group (TaCN) or tantalum oxynitride (TaCNO). Next, a conductive layer 64 composed of a low-resistance material is filled in the NMOS transistor region 14 and the 1> metallization layer 62 of the PMOS transistor region 16 and fills the opening 58. In this embodiment, the conductive layer 64 is composed of aluminum, tungsten, titanium aluminum 16 201011837 alloy (TiAl) or c〇balt tungsten phosphide (CoWP) special low-resistance material. Finally, as shown in FIG. 9, another CMP process is performed to remove the conductive layer 64 and the Ρ-type metal layer 62 of the knives to form simultaneously in the 1SHV10S transistor region 14 & PM 〇 S transistor region 16 - A transistor having metal closed ends 66, 68. As shown in FIG. 9, the present invention further discloses a metal gate 66, 68 @ CMOS transistor structure according to the above process, which mainly comprises a substrate 12 and two metal gates 66 and 68 respectively disposed on the substrate 12. The NMOS transistor region 14 and the pM 〇s transistor region 16 and the two source/pole regions 48, 50 are respectively formed in the substrate 12 on both sides of the metal gates 66, 68. The metal closed electrode 66 of the 'Lithium S t crystal region 14 includes a gate insulating layer 20 disposed at the bottom of the metal gate 66, and a high-k dielectric layer 22 disposed on the gate insulating layer 20 for covering The layer 24 is disposed on the high-k dielectric layer 22, and an N-type metal layer 26 is disposed on the surface of the mask layer 24 and does not extend upward to form a sidewall of the metal gate 66. A U-shaped p-type metal layer 62 is disposed on the N. The metal layer 26 extends upwardly and extends into the sidewall of the metal gate 66 and a conductive layer 64 is disposed on the sidewall. The metal layer 62 is filled with the original opening 58 of the NMOS transistor region 14. In the present embodiment, the high-k dielectric layer 22, the cap layer 24, and the N-type gold layer 26 are both disposed at opposite ends of the metal closed and do not extend into the sidewalls of the metal gate 66. 17 201011837 * PMOS transistor region 16 $ metal gate 68 丨 i includes - gate insulating layer 20 is provided at the bottom of metal gate 66, a high-k dielectric layer 22 is provided at the gate insulating layer. The upper U-type P-type metal layer 62 is disposed on the high-k dielectric layer 22 and simultaneously extends upward to form the sidewall of the metal gate 68 and the conductive layer 64 β and the P-type metal layer 62 are filled in. The original opening 58 of the pM〇s transistor region 16 is full.综 In summary, the present invention mainly deposits a multilayer stacked film composed of a high-k dielectric layer, an N-type metal layer and a polycrystalline germanium material on a substrate, and then patterned the stacked film to form The required gate. A planarized interlayer dielectric layer is then formed, and the polysilicon material in the gate is removed and the desired P-type metal and low resistance material are sequentially filled. Since the N-type metal layer is already disposed at the bottom of the metal gate before the removal of the polycrystalline material, the subsequent filling of the low-resistance material into the Nm〇s transistor region does not cause the N-type metal to occupy the sidewall of the gate. The space that can be placed by the low-resistance material is reduced. By the above method, the present invention can obtain a more uniform resistance value on both sides of the transistor region, thereby improving the overall efficiency of the CM〇s transistor. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be within the scope of the present invention. 0 18 201011837 ' [Simple description of the drawing] * Figure 1 9 is a schematic view of a transistor having a metal gate in accordance with a preferred embodiment of the present invention.
【主要元件符號說明】 12 基底 14 NMOS電晶體區 16 PMOS電晶體區 18 淺溝隔離結構 20 閘極絕緣層 22 高介電常數介電層 24 遮蓋層 26 N型金屬層 28 多晶^夕層 30 遮罩層 32 閘極 34 輕摻雜汲極 36 輕摻雜汲極 38 氧化矽層 40 氮化矽層 42 保護層 44 矽鍺層 46 側壁子 48 源極/汲極區域 50 源極/汲極區域 52 矽化金屬層 54 氮化矽層 56 層間介電層 58 開口 60 圖案化光阻層 62 P型金屬層 64 導電層 66 金屬閘極 68 金屬閘極 19[Main component symbol description] 12 Substrate 14 NMOS transistor region 16 PMOS transistor region 18 shallow trench isolation structure 20 gate insulating layer 22 high dielectric constant dielectric layer 24 mask layer 26 N-type metal layer 28 polycrystalline layer 30 Mask layer 32 Gate 34 Lightly doped drain 36 Lightly doped drain 38 Tantalum oxide layer 40 Tantalum nitride layer 42 Protective layer 44 Tantalum layer 46 Sidewall 48 Source/drain region 50 Source/汲Polar region 52 deuterated metal layer 54 tantalum nitride layer 56 interlayer dielectric layer 58 opening 60 patterned photoresist layer 62 p-type metal layer 64 conductive layer 66 metal gate 68 metal gate 19