201010546 九、發明說明： . 【發明所屬之技彳标領域】 本發明係有關於一種基板結構，特別係有關於—種可 減少界面金屬化合物形成之基板結構。 【先前技術】 如第1圖所示，習知基板結構100係包含一基板本體 110、複數個導電柱120以及一錫鍍層13〇，該基板本體 ❹：1〇係具有複數個導通孔lu，該些導電柱12〇係形成於 該些導通孔111内，每一導電柱12〇係具有一第一表面m 及一第二表面122,該錫鍍層13〇係形成於該些導電柱12〇 之該些第二表面122上而形成複數個導電接點，由於該些 導電柱120之材質係為銅，因此該些導電柱12〇與該錫鍍 層130之間會形成一界面金屬化合物層A，使得該些導電 接點之強度降低，故該基板結構100與另一基板結構藉由 该些導電接點進行接合時，容易造成電性連接失敗。 © 【發明内容】 本發明之主要目的係在於提供一種基板結構，其係包 含一基板本體、至少一導電柱、一金屬鍍層以及一錫鍍 層’ δ玄基板本體係具有一上表面、一下表面及至少一連通 該上表面及該下表面之導通孔，該導電柱係形成於該導通 孔’該導電柱係具有一第一表面及一第二表面，該金屬鑛 層係形成於該導電柱之該第二表面，該金屬錄層係具有複 數個覆蓋該第二表面之金屬島及複數個顯露該第二表面 之二間’#玄錫鍛層係形成於該金屬鍵層上，且覆蓋該金廣 201010546 錢層之該些金屬島並填充於該些空間以形成複數個導電 . 接點。其係藉由該金屬鍍層增加該導電柱與該錫鍍層間之 接合強度，並減少界面金屬化合物之形成以提高該些導電 接點之強度及可靠度。 【實施方式】 請參閱第2及3圖，依據本發明之一具體實施例係揭 示一種基板結構200，其係包含一基板本體21〇、至少一 ❹ 導電柱220、至少一銅墊230、一金屬鍍層24〇以及—錫 鍍層250 ’該基板本體210係具有一上表面2n、一下表 面212及至少一連通該上表面211及該下表面212之導通 孔213，在本實施例中，該基板本體21〇之材質係為矽， 該導電柱220係形成於該導通孔213，該導電柱22〇係具 有一第一表面221及一第二表面222，該導電柱22〇之材 質係為銅，在本實施例中，該導電柱22〇之該第一表面22工 係凸出於該基板本體210之該上表面211，該導電柱22〇 〇 之該第二表面 222係不凸出於該基板本體210之該下表面 212,該銅墊23〇係形成於該基板本體21〇之該上表面 211，並電性連接於該導電柱22〇，該金屬鍍層240係形成 於该導電柱220之該第二表面222，該金屬鍍層24〇係具 有複數個覆蓋該第二表面222之金屬島241及複數個顯露 該第二表面222之空間242，該金屬鍍層24〇之材質係為 銀’在本實施例中’該些金屬島241之厚度係介於1奈米 至5〇奈米之間，且該些金屬島241係可呈不規則排列， 該錫鍍層25 0係形成於該金屬鍍層240上，且覆蓋該金屬 201010546 錢層24〇之該些金屬島241並填充於該些空間242以 複數個導電接點’在本實施例中，該錫鍍層25q 介於〇· 1微米至i 5糌乎之„ 士找 又尔 ^ Μ木之間。本發明係藉由該金 240增加該些導電检220盘令線播JS -> 又曰 、 电狂興3亥錫鍍層250間之接合強度，201010546 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a substrate structure, and more particularly to a substrate structure which can reduce the formation of interfacial metal compounds. [Prior Art] As shown in FIG. 1 , the conventional substrate structure 100 includes a substrate body 110 , a plurality of conductive pillars 120 , and a tin plating layer 13 , the substrate body 〇: 1 〇 has a plurality of vias lu, The conductive pillars 12 are formed in the via holes 111. Each of the conductive pillars 12 has a first surface m and a second surface 122. The tin plating layer 13 is formed on the conductive pillars 12〇. A plurality of conductive contacts are formed on the second surface 122. Since the conductive pillars 120 are made of copper, an interface metal compound layer A is formed between the conductive pillars 12 and the tin plating layer 130. The strength of the conductive contacts is reduced. Therefore, when the substrate structure 100 and the other substrate structure are bonded by the conductive contacts, electrical connection failure is likely to occur. The main purpose of the present invention is to provide a substrate structure including a substrate body, at least one conductive pillar, a metal plating layer, and a tin plating layer. The δ-shaped substrate has an upper surface and a lower surface. At least one via hole connecting the upper surface and the lower surface, the conductive pillar is formed in the via hole. The conductive pillar has a first surface and a second surface, and the metal ore layer is formed on the conductive pillar The second surface, the metal recording layer has a plurality of metal islands covering the second surface, and a plurality of two "#" tin-forged layers that expose the second surface are formed on the metal bonding layer, and cover the metal layer Jin Guang 201010546 These metal islands of the money layer are filled in the spaces to form a plurality of conductive contacts. The metal plating layer increases the bonding strength between the conductive pillar and the tin plating layer, and reduces the formation of interfacial metal compounds to improve the strength and reliability of the conductive contacts. [Embodiment] Referring to Figures 2 and 3, a substrate structure 200 including a substrate body 21, at least one conductive pillar 220, at least one copper pad 230, and a substrate is disclosed. The substrate body 210 has an upper surface 2n, a lower surface 212, and at least one via hole 213 communicating with the upper surface 211 and the lower surface 212. In this embodiment, the substrate The conductive body 220 is formed on the via hole 213. The conductive pillar 22 has a first surface 221 and a second surface 222. The conductive pillar 22 is made of copper. In this embodiment, the first surface 22 of the conductive pillar 22 is protruded from the upper surface 211 of the substrate body 210, and the second surface 222 of the conductive pillar 22 is not protruded. The lower surface 212 of the substrate body 210 is formed on the upper surface 211 of the substrate body 21 and electrically connected to the conductive pillar 22, and the metal plating layer 240 is formed on the conductive pillar. The second surface 222 of 220, the metal plating layer There are a plurality of metal islands 241 covering the second surface 222 and a plurality of spaces 242 exposing the second surface 222. The material of the metal plating layer 24 is silver 'in the present embodiment, the thickness of the metal islands 241 The system is between 1 nm and 5 nanometers, and the metal islands 241 can be arranged in an irregular arrangement. The tin plating layer 25 is formed on the metal plating layer 240 and covers the metal layer 201010546. The metal islands 241 are filled in the spaces 242 to form a plurality of conductive contacts. In the embodiment, the tin plating layer 25q is between 〇·1 μm and i 5 „ 士 士 又 ^ ^ Μ木Between the present invention, the gold 240 is used to increase the bonding strength of the wire-switching JS->
並減少界面金屬化入物夕游# ,、丨& ▲ X 屬化口物之形成以提高該些導電接點 度及可靠度。 〇 ❹ 凊參閱第4圖，其係為複數個依據本創作之具體實施 例之基板結構接合之示意圖，其係包含有m结構 300及—第二基板結構彻，該第—基板結構300係包含 一第一基板本體310、複數個第一銅導電柱320、-第— 銀鏟層330以及_第—錫鑛層34()，該第—基板本體⑽ 係具有-第-上表面311、一第一下表面312及複數個連 通°亥第i表面311及該第-下表面312之第一導通孔 3 1 3在本實施例中，該第一基板本體3 ^ 〇之材質係為矽， 該些第—銅導電柱320係形成於該些第—導通孔313，每 -第-銅導電柱320係具有一第一表面321及一第二表面 322 ’在本實施例中’該第一銅導電柱320之該第-表面 321係凸出於該第—基板本體31〇之該第一上表面m， 該第銅導電柱3 20之該第二表面322係不凸出於該第一 基板本體310之該第一下表® 312,該第-銀制330係 形成於該些第一銅導電柱320之該些第二表面322，該第 一銀鐘層330係具有複數個覆蓋該些第二表面322之第一 金層島331及複數個顯露該些第二表面322之第一空間 332 ’且該些第—金屬島33 1係可呈不規則排列，該第一 201010546 . 錫鍍層340係形成於該第一銀鍍層33〇上，且覆蓋該第一 . 銀鍵層330之該些第一金屬島331並填充於該些第一空間 332以形成複數個第一導電接點。該第二基板結構4〇〇係 包含一第二基板本體41〇、複數個第二銅導電柱420、一 第一銀鍍層43 0以及一第二錫鍍層44〇，該第二基板本體 410係具有一第二上表面411、一第二下表面412及複數 個連通該第二上表面411及該第二下表面412之第二導通 0 孔413，在本實施例中，該第二基板本體410之材質係為 矽’该些第二銅導電柱42〇係形成於該些第二導通孔413， 每一第二鋼導電柱420係具有一第三表面421及一第四表 面422，在本實施例中，該第二銅導電柱42〇之該第三表 面421係凸出於該第二基板本體41〇之該第二上表面 411，該第二銅導電柱42〇之該第四表面422係不凸出於 該第二基板本體410之該第二下表面412，該第二銀鍍層 430係形成於該些第二銅導電柱42〇之該些第四表面 〇 422，該第二銀鍍層430係具有複數個覆蓋該些第四表面 422之第二金屬島43 1及複數個顯露該些第二表面422之 第二空間432’且該些第二金層島431係可呈不規則排列， 該第二錫鍵層440係形成於該第二銀鍵層43〇上，且覆蓋 該第二銀鍍層430之該些第二金屬島431並填充於該些第 二空間432以形成複數個第二導電接點。將該第二基板本 體41〇之該第二下表面412朝向該第一基板本體31〇之該 第一下表面312，且該些第一導電接點係對準該些第二導 電接點以電性連接該第一基板結構3〇〇與該第二基板結構 8 201010546 400 〇 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1囷：習知基板結構之截面示意圖。 第2圖：依據本發明之一具體實施例，一種基板結構之截 面示意圖。 第3圖：依據本發明之一具體實施例’該基板之局部立體 圖。 第4圖：依據本發明之一具體實施例，複數個基板結構電 性連接之載面示意圖。 【主要元件符號說明】 100 基板結構 110 基板本體 111 導通孔 120 導電柱 121 第一表面 122 第二表面 130 錫鍍層 200 基板結構 210 基板本體 211 上表面 212 下表面 213 導通孔 220 導電柱 221 第一表面 222 第二表面 230 銅墊 240 金屬鍍層 241 金屬島 242 空間 250 錫錢層 300 第一基板結構 310 第一基板本體 311 第一上表面 312 第一下表面 9 201010546And reduce the interface metallization into the eve # #,, 丨 & ▲ X is the formation of the mouth to improve the electrical contact and reliability. 4, which is a schematic diagram of a plurality of substrate structure joints according to a specific embodiment of the present invention, which includes an m structure 300 and a second substrate structure, the first substrate structure 300 includes a first substrate body 310, a plurality of first copper conductive pillars 320, a -th shovel layer 330, and a -th tin layer 34 (), the first substrate body (10) has a -first-upper surface 311, a a first lower surface 312 and a plurality of first via holes 311 connected to the first surface 311 and the first lower surface 312. In this embodiment, the material of the first substrate body 3 is 矽, The first-copper conductive pillars 320 are formed on the first via-holes 313, and each of the -copper conductive pillars 320 has a first surface 321 and a second surface 322'. In this embodiment, the first The first surface 321 of the copper conductive pillar 320 protrudes from the first upper surface m of the first substrate body 31, and the second surface 322 of the second conductive pillar 3 20 does not protrude from the first surface The first table 312 of the substrate body 310 is formed on the second surfaces of the first copper conductive pillars 320 322, the first silver clock layer 330 has a plurality of first gold layer islands 331 covering the second surfaces 322 and a plurality of first spaces 332 ′ that expose the second surfaces 322 and the first metal islands 33 1 series may be arranged in an irregular manner, the first 201010546. The tin plating layer 340 is formed on the first silver plating layer 33, and covers the first metal islands 331 of the first silver bond layer 330 and is filled in The first spaces 332 form a plurality of first conductive contacts. The second substrate structure 4 includes a second substrate body 41 , a plurality of second copper conductive pillars 420 , a first silver plating layer 43 0 , and a second tin plating layer 44 , the second substrate body 410 Having a second upper surface 411, a second lower surface 412, and a plurality of second conductive vias 413 that communicate with the second upper surface 411 and the second lower surface 412. In this embodiment, the second substrate body The material of the 410 is formed by the second copper conductive pillars 42 being formed in the second conductive vias 413. Each of the second steel conductive pillars 420 has a third surface 421 and a fourth surface 422. In this embodiment, the third surface 421 of the second copper conductive pillar 42 protrudes from the second upper surface 411 of the second substrate body 41, and the second copper conductive pillar 42 is fourth. The second surface 422 is not protruded from the second lower surface 412 of the second substrate body 410. The second silver plating layer 430 is formed on the fourth surface 422 of the second copper conductive pillars 42. The two silver plating layer 430 has a plurality of second metal islands 43 1 covering the fourth surfaces 422 and a plurality of the plurality of exposed portions The second space 432 ′ of the two surfaces 422 and the second gold layer islands 431 may be arranged in an irregular manner. The second tin bond layer 440 is formed on the second silver bond layer 43 , and covers the second The second metal islands 431 of the silver plating layer 430 are filled in the second spaces 432 to form a plurality of second conductive contacts. The second lower surface 412 of the second substrate body 41 is directed toward the first lower surface 312 of the first substrate body 31, and the first conductive contacts are aligned with the second conductive contacts. Electrically connecting the first substrate structure 3 and the second substrate structure 8 201010546 400 The scope of the present invention is defined by the scope of the appended claims, and anyone skilled in the art is not Any changes and modifications made within the spirit and scope of the invention are within the scope of the invention. [Simple description of the drawing] Section 1: A schematic cross-sectional view of a conventional substrate structure. Figure 2 is a cross-sectional view showing a substrate structure in accordance with an embodiment of the present invention. Figure 3 is a partial perspective view of the substrate in accordance with an embodiment of the present invention. Figure 4 is a schematic illustration of a carrier surface in which a plurality of substrate structures are electrically connected in accordance with an embodiment of the present invention. [Main component symbol description] 100 substrate structure 110 substrate body 111 via hole 120 conductive pillar 121 first surface 122 second surface 130 tin plating layer 200 substrate structure 210 substrate body 211 upper surface 212 lower surface 213 via hole 220 conductive pillar 221 first Surface 222 Second surface 230 Copper pad 240 Metal plating 241 Metal island 242 Space 250 Tin layer 300 First substrate structure 310 First substrate body 311 First upper surface 312 First lower surface 9 201010546
313第一導通孔 3 20第 322第二表面 330第 332第一空間 340第 400第二基板結構 410第二基板本體 411第 413第二導通孔 420第 422第四表面 430第 432第二空間 440第 A 界面金屬化合物層 一導電柱 321 第一表面 一銀鏡層 331 第一金屬島 一錫鍍層 二上表面 412 第二下表面 二導電柱 421 第三表面 二銀鍵層 431 第二金屬島 二錫鍵層 ❹ 10313 first via hole 3 20 322 second surface 330 332 first space 340 400th second substrate structure 410 second substrate body 411 413 second via 420 422 fourth surface 430 432 second space 440 The first interface metal compound layer-conductive pillar 321 the first surface a silver mirror layer 331 the first metal island-tin plating layer upper surface 412 the second lower surface two conductive pillars 421 the third surface two silver bond layer 431 the second metal island tin Key layer ❹ 10