TW201018331A - Method, system and computer program product for reference information based evaluation - Google Patents
Method, system and computer program product for reference information based evaluation Download PDFInfo
- Publication number
- TW201018331A TW201018331A TW97140441A TW97140441A TW201018331A TW 201018331 A TW201018331 A TW 201018331A TW 97140441 A TW97140441 A TW 97140441A TW 97140441 A TW97140441 A TW 97140441A TW 201018331 A TW201018331 A TW 201018331A
- Authority
- TW
- Taiwan
- Prior art keywords
- information
- circuit board
- printed circuit
- actual
- response
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000011156 evaluation Methods 0.000 title claims abstract description 30
- 238000004590 computer program Methods 0.000 title claims description 40
- 230000004044 response Effects 0.000 claims abstract description 87
- 238000013461 design Methods 0.000 claims abstract description 59
- 238000007619 statistical method Methods 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 238000006073 displacement reaction Methods 0.000 claims description 7
- 238000005553 drilling Methods 0.000 claims description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims 2
- 229910052742 iron Inorganic materials 0.000 claims 1
- 230000006870 function Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 241001270131 Agaricus moelleri Species 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000011960 computer-aided design Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- YTBRNEUEFCNVHC-UHFFFAOYSA-N 4,4'-dichlorobiphenyl Chemical compound C1=CC(Cl)=CC=C1C1=CC=C(Cl)C=C1 YTBRNEUEFCNVHC-UHFFFAOYSA-N 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003708 edge detection Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
Description
201018331 六、發明說明： 【發明所属之技術領域3 本發明係為用於以參考資訊為基礎之評估的方法、系 統及電腦程式產品。 5 10 15 •- 【先前技術2 發明背景 印刷電路板係以複雜的製程製造。印刷電路板之評估 方法包括比較實際印刷電路板資訊與代表期望的印刷電路 板之設計資訊。此項比較可能導致多重錯誤警訊及錯誤檢 測，原因在於設計資訊並非必然反應實際上可接受的印刷 電路板。 需要提供用於評估印刷電路板之一種有效評估方法。 c發明内容3 發明概要 一種用於以參考資訊為基礎之5平估方法’該方法包 括：回應於期望的印刷電路板之代表性設計資訊以及回應 於實際印刷電路板資訊之統計分析結果而產生參考資訊； 以及回應於代表該印刷電路板之實際印刷電路板與該參考 資訊間之關係評估一印刷電路板。 一種用於以參考資訊為基礎之評估方法，該方法包 括：回應於下列而產生參考資訊：包括代表期望的印刷電 路板之設計資訊之一第一資料結構；包括經估計得之印刷 電路板資訊之一第二資料結構；及包括實際印刷電路板資 訊之一第三資料結構；以及回應於該參考資訊與實際印刷 20 201018331 電路板資訊間之關係來評估一印刷電路板。 一種用於以參考資訊為基礎之評估系統，該系統包 括：一記憶體單元其係適合儲存代表期望的印刷電路板之 設計資訊及實際印刷電路板資訊之統計分析、结果；一參考 5資訊產生器其係適合回應於該設計資訊及回應於實際印刷 電路板資訊之統計分析結果而產生參考資訊；以及一評估 器其係適合回應於代表該印刷電路板之實際印刷電路板資 訊與該參考資訊間之關係評估一印刷電路板。 一種用於以參考資訊為基礎之評估系統，該系統包 10 括：適合用於儲存參考資訊之一記憶體單元；適合回應於 下列而產生參考資訊之一參考資訊產生器：包括代表期望 的印刷電路板之設計資訊之一第一資料結構；包括經估計 得之印刷電路板資訊之一第二資料結構；及包括實際印刷 電路板資訊之一第三資料結構；以及一評估器，其係適合 15 回應於該參考資訊與實際印刷電路板資訊間之關係來評估 —印刷電路板。 一種電腦程式產品，其包括儲存下列指令之一電腦可 讀取媒體：回應於期望的印刷電路板之代表性設計資訊以 及回應於實際印刷電路板資訊之統計分析結果而產生參考 20資訊；以及回應於代表該印刷電路板之實際印刷電路板與 該參考資訊間之關係評估一印刷電路板。 一種電腦程式產品，其包括儲存下列指令之一電腦可 讀取媒體：回應於下列而產生參考資訊：包括代表期望的 印刷電路板之設計資訊之一第一資料結構；包括經估計得 201018331 之印刷電路板資訊之一第二資料結構；及包括實際印刷電 路板資訊之一第三資料結構；以及回應於該參考資訊與實 際印刷電路板資訊間之關係來評估一印刷電路板。 圖式簡單說明 -5 由後文詳細說明結合附圖將更完整了解本發明，附圖 . 中： 第1圖顯示根據本發明之一實施例之一處理器及多種 資料結構； β 第2圖顯示根據本發明之一實施例之一印刷電路板之 10 期望掃描圖案及一條帶區分成為多個區； 第3圖顯示根據本發明之一實施例之一期望區及多個 期望的校準目標； 第4圖顯示根據本發明之一實施例之一期望區及多個 期望的感興趣區； 15 第5圖顯示根據本發明之一實施例之經估計的墊片及 經估計的焊罩及所接受的容差； 癰 W ' 第6圖顯示根據本發明之一實施例之一期望的感興趣 區及多個期望的不相關區； 第7圖顯示根據本發明之一實施例之一條帶之通用校 20 準； 第8圖顯示根據本發明之一實施例之一區之校準； 第9圖顯示根據本發明之一實施例之一參考結構的產 生； 第10圖顯示根據本發明之一實施例之臨界值及灰階資 5 201018331 訊； 第11圖顯示根據本發明之-實施例之4興趣區的產 第12圖顯轉據本發明之-實施狀參考校準目標的 第13圖顯不根據本發明之—實施例回應於錢孔所在 置之一感興趣的參考區及—參考不相_之產生； 第Η圖顯示根據本發明之_實施例之感興 層疊區之產生； 參考 10 種用於以參考資訊為基礎 種用於以參考資訊為基礎 第15圖顯示根據本發明之一 之評估方法；以及 第16圖顯示根據本發明之_ 之評估方法。201018331 VI. Description of the Invention: [Technical Field 3 of the Invention] The present invention is a method, system and computer program product for evaluation based on reference information. 5 10 15 •- [Prior Art 2 Background of the Invention Printed circuit boards are manufactured in a complicated process. The evaluation method for printed circuit boards involves comparing the actual printed circuit board information with the design information representing the desired printed circuit board. This comparison may result in multiple false alarms and false detections because the design information does not necessarily reflect the actual acceptable printed circuit board. There is a need to provide an effective evaluation method for evaluating printed circuit boards. c SUMMARY OF THE INVENTION 3 SUMMARY OF THE INVENTION A method for estimating a rating based on reference information 'This method includes: generating representative design information of a desired printed circuit board and generating statistical analysis results in response to actual printed circuit board information Reference information; and evaluating a printed circuit board in response to a relationship between the actual printed circuit board representing the printed circuit board and the reference information. An evaluation method based on reference information, the method comprising: generating reference information in response to: including a first data structure representing design information of a desired printed circuit board; including estimated printed circuit board information a second data structure; and a third data structure including actual printed circuit board information; and evaluating a printed circuit board in response to the relationship between the reference information and the actual printed data of the 201018331 circuit board. An evaluation system based on reference information, the system comprising: a memory unit adapted to store design information representing a desired printed circuit board and statistical analysis and results of actual printed circuit board information; The device is adapted to generate reference information in response to the design information and in response to statistical analysis of actual printed circuit board information; and an evaluator adapted to respond to actual printed circuit board information representing the printed circuit board and the reference information The relationship between the evaluation of a printed circuit board. A reference information-based evaluation system, the system package 10: a memory unit suitable for storing reference information; a reference information generator adapted to generate reference information in response to: including printing on behalf of the desired a first data structure of the design information of the circuit board; a second data structure including one of the estimated printed circuit board information; and a third data structure including actual printed circuit board information; and an evaluator suitable for 15 Evaluate the printed circuit board in response to the relationship between the reference information and the actual printed circuit board information. A computer program product comprising a computer readable medium storing one of the following instructions: generating representative information in response to a desired printed circuit board and generating a reference 20 information in response to statistical analysis of actual printed circuit board information; and responding A printed circuit board is evaluated for the relationship between the actual printed circuit board representing the printed circuit board and the reference information. A computer program product comprising a computer readable medium storing one of the following instructions: generating reference information in response to: including a first data structure representing design information of a desired printed circuit board; including printing of an estimated 201018331 a second data structure of the board information; and a third data structure including actual printed circuit board information; and evaluating a printed circuit board in response to the relationship between the reference information and the actual printed circuit board information. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 shows a processor and various data structures in accordance with an embodiment of the present invention; Displaying a desired scan pattern and a strip of a printed circuit board according to one embodiment of the present invention into a plurality of regions; FIG. 3 shows a desired region and a plurality of desired calibration targets in accordance with an embodiment of the present invention; Figure 4 shows a desired region and a plurality of desired regions of interest in accordance with an embodiment of the present invention; 15 Figure 5 shows an estimated gasket and an estimated weld shield and chamber in accordance with an embodiment of the present invention Accepted tolerance; 痈W' Figure 6 shows a desired region of interest and a plurality of desired unrelated regions in accordance with one of the embodiments of the present invention; Figure 7 shows a strip according to one embodiment of the present invention. General Figure 20; Figure 8 shows calibration of a region in accordance with one embodiment of the present invention; Figure 9 shows the generation of a reference structure in accordance with one embodiment of the present invention; Figure 10 shows an implementation in accordance with one embodiment of the present invention Criticality And grayscale 5, 201018331; Figure 11 shows the production of the region of interest according to the embodiment of the present invention. FIG. 12 is a perspective view of the present invention. FIG. 13 is not according to the present invention. - the embodiment responds to the reference area of interest of one of the money holes and the generation of the reference phase; the figure shows the generation of the immersion layer according to the embodiment of the invention; The information-based species is used to display the evaluation method according to one of the present invention based on the reference information, and the evaluation method according to the present invention is shown in FIG.
C資施方式;J 15較佳實施例之詳細說明 由於實施本發明之裝置大半係由熟諸技藝人士已矣 電子組件及電路所組成，為求明瞭及了解本發明之° :以及為了不藏淆或歧本發明之教示内容，將不 引文舉例說明所需之任何更大程度來解說電路細節。 20 >於後文說明書中，將參考本發明之實施例之特定細節 »兒月本發明。但顯然易知可未悖離如隨附之申請專利範圍 陳述之本發明之廣義精聽及範圍而於其中做出多項修改及 變化。 業已顯不經由比較實際印刷電路板（PCB)資訊與由 201018331 P C B設計資訊以及由先前得知的實際p c B資訊所導出之參 考資訊可改良實際PCB資訊之評估。參考資訊可界定感興 趣區及不相關區，其中於感興趣區内部之實際PCB資訊經 過遽且與參考特徵做比較，而於一不相干區内部之實際 5 PCB資訊被忽略不計。 第15圖顯示根據本發明之一實施例，一種用於以參考 資訊為基礎之評估方法1500。 方法1500始於階段1510、1520及1530。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE PRESENT INVENTION The majority of the apparatus for carrying out the present invention consists of electronic components and circuits that have been constructed by those skilled in the art to understand and understand the invention: and not to hide Confusion or ambiguity of the teachings of the present invention will not be exemplified to illustrate any particular degree of detail required to illustrate circuit details. 20 > In the following description, reference will be made to the specific details of the embodiments of the invention. It will be apparent, however, that various modifications and changes can be made therein without departing from the scope and scope of the invention as set forth in the appended claims. The evaluation of actual PCB information has been improved without comparing the actual printed circuit board (PCB) information with the reference information derived from the 201018331 P C B design information and the actual p c B information previously known. The reference information can define the interest area and the irrelevant area. The actual PCB information inside the area of interest is compared and compared with the reference feature, and the actual 5 PCB information inside an unrelated area is ignored. Figure 15 shows an evaluation method 1500 for reference information based on an embodiment of the present invention. Method 1500 begins at stages 1510, 1520, and 1530.
階段1510包括接收代表一期望的pCB之設計資訊。該 10設計資訊可經由應用電腦輔助設計（CAD)方法產生。該設計 資訊包括與全體PCB或與部分pCB相關之資訊。 15 20 PCB包括多個期望區，該等期望區理想上為相同，其 '•又"十資訊實質上為相同。一個期望區包括多個期望的校準 目標及多個感興趣區。參考第3圖陳述之實例，區ιι〇包括 期望之权準目標114、115及116。此等期望的校準目標中只 有4刀為校準所冑，如校準窗117、川及⑽舉例說明各 個校準窗包括-㈣的鮮目標之-部分。㈣的校準目 標可由不同材料製成且可能需要不同的遮罩。此等遮罩可 =定感興_同時切定科目關區。遮罩可為虛擬遮罩， ^遮罩係於參考資訊產生期間施用且此外或另外係於 ^評估_區之設計可經處理俾便界定—個或 固遮罩’諸如包括三個感興趣區113之第—遮罩ιΐ5，及包 ^趣區in及112之第二遮罩114’。於校準處理期間可 哥個區之校準目標但非必要。例如，唯有校準窗可搜 7 201018331 尋校準目標。 階段1510包括接收已處理的設計資訊或處理中的設計 資訊。處理包括例如施用圖形操作於設計資訊上諸如溶触 操作、擴大操作、減薄操作及開口操作。 5 階段1510包括接收或產生包括代表期望的PCB之設計 . 資訊之第一資料結構。參考第1圖’該資料結構標示為第一 資料結構10。 方便地’設計資訊可於多片PCB製造過程中更新。更 新可回應於PCB前次評估期間找到的製造缺陷。於此種情 〇 10況下，方法丨5〇〇包括接收或產生多於單一設計資訊資料結 構。例如，參考第1圖陳述之實例，第四資料結構40可用來 储存已更新的設計資訊。注意超過兩個時間點之設計資訊 可以不同方式儲存。 階段1520接收或產生所估計的PCB資訊，該資訊估計 15由设計資訊饋入製造程序所得結果。階段1520可包括回應 於代表期望的PCB及至少一項製程參數之設計資訊之所估 計的PCB胃訊。 ® 至少一項製程參數可為蝕刻因子、結構位移、反射因 子或其組合。不同結構及不同材料可具有不同的製程參數。 20 . 餘刻因子指示因蝕刻所導入的變形，指示於經估計的 姓刻程序施用來形成期望的結構後，該結構大小與所估計 之結構大小間之比。 結構位移參數可指示一結構由其期望之位置預期之偏 移。 8 201018331 反射因子指示預期由照明結構接收多少光。反射因子 影響由該結構所接收之檢測信號位準。反射因子為材料相 依性，也受預期的結構光滑度的影響。 參考第5圖所述實例，金墊於不同所在位置接觸焊罩， 5例如於範圍126以内接觸焊罩。換言之，金墊與焊罩間之邊 界可位在於範圍126以内之任何位置而不視為缺陷。如此， 可於範圍126以内分別接觸焊罩12ι、123及125之金墊120、 122及124被視為可接受的經估計的結構。 階段1520包括接收或產生包括經估計的PCB資訊之第 10二資料結構。參考第1圖，第二資料結構標示為第二資料結 構20。 方便地’估計得之PCB資訊可於多片PCB製程中更新。 更新可回應於前次PCB評估期間找到的製造缺陷。於此種 情況下，方法1500包括接收或產生多於單一估計得之PCB 15資訊資料結構。例如，參考第1圖陳述之實例。第五資料結 構50可用於儲存已更新的估計得之pCB資訊。發現可以多 種方式儲存多於兩個時間點之PCB資訊。 階段1530包括接收或產生實際PCb資訊。實際PCB資訊 係經由光學檢驗系統獲得。此種實際pCB資訊包括亮野資 20 訊、暗野資訊或其組合。方法1500可藉獲得實際PCB資訊 之光學檢驗系統實施，但也可藉由另一系統接收實際PCB 資訊之系統實施。本發明之方法15〇〇之又另一個實施例包 括接收若干實際PCB資訊及獲得（產生）若干實際PCB資 訊。例如產生亮野資訊及接收暗野資訊。又另一個實施例， 201018331 產生部分PCB之實際PCB資訊，同時接收另一部分之實際 PCB資訊。又另一個實施例中，產生與由第一材料所製成 之結構相關之實際PCB資訊，而接收由另一種材料所製成 之結構之實際PCB資訊。 5 實際PCB資訊可以多種方式獲得，諸如逐一條帶以光 柵樣式掃描PCB。各條帶包括多個理想上相同區，各區包 括一個或多個感興趣區及一個或多個校準標靶。參考第2 圖，藉多條帶諸如條帶1〇0(1) 1〇〇(k)掃描pcB 1〇〇，預期 各條帶包括理想上相同區諸如條帶1〇〇(1)之區11〇、12〇及 10 130 〇 於與參考結構比較前，須校準實際PCB資訊。鑑於感 興趣區及不相關區’校準區於pCB影像過濾之前進行。如 此，階段1530係包括或接著為校準實際pCB資訊與經預先 界定之座標，其也可校準參考資訊。 15 校準包括多期諸如：⑴整個條帶（諸如第7圏條帶171) 之實際PCB資讯與轴17〇所表示之座標系間之通用校準·⑼ 各區（諸如第8圖區181及18〇)與軸17〇所表示之座標系間之 以區為基礎之校準；及⑽其巾鮮每區之像素群之次區校 準。區校準及額外或另外可回應於校準目標諸如第6圖之參 2〇考校準目標130。次區校準可基於邊緣檢測及基於邊緣之校 準。 方法1500包括階段1530及額外或另外包括階段154〇。 階段1540包括執行實際PCB資狀統計分析來提供結果。 額外或另外’階段1540包括接收此種結果。 201018331 統計分析結果包括統計產生的pcB結構 。此等結構係 藉應用統計聽諸鮮.㈣平鱗而產生 。若階段1540 包括執行實際PCB資訊之統計分析來提供結果，則階段 1530係於階段1540之前進行。 5 目應於叹6十資訊(代表期望的PCB之資訊）及回應於實 際PCB=貝sfl之統计分析結果，階段151〇、152〇及154〇之後 接著為產生參考資訊之階段丨柳。注意於獲得結果之前(例 如於獲得實際PCB資訊之前），階段15魏括產生或接收初 參考資訊。初參考資訊係回應於階段151〇之結果而產生且 10另外或此外回應於階段1520之結果而產生。 若階段1550係於任選的階段152〇之前進行，則階段 1550也包括回應於估計得之PCB資訊而產生參考資訊。 階段1540之統計分析結果可與設計資訊組合來界定參 考結構。例如此項組合協助檢測出現於設計資訊但未出現 15 於所檢驗之PCB的遺漏的結構。 階段1550包括下列階段中之至少一者： 產生參考資訊之階段1551包含至少一個感興趣區、至 少一個不相關區、至少一個參考結構及至少一個參考校準 目標。 2〇 階段1552回應於已收縮之期望的結構以及回應於與該 期望的結構相關聯之多個實際結構之統計分析結果界定參 考結構。階段1552包括於統計上產生PCB結構所在位置或 已收縮之期望的結構所在位置產生參考結構。考慮期望的 結構可協助檢測遺漏的結構。期望的結構經收縮來補償實 11 201018331 際結構校準錯誤或異位，因此即使實際結構略與其期望的 結構異位’已收縮之期望的結構與實際結構間將重疊。 階段1553包括回應於與某個期望的結構相關聯之多個 實際結構内部之實際鑽孔位置，於與某個期望的結構相關 5聯之感興趣區内部界定不相關區。鑽孔包括空心鑽孔、經 . 部分填補之鑽孔及完全補滿之鑽孔由於代表錯孔之像素灰 階的起伏波動或變化而難以檢測。為了提高評估方法之強 勁度，須忽略鑽孔。鑽孔所在位置可與期望位置不同，但 通常係限於某個小區内。如第13圖所示，此小區可界定為 ❿ 10不相關區。小區620包括鑽孔630之可能所在位置，整個小 區620被界定為不相關區62卜如此，感興趣之參考區“ο包 括不相關區620。 方法1500包括回應於另一個參考結構而更新一個參考 結構’尤其當此等參考結構彼此緊密鄰近時尤為如此。 15 階段1554回應於與第二實際結構相關聯之參考結構而 界定與第-材料所製成之第一實際結構相關聯之參考結 構，該第二實際結構係位在該第-實際結構之緊鄰附近© 係由與該第—材料不同之第二材料所製成。例如，階段1554 包括回應於與金塾相關聯之第二參考結構MO,界定與層合 20物所製成之實際結構相關聯之第一參考結構BO。參考第Μ 圖陳述之實例，感興趣之期望區71〇包括圍繞期望之金塾 730之期望的層合物結構72〇。期望之金塾73〇具有矩形，但 參考金塾740 (於藉統計上產生的pcB金塾資訊更新此參考 、口構後）係小於期望之金塾73〇且具有圓化角隅。如此，回 12 201018331 應於參考金墊740之邊界，參考層合物結構750增高。 * 5 10 15 20 階段1555界定須視為屬於一個結構之多個像素之容呼 灰階範圍。階段1555包括分析統計上產生之PCB結構之像 素之灰階其界定臨界值。臨界值定義容許的灰階範圍之上 限及下限。臨界值可回應於評估方法期望之敏感度或重複 性定義。較大的範圍較敏感但提供較少重複結果。上限及 下限可定義作為具有相同灰階之灰階像素數目之函數。如 此，統计上產生之PCB結構之灰階可經建立，而出現於直 方圖中小於預定臨界值的像素將被忽略。定義參考結構邊 界之像素可具有與容許的灰階範圍之邊界相對應之灰階。 參考第10圖所示實例，直方圖1〇〇2表示每個統計上產 生之PCB結構1146(位在感興趣區1150内部）之灰階值之像 素數目。於決定臨界值操作（回應於灰階像素數目）後，容許 的灰階範圍1010之下限及上限定義為1020及1030。此等臨 界值定義參考結構1140之邊界1142，其中具有於容許灰階 範圍1010以外之灰階之像素（位於區1150内部）被視為屬於 參考結構1140之背景。此等像素可與零灰階校準。於階段 1560之評估期間，具有灰階於容許灰階度範圍1〇1〇以外之 實際PCB資訊之像素被忽略。 階段1555可依據材料、結構類別、遮罩等來定義容許 之灰階範圍。 階段1556計算遮罩。各個遮罩界定至少一個感興趣區 及至少一個不相關區。階段1556包括界定用於不同材料所 製成之結構之不同遮罩。 13 201018331 於執行階段1550後，產生已更新之參考資訊且可儲存 於資料庫，諸如第1圖之第五資料結構50。 階段1550包括界定略大於參考結構之感興趣區。參考 第11圖所示實例，感興趣區440包括參考結構420及背景像 5 素430。參考結構420可得自統計上產生之PCB結構、得自 期望之結構或其組合。 階段1510、1520、1530、1540及1550可重複多次來產 生已更新之參考資訊。鑑於已更新之參考資訊，於設計資 訊更新期間，階段1550之後可接著階段1510。於估計得之 _ 10 PCB資訊更新期間，階段1550之後可接著階段1520。 回應於參考資訊與代表PCB之實際PCB資訊間之關 係，階段1550之後接著為評估PCB之階段1560。該關係可 經由比較實際PCB資訊與參考資訊決定。 階段1560包括基於反應得自一個或多個其它PCB之實 15 際PCB資訊’評估某些PCB。例如於某個階段1510-1550之 迭代期間，第X片PCB之實際PCB資訊可獲得；反應至多第 (x-1)之參考資訊係於階段1560期間處理。如此，回應於第χ - ® 個實際PCB之參考資訊將於階段1560之下次迭代期間使 用。Stage 1510 includes receiving design information representative of a desired pCB. The 10 design information can be generated via a computer aided design (CAD) method. This design information includes information related to the entire PCB or to some of the pCB. 15 20 The PCB includes a plurality of desired regions, which are ideally the same, and the '•又" ten information is substantially the same. A desired area includes a plurality of desired calibration targets and a plurality of regions of interest. Referring to the example set forth in Figure 3, the zone ιι〇 includes the desired weight targets 114, 115 and 116. Only 4 of these expected calibration targets are calibrations, such as calibration windows 117, Sichuan, and (10) exemplifying that each calibration window includes - (d) the fresh target-part. The calibration objectives of (iv) may be made of different materials and may require different masks. These masks can be used to determine the subject area. The mask may be a virtual mask, the mask is applied during the generation of the reference information and, in addition or additionally, the design of the evaluation area may be processed to define a single or solid mask, such as including three regions of interest. 113 - the cover ιΐ5, and the second mask 114' of the cover area in and 112. Calibration targets may be used during the calibration process but are not necessary. For example, only the calibration window can be found in 201018331. Stage 1510 includes receiving processed design information or design information in processing. Processing includes, for example, application of graphic operations to design information such as touch-sensitive operations, expanded operations, thinning operations, and opening operations. 5 Stage 1510 includes receiving or generating a design including a representation of the desired PCB. The first data structure of the information. Referring to Figure 1, the data structure is labeled as the first data structure 10. Conveniently, design information can be updated during multiple PCB manufacturing processes. The update responds to manufacturing defects found during the previous evaluation of the PCB. In this case, the method 接收5〇〇 includes receiving or generating more than a single design information structure. For example, referring to the example set forth in Figure 1, the fourth data structure 40 can be used to store updated design information. Note that design information for more than two points in time can be stored in different ways. Stage 1520 receives or generates the estimated PCB information, which is estimated by the design information being fed into the manufacturing process. Stage 1520 can include an estimated PCB stomach message responsive to design information representative of the desired PCB and at least one process parameter. ® At least one process parameter can be an etch factor, a structural displacement, a reflection factor, or a combination thereof. Different structures and different materials may have different process parameters. 20. The residual factor indicates the deformation introduced by the etch, indicating the ratio of the size of the structure to the estimated size of the structure after the estimated surname program is applied to form the desired structure. The structural displacement parameter can indicate the expected deviation of a structure from its desired position. 8 201018331 The reflection factor indicates how much light is expected to be received by the illumination structure. The reflection factor affects the level of the detection signal received by the structure. The reflection factor is material dependent and is also affected by the expected structural smoothness. Referring to the example illustrated in Figure 5, the gold pad contacts the solder mask at different locations, 5 for example within a range 126 to contact the solder mask. In other words, the boundary between the gold pad and the solder mask can be located anywhere within the range 126 without being considered a defect. As such, the gold pads 120, 122, and 124 that can contact the weld caps 12i, 123, and 125, respectively, within range 126 are considered acceptable acceptable structures. Stage 1520 includes receiving or generating a data structure including the estimated PCB information. Referring to Figure 1, the second data structure is labeled as the second data structure 20. Conveniently, the estimated PCB information can be updated in multiple PCB processes. The update can be in response to manufacturing defects found during the previous PCB evaluation. In such a case, method 1500 includes receiving or generating more than a single estimated PCB 15 information structure. For example, refer to the example set forth in Figure 1. The fifth data structure 50 can be used to store updated estimated pCB information. It has been found that PCB information can be stored in more than two time points in multiple ways. Stage 1530 includes receiving or generating actual PCb information. Actual PCB information is obtained via an optical inspection system. Such actual pCB information includes Liangye Capital 20, Darkfield Information or a combination thereof. Method 1500 can be implemented by an optical inspection system that obtains actual PCB information, but can also be implemented by another system that receives actual PCB information. Yet another embodiment of the method of the present invention 15 includes receiving a number of actual PCB information and obtaining (generating) a number of actual PCB information. For example, generating bright field information and receiving dark field information. In yet another embodiment, 201018331 generates actual PCB information for a portion of the PCB while receiving actual PCB information for another portion. In still another embodiment, actual PCB information associated with the structure made of the first material is produced, and actual PCB information of the structure made of the other material is received. 5 Actual PCB information can be obtained in a variety of ways, such as scanning the PCB in a raster pattern one by one. Each strip includes a plurality of ideally identical regions, each region including one or more regions of interest and one or more calibration targets. Referring to Fig. 2, a plurality of strips such as strips 1〇0(1) 1〇〇(k) are scanned for pcB 1〇〇, and it is expected that each strip includes an area of ideally the same area such as strip 1〇〇(1). 11〇, 12〇 and 10 130 实际 The actual PCB information shall be calibrated before comparison with the reference structure. In view of the interest zone and the unrelated zone, the calibration zone was performed prior to pCB image filtering. Thus, stage 1530 includes or is followed by calibration of actual pCB information and pre-defined coordinates, which may also calibrate reference information. 15 Calibration includes multiple phases such as: (1) the actual PCB information of the entire strip (such as the 7th strip 171) and the common calibration between the coordinate systems represented by the axis 17〇. (9) Regions (such as Figure 8 and 18〇) a zone-based calibration between the coordinate systems represented by the axis 17〇; and (10) a sub-area calibration of the pixel group of each zone. The zone calibration and additional or additional responses may be made to the calibration target, such as reference numeral 6 of FIG. Sub-area calibration can be based on edge detection and edge-based calibration. Method 1500 includes stage 1530 and additionally or additionally includes stage 154A. Stage 1540 includes performing an actual PCB statistic analysis to provide results. Additional or additional 'stage 1540' includes receiving such results. 201018331 Statistical analysis results include statistically generated pcB structures. These structures are generated by applying statistics to the fresh (4) flat scales. If stage 1540 includes performing a statistical analysis of actual PCB information to provide results, stage 1530 is performed prior to stage 1540. 5 The purpose should be to sigh 6 information (representing the expected PCB information) and to respond to the actual PCB = sfl statistical analysis results, after the stages 151 〇, 152 〇 and 154 接着 and then to the stage of generating reference information. Note that before the result is obtained (for example, before the actual PCB information is obtained), the stage 15 generates or receives the initial reference information. The initial reference information is generated in response to the results of stage 151 and is additionally or additionally generated in response to the results of stage 1520. If stage 1550 is performed prior to the optional stage 152, then stage 1550 also includes generating reference information in response to the estimated PCB information. The statistical analysis results of stage 1540 can be combined with design information to define the reference structure. For example, this combination assists in the detection of structures that appear in the design information but do not appear to be missing from the PCB being inspected. Stage 1550 includes at least one of the following stages: Stage 1551 of generating reference information includes at least one region of interest, at least one unrelated region, at least one reference structure, and at least one reference calibration target. The stage 1552 defines a reference structure in response to the expected structure of the contraction and the statistical analysis results in response to the plurality of actual structures associated with the desired structure. Stage 1552 includes generating a reference structure at a location where the location of the PCB structure is statistically generated or where the desired structure has been shrunk. Considering the desired structure can assist in detecting missing structures. The desired structure is shrunk to compensate for the misalignment or ectopicity of the structural alignment, so even if the actual structure is slightly ectopic with its desired structure, the desired structure that has contracted will overlap with the actual structure. Stage 1553 includes responding to actual drill locations within a plurality of actual structures associated with a desired structure, defining unrelated regions within the region of interest associated with a desired structure. Drilling includes hollow boreholes, partially filled boreholes, and fully filled boreholes that are difficult to detect due to fluctuations or changes in the grayscale of the pixels representing the wrong holes. In order to increase the strength of the evaluation method, the drilling must be ignored. The location of the borehole can be different from the desired location, but is usually limited to a certain cell. As shown in Figure 13, this cell can be defined as ❿ 10 unrelated areas. Cell 620 includes the possible location of bore 630, and entire cell 620 is defined as uncorrelated zone 62. The reference zone of interest "o includes uncorrelated zone 620. Method 1500 includes updating a reference in response to another reference structure. The structure 'especially especially when such reference structures are in close proximity to each other. 15 Stage 1554 defines a reference structure associated with the first actual structure made of the first material in response to the reference structure associated with the second actual structure, The second actual structural system is located in close proximity to the first-actual structure. The second actual structure is made of a second material different from the first material. For example, stage 1554 includes responding to a second reference structure associated with the metal raft. MO, defining a first reference structure BO associated with the actual structure made by lamination 20. Referring to the example illustrated in the Figure, the desired region of interest 71 includes the desired lamination around the desired metal 730. The structure of the object is 72. The expected gold 塾 73〇 has a rectangular shape, but the reference 塾 740 (after updating the reference and the mouth structure by the statistically generated pcB 塾 information) is less than the expected gold 塾 7 3〇 has a rounded corner 隅. Thus, back to 12 201018331 should be at the boundary of the reference gold pad 740, the reference laminate structure 750 is increased. * 5 10 15 20 Stage 1555 defines a plurality of pixels that must be considered to belong to one structure Responsive grayscale range. Stage 1555 includes analyzing the grayscale of the pixels of the statistically generated PCB structure to define a threshold. The threshold defines the upper and lower limits of the allowable grayscale range. The threshold can be responsive to the sensitivity of the evaluation method. Or repetitive definition. Larger ranges are more sensitive but provide less repeating results. Upper and lower limits can be defined as a function of the number of gray-scale pixels with the same gray level. Thus, the gray scale of the statistically generated PCB structure can be A pixel that is less than a predetermined threshold in the histogram will be ignored. The pixel defining the boundary of the reference structure may have a gray level corresponding to the boundary of the allowable grayscale range. Referring to the example shown in Figure 10, the histogram 1〇〇2 represents the number of pixels of the grayscale value of each statistically generated PCB structure 1146 (located within the region of interest 1150). Operation at the decision threshold (in response to the grayscale image) After the number of primes, the lower and upper limits of the allowable grayscale range 1010 are defined as 1020 and 1030. These thresholds define the boundary 1142 of the reference structure 1140, with pixels of grayscale outside the allowable grayscale range 1010 (located in the region) 1150 internal) is considered to be in the background of reference structure 1140. These pixels can be calibrated with zero gray scale. During the evaluation of stage 1560, there are pixels with actual PCB information in grayscale outside the allowable grayscale range of 1〇1〇. Ignored Stage 1555 can define an allowable grayscale range based on material, structure type, mask, etc. Stage 1556 calculates a mask. Each mask defines at least one region of interest and at least one unrelated region. Stage 1556 includes defining different masks for structures made from different materials. 13 201018331 After the execution phase 1550, updated reference information is generated and may be stored in a database, such as the fifth data structure 50 of FIG. Stage 1550 includes defining a region of interest that is slightly larger than the reference structure. Referring to the example shown in FIG. 11, the region of interest 440 includes a reference structure 420 and a background image 430. Reference structure 420 can be derived from a statistically generated PCB structure, from a desired structure, or a combination thereof. Stages 1510, 1520, 1530, 1540, and 1550 can be repeated multiple times to produce updated reference information. In view of the updated reference information, during the design information update period, stage 1550 can be followed by stage 1510. During the estimated _ 10 PCB information update, stage 1550 may be followed by stage 1520. In response to the relationship between the reference information and the actual PCB information representing the PCB, stage 1550 is followed by a stage 1560 for evaluating the PCB. This relationship can be determined by comparing actual PCB information with reference information. Stage 1560 includes evaluating certain PCBs based on the actual PCB information from one or more other PCBs. For example, the actual PCB information of the X-th PCB can be obtained during the iteration of the stage 1510-1550; the reference information of the most (x-1) response is processed during the stage 1560. As such, the reference information in response to Dijon - ® actual PCBs will be used during the next iteration of Phase 1560.
20 階段1560包括評估PCB之一部分或多個部分，評估PCB 之一區或多區以及甚至評估一個或多個PCB結構。評估可 用於製程分析、產率測定等。 階段1560包括於具有灰階度於容許的灰階範圍内之實 際結構像素與具有灰階度於容許的灰階範圍内之參考結構 14 201018331 像素間做比較。如此可藉過濾出具有灰階度於容許的灰階 範圍以外之像素實施。 * 5 10 15 20 階段1560包括產生PCB之相關報告(諸如列印初之報告) 及/或產生PCB製程相關報告；於製程中導入變化(例如改變 製程之物理屬性）等。The 20 stage 1560 includes evaluating one or more portions of the PCB, evaluating one or more regions of the PCB, and even evaluating one or more PCB structures. Evaluation can be used for process analysis, yield determination, and the like. Stage 1560 is included between a real structured pixel having a grayscale within an allowable grayscale range and a reference structure 14 201018331 having a grayscale within an allowable grayscale range. This can be done by filtering out pixels with grayscale outside the allowable grayscale range. * 5 10 15 20 Stage 1560 includes the generation of PCB related reports (such as initial reports) and/or the generation of PCB process related reports; the introduction of changes in the process (such as changing the physical properties of the process).
階段1560之後接著為階段151〇，於階段151〇期間，鑑 於評估結果更新設計資訊。階段1550之後接著為階段 1520，於階段1520期間，鑑於評估結果更新估計得之PCB 資訊。 方法1500可更新設計資訊，且另外或此外回應於預先 界定之標準而更新估算得之PCB資訊，該等標準諸如自前 次更新以來之方法1500數目，或諸如需要更新之某些製造 錯誤（或實際PCB資訊數值之預先界定的變化)之檢測。 回頭參考第1圖，方法1500可藉系統100執行。系統1〇〇 包括：⑴適合儲存代表期望的印刷電路板之資訊及實際印 刷電路板資訊之統計分析結果之記憶體單元9〇 ; (π)適合回 應於設計資訊及回應於實際印刷電路板資訊之統計分析結 果而產生參考資訊之參考資訊產生器70;及(出)適合回應於 參考資訊與代表該印刷電路板及實際印刷電路板資訊間之 關係而評估一印刷電路板之評估器8〇。 評估器80及參考資訊產生器70可為硬體模組、軟體模 組或其組合。可藉一部或多部電腦諸如第i圖之處理器6〇實 施0 參考資訊產生器70可經組配而執行下列動作或其組合 15 201018331 ❹Stage 1560 is followed by stage 151. During stage 151, the design information is updated in response to the evaluation results. Stage 1550 is followed by stage 1520 during which the estimated PCB information is updated in view of the evaluation results. The method 1500 can update the design information and additionally or in addition update the estimated PCB information in response to pre-defined criteria, such as the number of methods 1500 since the previous update, or certain manufacturing errors such as those that need to be updated (or actual Detection of pre-defined changes in PCB information values). Referring back to FIG. 1, method 1500 can be performed by system 100. System 1 includes: (1) a memory unit that is suitable for storing statistical information representing the desired printed circuit board and the actual printed circuit board information; (π) is suitable for responding to design information and responding to actual printed circuit board information The reference information generator 70 that generates the reference information from the statistical analysis results; and (out) an evaluator that evaluates a printed circuit board in response to the relationship between the reference information and the information on the printed circuit board and the actual printed circuit board. . The evaluator 80 and the reference information generator 70 can be hardware modules, software modules, or a combination thereof. The reference information generator 70 can be configured to perform the following actions or a combination thereof by one or more computers such as the processor 6 of the i-th diagram. 15 201018331 ❹
中之至少十⑴產生參考資訊其包含至少一個感興趣 Q、至少-個不相關區、至少一個參考結構及至少一個參 考权準目標；⑼回應於已收縮之期望結構及回應於與該期 望的結構相關聯之多個實際結構之統計分析結果而界定一 5參考結構之形狀；⑽回應於與某個期望的結構相關聯之多 個實際結構内部之實際鑽孔位置，界定於與某個期望的結 構之感興趣區内部之一不相關區；（iv)回應於表示一第二實 際、、構之實際資訊，界定與第一材料所製成之一第一實際 結構相關聯之參考結構，該第二實際結構係位在於該第一 10實際結構之緊密鄰近且係由與該第一材料不同之一第二材 料所製成’（v)回應於金製印刷電路板之另一結構之感興趣 之參考區，界定層合物所製成之某個結構之一感興趣之參 考區，（vi)界定應視為屬於一結構之像素之容許的灰階範 圍；界定包含決定得自多個理想相同的實際結構之灰階資 15訊之臨界值；（vii)依據材料而界定容許的灰階範圍；（viii) 計算遮罩其中各遮罩界定至少一個感興趣區及至少一個不 相關區；（ix)用於不同材料所製成之結構之不同遮罩；（X) 回應於代表該期望的印刷電路板之設計資訊、至少一項製 程參數及實際印刷電路板資訊之統計分析結果而產生參考 20 資訊；其中至少一項製程資訊可為钱刻因子、結構位移及 反射因子；以及(xi)回應於表示期望印刷電路板之設計資 訊、印刷電路板資訊及實際印刷電路板資訊之統計分析姑 果而界定參考資訊。 參考第12圖所述實例，參考資訊產生器70可更新校準 16 201018331At least ten (1) generating reference information comprising at least one interest Q, at least one irrelevant region, at least one reference structure, and at least one reference authority target; (9) responding to the contracted desired structure and responding to the desired The shape of the reference structure is defined by the statistical analysis results of the plurality of actual structures associated with the structure; (10) the actual drilling position within the plurality of actual structures associated with a desired structure, defined in relation to a certain expectation One of the unrelated regions within the region of interest of the structure; (iv) in response to a second actual, actual information, defining a reference structure associated with a first actual structure made of the first material, The second actual structure is located in close proximity to the first 10 actual structure and is made of a second material different from the first material '(v) in response to another structure of the gold printed circuit board a reference region of interest, defining a reference region of interest to one of the structures made by the laminate, (vi) defining a permissible grayscale range of pixels that should be considered to belong to a structure; Containing a critical value of the gray scale that is determined from a plurality of ideally identical actual structures; (vii) defining a permissible grayscale range based on the material; (viii) calculating a mask in which each mask defines at least one region of interest And at least one unrelated zone; (ix) different masks for structures made of different materials; (X) responsive to design information representing the desired printed circuit board, at least one process parameter, and actual printed circuit board The statistical analysis results of the information produce reference 20 information; at least one of the process information can be a currency factor, a structural displacement and a reflection factor; and (xi) in response to a design information indicating the desired printed circuit board, printed circuit board information and actual The statistical analysis of printed circuit board information defines the reference information. Referring to the example described in FIG. 12, the reference information generator 70 can update the calibration 16 201018331
目標資訊來提供已更新的校準目標諸如已更新的校準目標 530、532、533、521及510。該更新可回應於統計上產生之 PCB校準目標及回應於期望的校準目標。統計上產生的pCB 权準目標係藉應用各階·^又堵如方法15〇〇之階段1550所產 5 生。 評估器80可組配而於具有於容許灰階範圍内之灰階之 實際結構像素與具有於容許灰階範圍内之灰階之參考結構 像素間做比較。 參照第9圖所述實施例’處理器60可藉下列步驟而產生 10 —參考結構221 :⑴接收多個理想上相同的結構之實際pcB 資訊’此等多個理想上相同的結構預期係位於諸如區2(Π、 202、203、204、205、206、207及208等各區内，特別係於 此等區内部之感興趣區内部；（ii)統計上處理與各個理想上 相同結構相關之實際PCB資訊來提供統計上產生的PCB結 15 構211 (於感興趣區210内部）；（iii)於統計上產生之pcb結構 211與經收縮之設計結構213(於感興趣區212内部）間提供 「及」操作（否則應用其它合併操作）來提供參考結構221 (於感興趣區220内部）。 第16圖顯示根據本發明之一實施例用於以參考資訊為 2〇 基礎之評估之方法1600。 方法1600始於回應於下列而產生參考資訊之階段 1610 : (i)包含代表期望的印刷電路板之設計資訊之一第一 資料結構；（ii)包含經估計得之印刷電路板資訊之一第二資 料結構；及(iii)包含實際印刷電路板資訊之一第三資料結 17 201018331 構。第三資料結構可儲存實際印刷電路板資訊之統計分析 結果’階段1610包括回應於該結構而產生參考資訊。 階段1610接著為階段1620 ’回應於參考資訊與表示該 PCB之實際PCB資訊間之關係而評估一pCb。 5 階段1610也接著為階段1630，儲存於第四資料結構之 已更新的設計資訊。於此種情況下，階段161〇也負責回應 第四資料結構。 階段1610也接著為階段1640 ’儲存於第四資料結構之 已更新的估計得之印刷電路板資訊。於此種情況下，階段 參 10 1610也負責回應第五資料結構。 回頭參考第1圖，方法1600可藉系統1〇〇評估。記憶體 單元90可儲存第一至第五資料結構1〇、2〇、30、40及50。 參考資訊產生器70適合回應於下列而產生參考資訊：包含 代表期望的印刷電路板之設計資訊之一第一資料結構1〇 ; 15 包含經估計得之印刷電路板資訊之一第二資料結構20 ;及 包含實際印刷電路板資訊之一第三資料結構30。評估器80 — 可回應於參考資訊與實際印刷電路板資訊間之關係而評估 ® 印刷電路板。 參考資訊產生器70可經組配而回應於實際印刷電路板 2〇 資訊之統計分析結果來產生參考資訊。 記憶體單元90可組配來儲存已更新之設計資訊於第四 資料結構40 ;以及參考資訊產生器7〇可組配來回應於第四 資料結構40而產生參考資訊。 記憶體單元90可組配來错存已更新之估計得之印刷電 18 201018331 路板資訊於第五資料結構5〇;以及參考資訊產生器70可組 配來回應於第五資料結構5〇而產生參考資訊。 系統100可執行方法1500與1600之組合。處理器60可執 行儲存於電腦可讀取媒體之指令，容後詳述。 5 提供一種電腦程式產品。其包括一電腦可讀取媒體儲 存下列指令：回應於期望的印刷電路板之代表性設計資訊 以及回應於實際印刷電路板資訊之統計分析結果而產生參 考資訊；以及回應於代表該印刷電路板之實際印刷電路板 與該參考資訊間之關係評估一印刷電路板。 1〇 該電腦程式產品包括用於產生參考資訊之指令，該參 考資訊包含至少一個感興趣區、至少一個不相關區、至少 一個參考結構及至少一個參考校準目標。 該電腦程式產品包括回應於已收縮之期望的結構及與 期望的結構相關之多個實際結構之統計分析結果，用於界 15定一參考結構之形狀之指令。 該電腦程式產品包括回應於與某個期望的結構相關聯 之多個實際結構内部之實際鑽孔位置，用於界定與某個期 望的結構相關聯之於一感興趣内部之一不相關區之指令。 該電腦程式產品包括回應於代表第二實際結構之一實 20際資訊，該第二實際結構係位於該第一實際結構之緊鄰附 近且係由與第一材料不同之第二材料所製成，用於界定與 由第一材料所製成之第一實際結構相關聯之一參考結構之 指令。 該電腦程式產品包括回應於今日印刷電路板之另一個 19 201018331 結構之一參考感興趣區，用於界定由層合物所製成之某個 結構之一參考感興趣區之指令。 該電腦程式產品包括用於界定須視為屬於一個結構之 像素之容許灰階範圍之結構；其中該界定包含決定得自多 5個理想上相同的實際結構之灰階資訊之臨界值。 - 該電腦程式產品包括用於依據材料界定容許的灰階範 圍之指令。 該電腦程式產品包括用於比較具有灰階於容許之灰階 範圍内之實際結構像素與具有灰階於容許的灰階範圍之參 參 10 考結構像素之指令。 該電腦程式產品包括用於計算遮罩之指令其中各個遮 罩界定至少一個感興趣區及至少一個不相關區。 該電腦程式產品包括用於界定由不同材料所製成之不 同結構遮罩之46個指令。 15 該電腦程式產品包括回應於代表該期望的印刷電路板 之設計資訊、至少一個製程參數及實際印刷電路板資訊之 統計分析結果用於產生參考資訊之指令β φ 該電腦程式產品包括其中該至少一個製程參數係選自 於由钱刻因子、結構位移及反射因子所組成之組群。 20 該電腦程式產品包括回應於代表該期望的印刷電路板 之設計資訊、估計得之印刷電路板資訊及實際印刷電路板 資訊之統計分析結果而產生參考資訊之指令。 提供一種電腦程式產品。其包括儲存下列指令之—電 腦4凟取媒體：回應於下列而產生參考資訊：包括代表期 20 201018331 望的印刷電路板之設計資訊之一第一資料結構；包括經估 計得之印刷電路板資之—第二資料結構；及包括實際印 刷電路板資訊之一第三資料結構；以及回應於該參考資訊 與實際印刷電路板資訊間之關係來評估一印刷電路板。 5 豸電腦程式產品包括回應於該實際印刷電路板資訊之 統計分析結果用以產生參考資訊之指令。 該電腦程式產品包括用於储存已更新之設計資訊於第 四資料結構及用於回應於該第四資料結構而產生參考資訊 該電腦程式產品包括用於儲存已更新之估計得之印刷 電路板資訊於第五資料結構；以及用於回應於該第五資料 結構而產生參考資訊之指令。 祕所述變化、修改及其它實現可未恃離如申請專利 15The target information provides updated calibration targets such as updated calibration targets 530, 532, 533, 521, and 510. This update can be in response to a statistically generated PCB calibration target and in response to a desired calibration target. The statistically generated pCB-weighted target is produced by applying the stages of the method 1515. The evaluator 80 can be combined to compare the actual structured pixels having gray scales within the allowable gray scale range with reference structure pixels having gray scales within the allowable gray scale range. Referring to the embodiment described in Fig. 9, the processor 60 can generate 10 by reference to the structure 221: (1) receiving actual pcB information of a plurality of ideally identical structures. 'The plurality of ideally identical structures are expected to be located. Such as Zone 2 (Π, 202, 203, 204, 205, 206, 207, and 208, etc., especially within the region of interest within such zones; (ii) statistical processing associated with each ideally identical structure The actual PCB information is provided to provide a statistically generated PCB junction 211 (within the region of interest 210); (iii) a statistically generated pcb structure 211 and a contracted design structure 213 (within the region of interest 212) An AND operation is provided (otherwise other merge operations are applied) to provide a reference structure 221 (within the region of interest 220). Figure 16 shows an evaluation based on a reference information in accordance with an embodiment of the present invention. Method 1600. Method 1600 begins with a stage 1610 of generating reference information in response to: (i) including a first data structure representing design information of a desired printed circuit board; (ii) including an estimated printed circuit board One of the second data structures; and (iii) one of the actual printed circuit board information. The third data structure 17 201018331. The third data structure can store the statistical analysis results of the actual printed circuit board information. Stage 1610 includes responding to the structure. The reference information is generated. Stage 1610 then evaluates a pCb for stage 1620' in response to the relationship between the reference information and the actual PCB information representing the PCB. 5 Stage 1610 is followed by stage 1630, which is updated in the fourth data structure. In this case, stage 161〇 is also responsible for responding to the fourth data structure. Stage 1610 is followed by stage 1640's updated estimated printed circuit board information stored in the fourth data structure. In this case, stage 10 1610 is also responsible for responding to the fifth data structure. Referring back to Figure 1, method 1600 can be evaluated by system 1. Memory unit 90 can store first to fifth data structures 1〇, 2〇, 30, 40 and 50. The reference information generator 70 is adapted to generate reference information in response to the following: one of the design information including the printed circuit board representing the desired Data structure 1〇; 15 includes a second data structure 20 of the estimated printed circuit board information; and a third data structure 30 containing actual printed circuit board information. The evaluator 80 - can respond to reference information and actual printing Evaluation of the relationship between board information® printed circuit boards. The reference information generator 70 can be configured to generate reference information in response to statistical analysis results of actual printed circuit board 2 information. The memory unit 90 can be configured to store The updated design information is in the fourth data structure 40; and the reference information generator 7 can be configured to generate reference information in response to the fourth data structure 40. The memory unit 90 can be configured to misplace the updated estimated printed circuit 18 201018331 and the fifth information structure 5; and the reference information generator 70 can be configured to respond to the fifth data structure. Generate reference information. System 100 can perform a combination of methods 1500 and 1600. The processor 60 can execute instructions stored on the computer readable medium, as detailed later. 5 Provide a computer program product. The utility model comprises a computer readable medium storing the following instructions: generating representative information in response to a desired design information of the printed circuit board and generating statistical information in response to actual statistical information of the printed circuit board; and responding to the representative of the printed circuit board A printed circuit board is evaluated by the relationship between the actual printed circuit board and the reference information. The computer program product includes instructions for generating reference information, the reference information including at least one region of interest, at least one unrelated region, at least one reference structure, and at least one reference calibration target. The computer program product includes statistical analysis results in response to a contracted desired structure and a plurality of actual structures associated with the desired structure, and instructions for defining the shape of the reference structure. The computer program product includes an actual drilling location within a plurality of actual structures associated with a desired structure for defining an unrelated region associated with a desired structure within an interested interior instruction. The computer program product includes, in response to representing a second actual structure, the second actual structure is located adjacent to the first actual structure and is made of a second material different from the first material. An instruction for defining a reference structure associated with a first actual structure made of the first material. The computer program product includes a reference region of interest in response to one of the 19 201018331 structures of today's printed circuit board for defining a reference to a region of interest of one of the structures made by the laminate. The computer program product includes a structure for defining a tolerable grayscale range of pixels that are considered to belong to a structure; wherein the definition includes a threshold value that determines grayscale information from more than five ideally identical actual structures. - The computer program product includes instructions for defining the allowable grayscale range based on the material. The computer program product includes instructions for comparing actual structured pixels having a grayscale within an allowable grayscale range and reference pixels having a grayscale within an allowable grayscale range. The computer program product includes instructions for calculating a mask, wherein each of the masks defines at least one region of interest and at least one unrelated region. The computer program product includes 46 instructions for defining different structural masks made of different materials. The computer program product includes instructions for generating a reference information in response to design information indicative of the desired printed circuit board, at least one process parameter, and statistical analysis of actual printed circuit board information. The computer program product includes the at least A process parameter is selected from the group consisting of a money engraving factor, a structural displacement, and a reflection factor. The computer program product includes instructions for generating reference information in response to statistical information on the design of the desired printed circuit board, estimated printed circuit board information and actual printed circuit board information. Provide a computer program product. It includes the following instructions: Computer 4 Capture Media: Generates reference information in response to the following: includes one of the first data structures for the design information of the printed circuit board on behalf of the period 20 201018331; including the estimated printed circuit board a second data structure; and a third data structure comprising actual printed circuit board information; and evaluating a printed circuit board in response to the relationship between the reference information and actual printed circuit board information. 5 Computer program products include instructions for generating reference information in response to statistical analysis of the actual printed circuit board information. The computer program product includes information for storing the updated design information in the fourth data structure and for generating reference information in response to the fourth data structure. The computer program product includes storing updated updated printed circuit board information. And a fifth data structure; and an instruction for generating reference information in response to the fifth data structure. The changes, modifications and other implementations mentioned in the Secretary may be as if they were applying for a patent.
20 ===之本發明之精髓及範圍此處所述之變化、修 文及其匕實現為熟諳技藝人士顯然易明。 功\熟°8技藝人士了解於前述之期望操作範圍内之 為;;:界僅供舉例說明之用。多項操作功能可組合成 外_之功能可分布於額外操作。此 多個其它實施==定操作之多個實例’操作順序可於 如此 上可f Μ須了解此處所述架構僅供舉例㈣之用，實際 實見達成相同功能之多種Α “ 有確切定義，任何欲、… 構。要言之，但仍然 關聯」達成期望的功能。於此處飞“ 収相 於此處可組合達成特定功能之任 ——— 21 201018331 二組件可視為彼此「相關聯」，因而達成期望的功能而與架 構或中間組件無關。同理，如此相關聯之任二組件可視為 彼此「操作式連結」或「操作絲合」來達軸望的功能。 但其它修改、變化及替代亦屬可能。如此說明書及附 5圖應視為舉例說明而非限制性意義。20 === The essence and scope of the invention The changes, the revisions, and the implementations described herein are apparent to those skilled in the art. The skill of the skilled person is understood to be within the scope of the aforementioned operational scope;;: the boundary is for illustrative purposes only. Multiple functions can be combined into functions. The functions can be distributed to additional operations. This multiple other implementations == multiple instances of the operation 'operation sequence can be used in this way. It is not necessary to understand that the architecture described here is for example (4). Actually, it can achieve the same function. Any desire, ... structure. To speak, but still associated" to achieve the desired function. Fly here "Accommodation here can be combined to achieve a specific function - 21 201018331 Two components can be seen as "associated" with each other, thus achieving the desired function regardless of the architecture or intermediate components. In the same way, any two components thus associated can be regarded as a function of "operating connection" or "operational wire bonding" to achieve the desired position. However, other modifications, changes and substitutions are also possible. The description and the accompanying drawings are to be regarded as illustrative and not restrictive.
「包含」一詞並未排除申請專利範圍中所列舉者以外 之其它元件或步驟的存在。須了解如此使用之術語於適當 情況下可互換，因此此處所述本發明之實施例可以此處所 述之方式以外之方式於其它方向操作。 10 此外，此處使用之「一」或「一個」等詞係定義為一The word "comprising" does not exclude the presence of elements or steps other than those recited in the claims. It is to be understood that the terms so used are interchangeable as appropriate, and the embodiments of the invention described herein may be practiced in other orientations other than those described herein. 10 In addition, the words "一" or "一" used herein are defined as one.
個或多於一個。此外，於申請專利範圍中使用引言措辭諸 如「至少-個」及「-個或多個」也不可解譯為暗示由不 定冠詞「-」A「-個」所介紹之另—個中請專利範圍元 件將含有此種所介紹之申請專利範圍元件之任何特定申請 15專利項限制於只含有一個此種元件之發明，即使該申請專 利項包括引言措辭「一個或多個」或「至少一個」以及不 定冠詞諸如「-」或「一個」二者時亦如此。有關定冠詞 的使用亦同。除非另行陳述，否則諸如「第一」及「第二 等詞係用來任意分配於所述元件間。如此此等術語並非必 20然意圖指示此種元件之時間順序或其它優先順位。單純表 示於不同申請專利範圍中所引述之某些辦法並未指示此等 辦法之組合無法優異地使用。 【明式簡單說明】 第1圖顯示根據本發明之一實施例之一處理器及多種 22 201018331 資料結構； 第2圖顯示根據本發明之一實施例之一印刷電路板之 期望掃描圖案及一條帶區分成為多個區； 第3圖顯示根據本發明之一實施例之一期望區及多個 • 5 期望的校準目標； . 第4圖顯示根據本發明之一實施例之一期望區及多個 期望的感興趣區； 第5圖顯示根據本發明之一實施例之經估計的墊片及 β 經估計的焊罩及所接受的容差； 10 第6圖顯示根據本發明之一實施例之一期望的感興趣 區及多個期望的不相關區； 第7圖顯示根據本發明之一實施例之一條帶之通用校 準； 第8圖顯示根據本發明之一實施例之一區之校準； 15 第9圖顯示根據本發明之一實施例之一參考結構的產 生； ® 第10圖顯示根據本發明之一實施例之臨界值及灰階資 訊； 第11圖顯示根據本發明之一實施例之一感興趣區的產 20 生； 第12圖顯示根據本發明之一實施例之參考校準目標的 產生； 第13圖顯示根據本發明之一實施例回應於鑽孔所在位 置之一感興趣的參考區及一參考不相關區之產生； 23 201018331 第14圖顯示根據本發明之一實施例之感興趣之一參考 層疊區之產生； 第15圖顯示根據本發明之一種用於以參考資訊為基礎 之評估方法；以及 5 第16圖顯示根據本發明之一種用於以參考資訊為基礎 之評估方法。One or more than one. In addition, the use of introductory terms such as "at least one" and "- or more" in the scope of the patent application may not be interpreted as implying that the indefinite article "-" A "-" is introduced in the other. The component limits any particular application 15 patent containing such described patentable component elements to an invention containing only one such component, even if the patent application includes the phrase "one or more" or "at least one" This is also true for indefinite articles such as "-" or "one". The use of definite articles is also the same. Terms such as "first" and "second" are used to arbitrarily assign between the elements unless otherwise stated. Such terms are not necessarily intended to indicate the chronological or other preferred order of the elements. Some of the methods cited in the different patent applications do not indicate that the combination of these methods cannot be used excellently. [Brief Description] FIG. 1 shows a processor and a plurality of 22 according to an embodiment of the present invention 2010 18331 Data structure; FIG. 2 is a view showing a desired scanning pattern of a printed circuit board and a strip divided into a plurality of regions according to an embodiment of the present invention; FIG. 3 is a view showing a desired region and a plurality of regions according to an embodiment of the present invention; • 5 desired calibration target; Figure 4 shows a desired area and a plurality of desired regions of interest in accordance with an embodiment of the present invention; Figure 5 shows an estimated spacer and an aperture according to an embodiment of the present invention β estimated weld cover and accepted tolerance; 10 Figure 6 shows a desired region of interest and a plurality of desired uncorrelated regions in accordance with one embodiment of the present invention; General calibration of a strip according to one embodiment of the invention; Figure 8 shows calibration of a region according to an embodiment of the invention; 15 Figure 9 shows the generation of a reference structure in accordance with an embodiment of the invention; ® FIG. 10 shows threshold values and gray scale information according to an embodiment of the present invention; FIG. 11 shows a production area of a region of interest according to an embodiment of the present invention; FIG. 12 shows one according to the present invention The generation of the reference calibration target of the embodiment; FIG. 13 shows the generation of the reference region of interest and a reference irrelevant region in response to one of the locations of the borehole according to an embodiment of the present invention; 23 201018331 Figure 14 shows One of the interests of one embodiment of the invention refers to the generation of a layered area; FIG. 15 shows an evaluation method based on reference information according to the present invention; and FIG. 16 shows a method for Reference information-based assessment methods.
【主要元件符就說明】 10…第一資料結構 126...範圍 20…第一資料結構 170…軸 30…第三資料結構 171...條帶 40…第四資料結構 180-181...區 50…第五資料結構 201-208…區 60...處理器 210…感興趣區 70…參考資訊產生器 211...統計上產生之PCB結構 80...評估器 212…感興趣區 90...記憶體單元 213…已收縮之設計結構 100...系統、PCB、印刷電路板 220...感興趣區 100(k)…條帶 221…參考結構 110-130 …區 420...參考結構 111-113…感興趣區 430...背景像素 114’·.·第二遮罩 440...感興趣區 115’...第一遮罩 510...已更新的校準目標 120、122、124...金墊 521.·.已更新的校準目標 m、123、125...接觸焊罩 530...已更新的校準目標 24 201018331 532...已更新的校準目標 1010...容許的灰階範圍 533...已更新的校準目標 1020...上限 610··.感興趣之參考區 1030...下限 620...小區、不相關區 1140...參考結構 • 630...鑽孔 1142...邊界 . 710...期望的感興趣區 1146...統計上產生的PCB結構 720...期望的層合結構 1150...感興趣區 730...期望的金墊 1500...方法 ❹ 740...參考金墊 1510-1560...階段 750...第一參考結構、參考層合 1600...方法 結構 1002...直方圖 1610-1640...階段 參 25[Main component description] 10... First data structure 126... Range 20... First data structure 170... Axis 30... Third data structure 171... Strip 40... Fourth data structure 180-181.. Area 50...Fifth Data Structure 201-208...Zone 60...Processor 210...Following Area 70...Reference Information Generator 211...Statistically Generated PCB Structure 80...Evaluator 212...Interested Zone 90...memory unit 213...contracted design structure 100...system, PCB, printed circuit board 220...region of interest 100(k)...strip 221...reference structure 110-130 ...block 420 ...reference structure 111-113...region of interest 430...background pixel 114'..second mask 440...region of interest 115'...first mask 510...updated Calibration target 120, 122, 124... gold pad 521.. updated calibration target m, 123, 125... contact weld 530... updated calibration target 24 201018331 532... updated Calibration target 1010... Allowable grayscale range 533... Updated calibration target 1020... Upper limit 610 ·. Interested reference zone 1030... Lower bound 620... Cell, unrelated zone 1140. ..reference Structure 630...Drilling 1142...Boundary. 710...Required Region of Interest 1146...Statistically produced PCB structure 720...Recommended laminate structure 1150...region of interest 730 ...the desired gold pad 1500...method ❹ 740...reference gold pad 1510-1560...stage 750...first reference structure, reference laminate 1600...method structure 1002...straight square Figure 1610-1640... stage reference 25
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097140441A TWI465165B (en) | 2008-10-22 | 2008-10-22 | Method, system and computer program product for reference information based evaluation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097140441A TWI465165B (en) | 2008-10-22 | 2008-10-22 | Method, system and computer program product for reference information based evaluation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201018331A true TW201018331A (en) | 2010-05-01 |
| TWI465165B TWI465165B (en) | 2014-12-11 |
Family
ID=44831175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097140441A TWI465165B (en) | 2008-10-22 | 2008-10-22 | Method, system and computer program product for reference information based evaluation |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI465165B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI448700B (en) * | 2010-11-23 | 2014-08-11 | Koh Young Tech Inc | Inspection method for a board |
| US9645097B2 (en) | 2014-06-20 | 2017-05-09 | Kla-Tencor Corporation | In-line wafer edge inspection, wafer pre-alignment, and wafer cleaning |
| US9885671B2 (en) | 2014-06-09 | 2018-02-06 | Kla-Tencor Corporation | Miniaturized imaging apparatus for wafer edge |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006041352A (en) * | 2004-07-29 | 2006-02-09 | Dainippon Screen Mfg Co Ltd | Coat inspection device, inspection system, program, coat inspection method and inspection method of printed circuit board |
-
2008
- 2008-10-22 TW TW097140441A patent/TWI465165B/en active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI448700B (en) * | 2010-11-23 | 2014-08-11 | Koh Young Tech Inc | Inspection method for a board |
| US9664628B2 (en) | 2010-11-23 | 2017-05-30 | Koh Young Technology Inc. | Inspection method |
| US9885671B2 (en) | 2014-06-09 | 2018-02-06 | Kla-Tencor Corporation | Miniaturized imaging apparatus for wafer edge |
| US9645097B2 (en) | 2014-06-20 | 2017-05-09 | Kla-Tencor Corporation | In-line wafer edge inspection, wafer pre-alignment, and wafer cleaning |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI465165B (en) | 2014-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI750553B (en) | Method of defect detection on a specimen and system thereof | |
| TWI684000B (en) | Method of generating an examination recipe and system thereof | |
| Megahed et al. | A spatiotemporal method for the monitoring of image data | |
| JP2006098152A (en) | Apparatus and method for detecting defect | |
| JP5864455B2 (en) | System, method, and computer program product for CAD-based alignment | |
| CN117911735B (en) | A printed circuit board quality detection method and system | |
| JP5956814B2 (en) | Appearance inspection apparatus, appearance inspection method, and computer program | |
| JP4982213B2 (en) | Defect inspection apparatus and defect inspection method | |
| JP6254763B2 (en) | System, method, and computer program product for CAD-based alignment | |
| JP2020102204A (en) | Adversarial learning system and method for noise labels | |
| CN104520983A (en) | Detection of defects embedded in noise for inspection in semiconductor manufacturing | |
| US8542912B2 (en) | Determining the uniqueness of a model for machine vision | |
| TW201018331A (en) | Method, system and computer program product for reference information based evaluation | |
| JP2002243428A (en) | Pattern inspection method and apparatus | |
| CN115698690A (en) | Image processing method, shape inspection method, image processing system, and shape inspection system | |
| JP4629086B2 (en) | Image defect inspection method and image defect inspection apparatus | |
| JP5155938B2 (en) | Pattern contour detection method | |
| JP2015201055A (en) | Defect location prediction apparatus, defect location prediction program, and defect location prediction method | |
| JP2002093875A (en) | Method for evaluating dangerous spot information of pattern of semiconductor device | |
| JP2004515830A (en) | Quadratic dispersion plot technique for defect detection | |
| JP3123275B2 (en) | Inspection data creation method for electronic parts shortage inspection | |
| CN119472177B (en) | Overlay error measurement method and device, storage medium and computer equipment | |
| CN109817538B (en) | SRAM failure online test method | |
| JP4074624B2 (en) | Pattern inspection method | |
| KR101053779B1 (en) | Metal mask inspection method of display means |