TW201015905A - A method and apparatus for deinterleaving in a digital communication system - Google Patents

Abstract

A method and apparatus for deinterleaving in a communication system is disclosed. The method and apparatus deinterleave data units using a data deinterleaver; compressed deinterleave input symbol quality information (SQI) units using a compressed deinterleaver, wherein at least one of the input SQI units deinterleaved by the compressed deinterleaver corresponds to at least one of the plurality of data units deinterleaved by the data deinterleaver; and apply the deinterleaved SQI units to the corresponding deinterleaved data units.

Description

201015905 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to the field of digital communication systems, and more particularly to deinterleavers utilized in such systems. CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of the benefit of Priority 61/104,688, the contents of which are incorporated herein by reference in their entirety. [Prior Art] An interleaver is generally used in a transmitter of a digital communication system for interleaving information such as bits or signals. Accordingly, a de-interlacing is generally employed in one of the receivers of a digital communication system for the reverse interleaving process at the $. Together with the effector of the de-interlacer, the $interleaver helps to spread the local variations in channel conditions more evenly, resulting in improved overall system performance. For example, at the connector, the burst error occurring in the communication channel due to noise or interference is extended by the deinterleaver in time, and the α improves the forward error correction (FEC) decompressor. The noise or interference may originate from the receiver 4 or may be caused by other functional blocks of the receiver itself. For example: - Error bursting is due to the error propagation in the decision feedback equalizer (reward) and the 33纟X error system also helps to mitigate the 201015905 ice degradation in the wireless communication channel. A father's fault is also an important component of a turbo encoder, and its use is high-performance - the key factor. The interleaving can be done at the bit level or at the signal level. An example system using bit interleaving is the Quadrature Division Multiple Access (OFDMA) mode of the IEEE 802.16e standard. One example system using symbol interleaving is China's Digital Terrestrial Multimedia Broadcasting (Dtmb) standard. See gb (10)6's China DTMB standard (hereafter referred to as "China DTMB Standard"). Power squares and convolutional interleavers are two general types of interleavers. The example system of the ©-function block interleaver is used in the IEEE 802.16e standard orthogonal division multiple access (〇FDMA) mode of the wireless communication device. One example system using a convolutional interleaver is the Chinese DTMB standard. More than one interleaver can be utilized at the transmitter, each of which may require a corresponding deinterleaver at the receiver. A single deinterleaver at the receiver can also be used to reverse the operation of multiple attention interlacers at the corresponding transmitter. The interleaving required memory and the interleaver delay or latency of the interleaver are two important parameters of the interleaver. The greater the delay in the interleaver, the stronger the function of reducing the error. The term "total time interval" as used herein for an interleaver or deinterlacer indicates the delay of the interleaver or deinterleaver in the time dimension. However, the greater the interleaver delay, the more memory is required for interleaving at the transmitter and deinterleaving at the receiver. Delay or latency is not a major issue in broadcast applications. So use a very large interleaver. Accordingly, and undesirably, the deinterleaver in the receiver requires a larger memory' to increase the cost of the receiver. Effective quantities such as dynamic quantization of signals and/or functional block floating point representations 201015905 are known to reduce word length and thereby reduce memory requirements. However, these techniques do not change the amount of quantization stored by itself, and thus the achievability of reducing memory is limited. Accordingly, without significantly reducing the cost of the receiver, there is a need to exceed the above-described techniques to reduce the amount of memory used in the deinterleaver. When the care interleaving operation at the transmitter is at the symbol level, there are two choices for the deinterlacing of the corresponding/main parent error. Most communication systems transmit data in the form of one of the mapped bits. The signals received at the receiver are subject to noise and other impairments. In an earlier carrier system, the received symbols can be converted to bit soft metrics for subsequent deinterleaving. Alternatively, the received symbols can be deinterleaved for subsequent conversion to a bit softness metric. 2 Try to get the trusted bit (four) metric from the signal, and the message information (SQI) is required. The transmitter does not transmit: 2: Q1 is information about the received signal, such as: and received: "signal-to-noise-to-interference ratio_. The receiver is available, and the SQI of each signal. Understand the interlaced received message:; receive the signal related ... Q! Department must also be deinterlaced, and the recipient is used to obtain the bit and the data system using similar social structure; 2. In the method of use, SQI or numerical storage space. According to this H error and deinterlacing, a similar number of misoperations are needed. f # Α θ This article discusses the system of memory error for the interleaving and dissolving systems. The use of a large number of interleaved interleaving systems in transmission benefits = is not ideal because of the increase in cost. The deinterlacing is implemented on the softness metrics that are usually obtained by using the SQI associated with it in 201015905. The received symbols are converted into bit softness metrics by using SQIs associated with the respective received symbols. The bit softness metrics are deinterleaved. Both the symbol and the bit interleaver Can be used at a conveyor. In the absence of a message interleaver, the current implementation does not separate the SQI before deinterlacing and the de-interleaved bit softness measure itself already contains the SQI effect. A large amount of memory is required for system systems such as broadcast systems. 'The broadcast system uses interleavers with large delays. ® Therefore, a need exists for a method and apparatus for reducing the amount of memory used to deinterlace at the receiver of a digital communication system, thereby lowering costs. Without experiencing significant performance loss. [Explanation] Φ 7 201015905 [Embodiment] The term "quantity" as used herein refers to any number that can be represented by a real number, an integer, or a complex number. The amount of memory used to store a set is based on the total amount (number) to be stored and the quantified word length used to present the quantity. The word "substantially" as used in this document is also understood to include just the same. The term "quantized word length" or "word length" as used herein refers to the number of quantization bits or the number of bits used to present a single quantity or value. With such an amount of effective quantization, a smaller word length can be used thereby reducing the memory requirement. The term "received message" as used herein refers to a signal at the turn-out or input of any function block in the receiver. The term "transmitted message" as used herein indicates the signal at the output or input of any function block in the transmitter. The word "signal" used in conjunction with 201015905 information from a transmitter or to a receiver indicates a transmitted message or a received message. In a multi-carrier system such as an OFDM system, this typically refers to the output of one of the discrete Fourier transform (DFT) functional blocks in the receiver. This system is also used to indicate the output of another functional block in the frequency domain processing component of the receiver. In a single carrier system, the received symbols are used to indicate the output of the equalizer. As used herein, the term "bit softness metric" is a measure of the probability that a bit is a value of "丨" or a value of "〇". As used herein, a "bit interleaving system" is a system at the transmitter that has a care interleaving operation to be performed at the bit level. The present invention generally describes a deinterleaver for use in a communication receiver. The deinterleaver includes a method and apparatus for deinterleaving received data and symbol quality information (SQI), respectively, when the corresponding attention interleaver at the transmitter is a bit parent. # When the attention interleaver at the transmitter performs bit interleaving or symbol deinterleaving, the deinterleaver includes methods and devices for deinterleaving the received data and SQ] respectively, and further The memory size requirements of the deinterleaver are reduced by utilizing the time and/or frequency dependent characteristics in the SQI and/or by deinterleaving the Sqj-converted representation. As used herein, the term "conversion" is used to indicate that the quantity is presented using a different form or using a quantity function, and the result of the quantity is presented instead of the quantity itself. Multiple quantities can be used to obtain a single number of conversion representations. This is different from techniques other than effective and known quantization techniques such as dynamic quantization and can be implemented. The 'de-interlaced sQI is then applied to 201015905 a conventional de-interlaced signal or bit softness metric, which is typically a system-forward error correction (FEC) decoding, before being applied to subsequent blocks. Device. Those skilled in the art will understand that the use or application of the SQI to produce a bit softness measure improves the quality of the bit softness. Various embodiments of the present invention provide a method and apparatus for reducing the memory required for deinterlacing when the primary care is a convolution or a functional block interleaver. This deinterleaver has low cost due to reduced memory size requirements. . The deinterleaver may also correspond to more than one interleave at the transmitter, 'and/or other operations at the transmitter to change the bit or sequence of signals. As used herein, the term "interfering at the transmitter" may also include a plurality of such interleavers corresponding to one of the deinterlacing effects being performed, and all such operations that change the bit order or the order of the signals. Other interlacers of interest may be present at the transmitter or may be used to change the bit or sequence of signals. It is reduced by utilizing the time and/or frequency dependent characteristics in the SQI, and/or by using a SQI. #换述述“Solution of the memory of the father's fault. In a multi-carrier system such as the 0 ugly system, different signals or bits are affected by the signal to interference and noise ratio (s). In various embodiments of the invention, the individual symbol systems may be associated with different SI funds or SQs, with the SINR being the SQI. In an embodiment of the invention, a symbol on a given subcarrier of a given ugly frame is associated with the input_: between the sequence of cells - a single I of the input A SQI can be such as Other functional blocks that may already exist in the receiver ς D τ Q

provide. Different sayings are: one ςη苗苗-衫咖士 M QI earlier corresponds to the early one OFDM frame 10 201015905 two one subcarrier. An example of the S!NR SQI is used to take the softness measure of the bit. In other systems such as single-carrier systems, two different bits or symbols can be affected by different channel conditions and appropriate use in this system can also improve performance. Long transmissions at the transmitter can improve performance, but the receiver also needs a long deinterleaver. By reducing the memory associated with the de-interlacing, the cost of the receiver is reduced. The received symbols in a single carrier system such as DTMB's single carrier mode may also have different SQIs associated with them due to changing channel or interference and noise conditions. Traditionally, the SQI is assumed to be ambiguous in all of the symbols, and is therefore ignored in the generation of bit softness metrics and thus deinterleaved. Conversely, the SQI can be used to generate bit softness metrics in a multi-carrier system to improve performance. The term "memory J or "memory module" as used herein refers to a specific application integrated circuit (ASK) "single- or multiple registers, or such as (static Ram) _, (dynamic RAM) DRAM Or the read-only memory (R〇M) module is randomly stored as a part of the memory (read) or all of it. The term "memory component" as used herein refers to a partial or complete sequence of a RAM or a set of registers that are used to store, for example, a received signal or bit softness metric, or - A single number or value of one of the SQI units. The term "memory size" shall be used to indicate the number of bits used to store a quantity or set of numbers. The bits can extend across multiple characters, or multiple RAMs or registers. The term "circuitry" as used herein refers to a combination of functional winter hardware or software or a combination of the two. The term "multiple of integer eight" as used herein refers to any integer b that can be divided by a person without a remainder (including the integer A itself). In this paper, the use of ""Strict multiples of numbers" refers to any multiple of the integer A except the integer a itself. The term "approximately the integer a" as used herein refers to any integer b that can be divided by A and has no remainder (including the integer A itself). The term "rigorous divisor of integer 」" as used herein refers to any fraction of the integer A other than the integer 本身 itself. The token ceiUA) represents the smallest integer number greater than or equal to a given real number A. The symbol fl〇〇r(A) represents the largest integer less than or equal to a given real number eight. The notation m 〇 d (j, k) represents the modulus of the integer j for k. As used herein, the term "branch" of a convolutional interleaver or deinterleaver indicates a collection of cells stored in a first-in, first-out (FIF) format. . The knives can be used for signal, bit softness metrics or message quality information. One of the concept representations of a convolutional deinterleaver includes several branches and each branch stores a different number of cells. In practice, however, a cell corresponding to a branch can be stored in a constant value FIF buffer constructed by the scratchpad, or can be stored in a RAM and stored in the FIF0 register. Addressed in the same order. In a practical implementation, all of the branches in the conceptual representation of the convolutional deinterleaver can be stored in a single RAM, and can be addressed in the order of multiple branches of different sizes FIF0 or access. The word "correspondence" as used herein refers to a one-to-one correspondence, a -to-multiple correspondence, a many-to-one correspondence, or a many-to-many correspondence. 12 201015905 The term "communication channel" as used herein refers to a physical communication channel that may carry all damage to the arm, such as noise and distortion. It may also include radio frequency (RF) electrons, quantization, the generation of estimation errors, or the effects of one or more functional blocks of the transmitter and/or the receiver itself. 'The memory size of the number of bits required to deinterlace is usually equal to the number of bits used by the deinterlaced signal representation multiplied by the number of memory elements used. For a one-bit interleaver, one The quantized bit system is only used to represent a data bit. However, if a soft decoding FEC is used in the receiver, the deinterleaver needs more than one quantization bit to present a data bit corresponding to a data bit 7L at the transmitter. Used to represent a quantity of quantized bits, the so-called word length. Therefore, the term "bit disjoint:" used in this document does not indicate that each data unit has a demultiplexer of quantization bits, and more precisely indicates that each data unit represents one of the imitation units. Deinterleaver. The term "historical size of the interleaver" is used to indicate the delay in the interleaver and the amount of storage required in the interleaver. This is one of the parameters of the interleaver. We use the notation Q1 to note this historical size. As used herein, the term "interleaver delay" is used to: a signal (or a bit) between a signal from the input of the interleaver to ^: a large delay. - For a given interleaver type, the larger the error of the error, the larger the interleaver history size is required, and vice versa - the error is compared with the same interleaver delay - the function block is crossed, two: : To be more than ^ historical size. The term "delay" as used herein refers to "interlacer delay" as defined in the above paragraphs. 1 is a communication system 10 showing one of the inventions of the present invention. The communication system 1 包含 includes - 3 transmitter 12' - receiver 14, and a communication channel 16. The M_° system, 'first instance' includes, but is not limited to, systems that are read from disk drives such as hard disks and compact discs, CDs, DVDs, and Blu-ray players. As used herein, the transmission of $ indicates a write medium such as a hard disk drive, optical or magnetic medium for storing information as bits or signals.

The beta receiver 14 does not include a deinterleaver detail, which in turn includes a data deinterleaver 2〇4 and a compressed deinterleaver Up the data deinterleaving 204 and the compressed deinterleaver 212. Each of the illustrated handles is coupled to the bit softness metric generating function block 2〇8. More specifically, the data decryption decoder 204 receives the data 2〇2 and generates the de-interlaced data 2〇6 to the function block 208. The difference is that function block 2〇8 receives one or more data units and produces one or more de-interleaved data units. The compressed deinterleaver 212 is shown receiving a plurality of input SQI units 214 and generating one or more deinterleaved SQI units 226 to a functional block 208. At least one input SQI unit 214 is associated with the data deinterleaver 204. At least one unit of the received data 202. The data deinterleaver 204 operates to generate one or more (deinterleaved) data units 2〇6, and at least one deinterleaved data unit at the output of the function block 204 is deinterleaved corresponding to the output of the function block 212. At least one of the SQI units 226. Function block 208 produces a bit softness metric 2 1 〇. The s-data deciphering decoder 204 is a de-interleaved data unit 202 to generate a de-interleaved data unit 206. The compression deinterleaver 21 2 implements the rounds 14 201015905

The SQI unit 214 is disgusting ** A You detract the interleaving to produce the deinterleaved SQI unit 226. The s-Hai-type solution is the de-interlaced SQI unit 226 generated by the de-interlace 3 204. The 6-bit 7C soft-steep metric generator is used by the data deinterlacing 3 204. The de-interleaved data unit and the de-interlaced SQI single 226 _ are used to generate a bit softness metric. In some embodiments, each of the deinterleaved SQI units 226 corresponds to at least one of the deinterleaved data units 2〇6. ❹

In some other embodiments, at least one of the input SQi units 214 does not correspond to any of the units in the data sheet A 2Q2. In these embodiments, the compressed deinterleaver 212 processes at least one input SQI unit 226 that does not correspond to a data unit 206 but produces a deinterlaced sqi unit 226 such that each single το corresponds to at least one of the data sheets & 2G6 - a unit. This may occur when the central/master data unit is combined or interleaved with a data unit or quantity that is not of interest to the data deinterleaver 204, and is subsequently referred to as "other data."

gS is early." In some embodiments, the compressed deinterleaver 2 1 2 also advantageously processes the SQI unit 226 corresponding to other data units, but only the deinterlaced SQI unit 226 corresponding to the deinterleaved data unit 206. This example is when a pilot subcarrier is mixed with a data subcarrier in an FDM system, wherein the SQI unit includes a corresponding Sq, and another instance is in the multicarrier mode of Dtmb, except for the data carrier. The system information subcarriers carrying information about the various options of the system are transmitted. In still another embodiment of the present invention, the SQI h 226 includes a corresponding system data carrier. The systems do not correspond to any of the data units. 15 201015905 In some embodiments, at least one of the data elements 206 does not correspond to any of the SQI units 226. For example, this may be done to estimate some SQI singles or to reduce the number of units to be processed by the compressed deinterleaver 212. In various embodiments of the invention, one of the SQI units 226 corresponds to (d) one of the units i 206. For example, this may be the case where the data is unambiguous as '204 is a symbol level deinterleaver and the data unit is a symbol. In other embodiments, one of the SQI units 226 corresponds to more than one data unit 206. For example, this may be the case where the data demultiplexer 204 is a one-level deinterleaver and the data unit 2〇6 is a bit softness metric. The compressed deinterleaver 212 performs compression deinterlacing on the SQI unit 214 including compression and expansion of the sqi unit. That is, the input sqi unit 2 1 4 is compressed and stored in the memory (shown in ® 7) with a reduced memory size requirement compared to the prior art, and then the expanded input SQI unit is expanded. A deinterleaved SQI unit 226 is generated. At any given time, the compression deinterleaver 212 stores a small amount or number of units that are smaller than the number of data units stored in the data processor. In generating the deinterleaved SQI unit 226, the number of cells in the deinterleaved SQI unit 226 is the same as the prior art and is greater than the number of numbers stored in the memory. Differently speaking, the compression deinterleaver 2 1 2 performs expansion on the compressed and contracted SQI units stored in the memory. This process typically causes some information to be lost. So if the signal deinterleaver is in the same way, the output system is not exactly the same as the first 4 technology, but it can be designed so that the difference is not so significant that the IT system significantly affects performance. The softness metric 210 is based on the fact that the received bit is 〇 or ι, and is usually received by the data unit in the data deinterleaver 204 used by the FEC decompressor using soft decoding techniques. At the time of the signal, the single data unit at the output of the data deinterleaver 204 is a bit. For example, if the data is dissected, the bamboo shoots are the de-interlacer, and the signal is selected from a 64-degree quadrature amplitude modulation (QAM) distribution map: The symbol represents 6 data bits, and thus the bit softness metric generator (10) produces a 6 bit softness metric as the bit readability metric 21〇 for each deinterlaced data symbol 206. The bit softness metric 21〇 can be fed into an FEC decoder. The bit softness + , oil 2 罝 2 1 0 system can log the similarity ratio (LLR) of the transmitted bits. In the present invention-embodiment, the data 2〇2 contains data elements which are generated by the output of the frequency domain equalizer (FEQ, W and Figure) of the multi-carrier system t. In another embodiment, the JT Becco 2〇2 system contains data elements that are generated by the output of one of the single carrier systems. In yet another embodiment, when interlacing the piano. When 27 is a one-dimensional interleaver, the data 202 is a preliminary bit softness metric such as a soft limiter. A soft limiter known to those skilled in the art is used to convert a data message into a set of soft values. Each of them is represented by a symbol. The soft-valued system indicates the reliability of the bit 〇 or 1. The data deinterleaver 204 typically performs the de-interlacing by using one of the memory sizes of the equal-sized bits, i τ kiss & It is used to store data using a W4 bit length. 2〇2 _ m Early in the sequence of the package 17 201015905 One of the data units Q1 is suitable for αο _ ... in the solution of the Wang Qi fork error data 206 ^ sequence Interleaved data units. Except for the different order (or the interleaving unit 226) is basically a lean unit that is opposite to the data unit 202. In the case of the same fine 4 degrees, when the capital is tilted; When the barrenness is the output of the received message, the word length in the system is generally - when the data 202 is - FEQ, the signal output is less than when the data 202 is not an FEQ output. Discrete Fourier Transform (DFT) rounding, such as is often done by the Fourier Transform (FFT) method. Because the feq is reduced due to changes in the channel frequency response, the dynamic range of the data 2G2 is in it -

The output is small. ''Q In one embodiment of the present invention, the data is provided in the multi-carrier receiver with = one input and one ... corresponding to each sub-carrier. In another embodiment, the data 202 is a signal at the output of a time domain equalizer in the single-carrier receiver.

The 214 series is provided for each signal position of the frame. In the -I example, when the attention interleaver at the transmitter is a one-bit interleaved real material 2 0 2 is a soft limiter on the 屮'' output, and the input _214 is for 2〇2 Each set is provided in a manner corresponding to a single received data message. Those skilled in the art will appreciate that SQI is usually applied to:: extracting signals, especially in the data metrics where the data symbols are _FEQ. In the embodiment, the SINR is commonly used for SQI when the operation is only performed by the rabbit method. Ma Yicheng 18 201015905 In accordance with an embodiment of the invention, the input SQI 214 is first compressed by the compressed deinterleaver 212 and is then stored in memory (shown in Figure 7). In other embodiments, the compression and storage functions are simultaneously implemented in accordance with various embodiments of the present invention. The input SQI 214 is the signal to interference and noise ratio (Sinr) associated with the corresponding data message. In other embodiments, the SQI unit of the input SQI 214 is the square of the absolute value of the channel gain associated with the corresponding data symbol. Referring to various embodiments of the present invention, the word length W5 used to represent and store the compressed sqi unit is much less than the word length used to represent the input SQI unit. In another embodiment, wherein the SQI unit is the square of the absolute value of the channel gain associated with the data message, the conversion expression of the A SQI unit (ie, the channel gain associated with the corresponding data symbol) The absolute value) is used inside the compression deinterleaver 212, whereby the milk system produced is less than the word length required to represent the input SQI unit without a large amount of loss accuracy. Note that this is different from dynamic quantization or functional block floating point representations that do not have the aforementioned conversions. In accordance with some embodiments of the present invention, the number of memory elements Q2 stored for generating a plurality of de-interlacing SQI units 226 is much less than the number of memory elements Q1 used to store a plurality of SQI units. (d) by using the compression deinterlacing of the compressed deinterleaver 212 of the input SQI 214, the compression or frequency range at least in the time range or the joint compression over the time frequency range is implemented on the input. . That is, the compression results of the I-saturated SQI unit are stored, and the results are then expanded to generate the de-interlaced SQI unit 226. The generated deinterlacing according to an embodiment of the present invention may be performed by group inputting a house contraction executed in SQI214 and using a disk value such as an average value or a median number.虺, - early - group function) is implemented in groups, which basically creates a magic to represent the group low user nw to compress the SQI and thereby reduce the memory size requirement of the SQI. Those skilled in the art will understand that J. has several averaging types that can be utilized by the deinterleaver 212, such as a shifting thyroid impulse response (IIR) type average. =TM ’’ both' and infinity 1 averaging includes the group of cells—the block average means that any cell outside this group has no effect. In another embodiment, the median system of the group elements into which the kiss is entered is used to represent the SQI unit group. In yet another embodiment, the aggregate of the group elements of the input SQI is used to represent the SQI early group system does not necessarily need to significantly derate the performance in various embodiments 'compressed deinterlacing Improve performance. This occurs because the cumulative or average operation of the input arbitrarily improves the SQI quality. For example, a mi4 single sputum can have an estimation error. In the embodiment where the summation or averaging is done by the compressed deinterleaver, the error ratio of the 1 sigma SQI unit is used to generate the compressed 8 (the individual input SQI unit of the unit is still small. The error is also lower in the deinterleaved SQI unit 226 as a result of the cumulative or averaging operation. Thus, the 'SQI system is applied to the decoded parent data unit 206' to thereby improve the system performance. .

In various embodiments, the compression system can be implemented in a time domain that spans multiple 〇FDM 20 201015905 messages or frames. In this case, the 压缩2 π example can be implemented in a frequency across multiple subcarriers and in various other embodiments of the Shishi, compression can be implemented in both the time domain or the frequency domain A ^ The amount stored on both is expanded to deinterlace SQI 226. It is not because of 呤. 土必〆1不门°法法•·Compressed deinterlacer 2 1 2 is configured as a shrunken input S q I 2 14 single open ^ _ 2 14 early, store compression results And subsequently, the stored results (remaining one by the wall τ, 、, 靥, SQI 兀) are generated to generate the deinterlaced s unit 226. In at least one of the data sheets 70 202 is a -signal, in various embodiments, the compression deinterlacing is performed on a plurality of inputs, ie, units, to produce a deinterleaved SQI unit 226, which Each unit in the deinterleaved list 226 corresponds to at least one of the deinterleaved data units 2〇6. FIG. 2 shows an exemplary frequency response diagram of one of the receivers 14. In Figure 2, the increase in intensity (in dB) is shown along the y-axis, and the frequency (in Hz) is shown along the X-axis. More specifically, Figure 2 shows a channel frequency response with a reference 0 dB echo at approximately 〇·9249 # sec delay. Note that the |J: 0 dB source channel is one of two paths with equal power. This channel has a notch of 1/0.9259 " sec in its frequency response, which is 1.08 MHz. For example, in the 7.5 6 MHz digital terrestrial multimedia broadcasting (DTMB) signal band, there are 7 notches as shown in 2〇. Figures 3 through 5 show the gain and frequency on the same axis as in Figure 2. In accordance with an embodiment of the invention, the compression system can be implemented on a plurality of frames; and in accordance with other embodiments of the present invention, the compression system can be implemented in as many as 21 201015905 subcarriers within a frame. Alternatively, a combination of the two compression methods can be used. Figure 3 shows a channel frequency response with a 〇 dB echo at approximately 〇丨32//sec delay. This channel has a notch with a spacing of 1/〇.132/Z S in its frequency response, which is 7.56 MHz. In the dvmb billion band of 7.56 MHz, there is exactly one notch as shown at 2 〇 3. In the multi-carrier mode of DTMB, there are 3780 subcarriers evenly spaced into the '"band. It is clear from Figures 2 to 3 that the frequency response of adjacent subcarriers is more similar than the system shown in Figure 2. As shown in Figure 3, the signal of Figure 3 has a better frequency coherence. Therefore, using multiple methods and embodiments of the present invention, a plurality of input SQI units can be used in the system of Figure 3. It is presented using fewer memory elements than in the system of Figure 2.

Figure 4 is a channel frequency response shown at approximately 259 9259 to delay the echo and has a (iv) z-Doppler frequency. (Note that in this frequency *, the Doppler frequency frequency exhibits a frequency offset between the two paths' causing the frequency response to change over time). The channel shown in _ 4 has a delay of 8 frames between the two frames. The ^5 series is shown in a channel frequency response with a 〇 dB echo and a 100 Hz Doppler frequency at approximately WWS delay. Again, there is a delay of 8 frames between the two frames of the channel response shown. 4 to 5 ^ 楚: No, the frequency response of the continuous frame is more similar to the case of Figure 4. In other words, the signal of item 4 is excellent in time correlation. Therefore, Figure 4 is more capable of presenting more frames together with a group of numbers than Figure 5. 22 201015905 Figures 2 to 5 illustrate the concept of time and frequency correlation. More specifically, Figures 2 and 3 illustrate less or better frequency coherence, respectively; while Figures 4 and $ illustrate better or less temporal coherence, respectively. In some embodiments, the memory component number Q2 and the word length W5 used to derive the quantity from the time and/or frequency compression of the input SQI are both less than Q1 and W2, respectively, whereby the compression deinterleaver 212 The memory system required for prior art structures is reduced. Figure 6 shows a communication system 2() in accordance with an embodiment of the present invention. The reference communication system 20 includes a transmitter Μ, a receiver 24, and a communication channel 26. The receiver 24 receives the information transmitted by the transmitter 22 via the communication channel 26. The transmitter 22 is shown as including an interleaver 227 for interleaving a plurality of bits or symbols prior to transmission to the receiver 24 through the communication channel 26. It should be appreciated that although an interleaver is included in the transmitter 22, multiple interleavers may be included in the transmitter 22. The interleaver 227 itself may also include multiple interleavers or multiple interleaving operations. In accordance with an embodiment of the invention, the receiver 14 includes a circuit 230 that is deinterlacer 268 when the interleaver 227 is a one-bit interleaver. The circuit 230 further includes a first bit soft steepness metric generator 242 and a second bit soft metric generator (functional block) 250. The deinterleaver 268 includes a data deinterleaver 246 and a compressed deinterleaver 264. According to an embodiment of the invention, the softness metric generator 242 is a soft limiter 23 201015905. This paragraph / 3⁄4: 昙 Yuan 丄 量 产生 generator 242 shows the information received 240 and the data early 244, f in - τν» 44 can be the beginning of the data deinterleaver 246 soft measure. The data deinterlacing @ 246 is configured to generate a plurality of deinterleaved data units 248 from the data unit 244. In one embodiment of the invention, the m-single & 244 is a preliminary bit softness metric. The data decryption parent 246 is shown to generate a meta-data deinterleaver output 248 which is the input of the bit 25 soft metric to produce g 25G. The bit softness metric generator 250 also receives input from the compressed deinterleaver (function block) 264. The compressed deinterleaver 264 is configured to compress deinterleave one or more input SQI units to produce one or more deinterleaver sqi. More specifically, the compressed deinterleaver (function block) 264 receives the input SQI 262 and produces a deinterleaved SQI 266 that is the input to the bit softness generator 250. The bit soft metric generator 250 generates a bit softness metric 2 5 2 by using or applying a de-interlacing Sqj 266 to the de-interlacing data unit 248. In accordance with an embodiment of the invention, the symbols 240 are received signals that are output from an FEQ in a multi-carrier system. According to another embodiment of the present invention, the signals received by the signals can be output from a first equalizer in a single carrier system. Function block 242 produces a data unit that is a preliminary bit softness metric. These data units are fed as input to the data deinterleaver (function block) 246. According to one embodiment of the invention, the soft metric generator (function block) 242 is a soft limiter. The soft metric generator (function block) 242 does not need to only use SQI as the input type. 24 201015905 In accordance with an embodiment of the present invention, the bit softness metric (or data information) present on data unit 244 is the bit similarity ratio (LLR) of the bit appearing on message 24. The data units 244 are then deinterleaved by the data deinterleaver 246 to cause a one-dimensional softness metric of the same configuration as the data bits input to the interleaver a of the transmitter 22. The compressed deinterleaver deinterleaves the input SQI 262 associated with the symbol 240. The input sqi 262 can also contain input SQI units that are not associated with the signal 24〇. The input SQI units are also processed by a compression deinterleaver. It will be understood by those skilled in the art that the plurality of data units of the data unit 244 can be associated with or correspond to a single unit of the input SQI 262. The number of multiple data units can be equal to the number of bits of the signal for each distribution. This is noted as "s". The deinterlacing unit 248 of the data deinterleaver 246 and the deinterleaving unit of the compressed deinterleaver 264 are used by the bit metric metric generator 25G to generate the bit softness 252. At any given time, the compressed deinterleaver 264 stores less than the number of data stored in the data deinterleaver 246. In some embodiments, the number of units or units stored by any of the devices 264 is less than the number of data units stored and divided by S. When the conveyor 22 is in contact with calcium. „”7 曰: When the 疋 固 该 ’’’’’’’’’’’ The opposite is the second electric L23. The system interleaves the soft bits. The soft bit differs from the bit in that it is interlaced, and the transmitter or the sequence of 1 is, however, the deinterlacing at the receiver 25 201015905 does not target the sequence of 〇 or i 'but the solution The interleaving is performed on the softness measure or softness level, which is used to present the number of similarities of the received bits to 〇 or 1. In an exemplary embodiment, the 'bit softness measure' is represented by the number of _31 to +31; wherein the negative number is likely to be 〇 and the _31 is the strongest, and the positive number may be 丨^ + 3l is the most ^. In this expression, a quantity of 0 is also one of the same as one. A word length of 6 quantized bits can be used to present a bit softness metric in this case. The number of memories used for deinterlacing in the prior art transmitter is typically Q1*W3 (the number of memories stored in the QH system and W3 is the word length). The number of memories used for deinterlacing in the embodiment of Figure 6 is typically the + W6 system used to present the word length of each number at the data unit 244 ' @ W7 is the word used to present the SQI unit of the compressed deinterlace _ long. Those skilled in the art will appreciate that variations in SINR associated with different bits are as large as 25 dB to 3 〇 dB in some wireless channel systems. In the prior art, the 'SQI system is not separated from the data that is being deinterleaved, and thus the data change (or dynamic range) in the prior art system is much larger than the change in the data unit 244. This is because the data unit 244 is derived from the auto-signal after the feq and SQI have been separated. The number of stored or decompressed SQI units stored in the data deinterleaver 246 is less than or equal to q1/s. For large distribution maps, the S system is the majority. The value of Q2 can be reduced to much lower than Q1/S by using frequency and time compression, which will be described below. This reduction is based on the 26 201015905 掳 channel characteristics. By selecting Q1*W6+Q2*W7<Q1*W3, the memory system used to resolve the error is reduced. In accordance with various embodiments of the present invention, when the transmitter performs bit-level disjunction, an open relationship is used at the receiver to determine if the deinterleaver is implemented as described above or using prior art methods. Φ Φ The switching operation performed by this switch is based on the channel characteristic decision function block. In one embodiment, the inter-day coherent interval is a time period in which the absolute value of the channel gain does not encounter a large change. In another embodiment, the temporal coherence interval is the longest time in which the absolute value of the channel gain is normalized by an average of the squares of the absolute values of the plurality of channel gains during a maximum time period, and the rate of change is less than a predetermined threshold. cycle. In one embodiment, the frequency coherent interval is the maximum number of connected subcarriers in which the absolute value of the channel gain is not encountered - a large number of changes. In another example, the frequency coherent interval is the maximum value of the channel gain in which the absolute value of the plurality of channel gains is normalized during the period, and the rate of change is less than a predetermined threshold. Connected 舆#, battle, skin number. In accordance with an embodiment of the invention, the functional block measures the time-frequency acquisition-time coherence interval estimate and the frequency ^, and the scores are used in some embodiments to estimate the values. Make adjustments. When this multiplier exceeds the -threshold value, the product is used after the 'solution' is used, otherwise a prior art structure is used, where ^268 is not separately demodulated. ', _ shell material and SQI and in at least one data unit is - only meta-softness, the compression de-interlacing is carried out in the round-in-the-month application 1 into the SQI unit to generate the solution 27 201015905 father error SQI a unit, wherein at least one of the de-interlaced sqi units corresponds to at least one of the de-interleaved data units. Figure 7 is a further detailed diagram showing a compressed deinterleaver 212 or 264 in accordance with an embodiment of the present invention. The compressed deinterleaver 2丨2 or the illustrated system includes a time/frequency coherence interval estimation function block 3丨〇 and a time/frequency coherence interval adjustment function block 312, an SQI compression function block 3 24, and an SQI expansion. Function block 34〇. Optionally, function block 31 can be part of receiver 24 and used for other purposes, and thus can be clamped outside of function block 2 1 2 or 264; since this is indicated by a dashed line. Alternatively, function block 3 1 may be located within receiver 24 or may be part of functional block 324 or 340. In an embodiment of the invention, function block 301 may also be positioned external to receiver 24 or as part of function block 324 or 340 and is therefore also shown in a dashed line. In some embodiments, the 'function block 3 1 0 or 3 1 2 may not be present. The SQI compression function block 324 includes an SQI processor 326, a first address generator 330, and a first memory 328. The SQI processor 326 is responsive to the input SQI unit 322 and is operative to generate the address G and the control signal 327, and the data signal 33 1 and the control signal 332. The first memory 328 receives the signal 327 and the signal 33 1 and generates a signal 338 to the SQI processor 326' where the content is in an identified location identified by the address in the signal 327 in the memory 328. The first address generator 330 is coupled to receive the signal 332 and to generate an address signal 334 (sometimes referred to herein as an "address generation signal 334") to the SQI processor 3 2 6 ° 28 201015905. The SQI expansion function block 34A includes a second memory 342, an output SQI generator 344, and a second address generator 346. The second memory 342 is shown coupled to the output sqj generator 344, and the second address generator is shown coupled to the output generator 344 as well. The output SQI generator generates a control signal 325 to a second address generator that generates a response to the memory address 354. The output sqi device provides an address and control signal 348 to the second memory 342. The second memory 342 responds to the output SQI generator with the signal 350 at the requested address contained in the signal 348. The deinterleaved SQI 36 generated by the output SQI generator 344 is generated as an output of the sqi expansion function block 340. Signal 339 is coupled to the output SQI generator 344 by the sqi processor 326. In some embodiments, the SQI compression function block 324 is responsive to the input SQI unit 322 and is configured to perform the step of converting the representation, accumulating, storing, or reading a location in the first memory 328. At least one or more. The operations may be performed by an SQI processor 326 that is coupled to the first memory port 328 and to the first address generator 330. The location in the first memory 328 is identified by the first address generator 33 = the live address. In some embodiments, the SQI expansion function block 340 is configured to perform at least one of an inverse conversion, a repetition, a scaling, and a read operation from a position in a second memory 342 for generating (4) interleaving. SQI. The operations may be performed by the output SQI generator 3 that is stolen to the second memory 342 and to the second address generator 346. The location in the second memory 342 is identified by one of the addresses generated by the second address generator (10). In some embodiments, the first memory 328 and the second memory 342 are the same physical memory. In other embodiments, the first address generator 330 and the second address generator 346 can be different physical memories. In still other embodiments of the present invention, the first address generator 33 The second address generator 346 is a different memory but periodically alternates. In some embodiments, the first memory 328 provides the generated address apostrophe 344 to the shai SQI processor 326 to respond to the control signal 332. In these embodiments, the second address generator 346 provides its generated bit address 354 in response to a control signal 352 from the output SQI generator 344. The time/frequency coherence interval adjustment function block 312 provides an adjusted time and frequency coherence interval value to the SQI compression function block 324 and to the SQI expansion function block 34A on the signal 316. The values may be provided to the SQI processor 326 and the first address generator 33A, and to the output SQI generator 344 and the second address generator 346. The time/frequency coherence interval estimator 31 provides a signal 314 to the time/frequency coherence interval adjustment function block 3 12 . The adjusted time coherent interval is represented by L 1 and the adjusted frequency coherence interval is represented by l2. The preliminary time coherence interval estimate L" and/or the preliminary frequency coherence interval estimate L_2 is used by the time/frequency coherence interval adjustment function block 312 to produce an adjusted time coherence interval L丨 and/or an adjusted frequency coherence interval L2. . The initial coherence interval estimate passed from the estimator 3 to the adjustment function block 314 on the signal 314 and the fading coherence interval estimate transmitted on the signal 3 16 may be followed. Time and/or frequency change 30 201015905 The time/frequency coherence interval adjustment function block 3 1 2 is optional and may not be in an alternative embodiment of the invention. It does not exist in function block 312. In the embodiment, the time and frequency coherence values used are directly provided by the estimator 31G. In another embodiment where functional block 3 1G does not exist, the time and frequency coherence values used are fixed to some design parameters. The input SQI 322 in accordance with the present invention-embodiment includes - or more input SQI units (or values). The input SQI 322 can be an input SQI 214 or an input SQI 262. The SQI processor is intended to process the input parameter SQI 322. According to a preferred embodiment of the present invention, the s 〇I processor 326 accepts the nth input SQI 322 when the communication system is a multi-carrier system, and the data decryption parent is a symbol level convolution deinterleaver. Providing a control signal 332 containing the value of n and generating a request for a memory address to the first address generator 330. In this embodiment of the invention, the first and second memories 328 and 342 are identical. The first address generator 33 then generates an address based on the values of η, L1 and L2 and provides it to the SQi processor 326. The address generated by the first address generator 330 may also depend on other factors, such as the need for a respective frequency deinterleaving operation for a frequency interleaving operation at the transmitter. Based on the values of at least n, L1, and L2, the SQI processor 326 performs one of the following two operations: a "write only/store only" operation in which the input SQI unit 322 (the value) is stored in the memory. The location identified by the address generated by the first address generator 330; and the "cumulative" operation where the memory content is read from the memory 3 28 by the young address generator 3 The address generated by 30 is identified and added to the input SQI unit 322 (the value), and the result is written or stored back to the same memory location via 31 201015905. The SQI processor 326 makes a decision between the two operations based on one of its cumulative-decision decisions. When the accumulation-decision is true or YES or 1, the cumulative operation is performed, otherwise the "write only" or "storage only" operation is performed. In both cases, a write or store operation occurs, but one read The operation only occurs when the accumulation-decision is TRUE. The address and control signal 327 contains the generated address signal 334 and control items to indicate whether the operation to be performed by the first memory 328 is a read or a write operation. The cumulative result or the value entered into the SQI unit 322 is accompanied by the address and write signal carried by the signal 327❿ and the data signal 33 is sent to the memory 3 28° when the number 327 contains a read control signal. The memory 328 provides the content at the memory location specified by signal 327 and provides this content to the SQI processor 326 via signal 338. The decision between "storing only" or accumulating two operations is also dependent on the need for respective frequency deinterleaving operations corresponding to the frequency interleaving operation at the transmitters included in interleaver 227. In the foregoing operation, one or more of the SQJ units 322 are stored or accumulated at a location or address of the memory 328. In this manner, the SQI can be compressed while being stored in the first memory 328. Differently speaking, the input SQI unit 322 can be compressed while being stored in the first memory 328. The first memory system stores the compressed SQZ unit. In this embodiment, the number of write or store operations is equal to the number of processed cells in the input 322. According to the above preferred embodiment of the present invention, the memory location is read from the memory 342 by 32 201015905. The scaling factor is scaled and the output SQ generator 344 is the mth unit in the deinterleaved SQI 360. As described above, the first memory 328 and the second memory 342 are physically the same memory in some embodiments. The e-memory location is identified by the address generated by the second address generator 346 in response to the control signal 352, which includes the value of m provided by the output SQI generator 344 and an address generation request. . The scaling factor used in the scaling operation is calculated by the output SQI generator 344 based on at least the values of m, u, and L2. The scaling factor for the number of values of m is 1/(L1*L2) when both SQI compression function block 324 performs both time and frequency compression. For other values of m, the output sqi generator 344 can take the scaling factor from the SQI processor 326. In various embodiments, the SQI processor 326 provides the scaling factor to the output SQI generator 344 via the signal 339 in response to the address provided by the output SQI function block 344 through the signal 339. The Sq processor obtains the scaling factor as the inverse of i and the cumulative number after the last stored (and: no accumulation) calculation at the address provided by the output kiss function block 344. By locating the memory therein and counting the last number of accumulated storages at the same address of the first memory 328 after the operation, the SQI processor 326 is continuously tracked after the last time only after storage. The cumulative number. This is particularly accomplished when the data solution = the wrong (246 or 204) is the convolution type deinterlacing ^ and the cumulative number is only continuously chasing (four) those memory locations' which correspond to branches equal to or equal to L1. 33 201015905 When the scaling factor is 1, the scaling operation can be ignored. A given memory location is read multiple times (not necessarily in order) to produce a unit of deinterlaced SQ 360. In this manner, the contents of memory 342 are expanded upon reading and scaling to produce deinterlaced SQ 360. In this embodiment, the number of read operations from the second s memory 346 is equal to the generated deinterleaved sq. The SQI compression function block 324 and the aforementioned operation of the sqi expansion function block 340 form a "compression deinterlacing". In other embodiments of the present invention, the SQI processor 326 may contain local memory owned by it for use in performing accumulation on the input SQI unit 322 prior to storage or accumulation to the first record hidden entity 328. Operation. This can be used to reduce the number of write operations to the first memory 328. In other embodiments of the present invention, the output SQj generator 344 can store the result of the scaling operation of one of the contents read from the second memory 342 in the local memory owned by the second memory 342, and repeat the local storage. The value is owed to produce a deinterleaved SQI unit 36〇. This system can be used to reduce the number of read operations from the second memory 342. In various other embodiments, the SQI processor 326 can also convert the representation of the input SQI unit 322 in addition to or in place of the above operations. In one embodiment, at least one single SQI unit of input SQI unit 322 can be converted to a single number of conversions. In another embodiment, multiple inputs are suppressed. The unit system can be converted into multiple conversion quantities, where the number of input sQi units to be converted is not necessarily equal to the number of converted numbers. As a result of the conversion operation, the word length used to present the input SQI unit can be lowered. Accordingly, in addition to or in place of the above operations, the inverse conversion can also be performed by the input sqi. In the embodiment Φ, also, >, although the input SQI is the absolute value of the channel benefit associated with the data message, the internal shoveling function 324 is used in the function block 324 as the data 1 ^ ^ The 5fl is the absolute value of the associated channel gain. in-

In this embodiment, the conversion is performed by the SQI processor 326 upon receiving the input SQI unit 322. In this embodiment, the input SQI generator performs an inverse conversion when generating a unit of the intersection SQI. In another embodiment, the '5' memory 328 stores the square root of the sum of the squares of the input SQI 322 in the -time and/or frequency coherent gates. In this embodiment, the output sqi generator does not perform an inverse conversion. 3 2 4 is configured, stored, and read. In various embodiments, the SQI compression function block is to perform at least one of a sampling operation at a location of the first memory 328. The operations may be performed by an SQI processor 326 coupled to the first memory 328 and to the first address generator 330. The location in the first suffix 328 is identified by an address generated by the first address generator 33A. In these embodiments, the SQI expansion function block 340 is configured to perform the following operations from a plurality of locations of the second memory 342: repeat, interpolate, and read. These operations can be performed by the output SQi generator 344. The plurality of locations in the second memory 342 are identified by a plurality of addresses generated by the second address generator 346. In an embodiment of the invention, the SQI processor 326 accepts units of the input SQI 322 and discards all units except one input SQI corresponding to a group of L1*L2 input SQI units (not necessarily in sequential order), and 35 201015905 stores the one input SQI in an address of the first memory 328 generated by the first address generator 330. The first address generator 33 generates the address in response to the control signal 332 from the SQI processor 326. Since several units of the input SQI can be discarded, it is not necessary to perform address generation for the input SQI units. Differently speaking, the SQI processor 326 basically samples the input sqj 322 by one sampling factor of L1*L2, and stores the sth in the first memory 3 28 . In these embodiments, the first memory 328 and the second memory 342 are physically the same memory. In one embodiment, the selected unit of the L1*L2 input SQI unit group is in the middle or middle of the group in both time and frequency bands. In various embodiments, the sampling system is not necessarily uniformly sampled. The output SQI generator 344 reads a plurality of memory locations identified by the plurality of addresses generated by the second address generator 346, and performs an interpolation operation on the read content to generate deinterleaving. Output a unit of SQI 360. The output SQI generator 344 can also perform a repeat operation. Those skilled in the art will understand that one of the repetitive computational interpolations is apparent. In accordance with an embodiment of the present invention, the input SQI 322 is inter-material compressed in a multi-carrier system by presenting a unit group of the unit sequence of the A SQI 322 on a given subcarrier but across the Li signal. The box or U character is completed 'where the L1 frame or L1 0FDM system is extended by a single quantity at the time ^ the value of the single quantity is the result of a function of one of the frames. For example, the sum of the numbers: the number can only be stored to significantly reduce the memory size requirement, rather than storing one u SQI unit for each L1 frame. In an embodiment 36 201015905 幡 ": an average of the values of the function U SQI unit. In another real case", when L1 is a product integer, the SQI unit is in the u frame: the value is used To represent the SQI unit group and discard the remaining units. For even numbers, either of the two s QI units between the L! consecutive frames are used to represent the SQI unit group and the remaining units are discarded. : The frequency compression of Q 22 (ie, compression over the frequency range) can be achieved by presenting the -input cell group in the - frame φ ❿ borrowing - the number across the L2 contiguous subcarriers This is done, wherein the value of the quantity is a function of one of the functions of the SQI unit on the subcarriers. In another embodiment, the function is an average or a median. In applications or environments where there is no significant change after successive subcarriers, it is particularly effective. In Figures 2 to 5, if the notch in the frequency response remains static or the same, the compression system can be implemented over a long period of time. Performance benefits are not affected; but if the notch is not static, then - Long-term cycle pressure: It is likely that the information is lost and is therefore less desirable. In one embodiment, the compression deinterleaver (212 or 264) performs joint compression over the frequency range. So that a quantity corresponding to the SQI unit group across time and frequency is stored. The different saying is that the compression deinterleaver step includes combining the time and frequency ranges. Several input SQI units, corresponding to The value of the number of remaining storages across the L1 contiguous frame and the subcarrier m sqi unit group is the result of the _function of the SQ! unit in the group. The open operation is then performed in the stored As a result, the SQI unit 37 201015905 is subdivided to produce an interleaved SQI. In one embodiment of the invention, the particular function is only one sum. In some embodiments, when the data deinterleaver (2〇4 or 246) For a functional block deinterleaver, the number of SQI units of the group is equal to the score of u and L2. In other embodiments, when the data deinterleaver (2〇4 or 246) is a convolutional deinterleaver When the size of the group is At or equal to the scores of L1 and L2. The time/frequency coherence interval estimator 3 1 〇 and/or the time/frequency coherence interval adjustment function block 312 is provided in the output 316 to the number 13 of u and L2 to the first The address generation function block 33 and the second address generation function block 346. According to an embodiment of the present invention, when the communication system 10 or 20 is a system, the initial frequency coherence 15L_2 is determined by any Given the number of consecutive subcarriers in the OFDM message or frame, the input SQI unit does not change significantly. According to an embodiment of the invention, 1-2 is broken down into subcarrier numbers, such that The ratio of the maximum SQI unit to the minimum SQI unit in the ^dfdm signal or frame is less than the design parameter ❹ = boundary value. According to an embodiment of the invention, the value of Lj 纟 L_2 is not necessarily constant but the reverse may be dynamic. The L_1 and L·2 systems in several OFDM symbols can be changed to the order of the first 胄LJ or the L" and L-2 of the several subcarriers can become the order of the previous L-2. In other embodiments of the invention, the value of L 1 Ji τ - -2 can be selected to be fixed for a long time on approximately several thousand OFDM frames and for all subcarriers. The time/frequency coherence interval estimate is already present in another portion of the receiver for implementation 38 201015905 various other functions, and thus is shown in phantom in Figure 7. According to various embodiments of the present invention, a value and a frame and/or subcarrier index or a signal index system when a value of L_1 and/or L-2 is changed is also provided to the SQI shrink function block 324 and the The SQI expands function block 340. These embodiments may be used, for example, when periodic pulsed noise is present in a single carrier system or when frequency selective interference is present in a multi-carrier system. According to an embodiment of the invention, when the data deinterleaver is a convolutional deinterleaver, the preliminary time and frequency coherent isolation can be further adjusted by the time/frequency framing interval adjustment function block 312, so that the L-2 system It can be rounded to the nearest divisor of the total number of data subcarriers κ to obtain L2. In other embodiments, the L_2 system can be rounded to the nearest multiple or the number of branches b to obtain L2. In various embodiments, Lj is rounded to the nearest divisor of the delay in the longest branch of the conceptual representation of the convolutional deinterleaver to obtain L1. In various embodiments of the invention, when the system is a single carrier system

The time range is not present and therefore the L2 value is equal to i. Different sayings; no frequency compression is required. According to the invention - the embodiment, when the data deinterleaver (class or (10)) is a - convolution deinterleaver and the number of data subcarriers κ is equal to the number of branches B, the concept of the U redundant element in the convolution deinterleaver The contents of the _ branch are represented by the early-memory component in the 罝a ancestor block in the compression deinterlacing function block. In various embodiments, when the data is dismissed, the Λ Λ 贝 贝 贝 胖 胖 胖 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 A set of lyric elements spans the convolutional deinterleaver " L2 coherent or continuous 39 201015905 content is a a-remember element of the longest branch number of the #L2 continuous sub- (four) The number is presented. The 〇〇 ϋ & % f instance 'L1 number may vary depending on the branch index of the corresponding concept of the convolutional de-interlacing. In an embodiment, when the data deinterleaver (2G4 or 246) is a signal level deconvolution deinterleaver, the L1 system may be equal to the time interval in the branch of the corresponding concept representation of the convolution deinterleaver, This does not store any time history. In an embodiment, when the number of data subcarriers is a multiple of B, the L1 system may be equal to the following: L \ = ceil {b - 1)( Μ )(~) Ganshan ^ %(1) , , middle The Μ represents the depth of the deinterlacer, and is the record of the coherent branch, the difference in the number of body components or the touch size, W represents the total number of branches, and b is the branch index from i to Β. In one embodiment, when ku is multiplied, L1 is expected to be a multiple or a divisor of M that is closest to L-丨. In the multi-carrier system in which the interleaver 227 is in the A column and the signal level functional side is wrong, the data deinterleaver (2〇4 or 246) is the historical size of B, and can be obtained by The A*B single-domain of the 202-square-by-row writes the A-column multiplied by the B-row—in the array and by self. The array is read column by column to generate the de-interlaced data symbol & If, according to the present invention, an embodiment of the present invention, K is the number of subcarriers and p is the number of 0FDM symbols on one of the A% data spans, causing κ*ρ=Α*Β to cause a multiple of the system to imply For the multiple of Β, the compression deinterlacing is as follows. The function block 324 may write or accumulate the nth unit in the unit sequence of one of the SQIs 322 into the memory address of the 201015905 body address or position according to the following Eq. (2), which may be according to the following equation The address generated by the first address generator 330: K floor (---) - (mod( floor (-ΖΓ^—), Ρ) + floor (mod( ^-1>/:)) +ι 11 Eq.(2) The private number n is changed from 1 to A*B. The above memory address or position is changed from i to A*B/(L1*L2). The above equation can be applied to it. The signal at the device is first written into the subcarrier first and then in an embodiment of the 〇fdm signal. The different statement in this embodiment is that the transmitter is in the next OFDM signal of the participating system. The carrier preamble uses all of the subcarriers in the FDm signal first. In an alternative embodiment in accordance with the present invention, the system may occur in a different order and those skilled in the art will recognize that the above equations can be made accordingly. Modifications According to an embodiment of the invention, the SQI processor 326 may also generate a cumulative decision to decide whether to accumulate. The nth unit (or value) of the input SQI can be written into the memory 328 at the position given by Eq. (2) when the decision is False or NO or 〇. The accumulation-decision system basis Obtained by the value of η. The input or storage of the input SQI overwrites any previous memory contents. When the accumulation-decision f is £ or T or , the nth input SQI unit (or numerical value) The content of the memory location given by 驷·(7) is added, and the result is written back to the same memory location. According to an embodiment of the present invention, the functional block deinterleaver can use y, ping p0ng The two separate memory banks or blocks of the form allow the input and output systems to be processed simultaneously. In this configuration, the memory-like or 342-system contains two memory banks, one for writing (4) 328 or 342 and the other is used to read from memory 328 or 342. Further in 201015905, in this configuration, two memory banks can be alternately periodically, and the first address generator 330 is paired. The SQI processor 326 indicates that the memory bank is selected as the - part of the signal 334 Therefore, the address and control signals 334 may include a memory bank or a function block selection indication in addition to the memory location of the incoming unit only "write/store only" or accumulate input SQI. Alternative implementation in accordance with the present invention For example, multiple identical computing systems can be implemented in different forms to obtain the same content of the memory 328 or 342. In this embodiment, the content of the memory 328 or 342 obtained above can be scaled and unconditionally discarded. , rounded to use the word length W5 to render. Only the first address generator 346 can provide the following address from the read content to generate the mth unit of the error SQI 360 as follows. First, the input index n of the mth unit corresponding to the output is taken according to the following equation. n, n = A* floor + rnod( m A) + l Eq> (3) Then 'previously generated by the first address Eq. (2) used by the device 33 is executed to replace n with the % obtained from Eq. (2). The aforementioned arithmetic system can be implemented by the first address generation state. The value of Μ is extracted by the output SQI generator. The generated address 354 is provided back to the output LV generator. According to an alternative embodiment of the invention, the total amount of memory allocated for the compression deinterlacing is fixed, and the values of L1 and L2 are selected to match the values of σ L_ 1 and L-2 for matching. Memory. According to an embodiment of the invention, when the attention interleaver and the frequency domain parent error generator are used at the transmitter, the first address generator and the second address generation 42 201015905 implement the interpretation of the frequency domain interleaver The mapping required. Figure 8 is a flow chart showing the steps of the receiver 14 or 24 in accordance with a method of the present invention, wherein the interleaver and the 4-element interleaver are at the transmitter. Those skilled in the art will appreciate that received signals on the 'f-subcarriers, such as multi-carrier communication systems utilizing ^FDM, are typically first passed through an FEQ function block. (d) The present invention-embodiment is used in step 4G2'. The FEQ output is used to measure the metric. These bit softness metrics are generated without the need to recognize or ignore the SQI, and all data symbols at the FEQ output can be considered to have the same SQI. The bit softness metric generated by the bit softness metric generator 242 (in FIG. 6) in step 402 is used, "Step 4". Step 4〇4 is carried out simultaneously with step 4〇2. Input at least one of the SQi262 corresponds to at least one data symbol at the FEQ input. In step 4-6, the data unit 240 is deinterleaved by the data deinterleaver 246 to produce deinterlaced data 248. Following step 404, in step 408, the input SQI unit 262 performs deinterleaving using a compression deinterleaving process to produce deinterleaved $ to unit 266. One of the s units in the de-interlaced SQI 266 is output to each of the input SQI 262, where t s is the number of bits of the signal for each profile. According to an alternative embodiment of the present invention, when a frequency domain interleaver is additionally included in the interleaver 227, the compression deinterleaving process also interprets the presence of the frequency errorer. DX Parent Step 402 Following step 406, the data elements are deinterleaved to produce a unit of deinterleaved data 248. Step 406 can be performed simultaneously with step 4〇8 at the same time as 43 201015905. After steps 406 and 408, in step 410, the output deinterleaved SQI 266 of the compression deinterleaving process can be applied to the deinterleaved data unit 248 generated in step 406 to generate a bit by the bit softness metric generator 25. Soft metrics. The bit softness measure can be similar to the output of a common bit deinterleaver, however the memory requirements of various embodiments of the present invention are significantly and advantageously less than the common bit deinterleaver. The above steps are repeated until all data messages are exhausted or a termination signal is received. Those skilled in the art will recognize that the bit softness metrics are fed into a subsequent FEC decoder. In the data interleaver, the average number S of the bit softness metrics fed to the FEC decoder for each FEQ output or input symbol is a one-bit interleaver or symbol interleaver. Figure 9 is a flow chart showing the execution of the depreciation of the input SQI unit by the compression deinterleaver of Figures 6 and 6 in accordance with a method of the present invention. #Previous description 'When at least one of the data units is a signal and the number of subcarriers K is a multiple of the number of branches B of the convolution deinterleaver, the compression deinterleaving process uses a compressed deinterleaver 212 to cause the generation of the solution and SQI unit 226. In this embodiment, the first memory 328 of the compression deinterlacer is identical to the second memory 342 and is hereinafter referred to as "compressed deinterleaver memory". In this embodiment, during the I-retraction, error step, the time and frequency compression of the input SQI is performed by the compression deinterleaver 212 'without the need to convert the individual units of the SQI before the time and frequency compression. Expression. Processed by the Compressed Deinterleaver 44 The input SQI unit of 201015905 is at least - _ 204 processed data sheet without φ ^ system corresponding to at least one of the (four) deinterlacer barren saponins. In one embodiment, the input to the small & ±λ Das. 丨 _ _ _ an input SQI unit corresponds to a data early 70. In another implementation 0 〇 ^ coffee also ~ τ at least one input SQI early system Corresponding to more than one data unit. In yet another embodiment, at least one input SQI unit does not correspond to any data unit. However, in this embodiment, the decoded parent error SQI unit corresponds to the deinterleaved data unit. In other embodiments, at least one of the data units does not have a phase-.,\SQI unit in the input SQI unit. In the embodiment of the present invention, the data sheet of the input data 202 is firstly sub-carriers. The second is the OFDM symbol, that is, before the (5) OFDM message or frame is processed, all received symbols on a given OFDM symbol or sub-carrier of the -fl frame are first input to the data deinterleaver 204. The steps 502 L_1 and l_2 are obtained by the time/frequency coherence interval estimator 310 providing the signal 314 and are set to be ambiguous (ie, not changing with time/frequency). Alternative embodiments in accordance with the present invention And as above, L The _1 and L-2 systems are not always ambiguous but can vary with time/frequency. In step 504, L_1 can be rounded to the convolutional deinterleaver, for example, by the time/frequency coherence interval «circle function block 312 The nearest multiplier or divisor of the depth Μ is adjusted to obtain the value of L lib LI, which can be further adjusted as explained below. Similarly, L_2 can be, for example, rounded to the number of branches in the convolution deinterleaver. The closest multiple or strict divisor of B is adjusted to obtain L2. The value of L2 can be adjusted as explained below. ~ 45 201015905 The subject of the art will recognize that the various equations presented below can be directed to the memory. A given organization chooses to obtain it by using cautious algebra and compression periods based on the idea of compression over time and/or frequency: the appropriate scaling required during the accumulation process and the expansion period to compensate for the SQI during the accumulation process Changes. Those skilled in the art will further recognize that memory systems can be organized in a number of different ways to create different sets of equations. The program is an exemplary method of performing compression deinterlacing. According to an embodiment of the invention, if L_2 is a multiple of B, no further adjustment is needed, and the number of memory elements required for the compression deinterleaver is The decision is: Q2 = Q1/(L1 *L2/2), where Q1 is given by Μ*Β*(Β-1)/2. The following notation is used to note a series of items T(i) with The integer I changes from 〇 to another integer R: 乙二. Note that T(i) implies that T is a function of I. According to an embodiment of the invention, if L2 is a strict divisor of B, then compression The number of memory components used in the deinterleaver is instead determined as: 〇Q2-Conv_mem(Ll , L2) =_*Σ:Γ(ηι) =M/L1 *(B- l+(B/L2-l *B/2) =M*B/(L 1 *L2)*((B+L2)/2-1) Eq. (4) In various embodiments, the available memory for implementing the deinterleaver The volume Q2_avail is based on other factors that are independent of L1 and L2. In these cases, the above values of L1 and L2 are adjusted (increased by 46 201015905 or reduced), causing Q2 (recalculated based on the adjusted values of L1 and L2) as close as possible to the available memory but no longer It is different from Q2_avai: the values of L1 and L2 are adjusted so that Q2<==Q2-avail. In various other embodiments of the invention, the values of 1 and 2 are not obtained and are adjusted to obtain L丨 and L2. L 丨 and L 2 are instead selected as design parameters. In this embodiment, there is no step 5 〇 2 . Steps 508, 510, and 512 start with an input processing loop or a compression loop 520. Steps 514 and 516 start with an output generating loop or an unrolling loop 522. According to an embodiment of the invention, after the memory is initialized to the memory by the SQI processor 326 using the address and control signal 327 in step 506, the compression loop 520 and the unrolling loop 522 can be started simultaneously. In accordance with an alternative steep embodiment of the present invention, the output generation loop 522 can be initiated after the Q1 input SQI unit is processed in the input processing loop $, and thereafter the input processing loop 520 and the output generating loop 522 can be simultaneously performed. The steps occurring substantially simultaneously or in parallel; or the steps of inputting the processing loop 52 and outputting the loop 522 may be performed in an alternating or substantially alternating form. This alternation can occur once per SQI unit or after multiple kiss units. In accordance with still other embodiments of the present invention, the steps of input processing loops and output generating loops 522 may be advanced in a time multiplex manner. At step 508, the elements of the SQI are accepted as inputs to the sq processor 326. Next, in the step, the desired address is generated by the first address generator 330 to the memory 328 and corresponds to the first unit of the input sqi. Similarly, the "accumulation" decision for the "unit" of the input SQI is determined by the SQI processor 326. 47 201015905 Next, at step 512', the input SQI unit system can be accumulated or written to be processed by the SQI. The memory address generated by the device 326. If the cumulative roll is TRUE (true s) or YES (1)', the input SQI unit is accumulated to the generated address; otherwise, the input SQI unit is written. The address may overwrite the previous content. The cumulative operation includes reading the content of the memory location identified by the generated address, adding the value of the input SQI unit to the content, and storing the added result back to the same memory. In various embodiments, step 506 is not implemented. Conversely, in step 5 10, the accumulation-decision is modified to achieve the same end effect. Those skilled in the art will be able to see: storing/writing an SQI unit. One of the addresses of the memory is equivalent to initializing the value at the memory address to 〇 and then accumulating the value by the SQI unit. According to an embodiment of the invention, when K=B, the corresponding input SQI The address signal 334 of the nth unit is obtained as: floor(mod(n-l5K)/B)*M*B/(Ll*L2)*((B+L2)/2-l)+M/ Ll*(floor(mod(nl, B)/L2))*(B-(floor(mod(nl,B)/L2)-l)*L2/2-l)+mod(floor((floor(( Nl)/K)/ L1 ), M/L 1 *(B-(fl〇〇r(mod(n-1 ,B)/L2))*L2-1 ))+1 Eq.(5) © and The accumulation-decision is obtained as follows: If floor((nl)/K) is an integer multiple of L1 and η-l is an integer multiple of L2, accumulate_decision=0; no Bay 4, accumulate_decision=l Eq. (6) According to an embodiment of the invention, if the obtained memory exceeds the calculated or retrievable memory, the obtained memory address is limited to the calculated or retrievable memory. 48 201015905 The cumulative computing system is established with a pressure blush. The compressed form stores the number of (4) turns as η increases. The control then returns to step 508, and the over-lighting can be repeated until all inputs are made or a stop signal is given by the receiver. According to an embodiment of the present invention, whenever the branch b=i and the rounded ones are directly transmitted to the output to generate the solution, the wax is waxed; Then, steps 510, 512, 514, and 516 can be omitted, and steps 514 and 516 include the output generation loop or the expansion loop (2), and the system displays how the pressure can be obtained. The output of the parent fault is solved. In step 514, the desired memory address is determined by the . The address generator 346 generates the first claw unit for generating the disjointed kiss. This is the case as follows. First _ First 'corresponding to the mth single of the deinterlaced SQI: -Transfer: SQI's single index & can be obtained as: nm=m + mod(m - ~(B~ 1)(M Then, the desired memory address can be obtained as described in Eq. = The content 35 of the address in the memory can be supplied to the output SQI generator 344 by a second memory 342. In step Μ, a scaling factor may also be generated by the output SQI generator 344, which corresponds to the mth unit of the deinterleaved SQI and is associated with the desired memory address. In various embodiments, the scaling factor is It is obtained by the following steps: adding i to the last time: only storage (that is, no accumulation) starts from the desired address, the number of calculations is counted, and the result of the reverse join is obtained. Each memory location continues to be tracked. In various embodiments, the: factor is set to Μ* for most of the suffix position, except for the corresponding branch index such that the time delay is less than or equal to ^ Therefore, the factor of 2010201090 is only for the memory location of the corresponding branch index. Continuous tracking. The time delay b of a branch index can be given as (^)*μ*β/κ. Next, in step 516', the content of the memory location identified by the memory address generated above can be The input A SQI generator 344 reads and is then scaled by the associated scaling factor to produce a unit of deinterlaced sq.

In various embodiments, the same memory address does not necessarily have to be broken one after the other. Therefore, the same memory content is read multiple times to {generate the unit of the SQI. The different sayings are: the memory content is expanded at time and / or frequency to generate a plurality of deinterlaced sqi units 0 ^ 514 and 516 can be justified steps 5 〇 8, 51 〇 and 512 repeat and then _ repeat 'Until all inputs or given compression deinterleaver 2 1 2/264 - termination signal. At any given time, the number of units stored in the decomposed deinterleaver is less than the number of data units stored in the beta deinterleaver. According to an embodiment of the present invention, the approximation of the stomach L2 = B aLl$M, the compression deinterleaver

The required memory pass II #士 L is established by using the value of L2 = B in Eq·(4) to obtain the following: τ Λ (5 — 1)---- 11 (11)(12) 2

Eq·(8) =° especially: for the number of compressed SQI units stored in the resource, early-eye and compression deinterleaver stored in the 'decompilation at any given time' data deinterleaver by Eq.(8) set. As shown in ε_, due to ~ ". FT, body reduction factor L2/2, and due to time compression factor 50 201015905 prime L1. This is valid as long as K is a multiple of B. The values of L1 and L2 are made whenever compression is used. Therefore, at any given time, the number of compressed Sqj units stored in the compressed deinterleaver is less than the number of data units stored in the data deinterleaver. When L2 is less than B and is a divisor of B, a memory reduction that is much greater than the above factors can be achieved. For example, in the DTMB standard, the parameters of the convolutional interleaver are B = 52 and M = 720. The number of memory locations required for the convolution deinterleaver is Ql = M * B * (B - l) / 2 = 954720. With L1=8 and L2=n, Eq•(4)® is given by Q2=1 1340, which is reduced by a factor of approximately 84. This is achieved by using complex logic in the accumulation, scaling, and address generation described above. In the case of an additional frequency domain deinterleaver in the case of DTMB multi-carrier mode, the above equations need to be modified and the equations and logic are even more complex. To avoid this, other embodiments such as those described below can be used. In various embodiments of the present invention, when the communication system is in a multi-carrier system and the data deinterleaver is a convolutional deinterleaver, the compression deinterlacer is stored equal to (T/L1)*ceil((J + The number or number of results of K)/L2), and the compression performed by a functional block deinterleaver is implemented. Therefore, the total time interval of the frames in the τ system deinterleaver is given by illusion. Therefore, the J system is a non-negative integer to note the number of subcarriers included in the SQj unit and the number of subcarriers included in the plurality of input Sqi units. The compressed deinterleaver also handles the SQ of the J subcarriers, which do not correspond to the data unit, as saying that at least one of the plurality of input sqi units does not correspond to any of the plurality of data units. However, the deinterleaved SQI units correspond to the deinterleaved data units and are exactly equal in number. In the embodiment, the sub-money forms all subcarriers together with the κ data subcarrier system, and thus (J+K) is the total number of subcarriers of the system. The SQI compression operation is performed as a function block deinterleaver and is therefore simplified. In the embodiment, although the memory contains more than the position required to expand the function block, the SQI expansion function block reads only the content at the memory location corresponding to the deinterleaved data unit in which the content read after scaling is read. In various embodiments, the additional memory locations can be removed by considering the characteristics of the frequency domain interleaver, thereby reducing memory without significantly affecting complexity. In one embodiment, the time delay corresponds to a branch, and the subcarrier index system of the unit of the complex de-interlaced data unit (4) corresponding to the desired unit in the plurality of deinterleaved SQI units is served. Given this subcarrier index and the value of the time delay and the value of B and τ, familiar with the technical person can easily obtain the address offset of the address of the SQI shift = function block by some algebra. Those who are familiar with this technology are also the same as the number p of Eq. This offset is combined with the write bit equivalent to the write address < SQI compression function block in the 2-block interleaver, and the memory address required for the SQ1 expansion loop is obtained. In various types: 2 cases, the address generated by the first and second address generators is a J-frequency deinterleaving operation. In various embodiments, the =domain interleaver, the sub-two frequency deinterleaver lookup table or map used in the address generation logic is obtained, resulting in a frequency domain interleaving operation. In the exemplary embodiment, when the first and second address generations 52, 201015905, 330 and 346 in FIG. 7 also perform the frequency domain deinterleaving operation corresponding to the interleaver and (2), the compressed deinterleaver Memorize == The province has been implemented to factor 18. Differently speaking, in various embodiments of the present invention, the kiss-interlacing is performed using a compression deinterleaver: the required memory size is reduced to about 6%, or reduced, and the display is shown in accordance with the present invention. - In the method, the compression method of the figure, the interleaver performs the compression and deinterlacing - the flow chart of the steps. For the flow chart of the graph-discrete deinterlacer, it can be used in the data decryption of the thief 204/246 as a symbol level convolution deinterlacing _ system, the number of subcarriers 卷 is the convolution deinterleaver : The system is a multiple of the number, and the number of times is 倍*Β. . In addition to step 602, the preliminary frequency coherence parameter L_2 can be obtained/frequency coherence interval estimator 31. In step 6〇2, the preliminary parameter can also be obtained from the time/frequency coherence interval estimate. Hey. = Invention - Alternate embodiment 'The preliminary time coherent number is again obtained by the system and then overwritten by the time/frequency coherence interval ==, 2 in step 6〇4. If not obtained or obtained followed by = overwrite' then the preliminary time coherence parameter in step can be adjusted by time/frequency coherence interval...

Release 1) Help to get L1. Therefore, the adjusted time coherent estimate = the system varies with the branch index b. The sub-section # D a ~, its "quote" sub-b branch branch size is given by, 1). In step two,. 53 201015905 The value of L_2 can be adjusted to obtain L2e. According to an embodiment of the invention, the adjustment can be only the nearest multiple or the divisor of the rounding operation (r〇unding 〇perati〇n) to B. In accordance with an alternative embodiment of the present invention, the adjustment may be a subordinate value operation (fl〇〇ring 〇perati〇n) to the closest divisor of B. In any of these embodiments, the number of memory elements required for the compression deinterleaver is taken as K/L2. The benefits of the present invention for L2 can be advantageously configured using a variety of methods. According to yet another embodiment of the invention, two values of L2 can be used. The first value of L2 can be equal to the second value of L-2ij, B2, which can be set to B-fl〇〇r(B/L2)*L2 when less than ❹B; or L2, can be When l 2 is greater than B, it is set to B*fl〇〇r(L2/B)-L2. When L_2 is less than B, the frequency compression system can be implemented on L2 consecutive subcarriers up to the subcarrier index H_(B/L2)*L2. The remaining L2' subcarrier systems can be compressed to a value earlier in the subsequent steps. In this embodiment, the amount of memory required for the compression deinterleaver can be obtained as ceil(B/L2)*K/B. In accordance with an implementation of the present invention, the value of J L2 can be selected by also taking into account the depth μ of the channel, and the Doppler spread or time coherent estimate. When the depth of the channel and/or the Doppler expansion is gradually increasing, a smaller value can be selected for L2. Even if L 2 is greater than B, the foregoing is still causing the value of L2 to be selected as the divisor of B. Since the selection is independent of the channel expansion or time coherence of the channel, having a smaller L2 value allows more values to be stored in the SQI temple regardless of frequency or time. After the desired memory is obtained and calculated, the process proceeds to step 606. According to an embodiment of the present invention, in step 606', in step 6〇4, the number of memory devices is determined. The SQI processor 326 is initialized to the full frame using the address and control signal 327. In step 6〇8, the input unit is grouped and averaged by the SQI processor 326 (e.g., block average). In an embodiment, the L 2 units of the input S Q Ϊ are grouped and summed. In yet another embodiment, only one sQl unit between the input L2 unit groups is selected and the remainder is discarded. In an embodiment, when the transmitter uses a frequency domain interleaver, the L2 unit of the kiss grouped for compression deinterlacing purposes is not necessarily a sequential order of β. In this embodiment, the physical order of the subcarriers is different from the order of the input SQI units, and the ordering is reversed during the group period so that the SQI units of the corresponding consecutive L2 subcarriers are grouped together instead of the packet. Continuous L2 SQI unit. The unit of input SQI is called - (called 叩 (8), where k is the subcarrier index and p is the DM FDM signal index. Next, in step 610, the desired address is addressed by the first address generator 33. The memory address can be obtained as floor((k·丨)/L2)+丨, where the memory address starts from ❿1. It should be noted that this value does not necessarily change with each k, but vice versa. The change is made across the L2 cell group of the input SQI (where the average is done in step 608). The quantity k can be obtained as m〇d(n'K)+b, where η is the index of the input sqi unit. π 612 612, the thief in step X is accumulated at the memory location identified by the address obtained from the first address generator 33 步骤 in step 610. According to an embodiment of the present invention, the accumulation system may Use as

One of the infinite impulse response (IIR) filters shown in Eq. (9) is: ^ 55 201015905 new_mem_content=old_mem_content*alpha + (1 -alpha)*avg_input_SQI_unit Eq.(9) In Eq.(9) , avg"nput_SQI_unit is the result from step 608, old_mem_content is the previous content at the memory location determined by step 6 10, and new_mem_content is the new cumulative value. The number new_mem__content is written back to the same memory location. According to an embodiment of the invention, the number alpha is a design parameter of a floor ((b-l) / L2) + l function. In such embodiments, no memory is required across time and the value of L1 may be M*(b-1)*B/K. It should be noted that the L1 system can change with each change in the branch index, but the alpha value changes only when the L2 value group spans b. According to another embodiment of the present invention, the IIR averaging parameter alpha may be a function of the branching index of the deinterlacer, whereby the alpha system may gradually become larger as the branching index becomes larger. This particular can be used when the L2 value is one. When b is much larger than 1, new_mem_content can be defined according to Eq.(10): new_mem_content=old_mem_content*min(l - l/(M*(b-1)),beta) + input_SQI_unit Eq.(10) Alternatively, when b is equal to 1, new_mem_content may be defined in accordance with Eq. (ll): new_mem_content=old_mem_content*beta+input_SQI_unit Eq. (ll) As described above, according to an embodiment of the present invention, b = floor(( Kl) / B) + l, where k is the data subcarrier index starting from 1. In accordance with an alternative embodiment of the present invention, the branch index can be derived using a mapping function determined by a frequency domain interleaver at the transmitter. The beta system may be equal to 〇; or the beta system may be selected based on the quantity or accuracy of the input SQI or the SINR of the system; the value of "L" may also be used to determine the beta. Steps 614 and 616 show how to obtain the output of the compressed deinterleaving function block 212 264. In step 614, the next desired memory address is generated by the first address generator 346 to obtain the deinterleaved (7)th unit. Obtaining the mth deinterlaced SQI unit can be obtained from: © fl〇〇r(mod(m-1 +mod(m-1 ,B)*M*B,K)/L2)+1 Eq.( l 2) where m is from 1 onwards. The content at step 616' at the memory address can be read by output sqi generator 344 to produce a deinterleaved SQI unit. Steps 614 and 616 can be repeated as long as steps 6〇8, 61〇, and 612 are repeated until all inputs are entered or compression deinterleaver 212/264 is provided to terminate the control signal. In accordance with an embodiment of the present invention, each time b = 1, steps 614 and 616 can be skipped and the incoming unit of the SQI can be used as a unit of the deinterleaved SQI. In the embodiment shown in Fig. 10, the deinterlacing of the signal is used in the department, the first in the 1989, the European Commission for the Commonwealth of Communications, the Ministry of Communications, the Ministry of Communications, and the digital mobile radio communication (final report) CC^ The τυ6 type channel discussed in T207, pp. 135 147, the "hidden size" of the compression deinterleaver has been implemented to exceed the factor of (10) with a small loss of performance. The different statement is that in various embodiments of the invention, the memory size of the 57 201015905 collapse deinterleaver has been reduced by approximately 99% with only a small loss of performance. Any function or operation of the compression deinterlacing can be implemented in hardware or software or a combination of the two. In addition, the reference to "functional blocks" when implemented in hardware or software or a combination of both does not indicate the actual implementation of the functional blocks. This system can also indicate a memory module. The hardware embodiments of any of the functions, operations, or functional blocks described above, including any logic or transistor circuit, can be automatically computer-based based on the syntax and semantics of a hardware description language as is known to those skilled in the art. A hard description of the form is given. Applicable hardware description languages are included in the Layout level, Circuit Netlist level, Register Dingcai level and Schematic Capture level. Examples of hardware description languages include GDS II and 〇ASIS (Lay0ut level), various SPICE and IBls (Cireuit Netlist level), Veril〇g and VHDL (Register Transfer level), and

Virtuoso customization is not a language and Design Architecture-IC customization design 浯s (Schematic Capture level). The hardware language can also be used, for example, for a variety of behavioral, logical, and circuit molding and simulation purposes. Although the present invention has been described in terms of specific embodiments, it is to be understood that modifications and variations of the present invention will be apparent to those skilled in the art. Therefore, it is intended that the scope of the appended claims be interpreted as covering all modifications and modifications that fall within the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a communication system 1 in accordance with an embodiment of the present invention. 58 201015905 Figures 2 to 5 are various frequency response diagrams of a communication system with channel gain (丫 axis, to account) versus frequency (χ axis, in Hz). Figure 6 is a diagram showing a communication system in accordance with an embodiment of the present invention. Figure 7 is a diagram showing further details of the compression and decoding function block of Figures 6 and 6 in accordance with an embodiment of the present invention. Figure 8 is a flow chart showing the steps of performing one of the de-interlacing by the receiver in a method in accordance with the present invention. Figure 9 is a flow chart showing the implementation of compression deinterleaving of input SQI units by the compression Φ de-parent of Figure 6 and in accordance with a method of the present invention. Figure 10 is a flow chart showing the steps performed by compression deinterleaving by the compression deinterleaver of Figures 1 and 6 in a method in accordance with the present invention. [Main component symbol description] 10,20 communication system 12,22 transmitter

14, 24 Receiver 16, 26 Communication Channel 200 Deinterleaver 201, 203 Notch 202 Data Unit 204 Data Deinterleaver 206 (Deinterleaved) Data Unit 2 〇 8 Bit Soft Measure Generator / Function Block 59 201015905 210 212 214 226 227 230 240 242 244 246 248 250 252 262 264 266 268 310 312 314 3 16 322 324 326 bit soft metric compression deinterleaver/function block input SQI unit deinterleaved (input) SQI unit interleaver circuit data unit /Information symbol first bit soft metric generator/function block data unit data deinterleaver deinterleaved data/bit data deinterleaver output second bit soft metric generator/function block bit soft metric input SQI Unit Compression Deinterleaver / Function Block Input / Deinterleaved SQI Unit Deinterleaver Time / Frequency Coherence Interval Estimator / Function Block Time / Frequency Coherence Interval Adjustment Function Block Signal Signal / Output Input SQI Unit SQI Compression Function Block SQI Processing 60 201015905

327 Address and Control Signal 328 First Memory 330 First Address Generator/Function Block 331 Data Signal 332 Control Signal 334 Address and Control Signal/Address Generate Signal 338, 339 Signal 340 SQI Expand Function Block 342 Second Memory 344 Output SQI Generator 346 Address Generator/Function Block 348 Address and Control Signal 350 Signal/Content 352 Control Signal 354 Memory Address 360 Deinterleaved SQI Unit

61

Claims (1)

201015905 VII. Patent application scope: 1 · A method for deinterleaving in a communication system using a communication channel, the method includes: Deinterleaving a plurality of data units using a data deinterleaver to generate a plurality of data units Deinterleaving the data unit; compressing and deinterleaving a plurality of input quality information (SQI) units by a compression deinterleaver to generate a plurality of deinterleaved SQI units, wherein at least one of the plurality of input SQI units Corresponding to at least one of the plurality of data units; and applying the deinterleaved SQI unit to the corresponding deinterleaved data unit, in; at any given time, the compressed SQI unit stored by the desired deinterleaver The number is less than the number of data units stored by the data deinterleaver. 2_ As in the method of the patent application, wherein the compression deinterlacing includes -averaging or summing operations, the SQI estimation error is reduced and the receiver performance is improved. 3. The method of claim 2, wherein the de-interlacing and compression de-interlacing of the plurality of data sheets are simultaneously or substantially simultaneously performed (eg, the method of applying for the scope of the patent item i) The data sheet is deinterlaced and compressed and deinterleaved. The method of claim 1 is applied. 5. The method of claim 1 wherein the de-interlacing and compression de-interlacing of the plurality of data units are performed at a signal level. Performing at least one of a plurality of data units - a symbol. ^ wherein the plurality of data sheets 6. At least one of the methods of claim 61, paragraph 1 of 201015905 is a meta-softness measure. In the method of the first aspect of the patent scope, the method of compressing the decimation step, compressing the plurality of rounds of the sqi unit in the time range, and the plurality of input SQI units in the frequency range, β “Y 7〇, and at least the steps in the conversion of the expressions are carried out, and the foregoing results are stored in advance, and (4) the stored results are actually stored in the H-stored results package. A compressed SQI unit. 8. As claimed in the first paragraph of the patent scope, _ spear < 10,000, wherein the compression deinterlacing is performed by using the plurality of input SQI units as early as possible - The conversion statement is actually set, wherein the conversion expression allows the use of a smaller word length than the use of the transmission. V is 7 〇 9 如 9. As in the scope of the patent application, the kr I to the § Hai expansion operation system ^, One of the stored results reads, , , ^ ^ 2 bite different than at least one stored, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , For example, the seventh item of the patent scope includes at least two stored spoils...nhai expansion calculation system 1 solid storage results - read operation, one of the stored results on the reverse spine ^ '- at least two At least one of them. /, Repeat the nose u. For example, the method of applying for the scope of patent 帛i, in which the steps are in a single-click operation, such as the step of interleaving, including the combination of time and frequency range 1 + round SQI single cloud 0 & a λ vertical set the number of real - The result of the storage joint compression and the expansion of the stored fruit ... 果 果 果 果 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · # # # # # The step further includes evaluating the number of inputs of the group 2 into the SQI unit included in the unit, and the U system is much larger than the integer, and the function is a function: a group corresponding to the L1 input Sq. A quantity of the group, stored as a method of claim 12, which is a sum of L1 input groups of SQI units. ...the result of the number I4·If the method of claim 2, in which the integer is 'the result of the function is in the input SQI unit between the u input _ ", and when T] j group, When S L1 is an even integer, the letter is in the L 1 input s〇l罝 罝4 + number, and one of the words. Two rounds of the kissing unit in the middle of the group 15. Please refer to the method of the patent scope 帛7, the escape bar η...η全^丄m frequency, the storage system of the result of compression in the enclosure is further included in the evaluation unit (4) input SQI single (four) - group electricity number two :transmission = medium L2 is a function much larger than i, the result of A ff ^ r ^ and (d) function is stored as a number of groups corresponding to the L2 input SQI unit. The storage step of the result at the time of frequency and time compression includes evaluating the product of the 2 input_unit included in the complex == element to be a quantity greater than m and (4) (4) a number of groups of each kissing unit. In order to correspond to the loss of 17 · If the scope of the patent application is 15th jg Xi Shi · soil ^, _ ^ ^ . The method, wherein the communication system is a carrier system, the data deinterleaver is a convolutional deinterleaver, and the number of the stored numbers of the 64 201015905 i decomposed deinterleaver is deinterleaved with the data. The product is the product of the time division divided by the product of L1 s and the total number of battle waves, L1 and L2. 18. The method of claim 14, as in the method of claim 14, wherein L is based on the time-correlation of the communication channel. Interval Estimation*. Numerical system 19. The method of claim 15, wherein the frequency coherence interval is estimated based on one of the communication channels. The numerical system is 2〇·If the patent application scope 帛i item Lu QnT « . . ^ ' The correspondence between the input and the SQI in the middle of the 5th singularity is the noise-to-interference ratio (SINR) associated with the resource. 21. The method of applying the terms of the item I , wherein the data deinterleaver system, m total number B - convolution deinterleaver, 8 series, is an integer greater than one of i, and each data unit corresponds to one branch of a branch size, and the value of L1 Is set equal to lose The branch size of the branch unit corresponding to the SQI unit is multiplied by B divided by κ, which is the number of data subcarriers in the communication system. 22. A deinterleaver for use in a communication system, the deinterleaver comprising: a data deinterleaver configured to deinterleaver a plurality of data units; and a compressed deinterleaver configured Deinterlacing a plurality of input message quality information (SQI) units 'where at least one of the plurality of input SQI units corresponds to at least one of the plurality of data units and the compressed deinterleaver is configured to compress The plurality of SQI units generate 65 201015905 a plurality of compressed SQI units, store compressed s〇i箪; . ^, and perform a expansion operation on the stored compressed and reduced SQI units to generate a complex interleaved SQI The unit, wherein, at any given time, the number of compressed SQI units remaining by the compressed deinterleaver is less than the number of units stored by the resource deinterleaver. ' / 23. The deinterleaver of claim 22, wherein the compressed deinterleaver comprises: 'a first address generator configured to generate for identification - first memory a first address of the first location; an SQI compression function block responsive to the input SQI unit and configured to perform at least one of storing, reading, and accumulating operations at the location identified by the first address; a second address generator configured to generate a second address for identifying an address in a second memory; and an output SQI generator configured to read by the second address Retrieving one of the memory locations identified in the second memory and defining to read content, 0 configured to calculate a scaling factor, and configured to further scale the captured content by the scaling factor to generate A unit of a plurality of deinterleaved SQJ units. 24. The deinterleaver of claim 22, wherein the compressed deinterleaver comprises: a first address generator 'configured to generate a location for identifying a location in a first memory a first address; 66 201015905 an SQI compression function block responsive to the input sqi unit and configured to perform at least one of sampling, storing, and reading operations at the location identified by the first address; An address generator configured to generate a plurality of addresses for identifying a plurality of locations in the second memory; and an output SQI generator configured to read the plurality of locations in the second memory The inner valley is configured to perform an interpolation operation using the read content to generate a unit of the plurality of deinterleaved SQI units. The deinterleaver of claim 22, wherein the address generation operation of at least one of the first address generator and the second address generator comprises a frequency deinterleave operation. 26_such as the deinterlacer of claim 22, wherein the data deinterleaver has a total number B of branches - a convolution deinterleaver, B is an integer greater than one, and each data unit corresponds to One branch of a branch size, and the value of L1 is set equal to the branch size of the data unit corresponding to the input SQI unit multiplied by B divided by κ, κ is the number of data subcarriers in the system . 27. The deinterleaver of claim 22, wherein the sQI compression function block is configured to perform compression of the plurality of input SQI units over a time range, compressing the plurality of input sqz units over a frequency range, And translating the representation of the input SQI unit to produce at least one of the operations of the result' and configured to further store the result. 28. The deinterleaver of claim 22, wherein the SQI compression function block is configured to jointly compress the 67 201015905 plurality of input SQI units over time and frequency ranges, store the result of the joint compression, and An expansion operation is performed on the stored result, the expansion operation including at least one of a stored operation of at least one stored result, a scaling operation of a scaling factor, and a repetition operation. Eight, schema. (such as the next page) 68