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TW201003590A - Display device - Google Patents

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Publication number
TW201003590A
TW201003590A TW098107756A TW98107756A TW201003590A TW 201003590 A TW201003590 A TW 201003590A TW 098107756 A TW098107756 A TW 098107756A TW 98107756 A TW98107756 A TW 98107756A TW 201003590 A TW201003590 A TW 201003590A
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TW
Taiwan
Prior art keywords
pixel
pixels
potential
voltage
color
Prior art date
Application number
TW098107756A
Other languages
Chinese (zh)
Other versions
TWI395169B (en
Inventor
Tetsuro Yamamoto
Katsuhide Uchino
Original Assignee
Sony Corp
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Application filed by Sony Corp filed Critical Sony Corp
Publication of TW201003590A publication Critical patent/TW201003590A/en
Application granted granted Critical
Publication of TWI395169B publication Critical patent/TWI395169B/en

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0439Pixel structures
    • G09G2300/0452Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/04Maintaining the quality of display appearance
    • G09G2320/043Preventing or counteracting the effects of ageing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30Devices specially adapted for multicolour light emission
    • H10K59/35Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A display device includes a pixel unit wherein N (N=3) colors including R (red), G (green), and B (blue) are assigned to N pixels. Each of the N pixels includes a sampling transistor (Ms), a driving transistor (Md), a retention capacitor (Cs), and a light emitting element (organic light emitting diode (OLED)). Out of the N pixels, a pixel easy to be a dark point in a given color (e.g. B) or a pixel in a given color (e.g. G) which has the highest relative visibility is provided with two or more sets of pixel circuit elements, each including the driving transistor (Md), the retention capacitor (Cs), and the organic light emitting diode (OLED), while the pixels assigned with other colors are provided with less number of sets of pixel circuit elements.

Description

201003590 六、發明說明: 【發明所屬之技術領域】 本七明係關於一種以3色以上連續之N個像素構成顯示ι 個色用的像素單元,規則地配置複數像素單元,而形成像 素列之顯示聚置。特別是本發明係關於含有在像素内使 、才曰疋色之發光特性而自發光之發光元件與其驅動電路之 4勿積體化的像素電路之顯示裝置。 【先前技術】 有使用冗度藉由施加之電壓及流入之電流而變化的光電 元件之顯不裝置。如亮度藉由施加電壓而變化之光電元件 的代表例係液aa顯示元件,亮度藉由流入之電流而變化之 光电元件的代表例係有機電致發光⑽沁EleCtr〇 uminescence)元件。有機電致發光元件一般稱為〇LE〇(有 機發光二極體)。差異之點為液晶顯示元件係調制來自光 源之光的光調制(亦即非自發光)元件,而〇LED係自行發 光之自發光元件。 OLED在下部電極與上部電極之間層積有作為有機電洞 輸送層及有機發光層等之功能的複數有機薄膜。其膜厚依 發光波長而不同,又因使其具有光增強效果等之理由而各 有不同,不過總之,因為係有機材料,薄地形成困難。 OLED係利用在有機薄膜中施加電場而發光之現象的光電 元件,且藉由控制流入〇LED之電流值而獲得發色之色 調。因而,使用OLED作為光電元件之顯示裝置,各像素 6又有包含控制OLED之電流量用的驅動電晶體之像素電 136030.doc 201003590 路。201003590 VI. Description of the Invention: [Technical Field] The present invention relates to a pixel unit for displaying ι colors by N pixels of three or more consecutive colors, and regularly arranging a plurality of pixel units to form a pixel column Display aggregation. In particular, the present invention relates to a display device for a pixel circuit which does not integrate a light-emitting element which emits light in a pixel and emits light, and which is self-illuminating. [Prior Art] There is a display device that uses a photovoltaic element whose redundancy is changed by the applied voltage and the current flowing in. A representative example of a photovoltaic element which changes in brightness by application of a voltage is a liquid aa display element, and a representative example of the photovoltaic element whose luminance changes by an inflow current is an organic electroluminescence (10) 沁 Ele Ctr um uminescence element. The organic electroluminescent element is generally referred to as 〇LE〇 (organic light-emitting diode). The difference is that the liquid crystal display element modulates the light modulation (i.e., non-self-luminous) elements of the light from the light source, and the 〇LED is a self-luminous element that emits light by itself. The OLED has a plurality of organic thin films which function as an organic hole transport layer and an organic light-emitting layer, between the lower electrode and the upper electrode. The film thickness varies depending on the wavelength of light emission, and it differs depending on the reason why it has a light-enhancing effect. However, in general, it is difficult to form a thin material because of an organic material. The OLED is a photovoltaic element that uses a phenomenon in which an electric field is applied to an organic thin film to emit light, and a color tone of a color is obtained by controlling a current value flowing into the 〇LED. Therefore, using the OLED as a display device for a photovoltaic element, each pixel 6 has a pixel electrode 136030.doc 201003590 including a driving transistor for controlling the amount of current of the OLED.

曾提出有各種像素電路,主要的習知有4個電晶體 (4T) . 1個電容器(1C)型、4T · 2C 型、5T · 1C 型、3T · 1C 型等。 此等均係將防止因從TFT(薄膜電晶體)形成之電晶體的 特性偏差而引起之晝質降低,且在像素電路内部一定地控 制驅動電流,藉此使晝面全體之一致性(亮度之均一性)提 高作為目的。特別是在像素電路内將OLED連接於電源 時,依輸入之影像訊號的資料電位來控制電流量之驅動電 晶體的特性偏差直接影響OLED之發光亮度。因而,需要 進行驅動電晶體之特性,亦即臨限值電壓的修正。 進一步,以進行臨限值電壓之修正為前提,而修正從驅 動電晶體之電流驅動能力減去臨限值偏差起因成分等的驅 動能力成分(一般而言,稱為移動率)時,獲得更加高的一 致性。 就驅動電晶體之臨限值電壓及移動率的修正,如詳細說 明於專利文獻1中。 [專利文獻1]曰本特開2006-215213號公報 【發明内容】 但是,製造OLED等之光電元件時,因為塵埃(dust)等附 著,容易在面板上產生發光不正常之未點亮缺陷等的顯示 瑕疵。此種顯示瑕疵在提高顯示裝置良率上成為阻礙因 素,而妨礙顯示裝置之低成本化。 特別是OLED係形成堆積了許多層有機薄膜之多層膜構 136030.doc 201003590 造時’附著於成膜裝置内而容易剝落之有機薄膜往往在成 膜裝置之處理室内漂浮而成為塵埃,因此種塵埃之附箸, OLED之電極間以某種電阻值而短路時,$易發生無法經 常發光的未點亮缺陷。 另外’產生了未點亮缺陷之情況’依其未點亮缺陷係由 進行色顯示之像素單元内的哪個色的像素而產生,瑕疮之 f . 辨識度不同。換言之,愈是辨識度高之色,因發生像素瑕 疲導致顯示品質降低也愈大。 "卜本《月人就產生了未點亮缺陷情況下,具有抑制 八影響之結構的像素之顯示裝 2〇〇7-3〇786im)o 破置已申味專利(日本特願 =發明所欲解決之問題,係提出-種產生了未點亮缺陷 之月况,比上述先前之申請案更可抑制像素面積之增大, ==效地抑制未點亮缺陷對畫面顯示之影響的像素電 關於本發明一種形態(第一形態)之顯示裝置含有將包含 / G(綠)、B(藍)之寧^3)色對連續之N個像素,在 母1個像素分配1色而槿忐 冓成像素早兀’並規則地配置有複數 月J述像素早凡之像素陣列。 勺=述像素陣列在構成其前述像素單元之ν個像素各個中 :;:拙樣電晶體、驅動電晶體、保持電容器及發光元 點:::持電容器結合於前述驅動電晶體之發光控制節 '.、保持經由前述抽樣電晶體而輸入之資料電塵。 I36030.doc 201003590 前述發光元件與前 流路徑,依所保持之 控制的驅動電流量, 光0 述驅動電晶體一起串聯連接於驅動電 前述資料電壓,依據前述驅動電晶體 以各像素所決定之色的發光特性自發 此外’於前述N個像音肉 ,^ „ ^..a 素内’在谷易成為未點亮缺陷之与 疋色或疋相對可見度最 動雷曰-、, 门之特疋色的像素中,包含前述, 動玉日日體、珂述保持 今的及别述發光元件之像素電路^ 素之、,且以比其他色的像乂 象常之則述組多的數量設有2组J; 上。 走關於本發明其他形態(第二形態)之顯示裝置,除了 h :二:態之特徵外’並且前述發光元件含有在陽極㈣ 、ι數右=極上層積有含有與發光之色相應的材質與厚心 為前述未點亮缺陷之特定二;=::形成於容“ 之總膜厚比前#他色二=:…述複數有趣 月j k八他已之像素的前述總膜厚小。 ==理想的是’前述其他色之像素中,在比心 :疋色之像素中之前述像素電路要素的組數少之範圍内, 别述後數有機薄膜之總膜厚愈薄,設愈 形態)。 (^ ·" ’除了上述 之特定色係 前述組數比 除了上述 關於本發明其他形態(第四形態)之顯示叢置 第一形態之特徵外’並且前述相對可見度最高 月'J述綠(G),前述R(紅)與前述B(藍)之各像素的 前述綠(G)少。 關於本發明其他形態(第五形態)之顯示裝置 136030.doc 201003590 第一形態之外,並且在〗個前述像素内存在複數前述組之 情況,以前述複數組共用地設有1個前述抽樣電晶體。 關於本發明其他形態(第六形態)之顯示裝置,除了上述 第一形態之外,並且在設於前述N個像素内之全部前述組 中,分別相同地設計前述驅動電晶體之通道導電型及尺 寸,以及前述保持電容器之電容值,且在相同像素内設置 複數前述發光元件之情況,藉由將該複數發光元件之前述 驅動電流路徑複數並聯連接於驅動電壓之供給端子,前述 各發光元件被分離。 關於本發明其他形態(第七形態)之顯示裝置,除了上述 述:=:外:並且對於前述特定色之像素,以使設有前 心述發光元件的孔徑部之合計面積,與前述 的方像素的前述孔徑部之面積大致相等 面積大疋則述特定色之像素面積比前述其他色之像素 ϋ 更理想的是,在前述其他色之像素間, 情況,以使前述各像素之孔徑部門= 之方式,使像素面積不同(“形㈠。料間大致相同 依照以上之結構,在進行丨個色顯 成該像素單元之_像素t I素早兀中,構 述驅動電晶體、前述保丄=定色之像素’包含前 路要素之組比其他色之像;Γ及别述發光元件之像素電 上。 像素的前述組數多,且設有2组以 h色之像素」係指容易成為未點亮缺陷之像 i36030.doc 201003590 素,如藍(B)等發光元件之多声 像素。或是,「特定色之像素:係指===最薄之 如綠(G)的像素。 對可見度隶尚之例 為了提高易懂性,舉一例說明 3個像素結構的像素單⑽ 在此,係R,G,B之 組上述像素電路要素之組,並在复I:在藍⑻之像素設2 組。 ^他色之像素設1組上述 該例中,像素單元内之上述 設有4個。假設4個發光 % 且UtM牛亦 亮缺陷產生時,成為未 ^面積相同’則1個未點 成為未點冗缺陷之概 相同為1/4。不過,在 仃毛光兀件均 積相等的前提下,在特1⑼ 其他色(R, G)孔徑面 声舰Ή ()孔徑部多1個部分,在特定 色()成為未點免缺陷之概率是其他色之2倍。 二卜:就色來觀察’在特定色(Β)之像素:外(r, G)產生 : 陷時,則就該色(R,G)全部不發光。但是,因為 =色㈣素係設有2個發光元件,所以即使其中= *因為其他1個發光,雖亮度為一半,不過仍 保作為色(B)之發光本身。 》 σ石 另外’就匕G,Β之3色’孔徑面積相等的情況,就特定 (Β),因為設有2個比其他色(R,G)之孔徑部為一半面積 的孔徑部,所以就色成為未點亮缺陷之概率,任何色均相 5而且。上述同樣地,在特定色⑻即使ι個發光元件因 塵埃等而成為未點亮缺陷,因為其他!個發光元件發光, 所以避免完全不進行Β發光的最差情況。 136030.doc 201003590 假設特定色之組數為3組以上時,組數愈多愈可抑制_ 發光元件因塵埃等而不發光的影響。換言之,組數為3的 情況下亮度成為2/3’可比亮度為1/2之情況減少未點亮缺 陷產生之影響。同樣地,組數為4以上時,亮度為Μ、 4/5、5/6、…組數愈多未點亮缺陷產生之影響愈小。不 過,在相同面積之像素中配置許多發光元件之孔徑部時, 因為!個孔徑面積亦相對地變小,所以初期設定之亮度(無 未點亮缺陷之情況的亮度)亦下ρ♦。因❿,一般而言,增 夕組數時’增多其組數之色的像素面積亦有增大的趨勢。 如此’-般而言,係以增大像素面積與抑制產生未點亮 缺陷時之影響(亮度降低之程度)的權衡來衫各色之組 數。 在:種狀況下適用本發明,則各色之組數並非一律,由 Μ容易成為未點亮缺陷或相對可見度高之特定色設更多 之組,因此緩和上述權衡。 u 依照本發明,可提出一種藉由上述權衡之缓和,壓抑像 素面積之增大,並可更有效地抑制未點亮缺陷對書面顧示 之影響的像素電路之結構。 【實施方式】 以了,以有機EL顯示器中適用本發明之情況為例,參照 圖式說明本發明之實施形態。 <全體結構> 广中顯示關於本發明之實施形態的有機虹顯示器之主 要結構。 136030.doc 201003590 電^:之了機广7^1含有:矩陣狀地配置了複數像素 电,J之素陣列2,及驅動像素陣列2之驅動電路。 驅動電路包含:垂直驅動電路(V掃描器(V Sean叫)4、盘 水平驅動電路(H掃描器(H Scanner) : H_ Scan)s。 。 V掃描器4藉由像素電路3之結構而設有複數。在此,v 掃描器4包含:水平像素線驅動電路(DSCN)41、與寫入m 號掃描電路(WSCN)42而構成。 '‘。 圖1所示之像素電路的符號「叫,L表示該像素電路具 有垂直方向(縱方向)之位址i(卜丨,2)與水平方向(橫方向)之 位址J(尸1,2, 3)。此等位址丨與』取最大值分別為「n」與 、」的1以上之整數。在此,為了圖之簡化,而顯^ n=2、m=3之情況。 該位址註記在以後之說明及圖式中,就像素電路之元 件、訊號及訊號線以及電壓等亦同樣地適用。 像素電路3(1,υ、3(2, υ連接於共用之垂直方向的第— 訊號線SIG(1)。同樣地,像素電路3(1,2)、3(2, 2)連接於 共用之垂直方向的第二訊號線SIG(2),像素電路3(丨,3)、 3(2, 3)連接於共用之垂直方向的第三訊號線SIG(3)。 第一列之像素電路3(1, υ、3(1, 2)及3(1,3)藉由共用之 掃描訊號線’可從水平像素線驅動電路4丨施加第一掃描气 號VSCANl(l)。同樣地,第二列之像素電路3(2,u 2)及3(2,3)藉由共用之掃描訊號線,可從水平像素線驅動 電路41施加第一掃描訊號vsc AN 1(2)。 此外,第一列之像素電路3(1,丨)、3(1,2)及3(1,W藉由 136030.doc •10· 201003590 共用之其他掃描訊號線,可從寫入訊號掃描電路42施加第 二掃描訊號VSCAN2(1)。同樣地,第二列之像素電路3(2, 1)、3(2,2)及3(2,3)藉由共用之其他掃描訊號線,可從寫 入訊號掃描電路42施加第二掃描訊號VSCAN2(2)。 <像素電路1> 圖2中顯示驅動電晶體由PMOS電晶體構成之情況的像素 電路3(i,j)最基本之結構。 圖解之像素電路3(i, j)係控制作為發光元件之有機發光 二極體OLED的電路。像素電路除了有機發光二極體OLED 之外,還含有:由PMOS型之TFT構成的驅動電晶體Md, 由NMOS型之TFT構成的抽樣電晶體Ms,及1個保持電容器 Cs。 有機發光二極體OLED含有如在由透明玻璃等構成之基 板上,形成使第一電極(陽極電極)、電洞輸送層、發光 層、電子輸送層、電子佈植層等依序堆積,而構成有機膜 之疊層體,且在該疊層體之上形成了第二電極(陰極電極) 之構造,不過並未特別圖示。陽極電極連接於正側之第一 電源,陰極電極連接於負側之第二電源。另外,亦可第二 電源係正側之電源,第一電源係負側之電源。其情況下, 陽極電極連接於第二電源,陰極電極連接於第一電源。 另外,圖2係顯示有機發光二極體OLED之陽極從正側之 第一電源接受高電位Vcc_ Η之供給,有機發光二極體 OLED之陰極連接於基準電壓,如接地電壓GND之情況。 在有機發光二極體OLED之陽極與陰極的電極間施加指 136030.doc • 11 - 201003590 定之偏屢電位時,佈槽 與%洞於發光層中再結合時 " '有機發光二極體0LED藉由適宜選擇構成有 機膜之有機材料,可t 再&有 ^ + 了以紅⑻、綠⑼、藍(B)之各色發光, 因此藉由將該有機枯斗泣Λ … /有機材#如可在各列之像素中排列r,G, 發光,可進行彩色顯示。 材料,而以遽色器之色二 使用白色發光之有機 _ 進仃R,G,B的區別。除了 R,G,B之 外,亦可為加上w(白)之4色結構。 :動電晶體_作為控制流人發光元件(有機 ;—)之電流量,以規㈣示色調之電流控制機構的= 月匕° 驅動電晶體Md之源極遠接於古币/ ㈣連接於南電位Vcc—Η的供給線, 汲極連接於有機發光二極體〇咖之陽極。 抽樣電晶體Ms連接於決定像紊♦ ^ .. 、色調之貧料4位Vsig的供 =(衫像《線DTL⑴)與驅動電晶體㈣的閘極之間。抽 樣电日日體M s之源極與汲極 万運接於驅動電晶體Md之 甲。 另一方連接於影像訊號绩ηττ ,·、 ^ ηττ 、 像Λ 5虎線DTL(J)。在影像訊號線 二上,從Η掃描器5施加資料電位W。抽樣電晶體· 二:貝科電位施加期間之適當時序,抽樣須以該像素電路 位準的貧料。這是為了排除在須抽樣之具有希望的 ^電位Vsig之資料脈衝的最前或後部,對位準不穩定之 轉移期間的顯示影像之影響。 •車ί Γ電位Vec—H之供給線與驅動電晶體Md之閘極之間 持電容器Cs。就保持電容器Cs之角色以後述之動 136030.doc 201003590 卜圖2係省略了圖j之藉由水平像素線驅動電路 控制的結構。該結構如亦可為連接於圖2之高心Vee H 的供給線與驅動電晶體_之間的其他電晶 - =一定周期反覆於指定時間程度施加高電:二: 此等結構係為了驅動掃描而設,因為驅動掃: 各種方式,所以在圖2省略。 <像素電路2> 圖3中顯示驅動電晶體 素電路3W)最基本之結構。S電曰曰體構成之情況的像 血像素電路3(i,』)除了驅動電晶體⑽之通道導電型 NM:同之外,成為同樣之結構。驅動電晶體Md為 S電晶體結構之情況,因為每單位尺寸可取大之驅動 與可以_道型形成像素電路内之全部電晶體,所 以具有可簡化製程的優點。 另外’像素電路!及像素電路2係像素電路内之全部電晶 體以T打形成。形成TFT之通道的薄膜半導體層由多結晶 石夕(P〇iys山c〇ne)或是非晶質石夕(咖_奶s出叫等之半導 體材料構成。多結晶石夕TFT雖可取高移動率,不過,因為 特性偏差大’所以不適於顯示裝置之大晝面化。因而含有 大晝面之顯示裝置一般而言係使用非晶質矽TFT。不過, 因為非晶質石夕TFT其P通道型TFT形成困難,所以應使用上 述之像素電路2或是將此作為基本結構的像素電路。 在此,以上之像素電路丨、像素電路2係在本實施形態可 適用之像素電路的-例,亦即係、2個電晶體(2τ)· i個電容 136030.doc -13- 201003590 為(ic)型之基本結構例。因而本實施形態 路亦可係、將像素電路1或料電路2作為基本結構1一素電 附加了電晶體及電容器之像辛恭 ^ m 诼常包路。具體而言,本實施形Various pixel circuits have been proposed, and the main conventional ones are four transistors (4T). One capacitor (1C) type, 4T · 2C type, 5T · 1C type, 3T · 1C type, and the like. All of these are to prevent deterioration of the quality due to variations in characteristics of the transistor formed from the TFT (Thin Film Transistor), and to control the driving current to be constant within the pixel circuit, thereby making the entire surface uniform (luminance) Uniformity) is raised as an end. In particular, when the OLED is connected to the power supply in the pixel circuit, the characteristic deviation of the driving transistor according to the data potential of the input image signal directly affects the luminescence brightness of the OLED. Therefore, it is necessary to perform the characteristics of the driving transistor, that is, the correction of the threshold voltage. Further, on the premise of correcting the threshold voltage, the drive capability component (generally referred to as the mobility ratio) such as the current drive capability of the drive transistor minus the threshold component of the threshold value is corrected. High consistency. The correction of the threshold voltage and the mobility of the driving transistor is described in detail in Patent Document 1. [Patent Document 1] JP-A-2006-215213 SUMMARY OF THE INVENTION However, when a photovoltaic element such as an OLED is manufactured, dust or the like is likely to adhere to the panel, and it is easy to cause an unlit defect such as an abnormal light emission on the panel. The display is 瑕疵. Such display 成为 is a hindrance factor in improving the display device yield, and hinders the cost reduction of the display device. In particular, the OLED system forms a multilayer film structure in which a plurality of organic thin films are deposited. 136030.doc 201003590 The organic film which adheres to the film forming apparatus and is easily peeled off tends to float in the processing chamber of the film forming apparatus to become dust, and thus the dust is formed. As a result, when the electrodes of the OLED are short-circuited with a certain resistance value, it is prone to an unlit defect that cannot be always emitted. Further, the case where an unlit defect occurs is generated depending on which color pixel in the pixel unit in which color display is performed, and the degree of recognition of the acne f is different. In other words, the more the color is recognized, the more the display quality is degraded due to pixel fatigue. "Buben "The moon has produced a display of pixels with a structure that suppresses eight influences in the case of unlit defects. 2〇〇7-3〇786im) o The patent has been dismissed (Japan's special wish = invention The problem to be solved is to propose a month condition in which an unlit defect is generated, which can suppress the increase of the pixel area more than the above-mentioned prior application, and == effectively suppress the influence of the unlit defect on the screen display. The display device according to one aspect of the present invention (first aspect) includes N pixels including a pair of /G (green) and B (blue) colors, and one color is assigned to one pixel of the mother. The pixels are formed early and are regularly arranged with a plurality of pixel arrays of a plurality of pixels. Spoon = the pixel array in each of the ν pixels constituting the aforementioned pixel unit::: 拙-like transistor, driving transistor, holding capacitor, and illuminating element::: Capacitor is coupled to the illuminating control section of the driving transistor '. Keep the data dust input through the aforementioned sampling transistor. I36030.doc 201003590 The light-emitting element and the front-end path are connected in series with the driving data according to the amount of driving current controlled by the driving, and the color determined by each pixel according to the driving transistor. The luminescence property is spontaneously in addition to the above-mentioned N vocal flesh, ^ „ ^..a 素in 'in the valley is the unlit defect and the relative visibility of the twilight or sputum is the most dynamic thunder -,, the special feature of the door The color pixels include the above-mentioned pixel circuits of the illuminating elements and the illuminating elements of the illuminating elements, and are arranged in a larger number than the image groups of other colors. There are two groups of J; the above. In the display device according to another aspect (second aspect) of the present invention, except for the feature of the h: two: state, and the light-emitting element is contained in the anode (four), the number of the right = the upper layer is contained. The material and the center of the thickness corresponding to the color of the illuminate are the specific two of the aforementioned unlit defects; =:: formed in the total film thickness of the volume "previously #他色二=:...the plural number of interesting months jk eight his pixels The aforementioned total film thickness is small. == ideally, in the pixel of the other color, in the range of the number of groups of the pixel circuit elements in the pixel of the color: the color, the thinner the total film thickness of the organic film is form). (^ ·" 'In addition to the above-described specific color system, the number of the above-mentioned groups is smaller than the above-described display of the first aspect of the present invention with respect to the other aspects (fourth aspect) of the present invention, and the aforementioned relative visibility is the highest month 'J green ( G), the green (G) of each of the above-mentioned R (red) and the above-mentioned B (blue) is small. The display device of the other aspect (fifth aspect) of the present invention is 136030.doc 201003590 In the case where a plurality of the above-described groups are present in the plurality of pixels, one of the sampling transistors is provided in common with the plurality of arrays. The display device according to another aspect (sixth aspect) of the present invention is not limited to the first aspect described above, and In all of the foregoing groups of the N pixels, the channel conductivity type and size of the driving transistor and the capacitance value of the holding capacitor are respectively designed in the same manner, and a plurality of the light emitting elements are provided in the same pixel. Each of the light-emitting elements is separated by a plurality of parallel connection of the drive current paths of the plurality of light-emitting elements to a supply terminal of a drive voltage. In the display device of the other aspect (seventh aspect), in addition to the above-mentioned: =: and the pixel of the specific color, the total area of the aperture portions provided with the light-emitting elements of the front side is compared with the square pixels described above. Preferably, the area of the aperture portion is substantially equal to the area, and the pixel area of the specific color is more preferable than the pixel of the other color. Between the pixels of the other colors, the aperture unit of each pixel is determined to be , the pixel area is different ("shape (a). The material is substantially the same according to the above structure, in the _ pixel t I prime early in the color display, the drive transistor, the aforementioned protection = fixed color The pixel 'includes a group of anterior elements than other colors; Γ and the pixels of the other illuminating elements are electrically connected. The number of the above-mentioned pixels of the pixel is large, and two sets of pixels with h colors are provided. Image of bright defect i36030.doc 201003590 Prime, multi-sound pixels of light-emitting elements such as blue (B). Or, "Pixels of a specific color: refers to the pixel with the thinnest green (G) === visibility. Li Shang’s case for the sake of mention Easy-to-understand, for example, a pixel list of three pixel structures (10) Here, a group of the above-mentioned pixel circuit elements of R, G, and B, and two sets of pixels in the complex I: in the blue (8). In the above example, the number of pixels is set to four. In the case of the pixel unit, four are provided. If four light-emitting % are generated and the UtM is bright, the same area is the same, and then one un-point becomes an un-defective defect. The same is 1/4. However, under the premise that the average of the bristles is equal, in the 1 (9) other color (R, G) aperture surface acoustic ship Ή () aperture part more than one part, in a specific color () The probability of becoming a defect-free defect is twice that of other colors. Two Bu: Observe the color in the pixel of a specific color (Β): outside (r, G): When trapped, the color (R, G) ) All do not shine. However, since the two color elements are provided with the two color elements, even if the light is half of the light due to the other one, the light itself is the color (B). σ σ 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 As long as the color becomes the probability of unlit defects, any color is homogeneous 5 and. Similarly, in the case of the specific color (8), even if one light-emitting element becomes an unlit defect due to dust or the like, since the other light-emitting elements emit light, it is possible to avoid the worst case where the xenon light emission is not performed at all. 136030.doc 201003590 Assuming that the number of groups of a specific color is three or more, the more the number of groups, the more the light-emitting element can be suppressed from being emitted due to dust or the like. In other words, when the number of groups is 3, the luminance becomes 2/3', and the luminance is 1/2, which reduces the influence of the unlit defect. Similarly, when the number of groups is 4 or more, the brightness is Μ, 4/5, 5/6, ... the more the number of groups, the less the influence of the unlit defects. However, when a plurality of aperture portions of a plurality of light-emitting elements are arranged in pixels of the same area, since the area of the apertures is relatively small, the brightness of the initial setting (the brightness without the defect of the unlit) is also ρ♦. In general, the pixel area in which the number of groups is increased as the number of groups is increased is also increased. Thus, in general, the number of colors of the shirts is increased by increasing the pixel area and suppressing the influence of the occurrence of unlit defects (the degree of brightness reduction). When the present invention is applied in the following conditions, the number of sets of the respective colors is not uniform, and the above-mentioned trade-off is alleviated by the fact that it is easy to become an unlit defect or a more specific color set with higher visibility. u According to the present invention, it is possible to propose a structure of a pixel circuit which suppresses an increase in the pixel area by the above-mentioned trade-off, and can more effectively suppress the influence of unlit defects on the written description. [Embodiment] In the case where the present invention is applied to an organic EL display, an embodiment of the present invention will be described with reference to the drawings. <Overall Structure> The main structure of the organic rainbow display according to the embodiment of the present invention is shown in the wide area. 136030.doc 201003590 Electric ^: The machine wide 7^1 contains: a plurality of pixels, a matrix of pixels 2, and a driving circuit for driving the pixel array 2 are arranged in a matrix. The driving circuit includes: a vertical driving circuit (V scanner (V Sean called) 4, a disk horizontal driving circuit (H Scanner): H_Scan) s. The V scanner 4 is designed by the structure of the pixel circuit 3. Here, the v-scanner 4 includes a horizontal pixel line drive circuit (DSCN) 41 and a write-to-m scan circuit (WSCN) 42. ''. The symbol of the pixel circuit shown in FIG. L indicates that the pixel circuit has the address i (division, 2) in the vertical direction (longitudinal direction) and the address J (the corpse 1, 2, 3) in the horizontal direction (horizontal direction). The maximum value is an integer of 1 or more of "n" and "," Here, for the sake of simplification of the figure, the case where n = 2 and m = 3 is displayed. The address is described in the following description and the drawing. The same applies to the components of the pixel circuit, the signal, the signal line, and the voltage. The pixel circuit 3 (1, υ, 3 (2, υ is connected to the common vertical direction signal line SIG (1). Similarly , the pixel circuits 3 (1, 2), 3 (2, 2) are connected to the common vertical direction second signal line SIG (2), and the pixel circuits 3 (丨, 3), 3 (2, 3) are connected. The third signal line SIG(3) in the vertical direction is shared. The pixel circuits 3 (1, υ, 3(1, 2) and 3(1, 3) of the first column are horizontally available by sharing the scanning signal line' The pixel line driving circuit 4 丨 applies the first scanning gas number VSCAN1(1). Similarly, the pixel circuits 3 (2, u 2) and 3 (2, 3) of the second column are available from the common scanning signal line. The horizontal pixel line driving circuit 41 applies the first scanning signal vsc AN 1(2). Further, the pixel circuits 3 (1, 丨), 3 (1, 2), and 3 of the first column (1, W by 136030.doc • 10· 201003590 Other scan signal lines shared, the second scan signal VSCAN2(1) can be applied from the write signal scanning circuit 42. Similarly, the pixel circuits 3 (2, 1), 3 (2, 2) of the second column And 3(2,3), by sharing the other scan signal lines, the second scan signal VSCAN2(2) can be applied from the write signal scanning circuit 42. <Pixel Circuit 1> Figure 2 shows the drive transistor by PMOS The most basic structure of the pixel circuit 3(i,j) in the case of the transistor structure. The illustrated pixel circuit 3(i, j) is a circuit for controlling the organic light emitting diode OLED as a light emitting element. In addition to the light-emitting diode OLED, a driving transistor Md composed of a PMOS type TFT, a sampling transistor Ms composed of an NMOS type TFT, and a holding capacitor Cs are included. The organic light emitting diode OLED includes On the substrate made of transparent glass or the like, a laminate in which a first electrode (anode electrode), a hole transport layer, a light-emitting layer, an electron transport layer, an electron implant layer, and the like are sequentially deposited to form an organic film is formed. Further, a structure of the second electrode (cathode electrode) was formed on the laminate, but it was not particularly shown. The anode electrode is connected to the first power source on the positive side, and the cathode electrode is connected to the second power source on the negative side. Alternatively, the second power source may be a power source on the positive side, and the first power source is a power source on the negative side. In this case, the anode electrode is connected to the second power source, and the cathode electrode is connected to the first power source. Further, Fig. 2 shows a case where the anode of the organic light emitting diode OLED receives a supply of a high potential Vcc_? from the first power source on the positive side, and the cathode of the organic light emitting diode OLED is connected to a reference voltage such as a ground voltage GND. Applying the finger between the anode and cathode of the organic light-emitting diode OLED 136030.doc • 11 - 201003590 When the potential is repeated, the groove and the % hole are recombined in the light-emitting layer " 'organic light-emitting diode OLED By appropriately selecting the organic material constituting the organic film, it is possible to illuminate each of the colors of red (8), green (9), and blue (B), thereby soaking the organic cock... /organic material# If r, G, and illuminate can be arranged in the pixels of each column, color display can be performed. Material, and the color of the color is used. The difference between the use of white illuminating organic _ 仃 R, G, B. In addition to R, G, and B, a four-color structure of w (white) may be added. : electro-dynamic crystal _ as the current amount of the control human light-emitting element (organic; -), according to the (four) color tone control mechanism = month 匕 ° drive transistor Md source is far from the ancient currency / (four) connected to The south potential Vcc-Η supply line, the drain is connected to the anode of the organic light-emitting diode. The sampling transistor Ms is connected between the gates of the 4-bit Vsig (the line like DTL(1)) and the gate of the driving transistor (4). The source and the bungee of the sampled solar celestial body M s are connected to the driving transistor Md. The other party is connected to the image signal ηττ , ·, ^ ηττ , and Λ 5 tiger line DTL (J). On the image signal line 2, the data potential W is applied from the Η scanner 5. Sampling the transistor · 2: Appropriate timing during the application of the Becco potential, the sampling must be poor at the level of the pixel circuit. This is to exclude the influence of the display image during the transition of the level unstable transition at the forefront or the rear of the data pulse of the desired ^ potential Vsig to be sampled. • The capacitor Cs is held between the supply line of the driving potential Vec-H and the gate of the driving transistor Md. The movement of the capacitor Cs will be described later. 136030.doc 201003590 FIG. 2 omits the structure controlled by the horizontal pixel line driving circuit of FIG. The structure may also be other electro-crystals between the supply line connected to the high-center Vee H of FIG. 2 and the driving transistor _ - a certain period of time is applied to the specified time to apply high power: 2: These structures are driven Scanning is set, because the drive sweep: various ways, so it is omitted in Figure 2. <Pixel Circuit 2> The most basic structure of the driving transistor circuit 3W) is shown in FIG. The blood pixel circuit 3 (i, 』) in the case where the S electrode body is configured has the same structure except that the channel conductivity type NM of the transistor (10) is driven. The driving transistor Md is in the case of the S transistor structure, since a large driving unit can be formed in a unit type and can form all the transistors in the pixel circuit, so that the process can be simplified. In addition 'pixel circuit! And the pixel circuit 2 is formed by T-shaped all of the electric crystals in the pixel circuit. The thin film semiconductor layer forming the channel of the TFT is composed of a polycrystalline stone (P〇iys mountain c〇ne) or an amorphous stone material (a coffee material such as a coffee _ milk s.) However, since the characteristic deviation is large, it is not suitable for the large-scale display of the display device. Therefore, the display device including the large-faced surface generally uses an amorphous germanium TFT. However, since the amorphous stone-etched TFT has its P Since the channel type TFT is difficult to form, the above-described pixel circuit 2 or a pixel circuit having the basic structure should be used. Here, the above pixel circuit 丨 and pixel circuit 2 are examples of a pixel circuit to which the present embodiment is applicable. That is, two transistors (2τ)· i capacitors 136030.doc -13- 201003590 are basic structural examples of the (ic) type. Therefore, the circuit of this embodiment can also be used to connect the pixel circuit 1 or the material circuit 2 As a basic structure, a single crystal is attached with a picture of a transistor and a capacitor, and the present embodiment is shaped.

心可採用之像素電路如亦可為4丁· ic型、4T 5Τ· 1C型等’不過不討論詳細之結構。 <發光控制之概略> 上述2個像素電路中之概略的發光控制動作係如以下。 在驅動電晶體Md之控制節點紙上結合有保持電容器 C”來自,號線SIG⑴之訊號電壓¥化以抽樣電晶體^抽 樣,並將藉此獲得之資料電位Vsig施加於控制節點肋C。 圖4中顯示有機發光二極體〇LED之[V特性的圖形與驅 動電晶體Md之沒極電流Ids(相當於〇LED之驅動電流⑷的 一般式。 在驅動電晶體Md之閘極上施加了指定之資料電位 時,於<像素電路】:圖2>之情況,以p通道型之驅動電晶The pixel circuit that can be used for the heart can be, for example, a 4 □ ic type, a 4T 5 Τ · 1C type, etc., but the detailed structure is not discussed. <Summary of Light-Emitting Control> The outline of the above-described two pixel circuits is as follows. The control capacitor C" is coupled to the control node of the driving transistor Md, and the signal voltage of the line SIG(1) is sampled by the sampling transistor, and the data potential Vsig obtained thereby is applied to the control node rib C. The figure of the [V characteristic of the organic light-emitting diode 〇LED and the electrodeless current Ids of the driving transistor Md (corresponding to the general formula of the driving current (4) of the 〇LED) is applied to the gate of the driving transistor Md. In the case of the data potential, in the case of <pixel circuit]: Fig. 2>, the p-channel type is driven by the crystal.

Md的源極連接於電源,而始終在飽和區域動作的方式 设叶。為此,該P通道型之驅動電晶體Md成為具有以圖4 之公式表示的值之穩流源。該穩流源流出之汲極電流 ,依具有依施壓於P通道型之驅動電晶體Md的閘極之資 料電位的值之閘極源極間電壓Vgs而決定。因而,有機發 光二極體OLED係以依抽樣後之資料電位Vsig的亮度而發 光。 如熟知,有機發光二極體OLED藉由隨時間變化,其j-v 特性如圖4而變化。此時,因為穩流源想要流出相同值之 136030.doc -14- 201003590 驅動電流Id,所以有機發光二極體OLED之施加電壓V變 大,P通道型之驅動電晶體Md的没極電位上昇。但是,由 於P通道型之驅動電晶體Md的閘極源極間電壓Vgs —定, 所以在有機發光二極體OLED中流入一定量之驅動電流 Id,發光亮度不變化。 但是,將驅動電晶體Md替換成N通道型之 <像素電路2 : 圖3>,因為驅動電晶體Md之源極連接於有機發光二極體 OLED,所以閘極源極間電壓Vgs與有機發光二極體OLED 之隨時間變化一起變化。 藉此,流入有機發光二極體OLED之驅動電流Id變化, 結果,即使是指定之資料電位Vsig,發光亮度仍變化。 此外,因為各像素電路之驅動電晶體Md的臨限值電壓 Vth、移動率μ不同,所以依圖4之公式,汲極電流Ids中產 生偏差,即使給予之資料電位Vsig相同,像素之發光亮度 仍變化。 另外,在圖4之公式中,符號「Ids」表示流入在飽和區 域動作之驅動電晶體Md的汲極與源極間之電流。此外, 該驅動電晶體Md中,分別將「Vth」表示臨限值電壓, 「μ」表示移動率,「W」表示有效通道寬(有效閘極寬), 「L」表示有效通道長(有效閘極長)。此外,「Cox」表示 該驅動電晶體M d之早位閘極電容’亦即每早位面積之閘 極氧化膜電容與源極或汲極與閘極間之邊緣電容的總和。 含有N通道型之體驅動電晶體Md的像素電路雖有驅動能 力高可簡化製程的優點,不過,為了壓抑臨限值電壓Vth 136030.doc •15- 201003590 及移動率μ之偏差,需要在前述之發光控制動作之前進行 以下之修正動作。 <修正之概略> 具體之控制的詳細内容於後述,在抽樣之前,藉由保持 電容器Cs,而以其臨限值電壓Vth之位準保持驅動電晶體 Md之閘極源極間電壓Vgs。將該預備性之動作稱為「臨限 值修正」。 臨限值修正後,因為在驅動電晶體Md之閘極中加上抽 樣後之資料電壓Vin,所以閘極源極間電壓Vgs成為 「Vth+Vin」而被保持。驅動電晶體Md依此時之資料電壓 Vin的大小而接通。臨限值電壓Vth大而接通困難之驅動電 晶體Md的情況,「Vth+Vin」亦大。反之,臨限值電壓Vth 小而接通容易之驅動電晶體Md的情況,「Vth+Vin」亦 小。因而,從驅動電流排除臨限值電壓Vth之偏差的影 響,資料電壓Vin —定時,汲極電流Ids(驅動電流Id)亦一 定。 此外,如在資料抽樣之前,於臨限值修正後進行「移動 率(嚴格而言為驅動力)修正」。 移動率修正係從保持了電壓「Vth+Vin」之狀態,進一 步進行依驅動電晶體Md之電流驅動能力的閘極電位變 化。在驅動電晶體Md之閘極與源極或汲極之間,設藉由 其經由驅動電晶體Md之電流通道的電流而將保持電容器 充電或放電的通路,藉由控制是否在該通路中流入電流來 進行移動率修正,不過圖2及圖3中省略了圖示。 136030.doc -16- 201003590 其後 發光。 有機發光二極體oled被該一 疋之電流值驅動 而 上述移動率修正時之充放電通路的像The source of the Md is connected to the power supply, and the leaf is always set in the saturation region. For this reason, the P-channel type driving transistor Md becomes a steady current source having a value expressed by the formula of FIG. The drain current flowing out of the steady current source is determined by the gate-to-source voltage Vgs having a value of a material potential applied to the gate of the P-channel type driving transistor Md. Therefore, the organic light-emitting diode OLED emits light according to the brightness of the sampled data potential Vsig. As is well known, the organic light-emitting diode OLED changes its characteristics over time, and its j-v characteristics vary as shown in FIG. At this time, since the steady current source wants to flow out the same value of 136030.doc -14-201003590 driving current Id, the applied voltage V of the organic light emitting diode OLED becomes large, and the P-channel type driving transistor Md has a potential of zero. rise. However, since the gate-source voltage Vgs of the P-channel type driving transistor Md is constant, a certain amount of driving current Id flows into the organic light-emitting diode OLED, and the luminance of the light does not change. However, the driving transistor Md is replaced with the N-channel type <pixel circuit 2: Fig. 3>, since the source of the driving transistor Md is connected to the organic light emitting diode OLED, the gate-to-source voltage Vgs and the organic The change in the OLED of the OLED varies with time. Thereby, the driving current Id flowing into the organic light emitting diode OLED changes, and as a result, even if the specified data potential Vsig, the light emitting luminance changes. In addition, since the threshold voltage Vth and the shift rate μ of the driving transistor Md of each pixel circuit are different, a deviation occurs in the drain current Ids according to the formula of FIG. 4, even if the data potential Vsig given is the same, the luminance of the pixel Still changing. Further, in the formula of Fig. 4, the symbol "Ids" indicates the current flowing between the drain and the source of the driving transistor Md which operates in the saturation region. Further, in the drive transistor Md, "Vth" represents a threshold voltage, "μ" represents a mobility, "W" represents an effective channel width (effective gate width), and "L" represents a valid channel length (effective) The gate is very long). Further, "Cox" indicates the sum of the gate capacitance of the drive transistor Md, that is, the sum of the gate oxide film capacitance of each early area and the edge capacitance between the source or drain and the gate. The pixel circuit including the N-channel type body driving transistor Md has the advantage of high driving capability, which simplifies the process. However, in order to suppress the deviation of the threshold voltage Vth 136030.doc •15-201003590 and the mobility μ, it is necessary to The following correction actions are performed before the lighting control operation. <Summary of Correction> The details of the specific control will be described later. Before the sampling, the gate-source voltage Vgs of the driving transistor Md is maintained at the level of the threshold voltage Vth by the holding capacitor Cs. . This preparatory action is referred to as "preventing value correction". After the correction of the threshold value, since the sample voltage Vin after the sampling is applied to the gate of the driving transistor Md, the gate-to-source voltage Vgs is held at "Vth + Vin". The driving transistor Md is turned on according to the magnitude of the data voltage Vin at this time. In the case where the threshold voltage Vth is large and the driving transistor Md is difficult to turn on, "Vth+Vin" is also large. On the other hand, when the threshold voltage Vth is small and the driving transistor Md is easily turned on, "Vth+Vin" is also small. Therefore, the influence of the deviation of the threshold voltage Vth from the drive current is excluded, and the data voltage Vin - timing, the drain current Ids (drive current Id) is also determined. In addition, before the data sampling, the "movement rate (strictly speaking, driving force) correction" is performed after the threshold value is corrected. The movement rate correction further changes the gate potential according to the current driving capability of the driving transistor Md from the state where the voltage "Vth + Vin" is maintained. Between the gate of the driving transistor Md and the source or the drain, a path for charging or discharging the holding capacitor by the current flowing through the current path of the driving transistor Md is provided, by controlling whether or not the path flows in the path The current is corrected for the mobility, but the illustration is omitted in FIGS. 2 and 3. 136030.doc -16- 201003590 followed by illuminating. The OLED OLED is driven by the current value of the 疋, and the image of the charge and discharge path when the mobility is corrected

位)之間驅動驅動電晶體Md2汲極電壓而達成電源驅動。 此外,藉由從寫入訊號掃描電路42供給之寫入驅動脈衝 WS(!)(圖1及圖3之第二掃描訊號vscAN2(i)的脈衝註記)來 進行藉由抽樣電晶體Ms抽樣影像訊號Ssig(資料電位 Vsig)。 〈像素電路3&gt; 圖5中顯示考慮了 素電路2之變形例。 圖解於圖5之像素電路中,係將圖3之連接於驅動電晶體 _的閘極與汲極間之保持電容器。連接於驅動電晶編 之閘極與源極間。其他之結構,圖3與圖5同樣。不過,在 係藉由;^水平像素線驅動電路4 i供給之電源驅動脈衝 DS⑴(圖丨之第—掃描訊號VSCAm⑴之脈衝註記),在高 位準(如高電位Vcc—H)與低位準(低電位Vcc—L,如負電 另外’在 &lt;像素電路3&gt;之電源驅動不限定於該圖示不 過,以下在具體說明動作時,係將圖5之電源驅動方式作 為前提。 &lt;顯示控制之詳細例&gt; 將圖5之電路中的資料寫入時之動作,與臨限值電壓與 移動率之修正動作合併作說明。並將此等一連串動作稱為 「顯不控制」。 圖6(A)〜圖6(F)係顯示顯示控制中之各種訊號及電壓的 136030.doc -17- 201003590 寫入序圖。在此之顯示控制係以列單位依序進行資料 列)广—列之像素電路3(1』係寫入對象之列(顯示 υ ’弟:列之像素電路3(2, υ與第三列之像素電路取』) 6之=點並非寫人對象(係非顯示列)。對顯示列,顯示 於圖6二猎由從此說明之顯示控制寫入了資料後,顯示列 移動至第二列而進行同樣之顯示控制,藉由在第三列、第 四歹J ·:.反覆地進行同樣之顯示控制而顯示1個晝面。】個 畫面顯示後’同樣地必要次數反覆進行其他晝面顯示用之 顯示控制。 圖6(A)係影像訊號Ssig之波形圖。 圖6(m)與圖6(B2)係供給於寫入對象之第一列的寫入驅 動脈衝WS(1)與電源驅動脈衝DS⑴的波形圖。同樣地,圖 6(C1)與圖6(C2)係供給於非寫入對象之第二列的寫入驅動 脈衝WS(2)與電源驅動脈衝仍⑺之波形目,圖石⑼)與圖 (D2)係i、給於非寫入對象之第三列的寫入驅動脈衝ws(3) 與電源驅動脈衝DS(3)之波形圖。 圖6(E)係寫入對象之第一列的像素電路3(1,〗)中之驅動 電晶體Md的閘極電位(控制節點NDc的電位)之波形圖。 圖6(F)係寫入對象之第一列的像素電路3(l, d中之驅動 電晶體Md的源極電位(有機發光二極體〇LED的陽極電位) 之波形圖。 [期間之定義] 如記載於圖6(F)之下部,圖6係對NTSC影像訊號規格之 1個水平期間(1H) ’以其約4倍強之開度(Span)顯示波形 136030.doc -18- 201003590 圖j而後,在其最後之1個水平期間(1H)連續執行最後之 第三次的第三臨限值修正(VTC3)與移動率之修正及實際的 資料寫入〇ν&amp;μ)(主動作)。並^匕費在比其最後⑽水平:間 (1Η)進灯之主動作之前的3個水平期間αΐΗ)χ3),主要用於 初始化,與在最後之臨限值修正時考慮時間短而無法修正 的情況,預先二度進行臨限值修正至某種程度(預備動 如圖6之顯示控制’在顯示圖像之高解像度化進展,顯 示脈衝之驅動頻率非常高的現況下,以短W個水平期間 UH)無法-舉從臨限值電壓修正進行至資料寫人,特別是 有鐘於臨限值修正之時間不足,而將臨限值修正分成數次 來進行。不過’亦有時以驅動頻率不太高之小型至中型的 顯示脈衝等’主動作之時間幻個水平期間(ih)充分時, :了初始預備動作只要有i個水平期間(出)即充分。 〇 备然’預備動作亦可為2個水平期間(2H) ’亦可為4個 期間(4H)以上。 對某列進行主動作0主A , 動作時,就其次之列(及其次以後之 列、·..),因為可並聯地執行預備動作,所以預備動作時 間之長短幾乎不影響全體之顯示期間。然而,著眼 進仃臨限值包壓修正,應該充分地進行預備動作。、 〇以上,係以1個水平期間(1H)的一定尺度觀察之期間的 區分,不過亦可功能性地 草握3己載於圖6(F)之大約4個永 平期間。 \ 具體而t,如記載於圖6(A)之上部’在(ι場或i⑷前晝 136030.doc -19. 201003590 面之發光期間(LM〇)之後,按照時間序列之順戽 Φ如日m 只厅’經過故 K -CHG)、初始化期間(INT)、第—臨限值修正 (vtC1)、第—待機期間(WAT1)、f二臨限值修正期: (VTC2)、第二待機期間(WAT2)而執行「預備動作」。2 外,繼續經過第三臨限值修正(VTC3)、第三待機期= (WAT3)、寫入&amp;移動率修正期間(w&amp;“,轉移至該第一列 之像素電路3(1,j)的發光期間(LM1)來執行「主動作」。 [驅動脈衝之概略] 此外,圖6係在波形圖之適當部位,藉由符號「το〜 「', 」 T21」表示時間顯示。繼續,參照該時間顯示來說明影 像訊號及驅動脈衝之概略。 供給至第一列之寫入驅動脈衝ws(1)如圖6(Βι)所示, 「L」位準係非主動,「H」位準係主動之4個抽樣脈衝 (SP0〜SP3)周期性地出現。此時4個抽樣脈衝(sp〇〜sp3)之 周期通過預備動作(時間το〜時間T15)及主動作(時間τΐ5以 後)係一定。不過,主動作中之寫入驅動脈衝ws(1)成為在 第四個抽樣脈衝(SP3)之後重疊了寫入脈衝(wp)的波形。 對於此’供給至m條(數百〜1千數百條)之影像訊號線 DTL(j)(參照圖1及圖5)的影像訊號ssig於線依序顯示時, 同時供給至m條之影像訊號線DTL(j)。而後,反映將影像 訊號Ssig抽樣後獲得之資料電壓的訊號振幅vin,如圖6(A) 所示’相當於將在1個水平期間(1H)之前半部分反覆出現 的偏移電位(Vo)作為基準之在i個水平期間(1H)的後半部分 反覆出現的影像訊號脈衝(PP)的峰值。以下將訊號振幅 136030.doc -20- 201003590Driving the transistor Md2 with a drain voltage between the bits) to achieve power supply driving. Further, the image is sampled by the sampling transistor Ms by the write driving pulse WS(!) supplied from the write signal scanning circuit 42 (the pulse annotation of the second scanning signal vscAN2(i) of FIGS. 1 and 3). Signal Ssig (data potential Vsig). <Pixel Circuit 3> A modified example in which the pixel circuit 2 is considered is shown in Fig. 5 . Illustrated in the pixel circuit of Fig. 5, the holding capacitor of Fig. 3 is connected between the gate and the drain of the driving transistor. Connected between the gate and source of the drive IC. The other structure is the same as that of FIG. However, the power supply driving pulse DS(1) supplied by the horizontal pixel line driving circuit 4 i (the first pulse of the scanning signal VSCAm (1)) is at a high level (such as a high potential Vcc-H) and a low level ( The low potential Vcc_L, such as negative power, is not limited to the power supply of the <pixel circuit 3>. However, in the following description of the operation, the power supply driving method of Fig. 5 is premised. Detailed Example&gt; The operation of writing the data in the circuit of Fig. 5 is combined with the correction operation of the threshold voltage and the mobility. These series of operations are referred to as "display control". (A) ~ Figure 6 (F) shows the 136030.doc -17- 201003590 write sequence diagram showing various signals and voltages in the control. Here, the display control system performs the data column in order of the column units. The pixel circuit 3 (1) is written in the column of the object (display υ 'di: column pixel circuit 3 (2, 像素 and the pixel circuit of the third column) 6 = the point is not a write object (not displayed) Column). For the display column, shown in Figure 6 two hunting by the display from this description After the control writes the data, the display column moves to the second column to perform the same display control, and the same display control is repeatedly performed in the third column and the fourth frame J::. After the screen is displayed, the display control for the other side display is repeated as many times as necessary. Fig. 6(A) is a waveform diagram of the image signal Ssig. Fig. 6(m) and Fig. 6(B2) are supplied to the write target. The waveforms of the write drive pulse WS(1) and the power drive pulse DS(1) in the first column are similar. Similarly, FIG. 6 (C1) and FIG. 6 (C2) are applied to the second column of the non-write target. The drive pulse WS(2) and the power drive pulse are still (7), the waveform (9) and the diagram (D2) are i, the write drive pulse ws(3) for the third column of the non-write target and the power supply drive Waveform of the pulse DS(3) Fig. 6(E) is a waveform of the gate potential (potential of the control node NDc) of the driving transistor Md in the pixel circuit 3 (1, ???) of the first column of the writing target Fig. 6(F) is the source potential of the driving transistor Md in the pixel column 3 of the first column (the anode of the organic light emitting diode 〇LED) Waveform diagram of [Period definition] As shown in the lower part of Fig. 6 (F), Fig. 6 is the opening period (Span) of the NTSC video signal specification in one horizontal period (1H) Display waveform 136030.doc -18- 201003590 Figure j and then, in the last one horizontal period (1H), the third correction of the third threshold correction (VTC3) and the movement rate and the actual data are continuously executed. Write 〇ν&amp;μ) (main action). And 匕 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在In the case of the last threshold correction, the short-term correction cannot be performed, and the threshold correction is performed to a certain extent in advance (pre-action display control as shown in Fig. 6] progresses in the high resolution of the display image, and the display pulse In the current situation where the driving frequency is very high, in the short W horizontal period UH) can not be lifted from the threshold voltage correction to the data writer, especially if there is insufficient time for the correction of the threshold, and the threshold is The correction is divided into several times. However, in the case of a small-to-medium-sized display pulse such as a driving frequency that is not too high, the time period of the main operation is sufficient (ih): the initial preparatory movement is sufficient as long as i horizontal periods (out) .备 It is also possible that the preparatory action can be two horizontal periods (2H) or four periods (4H) or more. When a main action 0 main A is performed for a certain column, the next step (and subsequent columns, ·..) can be performed in parallel, so the length of the preliminary operation time hardly affects the entire display period. . However, focusing on the threshold pressure correction, the preparatory action should be fully performed. 〇 〇 , , , , , , , , , , , , , , , , , , , , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 \ Specifically, t, as described in the upper part of Figure 6 (A) 'after the ι field or i (4) front 昼 136030.doc -19. 201003590 face illuminating period (LM 〇), according to the time series 戽 Φ 如m hall 'passing K-CHG', initialization period (INT), first-principal correction (vtC1), first-standby period (WAT1), f-second threshold correction period: (VTC2), second standby The "preparatory action" is executed during the period (WAT2). 2, continue to pass the third threshold correction (VTC3), the third standby period = (WAT3), write &amp; mobile rate correction period (w &amp; ", transfer to the pixel circuit 3 of the first column (1, The main operation is performed in the light-emitting period (LM1) of j). [Summary of the drive pulse] In addition, Fig. 6 shows the time display by the symbol "το~", "T21" in the appropriate part of the waveform diagram. Referring to the time display, the outline of the video signal and the drive pulse will be described. The write drive pulse ws(1) supplied to the first column is as shown in Fig. 6 (Βι), and the "L" level is inactive, "H". The four sampling pulses (SP0~SP3) of the active position periodically appear. At this time, the period of four sampling pulses (sp〇~sp3) passes the preparatory action (time το~ time T15) and the main action (after time τΐ5) The write drive pulse ws(1) in the main operation is a waveform in which the write pulse (wp) is superimposed after the fourth sampling pulse (SP3). For this, 'supplied to m (hundreds) ~1 thousand (100) video signal line DTL (j) (refer to Figure 1 and Figure 5) video signal ssig in line order At the same time, it is supplied to the image signal line DTL(j) of m. Then, the signal amplitude vin of the data voltage obtained by sampling the image signal Ssig is reflected, as shown in Fig. 6(A), which is equivalent to 1 The offset potential (Vo) that appears repeatedly in the previous half of the horizontal period (1H) serves as the reference for the peak of the image signal pulse (PP) that appears repeatedly in the second half of the i horizontal period (1H). The signal amplitude is 136030.doc below. -20- 201003590

Vin稱為資料電壓vin。 圖6⑷所示之複數影像訊號脈衝(pp)中,對第一列為重 要之影像訊號脈衝,係與寫入脈衝(wp)時間性重疊之主動 作時的影像訊號脈衝(PPx)。主動作時之影像訊號脈衝 (ppx)來自偏移電位(V。)的峰值,相當於在圖6欲顯示(欲寫 入)之色調值,亦即相當於資料電壓%。該色調值卜㈣ 亦有第-列之各像素為相同的情況(單色顯示之情況),不Vin is called the data voltage vin. In the complex image signal pulse (pp) shown in Fig. 6 (4), the first image is an important image signal pulse, which is an active image signal pulse (PPx) temporally overlapping with the write pulse (wp). The image signal pulse (ppx) at the time of main motion is derived from the peak value of the offset potential (V.), which corresponds to the tone value to be displayed (to be written) in Fig. 6, which is equivalent to the data voltage %. The tone value (4) also has the case where the pixels of the first column are the same (in the case of monochrome display),

過,通常係依顯示像素列之色調值而變化。圖6主要用於 說明在第-列内就!個像素之料,不過同—列之其他像 素’除了有該顯示色調值不同之外,控制本身係與圖示之 像素驅動控制並聯地執行。 供給至驅動電晶體而之汲極(參照圖5)的電源驅動脈衝 抓⑴’如圖6⑽所示,從時間別至最初之第—臨限值修 正期間(vtC1)的開始(時間T6)之前,以非主動之「l」位 準,如以低電位Vcc—L(如貞電壓)保持,在與第一臨限值 修正期間(vtci)之開始大致同時(時間T6),轉移至主動之 「Η」/立準’如轉移至高電位Vcc—Η。高電位Vcc—Η之保 持持續至發光期間(LM1)結束。 .就第一列(之像素電路3(2,』))、第三列(之像素電路3(3, J·)) ’分別如圖6(C1)與圖6(C2)、圖6(〇1)與圖6(D2)所示, 延遲各1個水平期間(1H)施加各脈衝。具體而言,在施加 對應於第-列之第一臨限值修正期間(VTCl)的第二個抽樣 脈衝_之時間T5〜T7的期間,第二列係施加對應於初始 化期間(ΙΝΤ)之第一個抽樣脈衝(Sp〇)。 136030.doc -21 - 201003590 在S亥脈衝施加中途’亦即在時間Τ6,第一列之電源驅動 脈衝DS(1)上升至高位準(高電位Vcc—Η)而成為主動。 其後’在施加對應於第一列之第二臨限值修正期間 (VTC2)的第三個抽樣脈衝(sp2)之時間T1〇〜Τ12的期間,第 二列係從第一列延遲1個水平期間(1Η),而施加上述第二 個抽樣脈衝(SP1),第三列係從第一列延遲2個水平周期 ((1Η)χ2),而施加上述第一個抽樣脈衝(Sp〇)。 在該脈衝施加中途,亦即在時間T1丨,第二列之電源驅 動脈衝DS(2)上升至高位準(高電位Vcc 一 H)而成為主動。 其後,在施加對應於第一列之第三臨限值修正期間 (VTC3)的第四個抽樣脈衝(sp3)之時間丁15〜丁丨7的期間,第However, it usually changes depending on the tone value of the display pixel column. Figure 6 is mainly used to illustrate in the first column! The pixel material, but the other pixels of the same column, are controlled in parallel with the pixel driving control shown in the figure except that the display tone value is different. The power supply pulse grab (1)' supplied to the drain of the drive transistor (see Fig. 5) is as shown in Fig. 6 (10), from the time until the start of the first-then-edge correction period (vtC1) (time T6) , in the unactive "l" level, if maintained at a low potential Vcc-L (such as 贞 voltage), at approximately the same time as the beginning of the first threshold correction period (vtci) (time T6), transfer to active "Η"/立准' as transferred to high potential Vcc-Η. The high potential Vcc-Η remains until the end of the illuminating period (LM1). For the first column (pixel circuit 3 (2, 』)), the third column (pixel circuit 3 (3, J ·)) ' as shown in Figure 6 (C1) and Figure 6 (C2), Figure 6 ( 〇1) As shown in Fig. 6 (D2), each pulse is applied for one horizontal period (1H). Specifically, during the period T5 to T7 at which the second sampling pulse _ corresponding to the first threshold correction period (VTCl) of the first column is applied, the second column is applied corresponding to the initialization period (ΙΝΤ). The first sample pulse (Sp〇). 136030.doc -21 - 201003590 In the middle of the application of the pulse of Shai, that is, at time Τ6, the power-drive pulse DS(1) of the first column rises to a high level (high potential Vcc-Η) and becomes active. Thereafter, during the period T1〇 to Τ12 of the third sampling pulse (sp2) corresponding to the second threshold correction period (VTC2) of the first column, the second column is delayed by one from the first column. During the horizontal period (1Η), the second sampling pulse (SP1) is applied, and the third column is delayed by 2 horizontal periods ((1Η)χ2) from the first column, and the first sampling pulse (Sp〇) is applied. . In the middle of the pulse application, i.e., at time T1, the power drive pulse DS(2) of the second column rises to a high level (high potential Vcc - H) and becomes active. Thereafter, during the period of applying the fourth sampling pulse (sp3) corresponding to the third threshold correction period (VTC3) of the first column, the period from 1515 to 丨7,

動脈衝卿)上升至高位準(高電位IDynamic pulse) rises to a high level (high potential I

&gt; 丨八奶咖丨队世电澄修正 期間的時間短達可忽略之程 修正分成數次,實質地不產 136030.doc -22. 201003590 生時間性之損失。 其次’就顯示於圖6(A)之各期間,說明在以上之脈衝控 制下的顯示於圖6(E)及圖6(F)之驅動電晶體Md的源極及閘 極之電位變化與伴隨其之動作。 另外在此適宜參照圖7(A)〜圖9(B)所示之第一列的像 素電路3(1,j)之預備動作說明圖,圖1〇所示之源極電位 ^夺間推移圖形’圖丨丨(A)〜圖丨丨(c)所示之第一列的像素 電路3(1,j)之主動作說明圖以及圖5等。 [前畫面之發光期間(LM0)] 就第一列之像素電路3(1,』),就時間丁〇以前之1場或1幀 程度之前的晝面(以下稱為前晝面)之發光期間(LM0),如 圖6(B1)所示,因為寫入驅動脈衝ws⑴係「l」位準,所 以抽樣電晶體Ms斷開。此外’如圖6(B2)所示,電源驅動 脈衝DS⑴在高電位Vcc—H之施加狀態。 Ν'》圖7(A)所不’依藉由前晝面之資料寫入動作而 輸入保持於驅動雷旦辨日日t 呢勒电日日肢Md之閘極的資料電壓Vin〇,有機 發先一極體〇LED在發光狀態。因為驅動電晶體㈣設定成 ::和區域動作,所以流入有機發光二極體〇咖之驅動 屯机Id(-Ids)依保持於保持電容 器Cs之驅動電晶體Md的閘 極源極間電壓v g s,而敌此 gS而取Μ迷圖4所示之公式算出的值。 L放電期間(D-CHG);] 圖6中,從時間丁〇起 , 顯示之處理。 1始關於線依序掃描之新的畫面 為寺間Τ〇0”水平像素線驅動電路4!(參照圖5)如圖 136〇3〇,d〇c •23· 201003590 6(B2)所示地將電源驅動脈衝DS(1)從高電位Vcc_H切換至 低電位Vcc_ L。驅動電晶體Md因為在此之前作為汲極功 能之節點的電位急遽地掉落至低電位Vcc_L,源極與汲極 之電位逆轉,所以將在此之前係汲極之節點作為源極,並 將在此之前係源極之節點作為汲極,而進行抽出該汲極電 位(不過,圖中之註記仍然為源極電位Vs)的放電動作。 因此,如圖7(B)所示,與在此之前反向之汲極電流Ids流 入驅動電晶體Md。 將在該驅動電晶體M d中流入反向電流的期間’在圖6係 註記為「放電期間(D-CHG)」。 開始放電期間(D-CHG)時,如圖6(F)所示,將時間T0作 為邊界,而將驅動電晶體Md之源極電位Vs(實際之動作上 係汲極電位)急遽地放電,而降低至大致低電位Vcc_ L附 近。 此時,低電位Vcc— L比有機發光二極體OLED之臨限值 電壓Vth_oled.與陰極電位Vcath之和小時,換言之,係 「Vcc_L&lt;Vth—oled. + Vcath」時,有機發光二極體 OLED 消 光。 另外,在放電期間(D-CHG)結束(時間T1)之前,如圖 6(A)所示,影像訊號Ssig之電位從資料電位Vsig下降至資 料基準電位Vo。 在時間T0,如圖7(B)所示,抽樣電晶體Ms斷開,控制節 點NDc在漂浮狀態。因而如圖6(E)所示,以時間T0為邊 界,驅動電晶體Md之閘極電壓Vg降低。 136030.doc -24· 201003590 [初始化期間(ΙΝΤ)] 其次’寫入訊號掃描電路42(參照圖5)如圖6(Β1)所禾, 在時間τι,使寫入驅動脈衝ws(1)&amp;「L」位準轉移至 H」位準,而將第一個抽樣脈衝(SP〇)給予抽樣電晶體ms 之閘極。 在該時間T1,放電期間(D_CHG)結束,初始化期間 ' (INT)從此開始。 () 回應在時間T1之抽樣脈衝(SP0)的施加,如圖7(C)所 示,抽樣電晶體Ms接通。如前述,在到達時間T1時,影 像訊號Ssig之電位切換成資料基準電位v〇。因此,抽樣電 晶體Ms抽樣影像訊號Ssig之資料基準電位Vo,並將抽樣後 之貝料基準電位v〇傳達至驅動電晶體Md之閘極。 藉由該抽樣動作,如圖6(E)所示,時間τ〇為邊界而降低 之驅動電晶體Md的閘極電壓Vg收斂成資料基準電位v〇。 圖6(B1)所示之抽樣脈衝(Sp〇)從時間Tl,該電位收斂 (J 時,在經過充分時間之時間T2結束,抽樣電晶體吣斷 開。因而’其次到抽樣電晶體Ms接通之時間T5,驅動電 晶體Md之閘極成為電性漂浮狀態。 在該時間T5,使抽樣電晶體Ms再度接通之時序,係以 控制成與最初之丨個水平期間(1H)的結束大致相同,且在 時間T2〜T5之期間内,容納該}個水平期間(1H)中之影像訊 號脈衝(pp)的方式設計時序(參照圖6(A)與(Bi))。 k抽樣脈衝(SP〇)觀察此時,將寫入驅動脈衝ws(1)形成 H」位準之抽樣脈衝(sp〇)的持續時間(時間τι〜τ2)成為1 136030.doc -25· 201003590 個水平期間(1H)之前半部分的影像訊號Ssig取資料基準電 位Vo之期間(時間το〜T3)内。 而後,在時間丁2,使抽樣電晶體Ms斷開狀態下,等待 〜像Λ 5虎線DTL(j)之電位藉由影像訊號脈衝(pp)而偏差結 束的時間T4之經過’在其後之時間T5,將再度抽樣資料基 準電位Vo用之第二個抽樣脈衝(spi)上升。 土 該控制之結果,在將第二個抽樣脈衝(spi)上升之時間 T5,避免錯誤地抽樣影像訊號Ssig之資料電位vsig。曰 另外,在時間T5中之第二次之抽樣開 _ ---- ^ ^ 不’閘極電壓Vg已經保持有資料基準電位%。因此, j有藉由第2次抽樣補償漏電流等之微小損失,一般 言,閘極電壓Vg幾乎不偏差。 又 將時間軸上之說明向前返回若干時,在時間丁丨,藉由 加第一個抽樣脈衝(SP〇),抽樣電晶體Ms接通,如圖6( ’驅動電晶體Md之閘極電壓Vg收斂成資料基準電 「〇時’保持電容器CS之保持電壓與其連動而降低,成 位:0 Vcc—Lj (圖6(F))。此因藉由圖7(B)之放電,源極 形成低電位Vcc-L,而以低電位Vcc—L為基準之 極電壓Vg規定保持電容器。之保持電壓。換令: ,)中,閉極電麼Vg下降至資料基準電位v。時:保持電 ^CS之保持電壓與其連動而、 「V0-Vcc乙。s ^ 、 孩保持電壓收斂 —」另外,因為該保持電壓「% 一 閘極源極間電愿v C~L」就 體Md之”:: 原極間電壓%不比驅動電 …值電壓她大時’在其後無法進行臨限值修. 136030.doc -26- 201003590 動作,所以係以成為「Vo-Vcc_L&gt;Vth」之方式決定電位關 係。 因而’猎由將驅動電晶體M d之閘極電壓V g及源極電位 Vs初始化,臨限值修正動作之準備完成。 [第一臨限值修正期間(VTC1)] 在時間T5,抽樣電晶體Ms開始第二次之Vo抽樣後,如 圖6(B2)所示,在時間T6,電源驅動脈衝DS(1)從VSS位準 上升至VDD位準時,該初始化期間(INT)結束,第一臨限 值修正期間(VTC1)開始。 在第一臨限值修正期間(VTC1)開始時(時間T6)之前,因 為接通狀態之抽樣電晶體Ms抽樣資料基準電位Vo中,所 以驅動電晶體Md之閘極電壓Vg在以一定之資料基準電位 Vo而電性固定的狀態。 該狀態下,在時間T6,水平像素線驅動電路41(參照圖 5)如圖6(B2)所示,將電源驅動脈衝DS(1)從「L」位準 (=VSS)上升至「H」位準(=VDD)。水平像素線驅動電路41 在時間T6以後,於其次幀(或是場)的處理開始前,預先將 對驅動電晶體M d之電源供給線的電位保持在南電位V c c_ Η。 藉由電源驅動脈衝D S (1)之啟動,而在驅動電晶體Md之 源極與汲極間施加「VDD-VSS」之電壓。因而,汲極電流 Ids從電源流至驅動電晶體Md。 措由沒極電流I d s將驅動電晶體M d之源極充電’如圖 6(F)所示,因為源極電位Vs上昇,之前取「Vo-Vcc_L」之 136030.doc -27- 201003590 值的驅動電晶體Md之閘極源極間電壓Vgs(保持電容器Cs 之保持電壓)逐漸變小(圖6(E)及(F))。 此時驅動電晶體Md藉由汲極電流Ids之源極充電速度不 太大。參照圖8(A)敘述其理由。 如圖8 (A)所不 *以貢料基準電位Vo規定施加於驅動電晶 體Md之閘極電壓Vg的閘極偏壓電位,因為該偏壓電位不 太大,所以驅動電晶體Md以淺接通狀態,亦即以驅動能 力不太大之狀態接通(第一理由)。 此外,雖汲極電流Ids流入保持電容器Cs,不過,因為 有機發光二極體OLED之電容Coled.的充電亦消耗汲極電 流Ids,所以源極電位Vs不易提高(第二理由)。 進一步,因為需要使抽樣脈衝(SP1)在比其次影像訊號 Ssig轉移為資料電位Vsig之時間T8之前的時間T7結束(參照 圖6(B 1)),所以源極電位Vs之充電時間不充分(第三理 由)。 若圖6(B1)所示之第二個抽樣脈衝(SP1)可超過時間T7而 充分長地持續時,如圖1 〇所示,驅動電晶體Md之源極電 位Vs(有機發光二極體OLED之陽極電位)係將時間T6作為 起點而與時間一起上昇,並以「Vo-Vth」收斂(藉由圖1 0 之虛線顯示的曲線CV)。換言之,應該在閘極源極間電壓 Vgs(保持電容器Cs之保持電壓)正好成為驅動電晶體Md之 臨限值電壓Vth之處,源極電位Vs的上昇大致結束。 [第一待機期間(WAT1)] 但是實際上,因為時間T7係在到達其收斂點之前,所以 136030.doc -28- 201003590 抽樣脈衝(SP1)之持續時間結束,藉此,第—臨限值 期間(VTC1)結束’ *第—待機期間(wati)開始。* 具體而言,驅動電晶體Md之間極源極間電 Vxl(&gt;vth)時,換5之,如圖1〇所示’在驅動電晶體则^ 源極電位Vs從低電位Vcc—L上昇至「ν〇_νχΐ」的 間限值修正期間(VTC1)結束。此時(時間 T7),將電壓值Vxl保持於保持電容器a。&gt; 丨 奶 丨 丨 世 世 世 世 修正 修正 修正 修正 修正 修正 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 136 Next, it is shown in each period of FIG. 6(A), and the potential changes of the source and the gate of the driving transistor Md shown in FIG. 6(E) and FIG. 6(F) under the above pulse control are explained. Accompanied by its actions. Further, it is preferable to refer to the preliminary operation explanatory diagram of the pixel circuit 3 (1, j) in the first column shown in FIGS. 7(A) to 9(B), and the source potential transition shown in FIG. The main operation explanatory diagram of the pixel circuit 3 (1, j) in the first column shown in the figure 'A' to (c) is shown in FIG. 5 and the like. [Light-emitting period of the front screen (LM0)] The pixel circuit 3 (1, 』) of the first column is the luminescence of the front surface (hereinafter referred to as the front surface) before the time of one field or one frame. In the period (LM0), as shown in Fig. 6 (B1), since the write drive pulse ws(1) is at the "1" level, the sampling transistor Ms is turned off. Further, as shown in Fig. 6 (B2), the power supply driving pulse DS(1) is applied at a high potential Vcc - H. Ν'》Fig. 7(A) does not rely on the data writing action of the front side to input the data voltage that keeps driving the gate of the dynasty Md. The first LED is in the state of illumination. Since the driving transistor (4) is set to :: and the area operation, the driving device Id (-Ids) flowing into the organic light emitting diode is connected to the gate source voltage vgs of the driving transistor Md held by the holding capacitor Cs. And the enemy gS takes the value calculated by the formula shown in Fig. 4. L discharge period (D-CHG);] In Fig. 6, the processing is shown from time to time. 1 The new screen for the sequential scan of the line is the Τ〇0” horizontal pixel line drive circuit 4! (see Fig. 5) as shown in Fig. 136〇3〇, d〇c • 23· 201003590 6(B2) The power drive pulse DS(1) is switched from the high potential Vcc_H to the low potential Vcc_L. The drive transistor Md is dropped sharply to the low potential Vcc_L, the source and the drain due to the potential of the node which is the function of the drain before. The potential is reversed, so the node of the drain is used as the source before, and the node of the source is used as the drain before, and the drain potential is extracted (however, the note in the figure is still the source). Therefore, as shown in Fig. 7(B), the drain current Ids which is reversed beforehand flows into the driving transistor Md. During the period in which the reverse current flows in the driving transistor Md 'In Figure 6, the note is "Discharge Period (D-CHG)". When the discharge period (D-CHG) is started, as shown in FIG. 6(F), the time T0 is set as a boundary, and the source potential Vs of the driving transistor Md (actually operating the gate potential) is rapidly discharged. It is reduced to approximately the vicinity of the low potential Vcc_L. At this time, the low potential Vcc-L is smaller than the sum of the threshold voltage Vth_oled. of the organic light emitting diode OLED and the cathode potential Vcath, in other words, the "Vcc_L&lt;Vth_oled. + Vcath", the organic light emitting diode OLED extinction. Further, before the end of the discharge period (D-CHG) (time T1), as shown in Fig. 6(A), the potential of the video signal Ssig falls from the data potential Vsig to the data reference potential Vo. At time T0, as shown in Fig. 7(B), the sampling transistor Ms is turned off, and the control node NDc is in a floating state. Therefore, as shown in Fig. 6(E), with the time T0 as the boundary, the gate voltage Vg of the driving transistor Md is lowered. 136030.doc -24· 201003590 [Initialization period (ΙΝΤ)] Next, the write signal scanning circuit 42 (refer to FIG. 5) is as shown in FIG. 6 (Β1), and at time τ, the write drive pulse ws(1)&amp; The "L" level is transferred to the H" level, and the first sampling pulse (SP〇) is given to the gate of the sampling transistor ms. At this time T1, the discharge period (D_CHG) ends, and the initialization period '(INT) starts from here. () In response to the application of the sampling pulse (SP0) at time T1, as shown in Fig. 7(C), the sampling transistor Ms is turned on. As described above, at the time T1 of arrival, the potential of the image signal Ssig is switched to the reference potential v〇. Therefore, the sampling transistor Ms samples the data reference potential Vo of the image signal Ssig, and transmits the sampled reference potential v 抽样 to the gate of the driving transistor Md. By this sampling operation, as shown in Fig. 6(E), the gate voltage Vg of the driving transistor Md which is lowered by the time τ 〇 is converged to the data reference potential v 。. The sampling pulse (Sp 〇) shown in Fig. 6 (B1) converges from the time T1, and the potential converges (J, when the time T2 elapses for a sufficient time, the sampling transistor 吣 is turned off. Thus, 'Secondly, the sampling transistor Ms is connected. At the time T5, the gate of the driving transistor Md becomes electrically floating. At this time T5, the timing at which the sampling transistor Ms is turned on again is controlled to be the end of the first horizontal period (1H). The timing is basically the same, and the timing of the image signal pulse (pp) in the horizontal period (1H) is accommodated during the period of time T2 to T5 (refer to FIGS. 6(A) and (Bi)). k sampling pulse (SP〇) Observe that at this time, the duration (time τι~τ2) of the sampling pulse (sp〇) at which the write drive pulse ws(1) forms the H" level becomes 1 136030.doc -25· 201003590 horizontal periods (1H) The image signal Ssig of the previous half is taken during the period of the reference potential potential Vo (time το~T3). Then, at time D, the sampling transistor Ms is turned off, waiting for ~ Λ 5 tiger line DTL (j) The potential of the time T4 after the end of the deviation by the image signal pulse (pp) At a later time T5, the second sampling pulse (spi) of the resampled data reference potential Vo is raised by the second sampling pulse (spi) of the soil. The result of the control is to avoid the erroneous sampling at the time T5 when the second sampling pulse (spi) is raised. The signal potential of the image signal Ssig is vsig. In addition, the second sampling in time T5 is _ ---- ^ ^ No. The gate voltage Vg has been kept at the reference potential of the data. Therefore, j has The second sampling compensates for the small loss of leakage current, etc. Generally speaking, the gate voltage Vg is hardly deviated. When the description on the time axis is returned forward a few times, at the time, by adding the first sampling pulse (SP) 〇), the sampling transistor Ms is turned on, as shown in Fig. 6 ('The gate voltage Vg of the driving transistor Md converges to the data reference voltage "When the voltage is held, the holding voltage of the capacitor CS is reduced in conjunction with it, in place: 0 Vcc - Lj (Fig. 6(F)). Because of the discharge of Fig. 7(B), the source forms a low potential Vcc-L, and the pole voltage Vg with reference to the low potential Vcc-L defines a holding capacitor. Change order: ,), when the pole is closed, Vg drops to the data reference potential v. : Keep the holding voltage of the electric ^CS in conjunction with it, "V0-Vcc B.s ^, the child keeps the voltage converging—" In addition, because the holding voltage "%, the gate source and the electric source are willing to v C~L" Md":: The voltage between the primary poles is not higher than the driving voltage... When the voltage is large, she can't carry out the threshold repair afterwards. 136030.doc -26- 201003590 Action, so it becomes "Vo-Vcc_L&gt;Vth" The way to determine the potential relationship. Therefore, the hunting is completed by the gate voltage V g and the source potential Vs of the driving transistor M d , and the preparation of the threshold correction operation is completed. [First threshold correction period (VTC1)] After the sampling transistor Ms starts the second Vo sampling at time T5, as shown in Fig. 6 (B2), at time T6, the power supply driving pulse DS(1) is from When the VSS level rises to the VDD level, the initialization period (INT) ends and the first threshold correction period (VTC1) starts. Before the start of the first threshold correction period (VTC1) (time T6), since the sampling transistor Ms in the on state samples the reference potential Vo in the data, the gate voltage Vg of the driving transistor Md is in a certain data. A state in which the reference potential Vo is electrically fixed. In this state, at time T6, the horizontal pixel line drive circuit 41 (see FIG. 5) raises the power supply drive pulse DS(1) from the "L" level (=VSS) to "H" as shown in FIG. 6(B2). Level (=VDD). The horizontal pixel line drive circuit 41 maintains the potential of the power supply line for driving the transistor M d at the south potential V c c — 预先 before time T6 and before the start of the processing of the next frame (or field). A voltage of "VDD-VSS" is applied between the source and the drain of the driving transistor Md by the start of the power supply driving pulse D S (1). Thus, the drain current Ids flows from the power source to the driving transistor Md. The source of the driving transistor M d is charged by the immersion current I ds as shown in Fig. 6(F). Since the source potential Vs rises, the value of 136030.doc -27- 201003590 of "Vo-Vcc_L" is taken before. The gate-source voltage Vgs of the driving transistor Md (the holding voltage of the holding capacitor Cs) gradually becomes smaller (FIG. 6(E) and (F)). At this time, the source charging speed of the driving transistor Md by the drain current Ids is not too large. The reason will be described with reference to Fig. 8(A). As shown in FIG. 8(A), the gate bias potential applied to the gate voltage Vg of the driving transistor Md is defined by the reference potential potential Vo, and since the bias potential is not too large, the transistor Md is driven. It is turned on in a shallow on state, that is, in a state in which the driving ability is not too large (first reason). Further, although the drain current Ids flows into the holding capacitor Cs, since the charging of the capacitor Coled. of the organic light emitting diode OLED also consumes the drain current Ids, the source potential Vs is not easily improved (second reason). Further, since it is necessary to terminate the sampling pulse (SP1) at a time T7 before the time T8 when the next image signal Ssig is shifted to the data potential Vsig (refer to FIG. 6 (B1)), the charging time of the source potential Vs is insufficient ( The third reason). If the second sampling pulse (SP1) shown in FIG. 6(B1) can continue for a sufficient length of time beyond the time T7, as shown in FIG. 1A, the source potential Vs of the driving transistor Md (organic light-emitting diode) The anode potential of the OLED is raised with time as the starting point of time T6, and converges with "Vo-Vth" (curve CV shown by the broken line of Fig. 10). In other words, the rise of the source potential Vs is substantially completed when the gate-to-source voltage Vgs (the holding voltage of the holding capacitor Cs) is just at the threshold voltage Vth of the driving transistor Md. [First Standby Period (WAT1)] But in reality, since time T7 is before reaching its convergence point, the duration of 136030.doc -28- 201003590 sampling pulse (SP1) ends, whereby the first threshold The period (VTC1) ends '*The first-standby period (wati) starts. * Specifically, when driving the inter-electrode-to-source Vxl (&gt;vth) between the transistors Md, change 5, as shown in Figure 1A. 'When driving the transistor, the source potential Vs is from the low potential Vcc- L increases to the interval value correction period (VTC1) of "ν〇_νχΐ". At this time (time T7), the voltage value Vx1 is held in the holding capacitor a.

第一臨限值修正期間(VTr】、έ士 )、、、°束呀,因為抽樣電晶體The first threshold correction period (VTr), gentleman), ,, ° beam, because the sampling transistor

Ms斷開,所以驅動電晶體咖之間極從以資料基準電位% 而電性固定之狀態推移至電性漂浮狀態。 二::夺間T7以後,源極電位Vs上昇時,電容結合於源 的閘極之電位(Vg)亦伴隨其而上昇(圖6⑻盘 2。結果,本例在第—待機期間(WAT1)之結束時點(時間 τ⑼’源極電位Vs比收叙目標之「v〇_Vth」大(參照圖 )另外,如圖6(E)及(F)所示,閘極源極間電壓Vgs不縮 於A兩待機期間(WAT1)與之前說明的初始化期間(聰)同 :’「需要等待影像訊號脈衝(PP)之通過,並以其含意而稱 ::機期間」。但是,時間T7〜T1。之比較長的待機期間 甲極電壓Vg之上昇’此外如上述,閘極源極間電壓 gS不進行向臨限值電壓Vth之收斂。 '、u「Val」表示閘極電壓Vg在第一待機期間 (WA11)中之l曰 結人带_ 幵。卩分。另外,亦以「Val」相同作為經由 ! '、持電谷器Cs)之成為藉由自舉(bootstrap)動作 136030.doc -29· 201003590 引起該閘極電壓Vg之上昇的原因之源極電位Vs的上昇部 分時,源極電位Vs在第一待機期間(WAT1)之結束時點(時 間 T10)成為「Vo-Vxl+Val」(參照圖 8(B))。 因而,需要將閘極電位返回初始化位準之資料基準電位 Vo,並且再度進行臨限值修正。 [第二臨限值修正期間(VTC2)] 因此,本實施形態之動作例,在其次之1個水平期間 (1H)(時間T10〜T15),係進行與在之前的1個水平期間 (1H)(時間T5〜T10)進行之第一臨限值修正期間(VTC1)與第 一待機期間(WAT1)同樣之處理,亦即係執行第二臨限值修 正期間(VTC2)與第二待機期間(WAT2)。 不過,在開始第一臨限值修正期間(VTC1)之時間T5, 閘極源極間電壓V g s (保持電容器C s之保持電壓)係「Vo _ Vcc—L」的比較大之值,而在開始第二臨限值修正期間 (VTC2)之時間T10,該保持電壓縮小成更小之「Vxl」。 如圖6(B1)所示,在時間T10,抽樣脈衝(SP2)上升而抽 樣電晶體Ms接通時,驅動電晶體Md之閘極電壓Vg( = 「Vo+Val」)連接於更低電位(Vo)之影像訊號線DTL(j)。 因而’相當於其差分(Val)之電流從驅動電晶體Md之閘極 流入影像訊號線DTL(j),如圖8(C)所示,將閘極電壓Vg強 制性下降至資料基準電位Vo。 該驅動電晶體M d之閘極中的電位(Va 1)偏差經由保持電 容器Cs及驅動電晶體Md之閘極源極間寄生電容Cgs而輸入 驅動電晶體Md之源極,而將源極電位Vs拉下。 136030.doc -30- 201003590 此時之源極電位Vs的拉下量,使用電容結合比g,而表 示為「g*Val」。在此,電容結合比g使用上述閘極源極間 寄生電容Cgs、與保持電容器Cs同一符號之其電容值 (Cs)、有機發光二極體OLED之電容Coled.,而表示為 g=(Cgs + Cs)/(Cgs+Cs+Coled.)。因而,源極電位 Vs係從之 前的「Vo-Vxl+Val」降低「g*Val」程度,而成為「¥〇-Vx 1 ( 1 -g)Va 1」。 因為電容結合比g為了從定義式能明暸而取比1小之值, 所以源極電位Vs之變化量「g*Val」比閘極電壓Vg之變化 量(Val)小。 在此5驅動電晶體之問極源極間電堡Vgs(=「Vxl-(1_ g)Val」)比驅動電晶體Md之臨限值電壓Vth大時,如圖 8(C)所示,汲極電流Ids流動。沒極電流Ids要流動至驅動 電晶體Md之源極電位Vs成為「Vo-Vth」,驅動電晶體Md切 斷。但是,本實施形態之動作例如圖6(E)及(F)所示,因為 在閘極源極間電壓Vgs成為「Vx2」(其中,Vx2含有滿足 Vxl&gt;Vx2&gt;Vth之大小)的時間T12,抽樣脈衝(SP2)結束,所 以抽樣電晶體Ms斷開。在時間T12之保持電容器Cs的保持 電壓係「Vx2」。 [第二待機期間(WAT2)] 第二待機期間(WAT2)從時間T12開始。 第二待機期間(WAT2)係與前次之第一待機期間(WAT1) 同樣地,因為抽樣電晶體Ms斷開,閘極電壓Vg成為電性 漂浮狀態,所以閘極電壓Vg亦依源極電位Vs之上昇而上 136030.doc •31 · 201003590 昇(參照圖9(A))。 但疋,閘極電廢Vg之電位上昇效果(自舉效果)因為盆開 始時點之閘極源極間電壓Vgs接近控制目標「杨」所以不 太大’而如圖6⑻及圖6(F)之時間Tl2〜T15所見,源極電 位Vs及閘極電壓Vg之電位上昇幅度很少。 u更弟、田而° ’在圖9(A)之第二待機期間(WAT2) ’因沒極 電流1^流動而源極電位…之上昇部分為「Va2」時,在待 機期間結束時(圖6之時間T15)源極電位力成為「v〇_ 化遏2」。該源極電位上昇ί程度經由問極源極間 寄生電容Cgs及料電容⑽而傳達至漂浮狀態的問極, 結果開極電壓〜亦上昇相同電位Ί程度。不過,如 圖6(E)所示’閉極電塵々之電位上昇部分「Va2」遠比在 第二待機期間(WAT1)之電位上昇部分「㈤」小。 [弟二缸限值修正(VTC3)] 從時間T15進入「主動作 始0 第三臨限值修正(VTC3)開 第三臨限值修正(VTC3)(時間Τ1 5〜τι 7)係執行與第二臨 限值修正期間(VTC2)同樣之處理。 不過在開始第二臨限值修正期間(VTC2)之時間Τ10, 1和、原極間電壓Vgs(保持電容器Cs之保持電壓)為m」 大的值,而在開始第三臨限值修正期間(VTC3)之時 間T15,縮小至更小的「Vx2」。 ;土本之動作為r第二臨限值修正期間2)」之反 匕不sw。「第二臨限值修正期間(VTC2)」之說 136030.doc •32- 201003590 明,藉由將「Val」替換成「Va2」,將「Vxl」替換成 「Vx2」,即可適用於該第三臨限值修正(VTC3)。此從圖 8(C)與圖9(B)之對比即可明瞭。 不過,與第二臨限值修正期間(VTC2)不同的是,在第三 臨限值修正(VTC3)結束之時間T17前,如圖6(E)及圖6(F) 所示,驅動電晶體Md之閘極源極間電壓Vgs(保持電容器 Cs之保持電壓)與臨限值電壓Vth相等。因而,驅動電晶體 Md在閘極源極間電壓Vgs與臨限值電壓Vth相等之處切 斷,其以後,汲極電流Ids不流動。此時之驅動電晶體Md 的源極電位Vs係「Vo-Vth」。 如以上所述,藉由包含將待機期間夾在中間之數次(本 例係3次)的臨限值電壓修正,保持電容器Cs之保持電壓將 其為一定之待機期間夾在中間收斂成階梯狀,最後成為臨 限值電壓Vth。 在此,若驅動電晶體之閘極源極間電壓變大了「Vin」 程度時,閘極源極間電壓成為「Vin+Vth」。此外,考慮臨 限值電壓Vth大之驅動電晶體與其小之驅動電晶體。 前者之臨限值電壓Vth大的驅動電晶體,閘極源極間電 壓大達臨限值電壓Vth大的部分程度,反之,臨限值電壓 Vth小之驅動電晶體,因為臨限值電壓Vth小所以閘極源極 間電壓變小。因而,就臨限值電壓Vth而言,藉由臨限值 電壓修正動作取消其偏差,為相同資料電壓Vin時,可將 相同〉及極電流I d s流入驅動電晶體。 另外,在包含3次之臨限值修正期間,亦即在第一臨限 136030.doc -33- 201003590 值修正期間(VTCl)、第二臨限值修正期間(VTC2)及第三 臨限值修正(VTC3)中,需要汲極電流Ids主要僅在流入保 持電容器Cs之一方電極側、有機發光二極體OLED之電容 Coled.的一方電極側時消耗,而有機發光二極體OLED不 接通。將有機發光二極體OLED之陽極電壓註記為 「Voled.」,將其臨限值電壓註記為「Vth_oled.」,將其陰 極電位註記為「Vcath」時,將有機發光二極體OLED維持 在斷開狀態之條件係「Voled. S Vcath+Vth—oled.」始終成 立。 在此,將有機發光二極體OLED之陰極電位Vcath保持在 低電位Vcc — L(如接地電壓GND)的情況,臨限值電壓 Vth_oled.非常大時,亦可使該公式始終成立。但是,臨限 值電壓Vth_oled.由有機發光二極體OLED之製作條件來決 定,此外,為了以低電壓有效率地發光,無法使臨限值電 壓Vth_oled.太大。因而應該在3個臨限值修正期間及其次 敘述之移動率修正期間結束前,藉由將陰極電位Vcath設 定成比低電位Vcc— L大,而使有機發光二極體OLED預先 反偏壓電位即可。 [第三待機期間(WAT3)] 以上係就臨限值電壓修正作說明,不過本動作例繼續是 「寫入&amp;移動率修正」用之待機期間(第三待機期間 (WAT3))開始。第三待機期間(WAT3)與這之前的臨限值電 壓修正用之第一待機期間(WAT1)及第二待機期間(WAT2) 不同,僅係在其後進行之「寫入&amp;移動率修正」時,不致 136030.doc -34- 201003590 電位變化不穩定的部位而待機的 錯誤抽樣影像訊號Ssig之 短暫待機期間。 〖如圖6(m)所示’在時間T17,抽樣脈衝卿)從位 準轉移至「L」位準時’第三待機期間(WAT3)從此開始。 _第三待機期間(WAT3)在其中途的時間τΐ8,如圖6(a)所 不,具有應以該像素電路3(1, υ顯示之資料電位—的影 像訊號脈衝(PPx)’作為影像訊號吨而供給至影像訊號線Since Ms is disconnected, the poles between the driving and the crystal coffee are switched from the state in which the data reference potential is electrically fixed to the electrically floating state. 2: After the T7 is tapped, when the source potential Vs rises, the potential (Vg) of the gate coupled to the source rises with it (Fig. 6(8), disk 2. As a result, this example is in the first-standby period (WAT1). At the end point (time τ(9)', the source potential Vs is larger than the "v〇_Vth" of the target (see figure). In addition, as shown in Figs. 6(E) and (F), the gate-to-source voltage Vgs is not The two standby periods (WAT1) are the same as the previously described initialization period (Cong): 'There is a need to wait for the passage of the image signal pulse (PP), and it is called ": machine period". However, time T7~ T1. The rise of the gate voltage Vg during the relatively long standby period. Further, as described above, the gate-to-source voltage gS does not converge toward the threshold voltage Vth. ', u "Val" indicates that the gate voltage Vg is at the In the standby period (WA11), the 曰 曰 带 带 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Val 。 Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val Val. Doc -29· 201003590 When the source potential Vs rises due to the rise of the gate voltage Vg, the source potential Vs is at the first At the end of the machine period (WAT1) (time T10), it becomes "Vo-Vxl+Val" (refer to Fig. 8(B)). Therefore, it is necessary to return the gate potential to the data reference potential Vo of the initializing level, and again. [Second threshold correction period (VTC2)] Therefore, in the second horizontal period (1H) (time T10 to T15), the previous operation is performed. The first margin correction period (VTC1) performed during the horizontal period (1H) (times T5 to T10) is the same as the first standby period (WAT1), that is, the second threshold correction period (VTC2) is executed. The second standby period (WAT2). However, at the time T5 at which the first threshold correction period (VTC1) is started, the gate-to-source voltage Vgs (the holding voltage of the holding capacitor Cs) is "Vo_Vcc-L". The larger value is, and at the time T10 at which the second threshold correction period (VTC2) is started, the holding voltage is reduced to a smaller "Vxl". As shown in Fig. 6 (B1), at time T10, sampling is performed. When the pulse (SP2) rises and the sampling transistor Ms is turned on, the gate voltage Vg of the driving transistor Md (= "Vo+Val" Connected to the lower potential (Vo) image signal line DTL(j). Thus, the current equivalent to its differential (Val) flows from the gate of the driving transistor Md into the image signal line DTL(j), as shown in Figure 8 (C). ), the gate voltage Vg is forcibly lowered to the data reference potential Vo. The potential (Va 1) deviation in the gate of the driving transistor M d is between the gate source of the holding capacitor Cs and the driving transistor Md. The parasitic capacitance Cgs is input to the source of the driving transistor Md, and the source potential Vs is pulled down. 136030.doc -30- 201003590 The amount of pull-down of the source potential Vs at this time is expressed as "g*Val" using the capacitance combination ratio g. Here, the capacitance coupling ratio g is expressed as g=(Cgs) using the above-described gate-source parasitic capacitance Cgs, the capacitance value (Cs) of the same symbol as the holding capacitor Cs, and the capacitance of the organic light-emitting diode OLED Coled. + Cs) / (Cgs + Cs + Coled.). Therefore, the source potential Vs is reduced by "g*Val" from the previous "Vo-Vxl+Val", and becomes "¥〇-Vx 1 (1 -g) Va 1". Since the capacitance coupling ratio g is smaller than 1 in order to be clear from the definition, the amount of change in the source potential Vs "g*Val" is smaller than the amount of change in the gate voltage Vg (Val). When the source-source inter-electrode Vgs (= "Vxl-(1_g)Val") of the 5-driving transistor is larger than the threshold voltage Vth of the driving transistor Md, as shown in FIG. 8(C), The drain current Ids flows. The source current Ids flows to the source potential Vs of the driving transistor Md to become "Vo-Vth", and the driving transistor Md is cut. However, as shown in Figs. 6(E) and (F), the operation of the present embodiment is such that the voltage Vgs between the gate and the source becomes "Vx2" (where Vx2 contains the magnitude of Vx1 &gt; Vx2 &gt; Vth). The sampling pulse (SP2) ends, so the sampling transistor Ms is turned off. The holding voltage of the capacitor Cs is held at time T12 "Vx2". [Second Standby Period (WAT2)] The second standby period (WAT2) starts from time T12. The second standby period (WAT2) is the same as the previous first standby period (WAT1). Since the sampling transistor Ms is turned off and the gate voltage Vg is electrically floating, the gate voltage Vg is also dependent on the source potential. The rise of Vs is up to 136030.doc •31 · 201003590 liters (see Figure 9(A)). However, the potential increase effect of the gate electric waste Vg (bootstrap effect) is because the gate-source voltage Vgs at the start of the basin is close to the control target "Yang", so it is not too big' as shown in Fig. 6(8) and Fig. 6(F). As seen from the time Tl2 to T15, the potential of the source potential Vs and the gate voltage Vg rises little. u, the younger brother, the field and the 'the second standby period (WAT2) of Fig. 9(A) 'When the inrush current 1^ flows and the source potential...the rising portion is "Va2", when the standby period ends ( At time T15 in Fig. 6, the source potential is "v〇_ 遏2". When the source potential rises, it is transmitted to the floating state by the parasitic capacitance Cgs and the material capacitance (10) between the source and the source. As a result, the open voltage ~ also rises by the same potential Ί. However, as shown in Fig. 6(E), the potential rising portion "Va2" of the closed-circuit electric dust lap is much smaller than the potential rising portion "(5)" in the second standby period (WAT1). [Different two-cylinder limit correction (VTC3)] From time T15, the main action starts to 0. The third threshold correction (VTC3) and the third threshold correction (VTC3) (time Τ1 5~τι 7) are executed. The second threshold correction period (VTC2) is handled in the same manner. However, during the second threshold correction period (VTC2), Τ10, 1 and the inter-electrode voltage Vgs (holding voltage of the holding capacitor Cs) are m" The large value is reduced to a smaller "Vx2" at time T15 at which the third margin correction period (VTC3) is started. The action of the soil is the reverse of the 2nd threshold correction period 2)" 匕 not sw. "Second Threshold Correction Period (VTC2)" 136030.doc •32- 201003590 Explicitly, by replacing "Val" with "Va2" and "Vxl" with "Vx2", it is applicable to Third threshold correction (VTC3). This can be seen from the comparison between Fig. 8(C) and Fig. 9(B). However, unlike the second threshold correction period (VTC2), before the end of the third threshold correction (VTC3) time T17, as shown in Fig. 6(E) and Fig. 6(F), the driving power is The gate-source voltage Vgs of the crystal Md (the holding voltage of the holding capacitor Cs) is equal to the threshold voltage Vth. Therefore, the driving transistor Md is cut at the point where the gate-to-source voltage Vgs is equal to the threshold voltage Vth, and thereafter, the drain current Ids does not flow. At this time, the source potential Vs of the driving transistor Md is "Vo-Vth". As described above, by the correction of the threshold voltage including the number of times in the middle of the standby period (this example is 3 times), the holding voltage of the holding capacitor Cs is converged to a certain period during the standby period. The shape finally becomes the threshold voltage Vth. Here, when the voltage between the gate and the source of the driving transistor is increased to "Vin", the voltage between the gate and the source becomes "Vin + Vth". Further, a driving transistor having a large threshold voltage Vth and a small driving transistor thereof are considered. In the former, the driving transistor having a large threshold voltage Vth, the voltage between the gate and the source is as large as the threshold voltage Vth, and vice versa, the driving voltage of the threshold voltage Vth is small because of the threshold voltage Vth. Small, so the voltage between the gate and the source becomes smaller. Therefore, in the case of the threshold voltage Vth, the deviation is canceled by the threshold voltage correcting operation, and when the same data voltage Vin is used, the same > and the pole current I d s can flow into the driving transistor. In addition, during the correction period including the third limit, that is, the first threshold 136030.doc -33 - 201003590 value correction period (VTCl), the second threshold correction period (VTC2), and the third threshold In the correction (VTC3), it is required that the drain current Ids is mainly consumed only when flowing into one of the electrode sides of the holding capacitor Cs and one electrode side of the capacitor of the organic light emitting diode OLED, and the organic light emitting diode OLED is not turned on. . The anode voltage of the organic light-emitting diode OLED is described as "Voled.", and the threshold voltage is described as "Vth_oled.", and when the cathode potential is described as "Vcath", the organic light-emitting diode OLED is maintained at The condition of the disconnected state is "Voled. S Vcath + Vth - oled." Here, when the cathode potential Vcath of the organic light-emitting diode OLED is kept at the low potential Vcc - L (e.g., the ground voltage GND), the threshold voltage Vth_oled. is extremely large, and the formula can always be established. However, the threshold voltage Vth_oled is determined by the manufacturing conditions of the organic light emitting diode OLED, and in addition, in order to efficiently emit light at a low voltage, the threshold voltage Vth_oled. cannot be made too large. Therefore, the organic light-emitting diode OLED should be pre-biased in advance by setting the cathode potential Vcath to be larger than the low potential Vcc-L before the end of the three threshold correction period and the second description of the mobility correction period. Just right. [Third standby period (WAT3)] The above description explains the threshold voltage correction. However, this operation example continues with the standby period (third standby period (WAT3)) for "write &amp; mobility correction". The third standby period (WAT3) is different from the first standby period (WAT1) and the second standby period (WAT2) for correcting the threshold voltage before, and is only the "write &amp; mobility correction" that follows. When not, 136030.doc -34- 201003590 The potential change is unstable and the standby error sampled the signal signal Ssig during the short standby period. As shown in Fig. 6(m), at the time T17, the sampling pulse is shifted from the level to the "L" level, and the third standby period (WAT3) is started. _ The third standby period (WAT3) is in the middle of the time τ ΐ 8, as shown in Fig. 6 (a), with the image signal pulse (PPx) of the pixel circuit 3 (1, υ displayed data potential as image) Signals are supplied to the video signal line

DTL(J)(參照圖11⑷)。影像訊號Ssig中,資料電位Vsig愈 資料基準電位V。之差分相當於對應於應以該像素電路顯: 之色調值的資料„Vin。換言之,f料電位Μ等於 「Vo+Vin」。 從在時間T18進行之電位變化起經過時間,在影像訊號DTL (J) (refer to Fig. 11 (4)). In the image signal Ssig, the data potential Vsig is higher than the reference potential V. The difference corresponds to the data „Vin corresponding to the tone value that should be displayed by the pixel circuit. In other words, the f potential Μ is equal to “Vo+Vin”. Elapsed time from the potential change at time T18, in the image signal

Ssig以資料電位Vsig而穩定的時間Τ19,該第三待機期間 (WAT3)結束。 [寫入&amp;移動率修正期間(w&amp;卩)] 寫入&amp;移動率修正期間(ψ&amp;μ)從時間Τ19開始。 如圖6㈤所示’在施加主動作時之影像訊號脈衝(ρρχ) 中的時間τ19,將寫入脈衝(wp)供給至抽樣電晶體Ms之閉 極。如此,如圖11(B)所示,抽樣電晶體Ms接通,影像訊 唬線DTL(J)之資料電位Vsig(=v〇+vin)中,與閘極電壓The time Ssig stabilizes at the data potential Vsig Τ 19, and the third standby period (WAT3) ends. [Write &amp; Move Rate Correction Period (w&amp;卩)] Write &amp; Move Rate Correction Period (ψ &amp; μ) starts from time Τ19. As shown in Fig. 6 (f), the time τ 19 in the image signal pulse (ρρχ) at the time of applying the main motion supplies the write pulse (wp) to the closed end of the sampling transistor Ms. Thus, as shown in Fig. 11(B), the sampling transistor Ms is turned on, and the data potential Vsig (= v 〇 + vin) of the image signal line DTL (J) is connected to the gate voltage.

Vg(=Vo)之差分,亦即資料電壓Vin輸入驅動電晶體之 閘極。結果閘極電壓Vg成為「v〇+Vin」。 閘極電壓vg上昇資料電壓Vin程度時,源極電位%亦與 其連動而上昇。此時,並非資料電壓vin照樣被傳達至源 136030.doc -35- 201003590 極包位Vs ’源極電位%係上昇依前述電容結合比g之比率 勺又化刀,亦即係上昇「g*Vin」程度。因而,變化後 之源極電位vs成為「VG_Vth+g*vin」。結果驅動電晶體㈣ 之閘極源極間電壓Vgs成為「(1_g)vin+vthj。 在此,就因移動率μ之偏差作說明。 在此之前的3個臨限值電壓修正,事實上,每次流出沒 極電流Ids時均含有因移動率μ之誤差,不過因為臨限值電 壓Vth之偏差大,所以不嚴格地議論因移動率^之誤差成 ^。此時不使用電容結合比g,而僅重新藉由「Val」及The difference of Vg (=Vo), that is, the data voltage Vin is input to the gate of the driving transistor. As a result, the gate voltage Vg becomes "v〇+Vin". When the gate voltage vg rises by the data voltage Vin, the source potential % also rises in conjunction with it. At this time, the data voltage vin is not transmitted to the source 136030.doc -35- 201003590. The polar package Vs 'the source potential % rises according to the ratio of the above-mentioned capacitance combination ratio g, and the knife is increased, that is, the system rises "g* Vin" degree. Therefore, the source potential vs after the change becomes "VG_Vth+g*vin". As a result, the voltage Vgs between the gate and the source of the driving transistor (4) becomes "(1_g) vin + vthj. Here, the deviation of the mobility μ is explained. The three threshold voltage corrections before this, in fact, Each time the out-of-pole current Ids is discharged, the error due to the mobility μ is included. However, since the deviation of the threshold voltage Vth is large, the error due to the mobility rate is not strictly discussed. In this case, the capacitance combination ratio is not used. And only by "Val" and

Va2」注δ己顯示結果程度之電壓作說明,係為了避免因 說明移動率之偏差的繁雜。 /另外,已經說明過,嚴格而言在進行了臨限值電塵修正 後,因為這時在保持電容器Cs中保持有臨限值電壓讀, 其後,使驅動電晶體_接通時,汲極電流他不依臨限值 電C Vth之大小而變動。因巾,藉由該臨限值電壓修正後 之驅動電晶體Md的導通1藉由該導通時之驅動電流咖 在保持ΐ合器Cs之保持電壓(閘極源極間電壓的值中 產生變動時,其偏差量Λν(可取正或負之極性)除了驅動電 晶體Md之移動率_偏差,更嚴格而言,除了係半導體材 料之物性參數的純粹之含意的移動率之外,反映了在電晶 體之構造上或製程上,影響電流驅動力之因素的综合性偏 差。 根據以上之内容而返回說明時,在圖u⑻中,抽樣電 晶體Ms接通,而在閘極電壓%中加上了資料電壓%時, 136030.doc • 36 - 201003590 驅動電晶體Md要將依其資料電壓Vin(色調值)之大小的汲 極電流Ids流入源極汲極間。此時汲極電流Ids依移動率μ而 偏差,結果源極電位Vs成為在「Vo-Vth+g*Vin」中加上了 因上述移動率μ之變動量AV的「Vo-Vth+g* Vin+AV」。 此時,為了不使有機發光二極體OLED發光,可以滿足 「Vs(=Vo-Vth+g* Vin+AV)&lt;Vth—oled.+Vcath」之方式,預 先設定依資料電壓Vin及電容結合比g等之陰極電位 Vcath。 預先進行該設定時,因為將有機發光二極體OLED反偏 壓電位,而在高阻抗狀態,所以不發光,此外,係顯示單 純之電容特性,並非二極體·特性。 此時,因為只要滿足上述條件式,源極電位Vs不超過有 機發光二極體OLED之臨限值電壓Vth_oled.與陰極電位 Vcath之和,所以係為了充電將保持電容器Cs之電容值(以 相同符號Cs註記)、有機發光二極體OLED之反偏壓電位時 等價電容的電容值(以與寄生電容相同符號Coled.註記)與 存在於驅動電晶體Md之閘極源極間的寄生電容(註記為 Cgs)相加之電容「C=Cs + Coled. + Cgs」,而使用汲極電流 I d s (驅動電流Id)。措此,驅動電晶體M d之源極電位V s上 昇。此時,因為驅動電晶體Md之臨限值修正動作已完 成,所以驅動電晶體Md流出之汲極電流Ids反映移動率μ。 圖6(E)及圖6(F)上,如藉由「(l-g)Vin+Vth-AV」之公式 所示,因為保持於保持電容器Cs之閘極源極間電壓Vgs 中,加入源極電位Vs之變動量AV為從臨限值修正後的閘 136030.doc -37- 201003590 極源極間電壓Vgs( = (l-g)Vin + Vth)減去,所以係以實施負 反鎖之方式將該變動量保持於保持電容器Cs。因而, 以下亦將變動量A V稱為「負反饋量」。 該負反饋量AV在有機發光二極體0LEDt施加了反偏壓 電位之狀態,可以△Vmds/fokd +Cs+Cgs)之公式表 不。從該公式瞭解,變動量AV係與汲極電流Ids之變動成 正比而變化的參數。 從上述負反饋量Δν之公式,附加於源極電位%之負色 饋量AV依存於汲極電流Ids之大小(該大小係與資料電遏 Vm之大小,亦即與色調值為正的相關關係),與汲極電济 Ids流動之時間,亦即圖6(31)所示之移動率修正時需要之 從時間T19至時間T2〇為止的時間⑴。換言之,色調值愈 大,且使用時間⑴愈長,負反饋量Δν愈大。 」 因此,有時移動率修正之時間⑴無需為一定,反而宜依 沒極電流⑷(色調值)作調整。如接近白顯示之沒極電^ 大的情況,縮短移動率修正之時間(t),反之,接近2 顯示而沒極電流Ids變小時,可延長設^移動率修正之: 間⑴。移動率修正時間依該色調值之自動調整,可藉由: 其功能預先設於圖5之寫入訊號掃描電路42等中來 [發光期間(LM1)] 、 在時間T20 ’寫入&amp;移動率修正期間(w&amp;㈠結束時 光期間(LM1)開始。 赞 在時間T20,因為寫入脈衝(wp)結束,所以抽樣電日姊 Ms斷開。驅動電晶體_之閘極成為電性漂浮狀態。㈣ 136030.doc -38- 201003590 接者,在比發光期間(LMl)之前的寫入&amp;移動率修正期 間(W&amp;p),驅動電晶體Md要流出依資料電壓Vin之汲極電 流Ids,不過實際上不限於流出。其理由係因流入有機發 光二極體OLED之電流值(Id)比流入驅動電晶體Md之電流 值(Ids)非常小時,抽樣電晶體Ms接通,所以驅動電晶體 Md之閘極電壓Vg固定於「Vo+Vin」,而源極電位Vs收敛成 從此下降臨限值電壓Vth部分的電位(「Vofs+Vin-Vth」)。 因而,即使將移動率修正之時間⑴延長若干,源極電位Vs 不致偏離到超過上述收斂點的電位。移動率修正係以其收 斂前之速度的差異監控移動率μ之差異來作修正。因此即 使輸入了最大亮度之白顯示的資料電壓Vin的情況,仍在 到達上述收斂之前決定移動率修正之時間⑴的終點。 發光期間(LM1)開始,驅動電晶體Md之閘極成為漂浮 時,其源極電位Vs可進一步上昇。因而,驅動電晶體Md 以流出依所輸入之資料電壓Vin的驅動電流Id之方式動Va2" indicates that the voltage indicating the degree of the result has been explained, in order to avoid the complexity of explaining the deviation of the mobility. / In addition, it has been explained that, strictly speaking, after the threshold electric dust correction is performed, since the threshold voltage reading is maintained in the holding capacitor Cs, then the driving transistor _ is turned on, and the drain is turned off. The current does not change according to the magnitude of the limit voltage C Vth. In the case of the towel, the conduction 1 of the driving transistor Md corrected by the threshold voltage is changed by the driving current at the time of the conduction of the holding current Cs (the value of the voltage between the gate and the source) When the deviation amount Λν (which may take a positive or negative polarity), in addition to the mobility ratio _ deviation of the driving transistor Md, more strictly, in addition to the purely intentional mobility of the physical properties of the semiconductor material, In the construction or process of the transistor, the comprehensive deviation of the factors affecting the current driving force. When returning from the above, in the figure u (8), the sampling transistor Ms is turned on, and the gate voltage % is added. When the data voltage is %, 136030.doc • 36 - 201003590 The driving transistor Md needs to flow the drain current Ids according to the data voltage Vin (tone value) into the source drain. At this time, the drain current Ids moves. As a result, the source potential Vs is "Vo-Vth+g* Vin+AV" in which "Vo-Vth+g*Vin" is added to the fluctuation amount AV of the above-described mobility ratio μ. In order not to cause the organic light emitting diode OLED to emit light, it can be satisfied In the case of "Vs (=Vo-Vth+g* Vin+AV)&lt;Vth_oled.+Vcath", the cathode potential Vcath according to the data voltage Vin and the capacitance coupling ratio g is set in advance. The organic light-emitting diode OLED is reverse-biased with a potential, and is in a high-impedance state, so that it does not emit light, and further, it exhibits a simple capacitance characteristic, and is not a diode/characteristic. At this time, since the above conditional expression is satisfied, the source The potential Vs does not exceed the sum of the threshold voltage Vth_oled. of the organic light-emitting diode OLED and the cathode potential Vcath, so the capacitance value of the capacitor Cs (noted by the same symbol Cs) is kept for charging, and the organic light-emitting diode OLED is used. The capacitance of the equivalent capacitor at the reverse bias potential (the same symbol as the parasitic capacitance, noted) and the parasitic capacitance (denoted as Cgs) existing between the gate and source of the driving transistor Md" C=Cs + Coled. + Cgs", and the drain current I ds (drive current Id) is used. As a result, the source potential V s of the driving transistor M d rises. At this time, because of the threshold of the driving transistor Md The value correction action has been completed, so the drive crystal The drain current Ids flowing out of Md reflects the mobility μ. As shown in the equation of "(lg)Vin+Vth-AV" in Fig. 6(E) and Fig. 6(F), since it is held in the holding capacitor Cs In the voltage Vgs between the gate and the source, the variation amount AV of the source potential Vs is subtracted from the gate 136030.doc -37- 201003590 corrected by the threshold value, and the voltage between the source and the source Vgs (= (lg) Vin + Vth) is subtracted. Going, the fluctuation amount is held in the holding capacitor Cs in such a manner as to implement a negative anti-locking. Therefore, the variation A V is also referred to as a "negative feedback amount" hereinafter. The negative feedback amount AV is expressed by the formula of ΔVmds/fokd + Cs + Cgs) in a state where the reverse bias potential is applied to the organic light emitting diode OLED. From this formula, it is understood that the variable amount AV is a parameter that changes in proportion to the variation of the drain current Ids. From the above formula of the negative feedback amount Δν, the negative color feed amount AV added to the source potential % depends on the magnitude of the drain current Ids (the magnitude is related to the magnitude of the data repression Vm, that is, the positive correlation with the tone value Relationship), the time from the time T19 to the time T2 需要 required for the movement rate correction shown in Fig. 6 (31), which is the time (1). In other words, the larger the tone value, and the longer the use time (1), the larger the negative feedback amount Δν. Therefore, sometimes the time (1) of the movement rate correction does not need to be constant, but it should be adjusted according to the immersion current (4) (tone value). If the power is not close to the white display, the time for correcting the movement rate (t) is shortened. Conversely, when the display is close to 2 and the current of the stepless current Ids is small, the correction of the movement rate can be extended: (1). The movement rate correction time is automatically adjusted according to the tone value, and the function is previously set in the write signal scanning circuit 42 of FIG. 5, etc. [lighting period (LM1)], writing &amp; moving at time T20' During the rate correction period (w&amp; (1) end time period (LM1) starts. Like at time T20, since the write pulse (wp) ends, the sampling electric 姊Ms is turned off. The gate of the driving transistor _ becomes electrically floating. (4) 136030.doc -38- 201003590 Receiver, during the write &amp; mobile rate correction period (W&amp;p) before the illuminating period (LMl), the driving transistor Md is required to flow out the drain current Ids according to the data voltage Vin However, the reason is not limited to the outflow. The reason is that the current value (Id) flowing into the organic light emitting diode OLED is very small compared to the current value (Ids) flowing into the driving transistor Md, and the sampling transistor Ms is turned on, so the driving power is driven. The gate voltage Vg of the crystal Md is fixed at "Vo+Vin", and the source potential Vs converges to a potential ("Vofs+Vin-Vth") which falls from the threshold voltage Vth portion. Therefore, even if the mobility is corrected The time (1) is extended by a few, and the source potential Vs is not Deviation to the potential exceeding the convergence point. The mobility correction is corrected by monitoring the difference in the mobility μ with the difference in the speed before convergence. Therefore, even if the data voltage Vin of the white displayed by the maximum luminance is input, The end point of the time (1) for determining the mobility correction before the convergence is reached. When the light-emitting period (LM1) starts and the gate of the driving transistor Md becomes floating, the source potential Vs can further rise. Therefore, the driving transistor Md flows out. The driving current Id of the input data voltage Vin is moved

結果,源極電位Vs(有機發光二極體OLED之陽極電位) 上昇,隨即解除有機發光二極體OLED之反偏壓電位狀 態,如圖11(C)所示,因為汲極電流Ids作為驅動電流Id開 始流入有機發光二極體OLED,所以有機發光二極體OLED 實際上開始發光。發光開始不久,驅動電晶體Md以依所 輸入之貢料電壓Vin的ί及極電流Ids而飽和,〉及極電流 Ids( = Id) —定時,有機發光二極體OLED成為依資料電壓 Vin之亮度的發光狀態。 136030.doc -39- 201003590 在從發光期間(LM1)之開始至亮度成為一定之間產生的 有機發光二極體OLED之陽極電位的上昇,不過是驅動電 晶體Md之源極電位Vs的上昇,將其作為「AVoled.」來表 示有機發光二極體OLED之陽極電壓Voled.的上昇量。驅動 電晶體Md之源極電位Vs成為「Vo-Vth+g*Vin+AV+AVoled.」 (參照圖6(F))。 另外,如圖6(E)所示,因為閘極電壓Vg係漂浮狀態,所 以與源極電位Vs連動而上昇與其上昇量AVoled.相同程 度,源極電位Vs伴隨沒極電流Ids之飽和而飽和時,閘極 電壓V g亦飽和。 結果,就閘極源極間電壓Vgs(保持電容器Cs之保持電 壓),在發光期間(LM1)中亦維持移動量修正時之值(「(卜 g)Vin+Vth-AV」)。 在發光期間(LM1),由於驅動電晶體Md作為穩流源而動 作,因此有機發光二極體OLED之I-V特性隨時間變化,驅 動電晶體Md之源極電位Vs亦伴隨其而變化。 但是,保持電容器Cs之保持電壓與有機發光二極體 OLED之I-V特性有無隨時間變化無關,而保持在「(1-g)Vin+Vth-AV」。而後,由於保持電容器Cs之保持電壓包 含修正驅動電晶體Md之臨限值電壓Vth的成分(+Vth)與修 正因移動率μ之變動的成分(-AV),因此,即使臨限值電壓 Vth及移動率μ在不同之像素間偏差,驅動電晶體Md之汲 極電流Ids,換言之有機發光二極體OLED之驅動電流Id仍 保持一定。 136030.doc -40- 201003590 具體而吕’ 1時電晶體Md之臨限值電麗Vth愈大,藉由 上述保持電廢之臨限值電麼修正成分(+vth)下降源極電日位 VS ’以更加流Μ極電流Ids(驅動電流Id)之方式增大源極 及極間電屋。因此,即使臨限值電壓vth有變動,沒極電 流I d s仍為一定。 此外,驅動電晶體Md於移動率只小且上述變動量^小之 情況,藉由保持電容!!Cs之保持的移動率修正成分 (-△V)而該保持電遂的降低量亦變小,所以相對而言,確 保大之源極沒極間電結果,係以更加流出汲極電流 油(驅動電流Id)的方式動作。因此即使移動率“有變動, 沒極電流Ids仍為一定。 &quot; 卩使在像素間驅動電晶體腕之臨限值電屢VthAs a result, the source potential Vs (the anode potential of the organic light-emitting diode OLED) rises, and the reverse bias potential state of the organic light-emitting diode OLED is released, as shown in FIG. 11(C), because the drain current Ids is taken as The driving current Id starts to flow into the organic light emitting diode OLED, so the organic light emitting diode OLED actually starts to emit light. Shortly after the light emission starts, the driving transistor Md is saturated according to the input tributary voltage Vin and the polar current Ids, and the polar current Ids (= Id) - timing, the organic light emitting diode OLED becomes the data voltage Vin The state of illumination of the brightness. 136030.doc -39- 201003590 The rise of the anode potential of the organic light-emitting diode OLED which occurs between the start of the light-emitting period (LM1) and the constant brightness, but the rise of the source potential Vs of the driving transistor Md, This is referred to as "AVoled." to indicate the amount of rise of the anode voltage Voled. of the organic light-emitting diode OLED. The source potential Vs of the driving transistor Md becomes "Vo-Vth+g*Vin+AV+AVoled." (refer to Fig. 6(F)). Further, as shown in FIG. 6(E), since the gate voltage Vg is in a floating state, the source potential Vs rises in accordance with the saturation of the no-pole current Ids as the source potential Vs rises in the same manner as the rise amount AVoled. At the same time, the gate voltage V g is also saturated. As a result, with respect to the gate-to-source voltage Vgs (holding voltage of the holding capacitor Cs), the value at the time of correction of the movement amount ("(g) Vin+Vth-AV") is also maintained in the light-emitting period (LM1). During the light-emitting period (LM1), since the driving transistor Md operates as a steady current source, the I-V characteristic of the organic light-emitting diode OLED changes with time, and the source potential Vs of the driving transistor Md also changes. However, the holding voltage of the holding capacitor Cs is independent of the time-dependent change of the I-V characteristic of the organic light-emitting diode OLED, and is maintained at "(1-g) Vin+Vth-AV". Then, since the holding voltage of the holding capacitor Cs includes the component (+Vth) for correcting the threshold voltage Vth of the driving transistor Md and the component (-AV) for correcting the variation of the moving rate μ, even the threshold voltage Vth And the mobility μ varies between different pixels, driving the drain current Ids of the transistor Md, in other words, the driving current Id of the organic light emitting diode OLED remains constant. 136030.doc -40- 201003590 Specifically, Lu's 1 time transistor Md's limit value is the larger the Vth, and by the above-mentioned electric waste, the correction component (+vth) decreases the source electric day. VS ' increases the source and inter-pole powerhouses in a way that flows more currents Ids (drive current Id). Therefore, even if the threshold voltage vth varies, the in-pole current I d s is still constant. Further, the driving transistor Md maintains the capacitance by the fact that the mobility is small and the amount of variation is small. ! The movement rate correction component (-ΔV) held by Cs is also reduced, so that the source of the large source is relatively small, so that the drain current is further flowed out. The driving current Id) acts. Therefore, even if the mobility rate "has changed, the immersed current Ids is still constant. &quot; 卩 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动

及移動率μ偏差,進一步即使驅叙φ s μ 电S 行 吏驅動電日日體Md之特性隨時間 雙化,只要資料電壓Vin相 光亮度亦保持一定。 有機發先二極體咖之發 &lt;像素電路對色之差異&gt; &gt;其=,將以上之像素電路的結構及動作為前提,就本實 施形悲之顯示裝置的特徵, 說明。 1即就像素結構對色之差異作 因為依構成有機發光二極體 ^ ^ ^ 有機膜的有機材料 ㈣,垂所以如之前的說明,即使像素之等價電路 際上依鄰接像素在包含材料時,結構上有不同。 口此,從同一列連續之n(n 廿脾禮I „ 冢素構成像素單元, 早元作為單位來觀察時,結構㈣。為編之3 136030.doc -41 - 201003590 原色顯*的情況,係W 3原色各個發光亮度之比率來顯示 任意的!色’且N=3。以下’將_之_的3原色顯示作 為前提。 如此,因為像素單元顯示任意之〗色,所以係在像素陣 列内具有相同結構之最小單位。本實施形態之特徵為: 「在像素單it内,於特定色之像素中,包含驅動電晶體、 保持電容器及發光元件的像素電路要素之組數比盆他色之 像素的組數多,且設有2組以上」。以下,將1個像素内之 「組」的數稱為「組數」。另外,就「特定色」詳述於 後。 在此,像素電路要素之「組」,如上述,「像素電路要 素」係至少包含驅動電晶體_、保持電容器〇及發光元 二本實施形態係有機發光二極體〇led)。只要滿足關於 &quot;組」之要件,像素電路可為前述之&lt;像素電路卜、〈像 素電路2&gt;'&lt;像素電路3&gt;, 4T1 型、5T.1C 型、3T 可為 4T.1C 型、 迠,择 C型等2T· lc型以外的。不 過,取好是&lt;像夸雷枚. ” ,亦即是圖5之像素電路結構,因 為其含有全部之電曰和广 非曰併 4(TFT)係大畫面化容易之N通道型的 非晶質矽TFT,電政姓接。D “ 、、孓旳 路、,Ό構早純,以及臨限 率μ的修正構造預弈裎徂μ你 及私動 負先k i、於像素電路等各種 將圖5之像素電路作為前提繼續說明。U以下, 本實施形態中,「特定 特定色」與「相^ W為未點^陷之 個。 見度取向之特定色」的2個之任何一 136030.doc -42- 201003590 就谷易成為未點亮缺陷之特定色」,統計性地調杳色 與未點亮缺陷之產生率時,有時某個色成為未點亮缺陷之 概率比其他色高,該情況下,將成為未點亮缺陷之概率高 的色作為「特定色」。 按照本發明人之調查,瞭解未點亮缺陷或是雖未形成未 點亮缺陷但是亮度未達希望之值(以下稱為半未點亮缺陷) 的瑕疲之產生態樣包含:在有機發光二極體〇led之形成And the mobility ratio μ deviation, further, even if the characteristics of the φ s μ electric S driving electric day body Md are doubled with time, as long as the data voltage Vin phase brightness is kept constant. The organic hair first diode coffee hair &lt;pixel circuit color difference&gt;&gt; ==, based on the structure and operation of the above pixel circuit, the characteristics of the display device of the present embodiment are explained. 1 that the difference in color of the pixel structure is due to the organic material (4) constituting the organic light-emitting diode ^ ^ ^ organic film, as described above, even if the equivalent circuit of the pixel is adjacent to the pixel when the material is contained The structure is different. In this case, from the same column of continuous n (n 廿 spleen I „ 冢 构成 构成 构成 构成 构成 构成 构成 构成 构成 构成 构成 构成 构成 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素 像素The ratio of the respective illuminances of the primary colors of W 3 is used to display an arbitrary ! color ' and N = 3. The following is the premise of displaying the three primary colors of _ _ of _. Thus, since the pixel unit displays an arbitrary color, it is in the pixel array. The minimum unit of the same structure is provided. The feature of the present embodiment is: "In the pixel unit it, the number of groups of pixel circuit elements including the driving transistor, the holding capacitor, and the light-emitting element in the pixel of the specific color is greater than the color of the pixel. In the following, the number of "groups" in one pixel is referred to as "group number". The "specific color" is described later. As described above, the "pixel circuit element" includes at least a driving transistor _, a holding capacitor 〇, and a light-emitting element (the organic light-emitting diode of the present embodiment). The pixel circuit may be the aforementioned &lt;pixel circuit, <pixel circuit 2&gt;'&lt;pixel circuit 3&gt;, 4T1 type, 5T.1C type, 3T may be 4T.1C type as long as the requirements for the &quot;group&quot; are satisfied. , 迠, choose C type and other 2T· lc type. However, it is better to use the image of the pixel circuit of Figure 5, because it contains all the power and the wide-screen 44 (TFT) system is easy to N-channel type. Amorphous 矽TFT, electric power surname. D " , , 孓旳 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Various descriptions will be continued on the premise of the pixel circuit of FIG. In the following, in the present embodiment, the "specific specific color" and the "phase is W are not in the spot. The specific color of the visibility orientation" is 136030.doc -42 - 201003590 When the specific color of the defect is not lit, and the rate of occurrence of the unlit defect is statistically adjusted, the probability that a certain color becomes an unlit defect may be higher than the other colors. In this case, it will become unpointed. A color with a high probability of bright defects is referred to as a "specific color." According to the investigation by the present inventors, it is known that the unstained defect or the value of the brightness that does not form an unlit defect but the brightness is not as high as desired (hereinafter referred to as a semi-unlit defect) includes: in the organic light emission Formation of diodes

步驟,流入其陽極與陰極之電流因斷線而阻斷的情況丨即 使未達到斷線,而配線之—部分及接點形成高電阻化之情 況;進一步因塵埃在陽極與陰極間形成短路,因有機發光 二極體OLED之驅動電流流入該短路而消&amp;,導致驅動電 流不流入有機發光二極體0LED,或是雖有流動但是電流 量不足的情況。 一而本發明人之調查,因短路而產生未點亮缺陷或半未點 凴缺陷為最多的瑕疵產生態樣。 圖12中顯示因塵埃而在有機發光二極體〇咖之陽極與 陰極間形成了短路時的像素電路3〇,」)之等價電路。 於形成有機發光二極體〇LED之有機多層膜時附著塵埃 時,有機發光二極體0咖之陽極與陰極間,目導電性之 塵埃或是因塵埃造成圖案瑕疲’冑由經由電阻r而連繫之 紐路導致電性連接。該情況下,流經驅動電晶體Md之汲 極電流此分歧成流經有機發光二極體〇led之驅動電流Η 與流經電阻R之電流ΙΓ。如前述,沒極電流他係依從影像 «線肌⑴預先輸人之資料㈣的―定電流,不過產生 136030.doc -43- 201003590 流經電阻R之電流卜時,驅動電流Id減少其部分,有機發光 二極體OLED之發光亮度降低(半未點亮缺陷)。 電阻R大時半未點亮缺陷不顯著,不過,電阻R愈小, 電流Ir愈增加,因驅動電流Id減少其部分,所以半未點亮 缺陷變顯著。而電阻變小某種程度時,驅動電流 流入有機發光二極體OLED,而產生未點亮缺陷。 某種大小之塵埃附著,基於該原因,有機發光二㈣ OLED之陽極與陰極經由電阻尺而電性短路之情況,塵埃愈 大造成短路之概率愈增加,此外,短路之電㈣亦有㈣ 塵埃愈大而變小的趨勢。這應該是起因於在塵埃周圍有一 部分未能形成有機多層膜,在其部分,陽極金屬與陰極金 屬間直接接觸,或是即使沒有直接接觸也會發生電場集 中,而在其部分之漏電流增加。本發明人之調查,係有: 發光二極體〇LED之有機多層膜相對薄之色的像素約略有 容易產生未點亮缺陷及半未點亮缺陷的趨勢。這印證上述 瑕麻發生的理由正確。 ’ 此種情況下,本實施形態可在像素單元内,以有機發光 二極體〇哪,將由複數有機薄膜構成之有機多層膜的總 膜厚最小之色的像素作為「容易成為未點亮缺陷之特定 廳之3原色顯示的情況,哪個色之有機多層膜的總膜 厚最小,係依使用之膜的材質、模構造等而不同。此外, 總膜厚亦依是否作為利用及射# + 巧W用反射先成分增強射出光的光 構造而不同。因此,尤At ^ ^ 月t* 一概而言哪個色之總膜厚最小, 136030.doc • 44 - 201003590 般性趨勢是在藍(B)中總 ?—— 不過RGB之3原色顯示的情況 膜厚比其他色小。 另外,「相對可見度最高之特^色」係表示依產生未點 亮缺陷及半未點亮缺陷時之影響是否高來決定色之方式的 表現。 具體而言,肉眼就RGB3原色之各色並非具有相同感 度’各色之感度(可見度)不同。相對可見度係表示各波長 之可見度對顯示最大可見度之波長(明處係⑸㈣,暗處 係⑽㈣)的可見度(單位:i m/w)之比率而加以標準化 的參數。 職之情況,綠(G)之相對可見度最高。此外,就赵⑻ 2言’歐美人之相對可見度比日本人之相對可見度相對較 而0 士因此,在顯示某色之晝面的1個像素單元内,於!個像素 =產=未點亮缺陷情況,其像素為綠(G)之情況下瑕庇明 他色(紅⑻及藍⑽之情況,比綠⑹之情況不明 之3原色顯示的情況,所謂「相對可見度 °寸疋色」即使稱為綠(G)亦無妨。 圖3(A)令,作為「容易成為未點亮缺陷之特定 一例,係就有機多層膜之總」, 「組數」比其他色之像素内的「έ赵 ⑻像素内的 個像素單元部分之等價 月况,頭示! 电路圖。此外,圖13⑻中,作為 相對可見度最高之特定洛.y , 作马 之「έ , 疋色」的一例,係就綠((})像辛内 之組」數比其他色之傻去&amp;μ^ I内 像素内的組」數多之情況,顯示 136030.doc -45· 201003590 1個像素單元部分之等價電路圖。 圖〗3係將更多之「組數」設為2,不過該數只須比更少 之「組數」1大即可,且為2以上之任意數。 另外’「組」中在此並未包含抽樣電晶體Ms,不過亦可 包含。 將圖13(A)之情況為例’在圖丨4(A)中顯示像素電路之主 區域區分’與在圖14(B)中顯示比主區域區分上層之主要 為有機發光二極體OLED的配置區域區分。如此,像素電 路之要素(電晶體、電容器及有機發光二極體)全部可不配 置於相同區分。該圖示例係圖14(B)所示之有機發光二極 體0㈣的配置區分就娜係大致相同面積,而圖14(八)所 不之電晶體及電容器的配置區分,僅「組數」為2之藍⑻ 像素比其他2色大。 「如此,以元件電路要素劃分配置區分時,具有藉由增多 ’’·數J各易確保元件電路要素之配置空間的優點。 &lt;平面及剖面之構造例&gt; 在此,就像素電路之平面圖案及剖面構造,參照圖式 說明。另外,在此之說明,由於係京尤「組數」係!之如 W像素作說明,因此為了容易觀察圖式,係使用全部i 置區域來配置像素電路要素,不過增多組數情況下,藉 配置區域擴大寺之對策進行配置空間之確保。 圖15(A)與圖15(B)係顯示就第W、第』行之像素電路叩, 的平面圖案。圖15(B)係省略了最上層之陰極電極(全面; 成)的平面圖,圖15⑷係省略了包含最上層之陰極電针 136030.doc -46- 201003590 面开》成)的有機發光二極體OLED之電極及有機多層膜的製 造中途之平面圖。 此外’圖16(A)係圖15(A)之A-A線的概略剖面圖,圖 16(B)係圖15(A)與圖ι5(Β)之b_b線的概略剖面圖。 圖16(A)及圖16(B)中,在無圖示之由玻璃等構成的基板 上,直接或經由其他膜形成有基底層1〇(絕緣層之一種)。 圖16(B)所示之剖面中,在基底層1〇上形成有由指定之 閘極金屬層(GM) ’如由鉬(Mo)等之高熔點金屬層構成的 閘極電極11A。圖16(B)之剖面顯示有圖5等之驅動電晶體 Md的形成部位,不過如圖15㈧所示,在抽樣電晶體洳之 形成部位亦同樣地形成有大小若干不同之閘極電極仙。 另外,在圖16(A)所示之剖面中,與閘極電極UA相同階 層,且由相同材質之閘極金屬層(GM)構成的第一高炼點金 屬配線層11B及第二高熔點金屬配線層uc形成於基底層1〇 上。如圖15(A)所示,第—高炼點金屬配線層1融第二古 :點金屬配線層UC在像素内離開,不過在鄰接像素‘ :換:之’圖15(A)所示之第一高熔點金屬配線層與 音:於^方^之一方(圖15(A)之更下方)的其他無圖示之像 '、 的第二高炼點金屬配線層11 cr盔m UUC(無圖不)作為圖案兩連 ^ 问樣地,圖1 5(A)所示之第-古栌科人s 帛一冋熔點金屬配線層llc與 運續於仃方向之另一方(圖丨 德去 )更上方)的其他無圖禾之 像素中的第一高熔點金屬配線層u 連繫。 κ(無圖不)作為圖案而 以覆蓋閘極電極11A之表 ^ 1圖16(β))、弟一高熔點金屬 J36030.d〇, -47- 201003590 配線層11B及第二高熔點金屬配線層uc之表面(圖 的方式,在基底層1 〇上全面地形成有閘極絕緣膜丨2。 在圖16(B)所示之剖面中,在閘極絕緣膜12上形成有如 由非晶質矽(P通道型TFT之情況,亦可為多晶矽)構成之驅 動電晶體Md的TFT層13A。如圖15(A)所示,雖然尺寸不 同,不過同樣地形成抽樣電晶體Ms之TFT層丨3 B。在圖 16(B)之TFT層13 A上形成有導入反導電型之雜質而彼此分 離的源極(S)與汲極(D)之各區域。這在TFT層i3B中亦同 樣。 在閘極絕緣膜12中,圖16(A)之剖面中係在第—高炫點 金屬配線層UB之端部上形成有接觸孔12入。同樣地,在 第二高炼點金屬配線層11C之端部上,於閘極絕緣膜12t 形成有接觸孔12C。 各配線連接部中各1個而合計為2個之接觸孔12A與 12B,係連接高熔點金屬配線層與其上之上層配線層的第 一接觸孔(1CH)。 具體而言,第-高熔點金屬配線層11B之端部係經由接 觸孔12A而連接於設於閘極絕緣膜12上,如由紹㈧)構成 之上層配線層UB的一方端冑。此外,第二高溶點金屬配 線層nc之端部係經由接觸孔i2c而連接於設於間極絕緣膜 12上之上述上層配線層14B的另一方端部。 在第一高炼點金屬配線層11B之上方,設有經由間極絕 緣膜12絕緣,並以圖宏命1 « * /、’、上層配線層14B分離之高電位Vcc — Η的i、、、、口線(以下’註記為電源電麼供給線vdDl)。電源 136030.doc -48· 201003590 電壓供給線VDDL在圖5中,係連接於水平像素線驅動電路 4 1,且對驅動電晶體Md之汲極交互地施加高電位Vcc_ Η 與低電位Vcc—L的配線。因此,如圖15(A)所示,電源電 壓供給線VDDL之分歧線(以同一符號VDDL註記)電性地以 低電阻接觸於成為TFT層13A之汲極(D)的區域。另外,與 電源電壓供給線VDDL相同階層且由相同材質(鋁(A1))構成 之保持電容器Cs的上部電極層14D,對成為驅動電晶體Md 之源極(S)的區域電性連接。如圖15(A)所示,上部電極層 14D與從閘極電極11A連續之保持電容器Cs的下部電極 層,在圖案上重疊,該部分形成MIS(金屬絕緣體半導體) 構造之保持電容器Cs。 圖1 6(B)中,在第二高熔點金屬配線層11C之上方,設有 經由閘極絕緣膜12絕緣,並以圖案而與上層配線層14B分 離的抽樣電晶體Ms之控制線SAML。控制線SAML在圖5中 係連接於寫入訊號掃描電路42,並對抽樣電晶體Ms之閘極 施加寫入驅動脈衝WS(i)的配線。因此,如圖1 5(A)所示, 控制線SAML經由第一接觸孔(1HC)、接觸孔12E而與下層 之抽樣電晶體Ms的閘極電極11D連接。 控制線SAML與電源電壓供給線VDDL平行地在列方向 延長配線。影像訊號線DTL(j)在與控制線SAML之交又部 分,含有將第二高熔點金屬配線層11C作為下方橋接之構 造(本說明書係稱為「下方橋接構造」)。同樣地,影像訊 號線DTL(j)在與電源電壓供給線VDDL之交叉部分,含有 將第一高熔點金屬配線層11B作為下方橋接之構造(下方橋 136030.doc -49- 201003590 接構造)。 另外,在抽樣電晶體^之”丁層13B的汲極側,在圖案 上連接上層配線層14B ,在源極側連接有由鋁(A1)構成, 且構成圖5之驅動電晶體Md的控制節點NDc之一部分的胞 内配線14E。胞内配線14E經由第一接觸孔(ihc)、接觸孔 12F而與下層之保持電容器心的下部電極層電性連接。 埋入如此所形成之鋁(A1)的各種配線,亦即電源電壓供 給線卿L、控制線SAML、上層配線層⑽、上部電極層 14D及胞内配線14E ’全面地形成有將此等階差予以平坦 化用的平坦化膜15(參照圖16(B))。 如圖16(B)之剖面所示,在上部電極層md上之平坦化膜 15部分,形成有以導電材料埋入形成於平坦化膜15之第二 接觸孔(2HC)的陽極接點〖5 a。 而後,依序堆積:形成於平坦化膜15上,並接觸於陽極 接點15A之端面的陽極電極(AE);形成於陽極電極(AE) 上,並含有比陽極電極(AE)小一周之開口部16八的保護膜 16,進一步堆積覆蓋其上之有機多層膜(〇ml);及在像素 佔用面積的全面形成外殼狀的陰極電極(CE);藉此形成有 有機發光二極體OLED。 採用以上之實施形態,在各像素單元中,僅最容易形成 未點亮缺陷之色的像素,或是僅相對可見度最高之色的像 素,藉由作為設複數分別具有驅動電晶體、保持電容器及 有機發光二極體之組的結構,容易成為未點亮缺陷之複數 像素不致作為未點亮缺陷,或是即使成為未點亮缺陷亦不 136030.doc •50- 201003590 顯著。結果可使良率提高。 此外,藉由組内之+ I表 邠要素(琶日日體、電容器、有機發 2二極體)不共用像素電路要素之配置區分(階層),而以配 效率最佳之方式’如形成有機發光二極體之階層比形成 其他元件之階層,Α έθ制_ 丁 m — 、,,數不同之像素間,縮小其面積比。 藉此,配置效率;^古,# η . β 回並且將配線之線與空間適當化,而 又得可防止因線間短路造成良率降低的利益。 【圖式簡單說明】 % / 圖1係顯示關於本發明之眚 月l κ施形恝的有機EL顯示器之主 要結構圖; 圖2係關於本發明之會运 ★如/3之K施形悲的〈像素電路〗&gt;之基本結 構圖; 圖3係關於本發明之實施形能的 &lt; 後|^ κ々也的 &lt; 像素電路2 &gt;之基本結 構圖; 圖4係顯示其顯示有機發光二極體之特性的圖形 : &gt; 之圖; 、、 圖5係關於本發明之實施形態的〈像素電路之 構圖; 土 口 圖6⑷,叫㈣叫似叫⑽),⑻,(f)係顯示 1於本發明之實施形態的顯示控制中之各種訊號及電壓波 形的時序圖; 圖7(A)-(C)係抽樣前之動作說明圖; 圖8(A)-(C)係第二臨限值修正前之動作說明圖; 圖9(A)、9(B)係第三臨限值修正前之動作說明圖; 136030.doc -51 201003590 圖1 〇係關於本發明之實施形態的源極電位之時間推移 圖, 圖11(A)-(C)係發光期間前之動作說明圖; 圖1 2係關於本發明之實施形態的像素電路,且係在有機 發光二極體中產生電極間短路之情況的等價電路圖; 圖13(A)、14(B)係顯示關於本發明之實施形態的像素單 元結構圖; 圖14(A)、14(B)係顯示關於本發明之實施形態,像素電 路要素之配置區分不同之例的平面圖; 圖15(A)、15(B)係關於本發明之實施形態的像素電路之 平面圖;及 圖1 6(A)、1 6(B)係關於本發明之實施形態的像素電路之 剖面圖。 【主要元件符號說明】 1 有機EL顯示器 2 像素陣列 3 像素電路 4 垂直驅動電路(V掃描器) 5 水平驅動電路(H掃描器) 10 基底層 11A 覆蓋閘極電極 11B 第一高熔點金屬配線層 11C 第二高熔點金屬配線層 11D 閘極電極 136030.doc -52- 201003590In the step, the current flowing into the anode and the cathode is blocked by the disconnection, and even if the disconnection is not reached, the wiring portion and the contact are formed with high resistance; further, the dust forms a short circuit between the anode and the cathode. When the driving current of the organic light emitting diode OLED flows into the short circuit, the driving current does not flow into the organic light emitting diode OLED, or the current is insufficient. As a result of investigations by the present inventors, an unilluminated defect or a semi-unfinished defect has the largest occurrence of defects due to a short circuit. Fig. 12 shows an equivalent circuit of the pixel circuit 3A, ") when a short circuit is formed between the anode and the cathode of the organic light-emitting diode, due to dust. When dust is adhered to the organic multilayer film forming the organic light-emitting diode 〇LED, between the anode and the cathode of the organic light-emitting diode, the dust of the conductive or the pattern is caused by the dust. The connected road leads to electrical connections. In this case, the turbulent current flowing through the driving transistor Md is divided into a driving current 流 flowing through the organic light emitting diode 〇led and a current 流 flowing through the resistor R. As mentioned above, the current without current is in accordance with the constant current of the image of the line «1 muscle (1), but the current Id is reduced by 136030.doc -43- 201003590 when the current flows through the resistor R. The luminance of the organic light-emitting diode OLED is lowered (half unlit defect). When the resistance R is large, the half unlit defect is not significant. However, the smaller the resistance R is, the more the current Ir increases, and the drive current Id decreases, so that the half unlit defect becomes remarkable. When the resistance becomes small to some extent, the driving current flows into the organic light emitting diode OLED to generate an unlit defect. For the reason that the dust of a certain size is attached, the anode and the cathode of the organic light-emitting two (four) OLED are electrically short-circuited via a resistor scale, and the greater the dust, the more the probability of short-circuit is increased, and the short-circuited electricity (4) also has (four) dust. The bigger and smaller the trend. This should be caused by a part of the dust that does not form an organic multilayer film, in which part of the anode metal is in direct contact with the cathode metal, or electric field concentration occurs even without direct contact, and leakage current increases in part thereof. . The inventors' investigations are as follows: The pixels of the relatively thin color of the organic multilayer film of the light-emitting diode 〇LED tend to have a tendency to cause unlit defects and semi-unlit defects. This confirms that the above reasons for the occurrence of castor are correct. In this case, in the present embodiment, in the pixel unit, the pixel having the smallest total thickness of the organic multilayer film composed of the plurality of organic thin films can be used as an "unlit defect" in the organic light-emitting diode. In the case of the display of the three primary colors of the specific hall, the total thickness of the organic multilayer film of which color is the smallest, depending on the material of the film to be used, the mold structure, etc. In addition, the total film thickness is also dependent on whether or not it is used. It is different from the light structure that reflects the emitted light by the reflection component. Therefore, the total film thickness of the color is the smallest at least, 136030.doc • 44 - 201003590 The general trend is in blue (B In the case of RGB's 3 primary colors, the film thickness is smaller than other colors. In addition, the "highest relative visibility" indicates whether the effect is caused by the occurrence of unlit defects and semi-unlit defects. High to determine the performance of the way of color. Specifically, the naked eye does not have the same sensitivity for each of the RGB3 primary colors, and the sensitivity (visibility) of each color is different. The relative visibility is a parameter that normalizes the visibility of each wavelength to the ratio of the visibility (unit: i m/w) of the wavelength showing the maximum visibility (the system (5) (four), the dark system (10) (four)). In the case of jobs, Green (G) has the highest relative visibility. In addition, Zhao (8) 2 words 'European and American people's relative visibility is relatively better than the Japanese's relative visibility and 0. Therefore, in a pixel unit showing the face of a certain color, at! pixels = production = not lit In the case of a defect, the case where the pixel is green (G), the case where the color is red (8) and the blue (10), and the case where the primary color is not known than the case of the green (6), the so-called "relative visibility ° inch color" even if It is also possible to call it green (G). As shown in Fig. 3(A), "the total number of organic multilayer films is a specific example of the problem that it is easy to become an unlit defect", and the "number of groups" is smaller than that of pixels of other colors. The equivalent monthly condition of the pixel unit part in the (8) pixel is shown in the circuit diagram. In addition, in Fig. 13 (8), as the specific relative .y, which is the highest relative visibility, an example of "έ, 疋色" is used as a horse. In the case where the number of green ((}) like the group of the symplectic is higher than the number of the other colors, the number of the groups in the pixels within the μ μ I shows 136030.doc -45· 201003590 1 pixel unit part, etc. Price circuit diagram. Figure 3 series sets more "group number" to 2, but the number only needs to be less than The number of groups is one large and is any number of two or more. In addition, the sampling transistor Ms is not included in the 'group', but may be included. The case of Fig. 13(A) is taken as an example. The main area division of the display pixel circuit in 丨4(A) is distinguished from the arrangement area of the organic light-emitting diode OLED which is different from the main area in FIG. 14(B). Thus, the elements of the pixel circuit (electrical All of the crystals, capacitors, and organic light-emitting diodes may not be disposed in the same division. The example of the arrangement of the organic light-emitting diodes 0 (4) shown in Fig. 14(B) is roughly the same area, and Figure 14 ( VIII) The arrangement of the transistors and capacitors is different. Only the "group number" is 2 blue (8) pixels are larger than the other two colors. "So, when the device circuit elements are divided and arranged, there is an increase in the number of '' Each of J easily ensures the advantage of the arrangement space of the element circuit elements. <Configuration Example of Plane and Cross Section> Here, the planar pattern and the cross-sectional structure of the pixel circuit will be described with reference to the drawings. Jingyou "number of groups" is like W! In order to make it easy to observe the pattern, the pixel circuit elements are arranged using all the areas, but in the case of increasing the number of groups, the arrangement space is enlarged by the arrangement of the area expansion. Fig. 15(A) and 15(B) shows the planar pattern of the pixel circuit 第 of the Wth and ninth rows. Fig. 15(B) omits the plan view of the uppermost cathode electrode (all-in-one), and Fig. 15(4) omits the most A plan view of the electrode of the organic light-emitting diode OLED and the organic multilayer film in the upper layer of the cathode electro-acupuncture 136030.doc -46-201003590. In addition, Fig. 16(A) is shown in Fig. 15(A) A schematic cross-sectional view of the AA line, and Fig. 16(B) is a schematic cross-sectional view of the line b_b of Fig. 15 (A) and Fig. 5 (Β). In Figs. 16(A) and 16(B), a base layer 1 (one type of insulating layer) is formed directly or via another film on a substrate made of glass or the like (not shown). In the cross section shown in Fig. 16(B), a gate electrode 11A composed of a predetermined gate metal layer (GM) such as a high melting point metal layer of molybdenum (Mo) or the like is formed on the underlayer 1B. The cross section of Fig. 16(B) shows the formation portion of the driving transistor Md of Fig. 5 and the like. However, as shown in Fig. 15 (A), gate electrodes of different sizes are formed in the same manner at the portion where the sampling transistor is formed. Further, in the cross section shown in FIG. 16(A), the first high-refining metal wiring layer 11B and the second high melting point which are formed of the gate metal layer (GM) of the same material in the same level as the gate electrode UA The metal wiring layer uc is formed on the underlying layer 1 . As shown in Fig. 15(A), the first high-metal wire layer 1 is melted in the second place: the dot metal wiring layer UC is separated in the pixel, but in the adjacent pixel ': change: 'Fig. 15(A) The first high-melting-point metal wiring layer and the sound: the other high-definition metal wiring layer 11 of one of the other sides (Fig. 15 (A) below), the second high-finished metal wiring layer 11 cr helmet m UUC (No picture is not) as a pattern of two connections ^ Question, Figure 1 5 (A), the first - 栌 栌 人 帛 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋 冋De)) is connected to the first high-melting-point metal wiring layer u in the other pixels. κ (not shown) as a pattern covering the surface of the gate electrode 11A, FIG. 16 (β), and a high melting point metal J36030.d〇, -47- 201003590, the wiring layer 11B and the second high melting point metal wiring The surface of the layer uc (in the manner of the figure, the gate insulating film 丨2 is formed entirely on the base layer 1 。. In the cross section shown in Fig. 16(B), the gate insulating film 12 is formed as amorphous As shown in FIG. 15(A), the TFT layer 13A of the driving transistor Ms is formed in the same manner as in the case of the P-channel type TFT (which may be a polysilicon).丨3 B. The regions of the source (S) and the drain (D) which are separated from each other by introducing impurities of the reverse conductivity type are formed on the TFT layer 13 A of Fig. 16(B). This is also in the TFT layer i3B. Similarly, in the gate insulating film 12, a contact hole 12 is formed in the end portion of the first-high-point metal wiring layer UB in the cross section of Fig. 16(A). Similarly, the second high-point metal is formed. A contact hole 12C is formed in the gate insulating film 12t at the end of the wiring layer 11C. One of the wiring connecting portions and a total of two contact holes 12A and 12B are connected. The first contact hole (1CH) of the high-melting-point metal wiring layer and the upper wiring layer is connected. Specifically, the end of the first high-melting-point metal wiring layer 11B is connected to the gate insulating film via the contact hole 12A. On the 12th, as shown by (8), one end of the upper wiring layer UB is formed. Further, the end portion of the second high-melting point metal wiring layer nc is connected to the other end portion of the upper wiring layer 14B provided on the interlayer insulating film 12 via the contact hole i2c. Above the first high-refining-point metal wiring layer 11B, there is provided an i, which is insulated by the interlayer insulating film 12 and separated by a high potential Vcc — 图 separated by the macro layer 1 « * /, ' and the upper wiring layer 14B. ,, mouth line (the following 'Notes as power supply line supply line vdDl). Power supply 136030.doc -48· 201003590 The voltage supply line VDDL is connected to the horizontal pixel line drive circuit 4 1 in FIG. 5 and applies a high potential Vcc_ Η and a low potential Vcc-L to the drain of the drive transistor Md. Wiring. Therefore, as shown in Fig. 15(A), the branch line of the power supply voltage supply line VDDL (indicated by the same symbol VDDL) is electrically contacted to the region which becomes the drain (D) of the TFT layer 13A with low resistance. Further, the upper electrode layer 14D of the holding capacitor Cs having the same material as the power supply voltage supply line VDDL and having the same material (aluminum (A1)) is electrically connected to a region serving as a source (S) of the driving transistor Md. As shown in Fig. 15(A), the upper electrode layer 14D and the lower electrode layer of the holding capacitor Cs continuous from the gate electrode 11A are superposed on the pattern, and this portion forms a holding capacitor Cs of a MIS (Metal Insulator Semiconductor) structure. In Fig. 16 (B), above the second high-melting-point metal wiring layer 11C, a control line SAML of the sampling transistor Ms which is insulated by the gate insulating film 12 and separated from the upper wiring layer 14B by a pattern is provided. The control line SAML is connected to the write signal scanning circuit 42 in Fig. 5, and applies wiring for writing the drive pulse WS(i) to the gate of the sampling transistor Ms. Therefore, as shown in Fig. 15(A), the control line SAML is connected to the gate electrode 11D of the lower sampling transistor Ms via the first contact hole (1HC) and the contact hole 12E. The control line SAML extends the wiring in the column direction in parallel with the power supply voltage supply line VDDL. The image signal line DTL(j) is further connected to the control line SAML, and includes a structure in which the second high-melting-point metal wiring layer 11C is bridged downward (this embodiment is referred to as a "lower bridge structure"). Similarly, the image signal line DTL(j) has a structure in which the first high-melting-point metal wiring layer 11B is bridged downward at a portion intersecting the power supply voltage supply line VDDL (lower bridge 136030.doc -49 - 201003590). Further, on the drain side of the dicing layer 13B of the sampling transistor, the upper wiring layer 14B is connected to the pattern, and the source side is connected with aluminum (A1), and the driving transistor Md of Fig. 5 is controlled. The intracellular wiring 14E of a portion of the node NDc. The intracellular wiring 14E is electrically connected to the lower electrode layer of the lower holding capacitor core via the first contact hole (ihc) and the contact hole 12F. The aluminum thus formed is buried (A1) The various wirings, that is, the power supply voltage supply line L, the control line SAML, the upper wiring layer (10), the upper electrode layer 14D, and the intra-cell wiring 14E' are integrally formed with a planarizing film for flattening these steps. 15 (refer to Fig. 16 (B)). As shown in the cross section of Fig. 16 (B), a portion of the planarizing film 15 on the upper electrode layer md is formed with a conductive material embedded in the second layer of the planarizing film 15. The anode contact of the contact hole (2HC) is 5 a. Then, sequentially stacked: an anode electrode (AE) formed on the planarization film 15 and contacting the end face of the anode contact 15A; formed on the anode electrode (AE) Above, and contains a protection of the opening 16 of the anode electrode (AE) for one week 16. Further depositing an organic multilayer film (〇ml) overlying thereon; and forming a shell-shaped cathode electrode (CE) in a pixel-occupying area; thereby forming an organic light-emitting diode OLED. With the above embodiment, In each of the pixel units, only the pixels which are the easiest to form the color of the unlit defect, or the pixels which are only the one with the highest visibility, are respectively provided with the driving transistor, the holding capacitor, and the organic light emitting diode as the complex number. The structure of the group, which is easy to be an unilluminated defect, does not act as an unlit defect, or even if it becomes an unlit defect, it is not significant. 136030.doc • 50- 201003590 is remarkable. As a result, the yield can be improved. The +I 邠 element in the group (the next day, the capacitor, the organic hair 2 diode) does not share the configuration distinction (hierarchy) of the pixel circuit elements, but in the best way of matching efficiency, such as the formation of organic light-emitting diodes The hierarchical level of the body is smaller than the level of the other components, Α έ θ _ m m — , ,, between the pixels with different numbers, the area ratio is reduced. Thereby, the allocation efficiency; ^ ancient, # η . Moreover, the wiring line and the space are properly optimized, and the benefit of reducing the yield due to the short circuit between the lines can be prevented. [Simplified description of the drawing] % / Fig. 1 shows the 眚 l 施 施 关于 关于 关于The main structural diagram of the organic EL display; Fig. 2 is a basic structural diagram of the <pixel circuit> of the K-shaped sorrow of the present invention; Fig. 3 is a diagram relating to the implementation of the present invention. ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; <Pattern of the pixel circuit of the embodiment; Fig. 6(4), called (4) is called (10), and (8), (f) shows a timing chart of various signals and voltage waveforms in the display control of the embodiment of the present invention; Figure 7 (A) - (C) is an explanatory diagram of the operation before sampling; Figure 8 (A) - (C) is an operation explanatory diagram before the second threshold correction; Figure 9 (A), 9 (B) Description of the operation before the third threshold correction; 136030.doc -51 201003590 FIG. 1 is a source potential of an embodiment of the present invention FIG. 11(A)-(C) is an operation diagram before the light-emitting period; FIG. 1 is a pixel circuit according to an embodiment of the present invention, and is short-circuited between electrodes in the organic light-emitting diode. FIG. 13(A) and FIG. 14(B) are diagrams showing a configuration of a pixel unit according to an embodiment of the present invention; FIGS. 14(A) and 14(B) are diagrams showing a pixel according to an embodiment of the present invention. 15(A) and 15(B) are plan views of a pixel circuit according to an embodiment of the present invention; and FIGS. 16(A) and 16(B) relate to the present invention. A cross-sectional view of a pixel circuit in accordance with an embodiment of the present invention. [Main component symbol description] 1 Organic EL display 2 Pixel array 3 Pixel circuit 4 Vertical drive circuit (V scanner) 5 Horizontal drive circuit (H scanner) 10 Base layer 11A Cover gate electrode 11B First high melting point metal wiring layer 11C second high melting point metal wiring layer 11D gate electrode 136030.doc -52- 201003590

12 12A、12B、12C、(1CH)12 12A, 12B, 12C, (1CH)

13A、13B13A, 13B

14B14B

14D14D

14E 1514E 15

16 16A 4116 16A 41

42 AE B42 AE B

CECE

CsCs

Coled.Coled.

Cgs DS⑴Cgs DS(1)

D-CHG DTL(j)D-CHG DTL(j)

G gG g

GNDGND

GM 閘極絕緣膜 接觸孔 TFT層 上層配線層 上部電極層 胞内配線 平坦化膜 保護膜 開口部 水平像素線驅動電路 寫入訊號掃描電路 陽極電極 藍色像素 陰極電極 保持電容器 電容 閘極源極間寄生電容 電源驅動脈衝 放電期間 影像訊號線 綠色像素 電容結合比 接地電壓 閘極金屬層 136030.doc -53- 201003590GM gate insulating film contact hole TFT layer upper wiring layer upper electrode layer intracellular wiring flattening film protective film opening horizontal pixel line driving circuit write signal scanning circuit anode electrode blue pixel cathode electrode holding capacitor capacitance gate source Parasitic capacitance power supply driving pulse discharge during image signal line green pixel capacitance combined with ground voltage gate metal layer 136030.doc -53- 201003590

Id 驅動電流 Ids 汲極電流 INT 初始化期間 LMO、LM1 發光期間 Md 驅動電晶體 Ms 抽樣電晶體 NDc 控制節點 OLED 有機發光二極體 PPx ' PP 影像訊號脈衝 R 紅色像素 SPO〜SP3 抽樣脈衝 SAML 控制線 SIG(l)、SIG(2)、SIG(3)、SIG(j) 訊號線 Ssig 影像訊號 T0-T21 時間顯示 V 施加電壓 Vo 資料基準電位 VDD、VSS 位準 Vin 訊號振幅 Vg 閘極電壓 Vgs 閘極源極間電壓 Vs 源極電位 VSCANl(l)、VSCAN1(2)、 VSCANl(i) 第一掃描訊號 136030.doc -54- 201003590 VSCAN2(1)、VSCAN2(2)、 第二掃描訊號 VSCAN2(i) Vsig 資料電位 Vth 臨限值電壓 Vcc—H 尚電位 Vcc—L 低電位 Vth_oled. 臨限值電壓 Γ Vcath \ VTC1 陰極電位 第一臨限值修正期間 VTC2 WP 第二臨限值修正期間 寫入脈衝 WAT1 第一待機期間 WAT2 第二待機期間 WS(i)、WS(1) 寫入驅動脈衝 Ψ&amp;μ 寫入&amp;移動率修正期間 [j μ 移動率 136030.doc -55-Id drive current Ids 汲 电流 current INT Initialization period LMO, LM1 illuminating period Md driving transistor Ms sampling transistor NDc control node OLED organic light emitting diode PPx ' PP image signal pulse R red pixel SPO~SP3 sampling pulse SAML control line SIG (l), SIG(2), SIG(3), SIG(j) Signal line Ssig Image signal T0-T21 Time display V Applied voltage Vo Data reference potential VDD, VSS level Vin Signal amplitude Vg Gate voltage Vgs Gate Source-to-source voltage Vs Source potential VSCANl(l), VSCAN1(2), VSCANl(i) First scan signal 136030.doc -54- 201003590 VSCAN2(1), VSCAN2(2), second scan signal VSCAN2(i Vsig data potential Vth threshold voltage Vcc-H still potential Vcc-L low potential Vth_oled. threshold voltage Γ Vcath \ VTC1 cathode potential first threshold correction period VTC2 WP second threshold correction period write pulse WAT1 First standby period WAT2 Second standby period WS(i), WS(1) Write drive pulse Ψ&amp;μ Write &amp; Move rate correction period [j μ Movement rate 136030.doc -55-

Claims (1)

201003590 七、申請專利範圍: 1_ 一種顯示裝置,其含有將包含尺(紅)、G(綠)、B(藍)之 N(N = 3)色對連續之N個像素在每丨個像素分配i色而搆成 像素單元,並規則地配置有複數前述像素單元之像素陣 列; W述N個像素之各個中含有: 抽樣電晶體;201003590 VII. Patent application scope: 1_ A display device containing N (N = 3) colors including a ruler (red), G (green), and B (blue) for consecutive N pixels in each pixel a pixel unit is formed by i color, and a pixel array of the plurality of pixel units is regularly arranged; each of the N pixels includes: a sampling transistor; μ保持电今益,其係結合於前述驅動電晶體之發光控制 即點,保持經由前述抽樣電晶體而輸人之資料電壓;及 發光元件,其係與前述_電晶體—起串聯連接於驅 ^電流路徑’依據前述縣電晶體依所保持之前述資料 電遷而控制的驅動電流晋, 特性自發光;^里以各像素所決定之㈣發光 於别述Ν個像素内,在容 或是相對可男声一 自成為未點冗缺陷之特定色 雷曰妒竹疋色的像素中,包含前述驅動 电曰日體、前述保持電容 -f ^ ^ _ °則述赉光元件之像素電路要 京之,、且的數量比其他色的 以上。 素之别述組多,且設有2组 •如請求項1之顯示裝置,兑 或陰極之一方、⑦述毛光元件含有在陽極 與厚度之複數有機薄膜與另…“之色相應的材質 形成於容易成;%前、。'極的多層膜構造; 勿珉马刖述未點亮缺 前述複數有機薄膜之總膜、:特定色的像素内之 述其他色之像素的前述 J36030.doc 201003590 3. 4. 5. 6. 8. 總膜厚小。 如請求項2之心裝置,其中前述其他色之像素中,在 比前述特定色之像素中之前 ’、 — , 月J迹像素電路要素的叙數少之 耗圍内,前述複數有機薄媒 述組。 之、心膜厚愈溥,設愈多之前 如請求項!之顯示裝置’其中前 定色係前述綠(G); 兄度“之特 前述R(紅)與前述B(藍) (G)少。 合像素的别述組數比前述綠 如凊求項1之顯示裝詈,装由—,&amp; ^ # Μ其中在1個前述像素内存在複數 則述組之情況,以前述複數組 致 電晶體。 /、用地6又有1個w述抽樣 如睛求項1之顯示裝置,兑. ,、中在叹於别述Ν個像素内之全 邛則述組中,分別相同地 』边驅動電晶體之通道導 及尺寸,以及前述保持電容器之電容值, 前述像素内設置複數前述發光元 :相同 數路伞-μ 滑况精由將該複 η 几件之雨述驅動電流路徑複數並聯連接於驅動電 昼,供給端子,前述各發光元件被分離。 動電 如叫求項1之顯示裝置’其中對於前述特定色之像素, 以使設有前述崎程度之前述發光元件的鹤部之合 面積,與前述其他色之像素含有之各像素 大致相等的方式,設定前述特定色之像素面Si 述其他色之像素面積大。 如°月求項7之顯示裝置’其中在前述其他色之像素間, 136030.doc 201003590 前述組數不同之情況,以使前述各像素之孔徑部的面積 在像素間大致相同之方式,使像素面積不同。保持 保持 保持 保持 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ^ Current path 'According to the drive current controlled by the above-mentioned county crystal according to the above-mentioned data relocation, the characteristic self-luminous; ^ is determined by each pixel (4) illuminating in a different pixel, in the capacity or The pixel circuit of the calendering element is the same as the pixel of the specific color thunder and the bamboo color which is not the point of redundancy, including the driving electromagnet and the holding capacitor -f ^ ^ _ ° The number of , and is more than the other colors. There are many groups, and there are two groups. • The display device of claim 1, the one of the pair or the cathode, and the seven glare elements contain the material corresponding to the color of the anode and the thickness of the organic film and the other color. It is formed in a multi-layer film structure which is easy to form; % before the 'pole'; the above-mentioned J36030.doc 201003590 3 of the total film of the plurality of organic thin films which are not lit, and the pixels of other colors in the pixels of a specific color are formed. 4. 5. 6. 8. The total film thickness is small. According to the heart device of claim 2, wherein the pixels of the other colors are in the pixels of the specific color before the ', —, In the case of a small number of consumption, the above-mentioned plural organic thin medium is described. The thickness of the pericardium is more and more, and the more the display device is as requested before! The display device in which the front color is the green (G); The above R (red) is less than the aforementioned B (blue) (G). The number of sets of pixels in comparison with the display of the green as the item 1 is loaded by -, &amp; ^ # Μ where a plurality of said pixels exist in a plurality of said groups, and the complex array is used to call the crystal . /, the use of the ground 6 has a description of the sample device, such as the eye of the item 1, in the red, in the sigh of the 像素 Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν Ν The channel guide and size, and the capacitance value of the holding capacitor, the plurality of the illuminating elements are disposed in the pixel: the same number of umbrellas-μ sliding condition is connected by the plurality of singular pieces of the driving current path in parallel The electric power is supplied to the terminals, and the respective light-emitting elements are separated. In the display device of claim 1, the pixel of the specific color is such that the combined area of the cranes provided with the light-emitting elements of the sacrificial level is substantially equal to the pixels included in the pixels of the other colors. In this way, the pixel area of the specific color is set to be larger than the pixel area of the other color. For example, in the case where the display device of the item 7 of the above-mentioned item 7 is different between the pixels of the other colors, 136030.doc 201003590, the area of the aperture portion of each of the pixels is substantially the same between the pixels, so that the pixel is made The area is different. 136030.doc136030.doc
TW098107756A 2008-03-11 2009-03-10 Display device TWI395169B (en)

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