201001640 九、發明說明： 【發明所屬之技術領域】 本發明係令關於一種半導體結構及其製法，尤指 種 封裝基板及其製法。 【先前技術】 隨著電子產業的發達，半導體封裝技術亦隨之開發出 不同的封裝型態，其中，覆晶封裝(Flip Chip心⑽) 技術係將半導體晶片之電極墊直接電性連接封裝基板之 電性接觸墊，而不使用打線式（wirebQnding)之全線， 使得覆晶技術不僅可提高封裝結構佈㈣度，且可降低封 裝結構整體尺寸，以達微型化（化⑷心出加）的封裝 需未’甚至因不需使用導電路徑較長之金線，而可提高: 性功能；請參閱第1A至1 P m 拉丄田，丄 ^ 構之製法。 係提供習知覆晶式封裝結 如弟1A圖所示，首弁，〆么担乂从士 11Λ ^ 无仏釦供表面具有複數電性接 觸墊11 0之基板本體11 ;如第一 η ， 弟1 Β圖所不’於該基板本體 Π及該些電性接觸墊11G上形 I本體 1 9 .. ^ ΒΒ /方知層12，且該防焊層 12形成稷數開孔1 2〇，以斟旛Α 如 十應頒路各該電性接觸墊η〇 ; 不，於顯露之電性接觸墊U0上形成 塊13;如第id圖所干，裎徂&、胃 办成知科凸 口所不，美供—半導體晶 體晶片14具有電極墊ι41 且该+¥ i i 4 i以電性連接谭料 半導體晶片14置於美拓太_ ” 叶凸兒13而使 11Λ 基板本肢11上且電性連接該電性接鈣 墊110 ;如第ΙΕ ®拚-.^ 丈牧成屯|·生接觸 乐α圖所不，取後，於 焊層12之間形成底脒、，a 千钕體日曰片14與防 成底餐15’以包覆焊料凸塊13,且強化半 】10825 5 201001640 導體晶片14與基板本體m之機械性連接。 *之、、4^f知覆晶式封裝結構之製法不易控制底谬15 ，=Λ，^易造成㈣15流動超過預定範圍，即底 :現冢，於製造過程中，當底谬15漫流過基板本 之預定範㈣，該觸15將_在生產治具上 tiirr表面之其他7因此，將造成使用者不 ::具而浪費時間，且若使沾著底谬15 、·貝工作日㈣使底勝15沾著於另一基板本體u表面之A 他部位，而影響接合功效，導致產品的品f不佳。- 發生上述之問題’如何提供一種避免底膠溢流 X 封衣基板’實已成目前亟欲解決的重要課題。 【發明内容】 鑑=上述f知技術之缺失，本發明之主要目的係在於 k-種避免底膠溢流發生之封裝基板及其製法。 某板ίΓΓ目的，本發明揭露—種封裝基板，係包括： 土板本體’其至少一表面具有一置晶區 數電性接觸墊；第一防悝曆,日匕八有硬 性設於該基板本體表面及電 ，且具有複數開孔，以顯露各該電 以及第^方焊層，係設於該第一防谭層上，且具有觸一塾開 口，以頰露部份第一防焊層及電性接觸墊。 們、之封衣基板復可包括焊料凸塊’係設於該電性接 _ ，且該焊料凸塊係可為錫（Sn)、鉛（Pb)、銀（Ag)、 :(Cu)、鋅（Zn)、錢⑻）、銻（Ni)、把⑽或金㈤所組 成之群組。 110825 6 201001640 本發明復提供—種封 ^ ^ ^ 楂封裝基板之製法，係包括：提# .一基板本體，該基板本體至少—表面具有—置晶區，2 , 置晶區上具有複數電性尨έ 且5亥 觸墊上形成第一防焊層， 一包【生接 孔’喻各該電性接觸塾;於該第 ’ 防焊層，且於第二防焊層 小戚昂一 焊層及電性接觸墊。成一開口，以顯露部份第-防 ==、鋅㈤，,，)、_)或金)(： β相較於習知技術，本發明之封裝基板係藉由於第 焊層上設置第二防焊層，且藉由第_ 相卢罢曰「， 〃猎由第一防知層之開口而顯露 位在置aa區上之弟一防焊層及電性接觸墊，以使該 焊層設於置晶區的外圍，相較於習知技術，當殖入底心 晶區時，本發明之第二防焊層具有止擔作用以限制底膠之 流動範圍，而達到避免底膠溢流之目的。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容_ 瞭解本發明之其他優點及功效。 二 請參閱第2A至2E圖，係詳細說明本發明之封妒芙板 及其製法之剖視流程圖。其中，第2C，係為第f 視圖。 圚之上 110825 7 201001640 如第2B圖所示，於該基板本體21表面及該 觸塾川上形成第一防焊層22a，且於該第一防;= /成複數開孔220a，以對應顯露各該電性接觸 之局部表面。 I ϋ·1 第二及2C’圖所示，於該第一防焊層22&上形成 一知曰22b，且於該第二防焊層22b上形成一開口 2 2 0 b ’以顯露位在置曰p 〗 ^仕罝日日£ 21a中之第一防焊層22a及由開 孔22〇a顯露之部份電性接觸塾2n，以^成本發明之封 裝基板。 如第2D圖所示，於後續製程中，該第一防焊層2仏 開孔22Ga中以印刷、電錄或微植球方式形成有谭料凸 塊25，且該焊料凸塊25係為錫（Sn)、鉛（Pb)、銀（Ag)、 2(Cu)、鋅（Zn)、M(Bl)、鎳⑻）、纪（pd)及金（Au)所組 成之群組之其中一者。 如第2E圖所示H，提供一具有作用Φ 26a之半 料體晶片26,且該作用面26a上具有複數電極墊261，以 猎各該電極塾261結合至谭料凸塊25而電性連接該電性 妾觸墊2H，俾使該半導體晶片26設於置晶區如上； ::半導體晶片26之作用面26a與置晶區⑴之間形成 =為南分子樹脂材料所製成之底膠27，藉以包覆該焊料 鬼5並使該半導體晶片26與基板本體21之間形成 110825 8 201001640 良好機械性連接 由於第二防焊層22b的高度高於第一防焊層22a，以 使設於置晶區21a外圍之第二防焊層22b具有止擋作用， 以限制該底膠27之流動範圍，而避免底膠27溢流至該置 晶區21a的外圍。 本發明復揭露一種封裝基板，係包括：基板本體21， 其至少一表面具有一置晶區21a，該置晶區具有複數 電性接觸墊211;第-防焊層22a，係設於該基板本體21 t面及該些電性接觸墊211上，且該第—防焊層22a具有 複數開孔220a，以對應顯露各該電性接觸塾2ιι ;以及第 厂防焊層22b，係設於該第—防焊層，且該第二防 22b具有-開π 22此，以顯露位在該置晶區仏中 之弟一防焊層22a及電性接觸墊211。 焊料封裝基板復包括設於該電性接觸塾211上之 =凸塊25’其材料係為錫（％)、錯⑽）、銀（Ag)、銅 之群組之其中—者。 把⑽及金（Au)所組成 之第本發明之封裝基板主要藉由將具有一開口 之第：防I:设於弟—防焊層上’不僅顯露位在置晶區中 之第m 朗墊，且使弟-防焊層高於置晶區 & 弟一防知層具有止擋作用，而有效達 到避免底膠溢流之目的^ 4 _ 目的，進而提高封裝之良率。 上述貫施例係用以例千柯 效，；也m ]不性5兄明本發明之原理及豆功 政而非用於限制本笋明乂工乂 a ”刀 么月。任何熟習此項技藝 Π0825 9 201001640 . 在不違背本發明之精神及範訂 改。因此本發明之權利保護範圍=述貫施例進行修 圍所列。 應如便述之申請專利範 【圖式簡單説明】201001640 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a package substrate and a method of fabricating the same. [Prior Art] With the development of the electronics industry, semiconductor packaging technology has also developed different package types. Among them, the flip chip package (Flip Chip core (10)) technology directly connects the electrode pads of the semiconductor wafer to the package substrate. The electrical contact pads, instead of the wirebQnding, make the flip chip technology not only improve the package structure (four degrees), but also reduce the overall size of the package structure to achieve miniaturization (4 (heart) plus) The package needs to be 'even because it does not need to use a long gold wire with a conductive path, but can improve: Sexual function; please refer to the 1A to 1 P m method of pulling the field, the structure of the structure. The conventional flip-chip package is provided as shown in Figure 1A. The first 弁, 〆 乂 乂 乂 乂 乂 乂 仏 仏 仏 仏 仏 仏 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板The first body of the substrate body and the electrical contact pads 11G are shaped with a body 1 9 .. ^ ΒΒ / square layer 12, and the solder resist layer 12 forms a plurality of openings 1 2斟幡Α 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如The semiconductor crystal wafer 14 has an electrode pad ι41 and the +¥ ii 4 i is electrically connected to the semiconductor semiconductor wafer 14 to be placed in the Mei Tuo _ _ _ _ _ _ 13 11 and electrically connected to the electrical calcium pad 110; such as the first 拼 拼 - . . . 丈 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · a 钕 钕 曰 14 与 与 与 与 与 与 与 与 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 Cladding The structure of the structure is not easy to control the bottom 谬 15 , = Λ , ^ easy to cause ( four ) 15 flow exceeds the predetermined range , that is , the bottom : now , in the manufacturing process , when the bottom 谬 15 flow through the substrate of the predetermined fan (four) , the touch 15 _In the production fixture, the other 7 of the tiirr surface will cause the user to waste time, and if the bottom 谬15,·Bei working day (4), the bottom win 15 is attached to the other substrate body u A part of the surface, which affects the bonding effect, resulting in poor product quality.- The above problem 'how to provide a primer to avoid overflow X sealing substrate' has become an important issue that is currently being solved. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a package substrate for preventing the occurrence of overfill overflow and a method for fabricating the same. The present invention discloses a package substrate. The method includes: the at least one surface of the earth plate body has at least one surface having a plurality of electrical contact pads; and the first anti-corrosion calendar has a hard surface disposed on the surface of the substrate body and is electrically connected, and has a plurality of openings to reveal each The electric and the second welding layer The first anti-tank layer has a touch-opening opening, and the first solder resist layer and the electrical contact pad are exposed to the cheek portion. The sealing substrate of the sealing substrate may include a solder bump' Connected to _, and the solder bumps may be tin (Sn), lead (Pb), silver (Ag), : (Cu), zinc (Zn), money (8)), niobium (Ni), put (10) or gold (five) 110825 6 201001640 The invention provides a method for manufacturing a package substrate, comprising: a substrate body, the substrate body having at least a surface having a crystallizing region, 2 The crystal region has a plurality of electrical 尨έ and a first solder mask is formed on the 5H touch pad, and a package of "raw holes" is used for each of the electrical contacts; in the 'solderproof layer, and the second solder resist The layer is small and has a solder layer and an electrical contact pad. Forming an opening to reveal a portion of the first-prevention ==, zinc (five),,,), _) or gold) (: β compared to the prior art, the package substrate of the present invention is provided by the second layer on the solder layer The solder mask, and by the _ _ _ 卢 , , , , 由 由 由 由 由 由 由 由 由 由 由 由 由 由 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一The second solder mask of the present invention has a stopping function to limit the flow range of the primer, and is disposed on the periphery of the crystallizing zone, to avoid the bottom gel overflow when the bottom core region is implanted. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can understand the other advantages and effects of the present invention from the disclosure of the present specification. FIG. 2E is a cross-sectional view showing the sealing plate of the present invention and its manufacturing method in detail, wherein the second C is the f-th view. The upper surface 110825 7 201001640 is shown in FIG. 2B on the substrate. Forming a first solder resist layer 22a on the surface of the body 21 and the contact, and in the first defense; a plurality of openings 220a are formed to correspondingly expose a partial surface of each of the electrical contacts. I ϋ·1, as shown in the second and second views, forming a known 22b on the first solder resist layer 22& An opening 2 2 0 b ' is formed on the second solder resist layer 22b to expose the first solder resist layer 22a and the partial electric portion exposed by the opening 22〇a in the stamping date. Contacting the 塾 2n to the package substrate of the invention. As shown in FIG. 2D, in the subsequent process, the first solder resist layer 2 is formed in the opening 22Ga by printing, electro-recording or micro-balling. a bump 25, and the solder bump 25 is tin (Sn), lead (Pb), silver (Ag), 2 (Cu), zinc (Zn), M (Bl), nickel (8), and (pd) And one of the groups consisting of gold (Au). As shown in FIG. 2E, a half-body wafer 26 having a function Φ 26a is provided, and the active surface 26a has a plurality of electrode pads 261 for hunting. Each of the electrodes 261 is coupled to the tantalum bumps 25 to be electrically connected to the electrical contact pads 2H, such that the semiconductor wafers 26 are disposed in the crystallographic region as above; and the active surface 26a and the crystallizing region of the semiconductor wafer 26 (1) Formation between = a primer 27 made of a molecular resin material, thereby covering the solder ghost 5 and forming a good mechanical connection between the semiconductor wafer 26 and the substrate body 21. Since the height of the second solder resist 22b is higher than the first a solder resist layer 22a, so that the second solder resist layer 22b disposed on the periphery of the crystallizing region 21a has a stopper function to limit the flow range of the primer 27, and to prevent the primer 27 from overflowing to the crystallizing region 21a. The present invention recloses a package substrate, comprising: a substrate body 21 having at least one surface having a crystallized region 21a having a plurality of electrical contact pads 211; a first solder mask 22a On the surface of the substrate body 21 t and the electrical contact pads 211, and the first solder mask 22a has a plurality of openings 220a to correspondingly expose the electrical contacts 塾2 ι; and the first solder mask 22b, The second anti-welding layer is disposed on the first solder mask layer, and the second anti-solder layer 22b has an opening π 22 to expose the solder resist layer 22a and the electrical contact pad 211 located in the crystallographic region. The solder package substrate includes a bump 25' provided on the electrical contact pad 211, the material of which is one of a group of tin (%), error (10), silver (Ag), and copper. The package substrate of the present invention comprising (10) and gold (Au) is mainly formed by placing an opening having an opening: anti-I: on the solder-proof layer to not only reveal the m-th position in the crystal-forming region. The pad, and the brother-solderproof layer is higher than the crystallizing area & the first anti-knowledge layer has a stop function, and effectively achieves the purpose of avoiding the overflow of the primer, thereby improving the yield of the package. The above-mentioned examples are used to exemplify the effects of thousands of efficacies; also m] not sexual 5 brothers, the principle of the invention and the peas of the peasant administration, not for limiting the bamboo shoots and gongs a "knife month. Any familiar with this item Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π Π
第ϊ A至1 e圖係為習知覆B 示意圖，1及 «日日切裝結構之製法之剖視 示意圖； 其中，第2CN 【主要元件符號說明】 11，21 基板本體 110,211 電性接觸墊 12 防焊層 120,220a 開孔 13, 25 焊料凸塊 14, 26 半導體晶片 141,261 電極墊 15, 27 底膠 21a 置晶區 22a 第一防焊層 22b 第二防焊層 220b 開口 26a 作用面 110825 10ϊA to 1 e is a schematic diagram of a conventional B, 1 and « a schematic cross-sectional view of the manufacturing method of the daily cutting structure; wherein, 2CN [main symbol description] 11, 21 substrate body 110, 211 electrical contact pads 12 solder mask 120, 220a opening 13, 25 solder bump 14, 26 semiconductor wafer 141, 261 electrode pad 15, 27 primer 21a crystal region 22a first solder mask 22b second solder mask 220b opening 26a active surface 110825 10