201008406 九、發明說明： ΐ 【發明所屬之技術領域】 本發明係減-種連接線路，尤指―種可補償走線上電阻及 電容所造成之訊號傳輸時間延遲之訊號連接線路。 • 【先前技術】 在傳統TFT LCD主動元件陣列基板上，輸出端與輸入端之間 〇有扇出線(fanout，，因為每一輸出端與相連接之輸入端彼此之 間距離不同’因此每條連接走_長度差錄大，而走線的長度 又正比於走線的電阻，造成每條走線的電阻、以及在兩走線間所 形成之電容也都不相同。這些差異會造成同—個訊號在不同的走 線上傳輸的時候，有不同的時間延遲㈣*R*C)。不同的時間延竭 會導致各輸人端接㈣訊號㈣間不—致，造成訊號起始時間不 同步’使電路產生非預期的錯誤結果。請參考第丨圖，第】圖為 ❹先前未考慮等RC配線之一般輸出端與輸入端的接線圖。第i圖中 包含輸入端.⑽，輸出端1U_U8，以及走線l2M28。由第i 圖中可看出這種只單純連結輸人職輸出端的接線方式，會使得 中間走線124及125的距離最短，導致走線124及125㈣阻值 最小’而左右兩側走線121、122、127、128的距離較長，導致走 ⑵、127、128的電阻值較大。如果中間走線和左右兩側 走線的電阻值差雖大，將造成各條走線上訊號傳輸的時間延遲 =異也很大，㈣致錯誤的結果。齡考第2圖。第2圖為根 據此配線方式所得到的一訊號傳輸時間延遲比較圖。在第2圖中， 201008406 輸入端101及1〇4傳送一位準為high的訊號給輸出端⑴及叫， 訊號傳輸時間延遲根據計算公式為：tl=5*R1*cl，， 其中R1為走線121上之電阻值，C1為走線121上之電容值，R4 為走線m上之電阻值，C4為走線以上之電容值，ti為走線⑵ 上之訊號傳輸時間延遲，t4為走線124上之訊號傳輸時間延遲。 因為走線⑵的長度大於走線m，故似則；但各走線間並沒 有互相重㈣區域’因此走線間只錢向電容，但目為樺向電容 ❹的，非常因此電扣和〇可視為.幾乎相同，因此根據前述 之公式計算’ tl>t4。其輸出訊號與輸入訊號的波形如第2圖中所 示。，輸入訊號(以虛線表示)為一方波，而輸出端⑴和ιΐ4的輸出 訊號之波形(以實線表示)則有很明顯的差異。很明顯的由圖中可以 看出訊號上升到位準high的時間u>t4。 為了校正這種訊號在走線上傳輸時間延遲的差異，在傳統的 ❹技射’有人提出了 # RC配線的方法。請參考第3圖。第3圖為 先前技術中已考慮等RC配線的接線圖。第3圖中包含輸入端 201 208 ’輸出端211—218，以及走線221-228。由第3圖可知，設 冲者依&、每條走線的狀況，調整其長度來增加或減少走線的電阻 =例如圖中走'線213、214、215、加被設計成不同的鑛嵩狀以 ^加走線的長度，以達到等RC配線的目的。但此設計的缺點是： 二j上报困難，因為要將每一條走線之阻抗調成一致，就必須計 ^每條走線的電阻值。*且增加走線的長度的作法也會造成設計 二間的增加’在現今電路設計以輕薄短小為目標的趨勢下，這種 6 201008406 增加，線長度的做法，在高密度的TFTLCD主動元件陣列基板 上，實施起來困難重重。此作法也有另—種實施例即縮小走線的 線寬以增加走線的阻抗的作法，但此種作法會因為導線過細，而 導致製程的不良率上升。傳猶法巾也有另外增加補償電容來達 到，RC配線的作法，請參考第4圖，第4 _—根據先前技術， 在每條走線上增加-補償電容以調整該走線的Rc值。第4圖中包 3輸入&311-3Π ’走線32丨_327，以及電容補償電路區之弯曲走 〇線331-337 ’其中彎曲走線331_337分別包含形成補償電容圖案 307此作法的優點是可以依照每—條走線的電阻值的大小， 調整該走線㈣容值，由财可以纽，走線咖27的長度逐漸 變短，也就是電阻值逐漸變小，而補償電容圖案3關7就逐漸辦 加，使得每—敍_ Rc值婦，峨在每條練上的傳輸_ 間（遲⑶有太大的差異。但是此法—樣需要計算每條走線的電阻 值，以搭配所需要增加關觀容值；而且萬—訊號的配線需要 ❹有所改《，整個配線必須簡設計，實施起來非常麻煩。 综合以上所述’在傳統技術的作法當中，如果要達 1己t的目的，TFTLCD絲元㈣縣板的設計者都必須計算名 走線的電阻值及補償電容值，計算 ^ 必須額外增加導線的長度或補償電 碉丞板上 間，並不是非常理想。〜’佔據了玻璃基板很大的空 【發明内容】 201008406 本發明係揭露—稀# 訊號連接線路，包人=種 線訊賴輸時間延遲差異之 線寬之走線。該輸出端， 第η個輪出f ^ ’位於~弟—金屬層，其中苐I個至 働個==哟2" 十線左右對稱， ㈣而之弟1個至第，出端中之每 導通孔，η為-正整數。該2η個輸入端，位於:輪=含- ❹ ㈣ι__輪入端與第㈣個至第2讀==沁 =:仏.輸入端之第_)個至第^ 輸入女而包含-導通孔。該如條等線寬之走線，其中該条 條至第2〇條走線係形成於該第一金屬層，該2。條走 g 2至第2Π條走線之第—端係分別連接於該雜+1)個 第η個輸出端，該第㈣條至第如條走線之第二端係分別連 接於該第1個至第η個輸人端，該2η條走線之第丨條至第η條走 線中之第k條走線包含一形成於一第二金屬層且相對於一第_ 輸出端之導通孔，-形成於一第二金屬層且相對於一第㈣)個輸 入端之導通孔，-第—線路，—走線線段，以及—第二線路。該 第-線路，連接於-形成於該第一金屬層且位於該第㈣輸出端 之導通孔及該形成於該第二金屬層且相對於該^個輸出端之導 通孔。該走線線段，係形成於該第二金屬層上，連接於該形成於 該第二金屬層且相對於該第k個輸出端之導通孔及該形成於該第 二金屬層且相對於該第(η+k)個輸入端之導通孔。該第二線路，連 接於該形成於該第二金屬層且相對於該第(n+k)個輸入端之導通孔 及一形成於該第一金屬層且位於該第(n+k)個輸入端之導通孔。其 8 201008406 【實施方式】 請參考第5圖。第5圖為本 ❹ 5圖中包含8個輸出端卜2、3、二，的4_線圖。第 12、13、14、15、16、17、18 4、5、6、7、8,8個輸入端 11、 8 條走線 21、22、23、24、25、 出端靜二第一金屬層Ml’—第二金屬層Μ2。其中每個輸 (=:成… 4和5的中間)及8個輸入端的中 的中間m同-直線，且各輸出端及輸入端沿著中心 M ^稱剩。輸㈣1、2、3、4各包含-軸於第-金屬層 ^八之第—導通孔61、62、63、64，輸人端15、16、17、18亦各 匕含-形成於第-金屬層M1之第二導通孔7卜％、73、％。走 匕3走線線|又211，一第三導通孔41，一第四導通孔η， r走線2/一之第、線路’以及一走線21之第二線路。走線線段211 糸透過第三導通孔4卜第—導通孔6卜及連接於兩導通孔之間1 有特定圖#之賴導電材質輯成之走線21之第―線路(圖未 丁）連接於輸出端1 ;以及透過第四導通孔5卜第二導通孔^、 及連接於兩導通孔之間具有狀圖案之透明導紐質所構成之走 線21之第二線路(圖未示），連接於輸入端ls。走線22包含一走 201008406 〇 ❹ 線線段221，-第三導通孔42，一第四導通孔^，一走線^ 一線路，以及一走線22之第二線路。走線線段221係透過第三導 通孔42、第—導通孔62、及連接於兩導通孔之間具有特定圖案之 透明導電材質所構成之走線22之第一線路(圖未示），連接出 端2;以及透過第四導通孔52、第二導通孔72、及連接於兩^ 孔之間具有特定_之透日轉電材質所構成之走線22之第二線路 (圖未示），連接於輸入端16。走線23包含-走線線段23卜—第 二導通孔4二，-第四導通孔53，—走線23之第—線路，以及— 走線23之第二線路。走線線段231係透過第三導通孔β、第一導 通孔63、及連接於兩導通孔之間具有特賴案之咖導電材質所 構成之走線23之第一線路(圖未示），連接於輸出端以及透過 第四導通孔53、第二導通孔73、及連接於兩導通孔之間具有特定 圖案之透明導電材質所構成之走線23之第二線路(圖未示）’連接 於輸入端Π。走線24包含—走線線段241，一第三導通孔44，一 第四導通孔54，-走線24之第一線路，以及一走線^之第二線 路。走線線段241係透過第三導通孔44、第一導通孔64、及連接 2導通孔之間具有特定圖案之透明導電材質所構成之走線以之 一線路(圖未不）’連接於輸出端4;以及透過第四導通孔第 ^導通孔74、及連接於兩導通狀間财歡_之透明導電材 ^斤構成之走線山24之第二線路(圖未示），連接於輸入端18。走線 糸、，輸出端5及輪入端u，走線％係連接輸出端6及輸人 墙Λ，卜線27係連接輸出端7及輸人端13，走線28係連接輸出 輸入端14。走線線段21卜功、231、241，第三導通孔4卜 201008406 42、43、44，以及第四導通孔51、52、53、54係形成於第二金屬 層M2，走線25、26、27、28形成於第一金屬層M卜且盘走線線 段川、功、23卜撕等寬。在第5圖中，第二金屬層犯之走 線線段211-241係以虛線表示，第一金屬層M1之走線乃-烈係以 實線表示。輸出端卜2、3、4、5、6、7、8在顶咖主動元 件陣列基板上係為顯示區，輸入端U、12、13、14、15、ΐ6、Η、 18在TFTLCD絲元僻列基板上係為端子區，走線μ、％、 〇 27、28以及走線線段2U、22卜231、241在tft lcd主動元件 陣列基板上係為引線區。 个一亚，價iVlz，以及 基板S。基板S係位於最下方，上方覆蓋第一金屬層M1。第一 屬層M1之上方覆蓋絕緣層1，基板S上方域蓋第-金屬層, ，處，則直接覆蓋絕緣層J。絕緣層IJL方覆蓋第二金屬層M2 第二金屬層M2之上謂覆蓋保護層P。絕緣層I上林覆蓋第 金屬層M2之處，則直接覆蓋保護層p。第三導通孔41則是取 ^保護層P，連接於第二金屬層M2 ;同樣地，第―導通孔& 屈恩直接打穿保護層p及絕緣層1，連接第—金屬物。第一d 金屬層M2之間，有一具有特定圖案之透明㈣ 、冓成之線路互相連接、導通。該具有特定圖案之透明導電材 請參考第6圖。第6圖係為本發明第一實施例之等rc配線圖 的部分導通孔及金屬層的結構示意圖。第6圖包含—第—導通孔 6卜-第三導通孔41，-透明導電材質所構成之線路τ，一保護 層P，一絕緣層ί，一第一金屬層M卜一第二金屬層⑽，以及一 ❹ 就4tr C _ 钍I- η以… —《 201008406 為之線路係由氧化鱗(ITQ)或氧化靖(IZQ)㈣制構成。同樣 地’第-導通孔62、63、64與第三導通孔42、43、44之間，以 及第二導通孔Ή、72、73、74與第四導通孔5卜52、53、54之 間，亦透過相同的方式，分別連接。 由第5圖7知此種拉線方式可以使得每—條走線的長度趨 近於相等’因此每-條走線的電阻值也幾乎相等，形成了趨近等 〇電阻配線。而此時左右兩邊的走線(左邊：走線線段2ΐι_24ι，右 邊.走線25-28)互相對稱並交錯且等寬，在TFTLCD絲元件陣 列基板上形成的-互相重4的區域，而且因為此難線方式，左 右對稱’因此每-條走線上重疊的面積趨近相等，形成每一條走 線上的走線電谷值亦趨近相等。而由於每一條走線上的電阻值和 電令值都非接近，因此此種配線方式，缺傳統的配線方式， 可以產生較接近等RC的配線。走線線段211_241以及走線25_28 ❹可以互為對稱於中心線(也就是輸出端4和5的令間)的扇出狀伽 ⑽），或是對稱於中心線互相平行。請注意：本實施例中，走線、 輸入端、以及輸出端等之數目，只是一個例子，並非用來限定本 發明，本發明能應用於走線、輸入端、以及輸出端等之數目為一 偶數之任何電路。 假設我們要由輸入端15和18向輸出端！和4輸出h钟位譯 的_ ’則訊號傳輸時間延遲根據計算公式為·· ⑽*⑶201008406 IX. INSTRUCTIONS: ΐ Technical Field of the Invention The present invention is a subtractive connection line, especially a signal connection line that can compensate for signal transmission time delay caused by resistance and capacitance on the trace. • [Prior Art] On the traditional TFT LCD active device array substrate, there is a fanout between the output and the input (fanout, because each output and the connected input are at different distances from each other) The length of the strip connection is large, and the length of the trace is proportional to the resistance of the trace, so that the resistance of each trace and the capacitance formed between the traces are also different. These differences will cause the same - When a signal is transmitted on a different line, there is a different time delay (4) *R*C). Deferred time will cause each input to terminate (4) the signal (4) does not cause the signal start time to be unsynchronized, causing the circuit to produce unintended erroneous results. Please refer to the figure, the figure is the wiring diagram of the general output and input of RC wiring that has not been considered before. The i-th image contains the input terminal (10), the output terminal 1U_U8, and the trace l2M28. It can be seen from the i-th figure that the wiring method which only connects the input terminals of the input and output will make the distance between the intermediate traces 124 and 125 the shortest, resulting in the minimum resistance of the traces 124 and 125 (four) and the traces on the left and right sides 121. The distances of 122, 127, and 128 are longer, resulting in larger resistance values of (2), 127, and 128. If the resistance difference between the middle trace and the left and right traces is large, the time delay of the signal transmission on each trace will be large, and the result will be wrong. The second picture of the age test. Figure 2 is a comparison of the transmission time delay of a signal obtained based on this wiring method. In Fig. 2, 201008406 input terminals 101 and 1〇4 transmit a signal with a high signal to the output terminal (1) and call, and the signal transmission time delay is calculated according to the formula: tl=5*R1*cl, where R1 is The resistance value on the trace 121, C1 is the capacitance value on the trace 121, R4 is the resistance value on the trace m, C4 is the capacitance value above the trace, and ti is the signal transmission time delay on the trace (2), t4 The time delay for the signal transmission on trace 124. Because the length of the trace (2) is larger than the trace m, it seems to be; but the traces are not heavy (4) between the traces. Therefore, only the money is transferred to the capacitor, but the order is bifurcated, so the buckle is very 〇 can be regarded as almost the same, so 'tl> t4 is calculated according to the aforementioned formula. The waveforms of the output signals and input signals are shown in Figure 2. The input signal (indicated by the dotted line) is a square wave, and the waveforms of the output signals of the output terminals (1) and ι 4 (shown by solid lines) are significantly different. It is obvious that the time u> t4 when the signal rises to the level high can be seen from the figure. In order to correct the difference in the time delay of transmission of such signals on the traces, a method of #RC wiring has been proposed in the conventional technique. Please refer to Figure 3. Fig. 3 is a wiring diagram of the RC wiring which has been considered in the prior art. Figure 3 includes inputs 201 208 'outputs 211-218, and traces 221-228. It can be seen from Fig. 3 that the rusher adjusts the length of each trace according to the condition of each trace to increase or decrease the resistance of the trace = for example, the lines '213, 214, 215 in the figure are designed to be different. The shape of the ore is increased by the length of the wire to achieve the purpose of RC wiring. However, the disadvantages of this design are: The difficulty of reporting is because the impedance of each trace must be adjusted to the same value. * And increasing the length of the traces will also cause an increase in the design of the second room. 'In the current trend of circuit design aimed at thin and light, this 6 201008406 increase, line length approach, in high-density TFTLCD active device arrays On the substrate, it is difficult to implement. This practice also has another embodiment of reducing the line width of the trace to increase the impedance of the trace, but this practice may result in an increase in the defect rate of the process because the lead is too thin. The Uighur method also has an additional compensation capacitor to achieve, RC wiring, please refer to Figure 4, 4th _ - according to the prior art, add - compensation capacitor on each trace to adjust the Rc value of the trace. In Fig. 4, the packet 3 input & 311-3Π 'the trace 32丨_327, and the curved trace line of the capacitance compensation circuit area 331-337', wherein the curved trace 331_337 respectively contain the advantage of forming the compensation capacitor pattern 307 It is possible to adjust the value of the trace (four) according to the resistance value of each trace, and the length of the tracer 27 is gradually shortened, that is, the resistance value gradually becomes smaller, and the compensation capacitor pattern 3 Guan 7 is gradually added, so that every _ _ Rc value woman, 峨 每 每 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( In order to match the need to increase the value of Guan Guan; and the wiring of the Wan-signal needs to be changed, the entire wiring must be simple design, it is very troublesome to implement. In the above, in the traditional technology, if you want to reach 1 The purpose of the TFTLCD element (4) county board designers must calculate the resistance value of the name line and the compensation capacitor value, calculate ^ must increase the length of the wire or compensate the board between the board, not very ideal. Occupied glass The substrate is very large [invention] 201008406 The invention is disclosed in the thin-signal connection line, the package line = the line width of the difference in the line delay time difference. The output end, the nth round out f ^ 'Located in ~ brother - metal layer, where 苐I to = == 哟 2" tens of lines are symmetric, (4) and the brothers 1 to the first, each of the vias in the exit, η is a - positive integer. The 2η Inputs, located in: wheel = containing - ❹ (four) ι__ wheeled and (4) to 2nd reading == 沁 =: 仏. The input _) to the ^ input female and contain - conduction holes. The line width such as a strip, wherein the strip to the second strand is formed on the first metal layer, the second. The first end of the stripe g 2 to the second strand is connected to the +1)th nth output end, and the second end of the strip (4) to the strip line are respectively connected to the first end From the 1st to the nth input ends, the kth trace of the 2n traces to the nth trace includes a layer formed on a second metal layer and opposite to a first output terminal a via hole, a via hole formed in a second metal layer and opposite to a (four)th input terminal, a -first line, a trace line segment, and a second line. The first line is connected to a via hole formed in the first metal layer and located at the output end of the fourth (four) and a via hole formed in the second metal layer and opposite to the output end. The wiring line segment is formed on the second metal layer, connected to the via hole formed in the second metal layer and opposite to the kth output end, and formed on the second metal layer and opposite to the The via holes of the (n+k)th input terminals. The second line is connected to the via hole formed in the second metal layer and opposite to the (n+k)th input end, and is formed on the first metal layer and located at the (n+k)th Via hole at the input end. 8 201008406 [Embodiment] Please refer to Figure 5. Figure 5 is a 4-line diagram of the eight output terminals 2, 3, and 2 in Figure 5 of the figure. 12, 13, 14, 15, 16, 17, 18 4, 5, 6, 7, 8, 8 inputs 11, 8 traces 21, 22, 23, 24, 25, the first end Metal layer M1' - second metal layer Μ2. Each of the inputs (=: in the middle of ... 4 and 5) and the middle of the 8 inputs are the same - straight line, and each output and input are left along the center M ^ . The input (four) 1, 2, 3, and 4 each include a --axis in the first-metal layer - the first through-holes 61, 62, 63, 64, and the input ends 15, 16, 17, 18 are also included - formed in the - The second via hole 7 of the metal layer M1 is %, 73, %. The 匕3 trace line|and 211, a third via hole 41, a fourth via hole η, r trace 2/one, the line 'and the second line of a trace 21. The line segment 211 糸 passes through the third via hole 4 卜 - the via hole 6 and is connected between the two via holes 1 has a specific map # 导电 conductive material composed of the line 21 of the line - (not shown) Connected to the output terminal 1; and through the fourth via hole 5, the second via hole ^, and the second line connecting the trace 21 formed by the transparent guide material having a pattern between the two via holes (not shown) ), connected to the input ls. The trace 22 includes a walk 201008406 〇 线 line segment 221, a third via hole 42, a fourth via hole ^, a trace ^ a line, and a second line of a trace 22. The wiring line segment 221 is connected through a third via hole 42 , a first via hole 62 , and a first line (not shown) connected to the trace 22 formed by a transparent conductive material having a specific pattern between the two via holes. And a second line (not shown) through the fourth via hole 52, the second via hole 72, and the trace 22 connected to the day-to-day conductive material having a specific _ between the two holes , connected to the input terminal 16. The trace 23 includes a - line segment 23 - a second via 4, a fourth via 53, a first line of the trace 23, and a second line of the trace 23. The line segment 231 is transmitted through the third via hole β, the first via hole 63, and a first line (not shown) connected to the trace 23 formed by the conductive material of the coffee between the two via holes. a second line (not shown) connected to the output end and through the fourth via hole 53, the second via hole 73, and the trace 23 formed by a transparent conductive material having a specific pattern between the two via holes At the input end. The trace 24 includes a trace line segment 241, a third via hole 44, a fourth via hole 54, a first line of the trace 24, and a second line of a trace. The wiring line segment 241 is connected to the output by a trace formed by a transparent conductive material having a specific pattern between the third via hole 44, the first via hole 64, and the via 2 via the connecting via 2 (not shown). And a second line (not shown) connected to the fourth through hole of the fourth through hole, and the second conductive line (not shown) connected to the transparent conductive material of the two conductive forms, connected to the input End 18. The wiring line ,, the output end 5 and the wheel end terminal u, the line % is connected to the output end 6 and the input wall Λ, the line 27 is connected to the output end 7 and the input end 13 , and the line 28 is connected to the output input end 14. The wiring line segments 21, 231, 241, the third via holes 4 201008406 42 , 43 , 44 , and the fourth via holes 51 , 52 , 53 , 54 are formed in the second metal layer M2 , the traces 25 , 26 27, 28 is formed on the first metal layer M and the disk line segment is Sichuan, Gong, 23, and the like. In Fig. 5, the trace line segments 211-241 of the second metal layer are indicated by broken lines, and the traces of the first metal layer M1 are indicated by solid lines. The output terminals 2, 3, 4, 5, 6, 7, 8 are displayed on the top active device array substrate as display areas, and the input terminals U, 12, 13, 14, 15, ΐ6, Η, 18 are in the TFTLCD filament The singular substrate is a terminal area, and the traces μ, %, 〇 27, 28 and the trace segments 2U, 22, 231, and 241 are lead regions on the tft lcd active device array substrate. One Asia, the price iVlz, and the substrate S. The substrate S is located at the bottom, and the upper portion covers the first metal layer M1. The first layer M1 is covered with an insulating layer 1 above, and the upper surface of the substrate S is covered with a first metal layer, and the insulating layer J is directly covered. The insulating layer IJL covers the second metal layer M2. The second metal layer M2 is covered with a protective layer P. Where the forest layer on the insulating layer I covers the metal layer M2, the protective layer p is directly covered. The third via hole 41 is a protective layer P and is connected to the second metal layer M2. Similarly, the first via hole & 屈 directly penetrates the protective layer p and the insulating layer 1 to connect the first metal object. Between the first d metal layers M2, there is a transparent (four) with a specific pattern, and the lines formed are connected to each other and turned on. The transparent conductive material with a specific pattern Refer to Figure 6. Fig. 6 is a view showing the structure of a part of via holes and a metal layer in the rc wiring pattern of the first embodiment of the present invention. Figure 6 includes a first via layer 6 and a third via hole 41, a transparent conductive material, a protective layer P, an insulating layer, a first metal layer, and a second metal layer. (10), and a set of 4tr C _ 钍I- η with ... - "201008406 for the line system consists of oxidized scale (ITQ) or oxidized Jing (IZQ) (four) system. Similarly, between the first via holes 62, 63, 64 and the third via holes 42, 43, 44, and the second via holes 72, 72, 73, 74 and the fourth via holes 5 52, 53, 54 They are also connected in the same way. It can be seen from Fig. 5 that the drawing method can make the length of each of the traces be equal to each other'. Therefore, the resistance values of each of the traces are almost equal, and a nearly equal resistance resistance wiring is formed. At this time, the left and right traces (left: trace segment 2ΐι_24ι, right. trace 25-28) are symmetrical and staggered and are equal in width, forming a region of 4 on the TFTLCD filament element array substrate, and because This difficult line mode is bilaterally symmetric. Therefore, the overlapping areas on each of the traces are nearly equal, and the electric valleys of the traces forming each trace are also nearly equal. Since the resistance value and the electric value of each trace are not close to each other, such a wiring method lacks the conventional wiring method, and can generate wiring closer to the RC. The line segment 211_241 and the line 25_28 ❹ may be mutually symmetrical with respect to the center line (that is, the fan-out gamma (10) of the output terminals 4 and 5), or may be parallel to the center line. Please note that the number of the traces, the input terminals, the output terminals, and the like in this embodiment is only an example, and is not intended to limit the present invention. The present invention can be applied to the number of traces, inputs, and outputs, etc. Any circuit of an even number. Suppose we want to input 15 and 18 to the output! And _ ’ of the 4 output h clock translation, the signal transmission time delay is based on the calculation formula... (10)*(3)
t24=5*R24*C24，其中 Κ2Ϊ 在丰括 οι L 、T R21為走線21上之電阻值，C21為走線2] 201008406 之:合值’ R24為走線24上之電阻值，⑼為走線μ上之電容 ㈣為走線21上之訊號傳輸時間延遲，ί24為走線Μ上之訊 二，脚間延遲。因為走線21和走線％的長度趨近於相等，故 域面值幾Γ等於聰之電阻值；且各走線間互相重疊的區 三、，、乎相等，因此各走線間電容一幾乎相同，即。21之電 容值亦趨近等於C24之電容值。則根據前述之公式計算，卬亦近 〇 t Γ。請參考第7圖。第7圖係為根據本發明所得_訊號傳輸 時間延遲圖。其輸出訊號與輸人訊號的波形如第7财所示專由輸 輸入端15㈣傳來之輸人訊號(以虛線㈣為-方波，而輸出端 1和4的輸人讯叙波形(以實線表示順乎相同。很明顯的由圖 中可以看出訊號上升到位準high的_ m約等於似。各走線上 之訊號上升至位準high的時間愈接近，代表各輸入端接收到訊號 ^時間-致’訊號起始時間同步，愈能防止電路產生非預期的錯 誤結果。 請參考下列之表卜表2及第8圖。表丨係參考第丨圖之傳統 接線方式實驗·之走線長歧電阻差異之味表4 2係參考 第5圖之傳統接線方式實驗測量之走線紐及電阻差異之比較 表。第8關為根據表i及表2晴之電阻差異比較圖。由以上 三圖表中可看出，根據本發明之配線方式所產生之8條走線的電 阻值差異(23.84%)的確遠小於傳統第丨圖之配線方式所產生之8 條走線的電阻值差異(43%)。 13 201008406 走線 走線長度 電阻差異％ (um) 走線1 4.96 43.01 走線2 4.30 23.61 走線3 3.76 7.86 走線4 3.48 0.00 走線5 3.48 0.00 走線6 3.76 7.86 走線7 1.30 23.61 走線8 1.98 13.01 表1 走線 走線長度 電阻差異％ (um) 走線1 9.45 23.64 走線2 10.45 15.82 走線3 11.42 8.72 走線4 12.41 0.00 走線5 12.41 0.00 走線6 11.42 8.02 走線7 10.15 15.82 走線8 9.15 23.81 表2 14 201008406 /請注意：本實施例中，輸出端1-8、輸入端1Μ8、和走線& 係同樣形成於第-金屬層M1，而走線線段21l_24i則形成於第〜 金屬層M2，但本發明並不僅限於此情形，輸出端、輪入端和： 亦可以分別在不同的金屬層，但互相透過導通孔經由透明導^ 質所構成之第-線路以及第二線路相連接，此亦為本發明所^ 之範圍。 ^ Ο ❹ 由上述結果可知，本發明所提出之等Rc配線方式，利用赵 條走線在電路配線上的對稱性，及在不同的金屬層間進行接線， 只需要變更輸出端及輸入端的連接順序(例如輸出端i連接輸 15，而非類似傳統作法中，輸出端丨連接輸人端⑴，並 外去計算各條鱗上的雜電雜，只要配線完成，即可得到等 RC的配線。本發明具備有設計快速、rc差距小，修改容易等優 Γ而且制兩料關金初來配線，也可以使得走線的設計 二間加大’走線之線寬加寬，走線電阻下降，走線彼此間間隔較T24=5*R24*C24, where Κ2Ϊ is the resistance value on the trace 21 in the οι L and T R21, C21 is the trace 2] 201008406: the value of 'R24 is the resistance value on the trace 24, (9) The capacitance on the trace μ (4) is the signal transmission time delay on the trace 21, and the ί24 is the signal on the trace, and the delay between the feet. Because the length of the trace 21 and the trace % are close to each other, the domain value is equal to the resistance value of the clamp; and the three overlaps between the traces are equal, so the capacitance between the traces is almost The same, ie. The capacitance value of 21 also approaches the capacitance value of C24. According to the above formula, 卬 is also close to 〇 t Γ. Please refer to Figure 7. Figure 7 is a graph of the time delay of the signal transmission obtained in accordance with the present invention. The output signal and the input signal waveform are as shown in the seventh financial output of the input signal from the input terminal 15 (4) (with the dotted line (4) as the square wave, and the output signals of the output terminals 1 and 4 (in the The solid line indicates the same. It is obvious from the figure that the signal rises to the level high _ m is approximately equal. The closer the signal on each line rises to the level high, the more the signals are received at each input. ^Time-induced 'signal start time synchronization, the more the circuit can prevent unexpected erroneous results. Please refer to the following table Table 2 and Figure 8. The table is based on the traditional wiring method of the figure. The difference between the long-distance resistance of the line is shown in Table 4. The comparison table of the difference between the resistance and the resistance of the traditional connection method of the conventional wiring method of Figure 5 is shown. The eighth level is the comparison of the resistance difference according to Tables i and Table 2. It can be seen from the three graphs that the difference in resistance value (23.84%) of the eight traces generated by the wiring method according to the present invention is far smaller than the difference in resistance values of the eight traces generated by the conventional wiring pattern of the first graph ( 43%). 13 201008406 Trace length resistance difference %(um) Trace 1 4.96 43.01 Trace 2 4.30 23.61 Trace 3 3.76 7.86 Trace 4 3.48 0.00 Trace 5 3.48 0.00 Trace 6 3.76 7.86 Trace 7 1.30 23.61 Trace 8 1.98 13.01 Table 1 Line length resistance difference % (um) Trace 1 9.45 23.64 Trace 2 10.45 15.82 Trace 3 11.42 8.72 Trace 4 12.41 0.00 Trace 5 12.41 0.00 Trace 6 11.42 8.02 Trace 7 10.15 15.82 Trace 8 9.15 23.81 Table 2 14 201008406 / Please note that in this embodiment, the output terminal 1-8, the input terminal 1Μ8, and the trace & are also formed on the first metal layer M1, and the trace line segment 21l_24i is formed on the first metal layer M2. However, the present invention is not limited to this case. The output end, the wheel end, and the second line may be connected to each other through different conductive layers, but through the via holes through the transparent conductive material. It is also within the scope of the invention. ^ Ο ❹ According to the above results, the Rc wiring method proposed by the present invention utilizes the symmetry of the traces on the circuit wiring and the wiring between different metal layers. Need to change the output And the connection order of the input end (for example, the output terminal i is connected to the input 15 instead of the traditional method, the output terminal is connected to the input end (1), and the noise of each scale is calculated outside, as long as the wiring is completed, the The wiring of the RC, etc. The invention has the advantages of quick design, small rc gap, easy modification, and the first wiring of the two materials, and can also make the design of the wiring line increase the width of the line of the line. The line resistance drops, and the traces are spaced apart from each other.
0，更適合走線高密度的應用(例如高解析度面板），這些都是先前 技術中無法達到的優點。因此本發明實為-應用於TFTLCD 側與Ic聊錄線之處，或ic設計中，内部需要等rc配 、·友的地方等等的最佳電路配線方式。 以上所述僅為本發明之較佳實關，凡依本發明申請專利範 圍所做之均㈣化邮飾，皆闕本發明之涵蓋範圍。 15 201008406 【圖式簡單說明】 第1圖為一傳統作法的實施例的示意圖。 第2圖為一根據傳統配線方式所得到的訊號傳輸時間延遲圖。 第3圖為另—傳統作法的實施例的示意圖。 第4圖為一其它傳統作法的實施例的示意圖。 第5圖為一本發明的實施例的示意圖。 第6圖係為本發明第一實施例之等RC配線圖的部分導通孔及金屬 層的結構示意圖。 第7圖為一根據本發明所得到的訊號傳輸時間延遲圖。 第8圖為根據表1及表2所繪之電阻差異比較圖。 【主要元件符號說明】 1-8,111-118,211-218 11-18,101-108,201-208,311-317 61,62,63,64 71,72,73,74 41,42,43,44 51,52,53,54 21-28,121-128,221-228,321-327 331-337 輸出端 輸入端 第一導通孔 第二導通孔 第二·導通孔 第四導通孔 走線 電容補償電路區之彎、曲走 線 16 201008406 Ml 第一金屬層 M2 第二金屬層 S 基板 I 絕緣層 P 保護層 T 透明導電材質所構成之線 路 〇 211-241 走線線段 301-307 補償電容圖案0, more suitable for high-density applications (such as high-resolution panels), these are the advantages that were not possible in the prior art. Therefore, the present invention is actually applied to the TFT LCD side and the Ic chat line, or in the ic design, the internal circuit needs to be the best circuit wiring method such as rc matching, friends, and the like. The above description is only a preferred embodiment of the present invention, and all of the four (4) postal articles made in accordance with the scope of the present invention are within the scope of the present invention. 15 201008406 [Simple description of the drawings] Fig. 1 is a schematic diagram of an embodiment of a conventional method. Figure 2 is a time delay diagram of signal transmission obtained according to the conventional wiring method. Figure 3 is a schematic illustration of another embodiment of a conventional practice. Figure 4 is a schematic illustration of an embodiment of another conventional practice. Figure 5 is a schematic illustration of an embodiment of the invention. Fig. 6 is a view showing the structure of a part of via holes and a metal layer of the RC wiring pattern of the first embodiment of the present invention. Figure 7 is a timing diagram of signal transmission time delay obtained in accordance with the present invention. Figure 8 is a comparison of resistance differences based on Tables 1 and 2. [Description of main component symbols] 1-8,111-118,211-218 11-18,101-108,201-208,311-317 61,62,63,64 71,72,73,74 41,42,43,44 51,52,53,54 21-28,121-128,221-228,321-327 331-337 Output terminal input terminal first via hole second via hole second · via hole fourth via hole trace capacitance compensation circuit area bend, curved trace 16 201008406 Ml first Metal layer M2 Second metal layer S Substrate I Insulation layer P Protective layer T Transparent conductive material consisting of line 〇211-241 Thread line segment 301-307 Compensation capacitor pattern
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