TW200952119A - Semiconductor device and method of manufacturing same - Google Patents
Semiconductor device and method of manufacturing same Download PDFInfo
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- TW200952119A TW200952119A TW098106059A TW98106059A TW200952119A TW 200952119 A TW200952119 A TW 200952119A TW 098106059 A TW098106059 A TW 098106059A TW 98106059 A TW98106059 A TW 98106059A TW 200952119 A TW200952119 A TW 200952119A
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200952119 六、發明說明: 【發明所屬之技術領域】 【0001】 ’尤關於在該製造方 本發明係關於半導體裝置及其製造方法 法中,將配線構件(導電構件)還原之方法。 【先前技術】 【0002】 Ο 如日本專利公開公報2004—71956所揭示,經過侧 灰化步驟、之狀清洗步_露出之銅(Cu)_,容綠 除去銅(Cu)配線之氧化部,就上部配線層形成之前處理而言,自以 ,係,用NH3等還原氣體或祕氣體,於基板經加熱之狀離進行 ’或利用氬(&賊進行逆賤鑛而除去氧化銅等/ 疋’ ΐ使用還原氣體或鈍性氣體於加熱下進行還原處理, ^曰,於域或碳為主成分之層間絕緣膜造成損害。若利用使用 之” ’祕賴的銅(Cu)會沉積料間絕緣膜ί側 ,特性劣化。又,氬(Ar)撕於銅(Cu)之能量轉移$ 於接:、ί有効率地除去氧化銅(CU〇 4 CU2〇)。另一方φ,由於對 =成絕賴之尤其碳之能量轉移效率高,因此會有^ = :=°1題。於還原處理後進行之阻障膜形成步:Ϊ, 濺鑛(PVD)法’於此情形,對於層間絕緣膜之讎會造成大 【發明内容】 (發明欲解決之問題) 【0004】 的 配線ίΐΪΪί法希錢發祕量抑觸於相職膜之損害 (解決問題之方式) 200952119 【0005】 mm之製造枝猶诚鑲嵌咖丨 經氧化將有機雜氣财氫氣對於 構氣。亦即,本發明例如以下所示。 板之ί=5ίϊΙ為—種半導體裝置之製造方法,製造於基 以下步導構件及絕緣層之半導體裝置,特徵在於包含 絕绫居.板之上方形成導電構件,並於該導電構件上形成 道Ϊ存該導電構件上方之該絕緣層除去;及為了將存 【〇=】構件上之氧倾域還原’將有财錄航氣氣吹氣。[Technical Field] [Technical Field] The present invention relates to a method of reducing a wiring member (conductive member) in a semiconductor device and a method of manufacturing the same. [Prior Art] [0002] As disclosed in Japanese Patent Laid-Open Publication No. 2004-71956, after the side ashing step, the cleaning step _ exposed copper (Cu) _, the green portion removes the oxidized portion of the copper (Cu) wiring, For the treatment before the formation of the upper wiring layer, a reducing gas or a secret gas such as NH3 is used, and the substrate is heated to perform 'or use argon (& thief to perform antimony ore to remove copper oxide, etc. /疋 ' 还原 Use a reducing gas or a passive gas to carry out a reduction treatment under heating, ^ 曰, damage caused by the interlayer insulating film of the domain or carbon as the main component. If the use of the 'secret copper (Cu) will be deposited The insulating film is on the side, and the characteristics are deteriorated. In addition, the energy transfer of argon (Ar) to copper (Cu) is transferred to: ί, efficiently removes copper oxide (CU〇4 CU2〇). The other φ, due to = In particular, the energy transfer efficiency of carbon is high, so there will be ^ = :=°1. The barrier film formation step after reduction treatment: Ϊ, sputtering (PVD) method in this case, for The interlayer insulating film may cause a large [invention] (the problem to be solved by the invention) Line ΐΪΪ 法 法 法 钱 发 发 发 发 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 The present invention is as follows, for example, a method for manufacturing a semiconductor device, a semiconductor device manufactured by using a step guiding member and an insulating layer, and characterized in that a conductive member is formed over the substrate. Forming the insulating layer on the conductive member to remove the insulating layer above the conductive member; and in order to restore the oxygen-deposited region on the [〇=] member, there will be a gas-filled air-gas blow.
:番上述製造方法製造半導置,驗對於通孔及配線 4 a 3絕緣膜等的侧壁造成之損害儘可能減少,且可將經氧 化之配線_'。尤其’制絕緣膜個氟碳化合鮮時,由於氣 碳^匕δ物膜對於因為還原處理而產生之損害的财性低,因此使用 j述方法更有效。藉由儘量減少對於層間絕緣膜之損害,能提高 牛與層間絕緣膜之密合性,能製造高可靠性之半導體裝置C ,吹氣步驟,可更包含:藉由施用微波,而激發有機矽烷氣 ,與氫氣之步驟。藉由將該手法應用於半導體之製造方法,例如 ,要=低溫進行還原處理,因此仍能藉由使用微波激發氣體,有 效的還原配線材料之氧化部分。例如,使用對熱不耐之層間絕緣 膜之情形等為有效的。 【_】 該吹氣步驟’可藉由使該基板溫度從15〇°C上升至350°c之範 圍’將有機矽烷氣體及氫氣吹氣。藉由將該手法應用在半導體之 200952119 於單純對於配線材料之氧化部分吹送有機石夕競氣 ΐϋ 能更有效果的進行氧化部分之還原。 該ϋ人風步驟’亦可使該基板溫度從15〇〇c上升至3⑻。C之範 =將有機魏氣體及氫氣錢。藉由職手法應驗半導體之 1,^·法:她於單純對於配線材料之氧化部分將有機石夕炫氣體 及虱氣吹氣的情形,能更有效的進行氧化部分之 【0011】 ❹ ❹ 該有=财體也可為曱基魏氣體(si(CH3)x)。該有機石夕燒 ,體田y為早y基魏氣體、二甲基魏氣體、三甲基魏氣體 烧氣體等。該吹氣步驟’也可更包含:將該有機石夕炫 亂體吹祕’將氫氣吹氣之步驟。該導電構件,也可由含銅之材 料形成。該絕緣膜也可為氟碳化合物膜或SiCN膜。 【0012】 ' 、本發明之另-祕也可為—種轉财置之製造方法,係製 造於基板之上方具衫層絕緣層之半導難置,特徵在於包含以 下步驟: .於該多層絕緣層⑽成導電構件;除去該多層絕緣層之一部 分’及藉由时鮮層絕緣狀-部分或藉由清洗該多層絕緣 層’於該導f構件氧辦,對於轉電構件之經氧化部分將有機 矽烷氣體及氫氣吹氣而進行還原。 【0013】 ^以上述製造方法製造半導财置,能儘量減少對於通孔 及配線溝内之層間絕緣膜等側壁造成之損害,並將經氧化之配線 還原。尤其,層間絕緣膜使用氟碳化合物等時,由於免碳化合物 膜對於因為還原處理產生之損害的耐性低,因此個上述方法更 有效。藉由儘量減少對於層間絕緣膜之損害,能提高導電構件盘 層間絕緣膜之密合性,能製造高可靠性之半導體裝置。 /、 【0014】 、 該除去步驟,可包含於該多層絕緣層形成開口部之步驟。該 200952119 成阻障該$電構件之經氧化部分還原後’於該開口部形 '驟。該 步驟,可為—種半導體裝置,係藉由包含以下 乂驟之製&方法所製造:於基板上方形 ο 氣體;刻阻擋膜;及對於該導電構件將有祕 【0016】 ,由以上述製造方法製造轉體裝置,能儘量減於 =線溝内之層間絕緣_的儀造成之,且將經氧化之配 還】緣膜使用氟碳化合物等時,由於嫩合 絕懷層間絕緣膜之損害,能提高導電構 絕緣膜之密合性,能製造高可靠性之半導體裝置。The manufacturing method described above produces a semiconductor package, and the damage caused to the sidewalls of the via hole and the wiring 4 a 3 insulating film is minimized, and the oxidized wiring _' can be used. In particular, when the fluorocarbon compounding of the insulating film is performed, since the gas carbon 匕 δ film has low financial property due to the reduction treatment, it is more effective to use the method described. By minimizing the damage to the interlayer insulating film, the adhesion between the bovine and the interlayer insulating film can be improved, and the highly reliable semiconductor device C can be manufactured, and the blowing step can further include: exciting the organic decane by applying microwaves. Gas, the steps with hydrogen. By applying the method to a semiconductor manufacturing method, for example, to carry out a reduction treatment at a low temperature, it is possible to effectively reduce the oxidized portion of the wiring material by using a microwave excitation gas. For example, it is effective to use an interlayer insulating film which is insensitive to heat or the like. [_] The blowing step ' can blow the organic decane gas and the hydrogen gas by raising the substrate temperature from 15 ° C to 350 ° C. By applying this technique to the semiconductor 200952119, it is possible to perform the reduction of the oxidized portion more effectively by simply blowing the organic stone to the oxidized portion of the wiring material. The ϋ人风步骤' also raises the substrate temperature from 15〇〇c to 3(8). The van of C = will be organic Wei gas and hydrogen money. In the case of the semiconductor method, the method of the semiconductor is used. In the case of simply blowing the organic stone and the helium gas in the oxidized part of the wiring material, the oxidation part can be more effectively performed [0011] ❹ ❹ There is also = the financial body can also be thiol Wei gas (si (CH3) x). The organic stone is burned, and the field y is an early y-based Wei gas, a dimethyl Wei gas, a trimethyl Wei gas burning gas, or the like. The blowing step' may further comprise the step of blowing the hydrogen gas by blowing the organic stone. The conductive member may also be formed of a material containing copper. The insulating film may also be a fluorocarbon film or a SiCN film. [0012] ', another secret of the present invention may also be a manufacturing method of the kind of turn-over, which is a semi-conductive hard-wearing layer which is manufactured on the upper layer of the substrate, and is characterized by comprising the following steps: The insulating layer (10) is formed as a conductive member; the portion of the plurality of insulating layers is removed and the portion of the insulating layer is removed by the cleaning of the insulating layer, or by cleaning the multilayer insulating layer, for the oxidized portion of the rotating member The organic decane gas and hydrogen gas are blown and reduced. [0013] By manufacturing the semiconductor package by the above-described manufacturing method, damage to the sidewalls such as the interlayer insulating film in the via hole and the wiring trench can be minimized, and the oxidized wiring can be reduced. In particular, when a fluorocarbon compound or the like is used for the interlayer insulating film, the above method is more effective because the carbon-free compound film has low resistance to damage due to the reduction treatment. By minimizing the damage to the interlayer insulating film, the adhesion of the insulating film between the conductive members and the interlayer can be improved, and a highly reliable semiconductor device can be manufactured. [0014] The removing step may include the step of forming an opening in the plurality of insulating layers. The 200952119 barrier is reduced by the oxidized portion of the $ electrical component. This step can be a semiconductor device manufactured by a method comprising the following steps: a square gas on a substrate; a barrier film; and a secret for the conductive member [0016] The above manufacturing method can be used to manufacture a swivel device, which can be reduced as much as possible by the inter-layer insulation in the trench, and when the oxidized compound is used, the fluorocarbon is used as the edge film, and the interlayer insulating film is not preferable. The damage can improve the adhesion of the conductive insulating film, and can manufacture a highly reliable semiconductor device.
Q 於形成舰刻阻擔膜後,在該侧阻播膜 阻擋膜前,形成貫通該另一層間絕緣膜之開 除去該_ 【0018】 驟ΪΪί :藉由施用微波,使該有财烧氣體及氫 的步驟。藉由_手法細在半導體之製造方法,相較於 早純對於配制料之氧化部分將有财絲體及歧 形,能更有效果的進行氧化部分之還原。 【0019】 斤該吹氣步驟,可藉由使該基板之溫度從15〇〇c上升到35〇 範圍,將該有機魏氣體及氫氣吹氣。藉由將該手法應用於半導 200952119 > ?之製ίί法’她於單純對於配線材料之氧化部分將有機魏 氣體及氫氣吹氣之情形,能更有效果的進行氧化部分 。 【0020】 7' 該有機矽烷氣體亦可為三甲基矽烷氣體。 【0021】 本發明之另一態樣可為一種半導體裝置之製造方法,特徵在 於上=基板上形成多數配線層之步驟中,包含使用有機矽烷氣體 及氫氣將彼此之配線層間之接觸部吹氣之步驟。 【0022】 〇 該吹氣步驟,可更包含:於該有機矽烷氣體及氫氣施用微波 =步驟。該吹氣步驟,可使該基板之溫度從150〇c上升至35〇它之 範圍,將有機矽烷氣體及氫氣吹氣。 (發明之效果) 【0023】 藉由以上述製造方法製造半導體裝置,能儘可能減少對於通 孔及配線溝内之層間絕緣膜等的侧壁造成之損害,且還原經氡化 之配線。尤其,層間絕緣膜使用氟碳化合物等時,由於氟碳化合 物膜對於因為還原處理產生之損害的财性低,因此使用上述方法 更有效。耩由儘量減少對於層間絕緣膜之損害,能提高導電構件 0 與層間絕緣膜之密合性’能製造高可靠性之半導體裝置。 【實施方式】 (實施發明之最佳形態) [0024] 首先,說明本發明半導體裝置之製造方法。本發明之半導體 裝置之製造方法’可採用例如習知之雙重金屬鑲嵌法(DualDam_ ascene)、早一金屬鑲喪法(SingleDamascene)等。本發明之半導體 裝置之製造方法,具體而言包含以下步驟。 【0025】 .於基板上方形成填埋有導電構件之第1層間絕緣膜。 7 200952119 驟、①於第1層間絕緣膜及該導電構件之上形成則阻擋膜之步 g於該蝕刻阻擋臈上形成第2層間絕緣膜及罩蓋層之步驟、 之步f軸貫摘形成第2制絕賴及罩蓋紅職及配線溝 ④藉由蝕刻除去該蝕刻阻擋膜之步驟、 於露出在外部之該導電構件之表面及該通孔及配線溝 内之側壁,吹送有機矽烷氣體及氫氣之步驟、 ⑥ 於該通孔及配線溝内之侧壁形成阻障膜之步驟、 ⑦ 於該通孔及配線溝内沉積導電構件之步驟,及 _^利祕學機械研磨沿料麵研磨,使得料電構件僅殘 留於該通孔及配線溝内之步驟。 【0026】 以下依圖1〜9具體說明上述各步驟。圖1顯示本發明半導體 上形成有第1層間絕緣膜2, ^層間絕緣膜2中填埋有導電構件3。且,於第i層間絕緣膜 導電構件3上形成有蝕刻阻擋膜4。 、 【0027】After the formation of the resistive film, the opening of the insulating film is formed before the side of the film is blocked. [0018] And the step of hydrogen. By the method of manufacturing the semiconductor in a thin manner, the oxidized portion of the preparation material will have a rich body and a shape, and the reduction of the oxidized portion can be performed more effectively. [0019] In the blowing step, the organic Wei gas and the hydrogen gas may be blown by raising the temperature of the substrate from 15 〇〇c to 35 。. By applying this technique to the semi-conductor 200952119 > ί ίί method, she can more effectively carry out the oxidation part by simply blowing the organic Wei gas and hydrogen gas into the oxidized portion of the wiring material. [0020] 7' The organic decane gas may also be a trimethyl decane gas. [0021] Another aspect of the present invention may be a method of fabricating a semiconductor device, characterized in that the step of forming a plurality of wiring layers on the upper substrate comprises blowing the contact portions between the wiring layers of each other using an organic germane gas and hydrogen gas. The steps. [0022] 〇 The blowing step may further comprise: applying a microwave to the organic decane gas and the hydrogen step. The blowing step increases the temperature of the substrate from 150 〇c to 35 〇, and blows the organic decane gas and hydrogen gas. (Effect of the Invention) By manufacturing the semiconductor device by the above-described manufacturing method, damage to the sidewalls of the interlayer insulating film or the like in the via hole and the wiring trench can be reduced as much as possible, and the wiring which has been deuterated can be reduced. In particular, when a fluorocarbon compound or the like is used for the interlayer insulating film, the above method is more effective because the fluorocarbon compound film has low financial property due to damage caused by the reduction treatment. The semiconductor device can be manufactured with high reliability by minimizing damage to the interlayer insulating film and improving the adhesion between the conductive member 0 and the interlayer insulating film. [Embodiment] (Best Mode for Carrying Out the Invention) [0024] First, a method of manufacturing a semiconductor device of the present invention will be described. The method of manufacturing a semiconductor device of the present invention can employ, for example, a conventional dual damascene method (DualDam_ascene), a first metal damascene method (SingleDamascene), and the like. The method for producing a semiconductor device of the present invention specifically includes the following steps. [0025] A first interlayer insulating film in which a conductive member is buried is formed over the substrate. 7 200952119, a step of forming a second interlayer insulating film and a cap layer on the first barrier insulating film and the conductive member, and forming a second interlayer insulating film and a cap layer on the etching stopper, and f-axis forming The second system does not completely cover the red metal and the wiring trenches 4 by etching to remove the etching stopper film, exposing the surface of the conductive member and the sidewalls in the via hole and the wiring trench, and blowing the organic germane gas. And a step of hydrogen, a step of forming a barrier film on the sidewalls of the via hole and the wiring trench, a step of depositing a conductive member in the via hole and the wiring trench, and a step of mechanically grinding the material along the material surface The step of grinding causes the electrical component to remain only in the through hole and the wiring trench. The above steps will be specifically described below with reference to FIGS. 1 to 9. Fig. 1 shows that a first interlayer insulating film 2 is formed on a semiconductor of the present invention, and a conductive member 3 is filled in the interlayer insulating film 2. Further, an etching stopper film 4 is formed on the i-th interlayer insulating film conductive member 3. , [0027]
Chemical Vapor Deposition)法進行。此時,第i層間絕膜 厚’可定為約lOOnm〜300nm。第1層間絕緣膜2可使用例如、 矽(Si〇2)、氮化石夕(SixNy)、氮化珍(siCN)、si〇N、SiCOH、P口 CFX 等。 n H 【0028】 、“ί—方面,導電構件宜由例如1種以上之金屬元素為主成分之 導電材料構成。導電構件宜以銅為主成分。導電構件藉由^刀之 可達成低電阻配線。導電構件此外可使用鋁等。又,在 ]。 可意指以導電構件全體定為100%時,佔有約5〇%以上之 ^等導電構件3之形成,可使_鍍法、電解電鍍法或無電解^ 第1層間絕緣膜2之形成,例如可利用(化學氣相沉 匕 ❹ 200952119 [0029】 另一方面,蝕刻阻擋膜4之形成方法可採用例如〇:^法。蝕刻 阻擋膜4之材質,例如可使用氧化矽(Si〇2)、氮化矽(SixNy)、碳^匕 矽(SiC)及氮化矽(SiCN)、SiON、SiCO、SiCHO等。蝕刻阻撐膜4 之材質使用SiCN時,其成膜氣體例如:甲烷及矽烷、單曱^石夕燒 (MMS)、二甲基矽烷(DMS)、三甲基矽烷(TMS)、四曱基石夕^兀 (TMS)、梦氮烷等。可混合該等氣體使用。又,除了上述氣體,可 添加氮氣(N2)、氣氣(NH3)等並成膜。触刻阻擔膜4之膜厚可定為約 5nm 〜60nm ° 【0030】 其次說明圖2。圖2顯示本發明半導體裝置之製造方法之一步 驟。圖2係於圖1所説明之钱刻阻擋膜4之上進一步形成第2層間絕 緣膜5之步驟。 ' 【0031】 第2層間絕緣膜之形成方法例如CVD法等。第2層間絕緣膜例 如可使用氧化秒(Si02)、氮化石夕(sixNy)、氮化梦(SiCN)、SiON、 SiCOH、CHX、CF#。第2層間絕緣膜’例如更佳為由破原子(c) 及氟原子(F)合成之氟碳化合物膜。在此’所指氟碳化合物膜,例 如可意指於該膜中之構成成分碳原子與氟原子約為1 : 1之比例的 > CF膜。又,CF膜可為例如含有碳原子及氟原子作為該膜構成成分 95%以上,且含有其他成分約5%以下之膜。 【0032】 利用CVD法形成氟碳化合物膜作為第2層間絕緣膜時,原料氣 體(成膜氣體)可使用 c2f4、(:2f6、c3f8、c4f8、c5f8、e6p6、ch2f2、 CHF3等。經成膜之氟碳化合物膜中,可以部分含氫氣。此時,CVD 裝置可使用平行平板型CVD裝置或使用利用了 rlsa(輻射狀槽孔 天線)之微波電漿的CVD裝置其中任一者。又,第2層間絕緣膜之 膜厚以70nm〜280nm為佳。 【0033】 其次說明圖3。圖3顯示本發明中半導體裝置之製造方法之一 9 2〇〇952ii9 2。。圖3顯示於圖2説明之第2層間絕緣膜5之上更形成罩蓋膜6之 【0034】 」一方面’罩蓋膜6之形成方法例如可採ffiCVD法。罩蓋膜6 可使用氧切_)、氮化柳ixNy)、碳化石夕(si〇及 'sico'SiCHo# ° 其石jm、成^體例如甲烧及魏、單甲基矽烷(難习、二甲 2-J^ S)、二曱基矽烷(TMS)、四甲基矽烷(TMS)、矽氮烷等。 二體Ϊ合使用。又,除了上述氣體以外,可添加氣氣 2 师3)等進打成膜。罩蓋膜6之膜厚’可定為約3〇nm〜 【0035】 分,钱刻阻撐膜4與罩蓋膜6可使用同樣材料,作是,兮等可 侧侧娜。罩 。二 通孔及配線溝内之導電構件後發揮⑽ 【0036】 ^次說明圖4。圖4顯示本發明半導體裝置 . 驟。圖4係形成貫通圖3所示第2層間絕/ 步 =之轉。_中,綠孔及配 成具有開π的遮罩。遮罩例 #上^^域形 【0037】 絕緣膜5及罩蓋膜6,可^,劑。其次’ _第2層間 式钱刻法或乾式鞋刻法實施Y及配線溝7。該侧例如可利用濕 其次說明圖5。圖5顯示本發明半導體穿 糊法雜。 ,u^2il9 — 部分8氧化,形成CuO、 外部環魏氛’使導電構件表面 【〇〇38】 將蝕刻阻擋膜4以蝕刻除去後, ,’通常前述導電構件暴露於外部於該步 US分8受氧化,形成CU0、㈣ 表 Ο 【二】該氧化之部分還原,該步驟係為此而實施 層間絕緣膜及她擋膜之側壁或溝二之 :U用圖6所不步驟進行還原處理,則不 居° :疋, 還原。又,若依照f 8完全 ❹ 間絕綾膜改曾夕吟! Λ 還原處理,能得到將第2層 時,可切為由於太、^f ’於第2層間絕'緣膜為氟碳化合物膜 ,^r,r;rc" ^ cf ,缺-‘,且Km;壁受 及配將有機魏氣體及氯吹氣時’可將通孔 上升之狀祕摘錢步驟,能更有效_行氧 又Chemical Vapor Deposition). At this time, the thickness of the i-th interlayer film may be set to be about 100 nm to 300 nm. For the first interlayer insulating film 2, for example, bismuth (Si〇2), nitrite (SixNy), nitridane (siCN), si〇N, SiCOH, P-port CFX, or the like can be used. n H [0028] In the case of ", the conductive member is preferably made of a conductive material containing, for example, one or more kinds of metal elements as a main component. The conductive member is preferably composed of copper as a main component. The conductive member can achieve low resistance by means of a knife. In addition, the conductive member may be made of aluminum or the like. In addition, it may mean that the conductive member 3 is formed in an amount of about 5% or more when the entire conductive member is 100%, and the plating method and the electrolysis can be performed. Electroplating method or electroless plating The formation of the first interlayer insulating film 2 can be utilized, for example, (Chemical Vapor Deposition 200952119) On the other hand, the etching barrier film 4 can be formed by, for example, a method of etching. As the material of the film 4, for example, iridium oxide (Si〇2), tantalum nitride (SixNy), carbon ruthenium (SiC), tantalum nitride (SiCN), SiON, SiCO, SiCHO, or the like can be used. The barrier film 4 is etched. When SiCN is used as a material, the film forming gas is, for example, methane and decane, monoterpene (MMS), dimethyl decane (DMS), trimethyl decane (TMS), and tetrakisyl chloride (TMS). ), dream azane, etc. can be used in combination with these gases. In addition, in addition to the above gases, nitrogen (N2), gas (can be added) NH3) is formed into a film. The film thickness of the resistive resistive film 4 can be set to about 5 nm to 60 nm. [0030] Next, Fig. 2 will be described. Fig. 2 shows one step of the manufacturing method of the semiconductor device of the present invention. The step of forming the second interlayer insulating film 5 on the surface of the resist film 4 illustrated in Fig. 1. [0031] A method of forming the second interlayer insulating film is, for example, a CVD method, etc. The second interlayer insulating film can be, for example, an oxidized second. (Si02), nitrite (sixNy), nitriding dream (SiCN), SiON, SiCOH, CHX, CF#. The second interlayer insulating film 'is more preferably synthesized by breaking atoms (c) and fluorine atoms (F) The fluorocarbon film, as used herein, may mean, for example, a CF film having a ratio of a carbon atom to a fluorine atom of about 1:1 in the film. Further, the CF film may be used. For example, a film containing a carbon atom and a fluorine atom as a constituent component of the film of 95% or more and containing another component of about 5% or less. [0032] When a fluorocarbon film is formed by a CVD method as a second interlayer insulating film, a material gas ( As the film forming gas), c2f4, (: 2f6, c3f8, c4f8, c5f8, e6p6, ch2f2, CHF3, etc. may be used. In the fluorocarbon film, hydrogen may be partially contained. In this case, the CVD apparatus may use either a parallel plate type CVD apparatus or a CVD apparatus using a microwave plasma using rlsa (radiation slot antenna). The film thickness of the second interlayer insulating film is preferably 70 nm to 280 nm. [0033] Next, Fig. 3 will be described. Fig. 3 shows one of the manufacturing methods of the semiconductor device of the present invention 9 2 〇〇 952 ii 9 2 . . Fig. 3 shows that the cover film 6 is further formed on the second interlayer insulating film 5 illustrated in Fig. 2. The method of forming the cover film 6 is, for example, a ffiCVD method. The cover film 6 can use oxygen cut_), nitrided ixNy), carbonized stone (si〇 and 'sico'SiCHo# ° its stone jm, into a body such as a burnt and Wei, monomethyl decane (difficult , dimethyl 2-J^ S), dimethyl decane (TMS), tetramethyl decane (TMS), decazane, etc. The two bodies are used together. In addition to the above gases, a gas can be added. 3) Wait for the film to form. The film thickness ' of the cover film 6 can be set to about 3 〇 nm to 0035 minutes. The same material can be used for the resist film 4 and the cover film 6, and the enamel or the like can be side-side. Cover. After the two via holes and the conductive members in the wiring trench are used (10) [0036] Fig. 4 is explained. Figure 4 shows a semiconductor device of the present invention. Fig. 4 is a transition through the second layer between the second layer shown in Fig. 3. In _, the green hole and the mask have a π opening. Mask example #上^^ Domain shape [0037] The insulating film 5 and the cover film 6 can be used. Next, the Y and the wiring groove 7 are implemented by the second inter-layer money engraving method or the dry shoe engraving method. This side can be utilized, for example, wet. Next, Fig. 5 will be described. Fig. 5 shows the semiconductor paste method of the present invention. , u^2il9 - Part 8 is oxidized to form CuO, external ring Wei's surface of the conductive member [〇〇38] After the etching barrier film 4 is removed by etching, 'usually the aforementioned conductive member is exposed to the outside of the US step 8 is oxidized to form CU0, (4) Table Ο [2] The partial oxidation or reduction of the oxidized layer is performed for this purpose by performing the interlayer insulating film and the sidewall or groove of the film of the barrier film: U is subjected to reduction treatment by the steps of FIG. , then do not live ° : 疋, restore. Also, if you follow the f 8 complete 绫 绫 绫 曾 曾 曾 曾 吟!还原 Reductive treatment, when the second layer can be obtained, it can be cut as the fluorocarbon film of the second layer of the second layer, ^r, r; rc " ^ cf , lack - ', and Km; when the wall is subjected to the organic Wei gas and chlorine blowing, the step of lifting the through hole can be more effective.
若,該既定溫射高至約縦“上而將通孔及配 軋處理,則V電構件(例如Cu)因為_變形之危險古,:二 佳。該既定溫度宜為靴附近以下,若於300t附近t于吹U 11 200952119 理 膜之層2緣膜之密合性更為提高。若考慮對於層間絕緣 於約15G°C〜3贼進行吹氣處理。 (TMS等)以進行。者你闲料勒丈a β日曰 狀雜以料使對熱不耐之層間絕緣膜時,高受織 奸i辦仃還原步驟’但是’但於此情形藉由不升溫, 氣時另可2拖當對於通孔及配線溝内將有機石夕燒氣體及氬氣吹 理。藉由將㈣Γ絲體、氫氣射之—或兩者進行電漿輔助處 還原:電理納人吹氣步驟,能更有效的進行氧化部分之 ,麗與常錄^賴後,藉料人錢雅氣體 行電漿處理而進行還屑虚裡π二〜丨月取粮w个开孤,疋 化時,可你田加還原處可有效率的進行還原。將氣體電漿 平Γ板型之賴產生裝置,或使用採用 ΪΪΪ理料剌錢量之魏,故可儘量不造成·地進行 需要於低溫 進 ❹ 【0043】 另一方面 數分鐘後(約3分鐘等)導入氫氣 石夕烧氣體。 【0044】 又’可於導入氫氣後,導入有機 ❹ 之有機魏氣體之種類不_限定, 例如可 烷最為有效。使用之有機t氣m巧等)等’使用三曱基矽 负機矽烷軋體可僅有1種,也可將多種混合 使用。 【0045】 驟。顯林發明轉·置之製造方法之一步 障膜9之;驟進:所後,於通孔及配線溝内形成阻 障膜9之形成例如可利用濺鍍法進行。在此,沿 12 .200952119 及溝之㈣及罩細表面形姐賴。啡膜形成於 間絕構件之原子侵入層 【0046】 用ϊ’ίϊϊίΐ提高導電構件與第2層間絕緣膜之密合力的作 絕_之2 ίί抑轉電構制含之金屬材_制第2層間 以州μ ΓΓ Tl、T_。阻障膜之膜厚, 〇 ^品〜成為佳。又’阻障膜可以單層構成,也可疊層構成。例 ^丄宜層Ta/TaN時’可藉由以阻障性高之Ta為下層,與Cu之密合 上層’製作高阻雜絲合性之轉膜Γ ° 可於2阻Ϊ膜為含有金屬元素之媒,可僅由金屬元素形成,也 2金f70素以外含有金屬以外之其他元素。該阻障膜可僅含1種 • j*70素’也可含2種以上金屬元素。形成阻障膜時,具有抑制導 電„〇!等}往層間絕賴(CFx等〉擴散的效果。又,阻障膜尚具 有提咼導電構件與層間絕緣膜之密合性的效果。 、'、 【0048】 其次說明圖8。圖8顯示本發明半導體裝置之製造方法之一步 驟。圖8係於通孔及配線溝内形成阻障膜後,導入導電構件⑺之步 驟。在此,將導電構件10充填於通孔及配線溝内,並以覆蓋阻障 膜表面,方式形成導電構件。導電構件以銅為主成分為佳。導 電構件藉由使用銅,能達成低電阻配線。導電構件除. ^吏用銘等。又,在此主成分,也可意指當導電構件全體定為卜二 4 ’佔有約50%以上比例之成分。導電構件之形成,可使用習知方 法°可使用濺鍍法、電解電鍍法或無電解電鍍法等。 【_】 其次說明圖9。圖9顯示本發明半導體裝置之製造方法之一步 驟圖9係導入導電構件10後’將導電構件及阻障膜除去至罩雲'膜 露出於頂面之程度的步驟。導電構件及阻障膜之除去,例如ϋ、 13 200952119 ^ Che^Cal^nical polish 〇 等,i;=;置=此吹 電〇構件暴露於大氣’使前述導電構件i面 ^露於大氣,轉真妹態進行前述各步驟,^ 表面氧化之觀點為較佳。 電構件 【0051】 具體而言,藉由於如圖10及圖u所示,於吹 Ο 前述基板存在之環境為真空狀態,能以ϊ 置占連續通過進行侧錢步驟之處理空間20 ς ,,處理空間21兩方之真空空間。如此,藉由使該半導體^ ίϊΐϊ於^止前述導電構件露出於大氣。圖10所^ 載之裝置,由進d處理之任意真级理_2 〇 之傳送她26、臂25、真空珊馳27、輯她28、置 GV(閥門阳及F〇UP(前開口式通用容器)3〇所構成。另一方面早 11顯示改變—部分_之裝置構成的狀態。圖11顯示_所干僖 送模組26、臂25、GV23、TMS吹氣空間2〇及轉膜形成空間= 圖11顯示對於位在製造步驟中途之半導體裝置,於最初之咖門2〇 進行TMS吹氣步驟後,經由可控制為減壓氛圍之傳送模組某 板,於其次空間21進行阻障膜形成。圖中之箭頭代表使位於^ 步驟中途之半導體裝置移動之順序,首先使該半導體裝置移 空間20,進行吹氣’之後於空間21進行阻障膜形成。進行此 驟之期間,希望保持真空狀態並運送基板。又,就另一方法,藉 由在TMS吹氣處理裝置與阻障膜形成裝置之間以^^现於丨小時以 内輸送’也能保持前述導電構件為真空狀態,防止表面氧化。又, 於圖10及11中,用於使裝置内為真空之裝置可為任意者。 【0052】 〜 14 200952119 以上,可利用上述步驟製造本發明之半導體製造裝置。又, 1進一步視需要反複上述步驟,可形成多層配線。 【0053】 斤、其次’關於對於經氧化之銅配線使用三曱基碎烷(TMS)氣體進 行還巧時之實驗結果,依據圖12〜17進行説明。圖12〜14顯示以 經過還原處理之氧化銅為樣本進行XPS分析之結果。 圖12〜14所示 編號①〜⑧之測定條件,如以下表1所示。 【0054】 【表1】 ΟIf the predetermined temperature is as high as about 縦, and the through hole and the distribution process are performed, the V electrical component (for example, Cu) is old because of the danger of _ deformation: the preferred temperature is preferably below the boot, if In the vicinity of 300t, the adhesion of the film of the layer 2 of the film is further improved. If it is considered that the interlayer insulation is about 15G ° C ~ 3 thieves blow air treatment (TMS, etc.). When you are idle, you can use the material to make the insulation film that is not resistant to heat. When you are in the process of reducing the insulation, you can do the reduction step 'but' but in this case, by not heating up, the gas can be 2 Drag and drop the organic stone gas and argon gas in the through hole and the wiring groove. By (4) the silk body, the hydrogen gas, or both, the plasma assisted reduction: the electric charge blowing step, It is possible to carry out the oxidation part more effectively. After Li and Chang recorded it, the borrower Qian Ya gas is treated with plasma to carry out the swarf π 2 ~ 丨月取粮W an open, 疋化, You can restore it efficiently in the reduction zone of the Tianjia. The gas plasma is used to produce the device, or the amount of money used for the treatment. Wei, so you can try to do it at low temperature. [0043] On the other hand, after a few minutes (about 3 minutes, etc.), hydrogen gas is introduced into the gas. [0044] In addition, after introducing hydrogen, organic is introduced. ❹ The type of organic Wei gas is not limited, for example, the most effective of the alkane. The organic t gas used in the m, etc.), etc. 'The use of the triterpene based negative decane rolling body can be only one type, or a plurality of mixed use. [0045] In the first step, the formation of the barrier film 9 is performed in the via hole and the wiring trench, and the formation of the barrier film 9 can be performed, for example, by sputtering. Here, along with 12.200952119 and the groove (4) and the cover surface, the film is formed in the atomic intrusion layer of the intervening member. [0046] The adhesion between the conductive member and the second interlayer insulating film is improved by ϊ'ίϊϊίΐ 2 ίί 抑 电 电 电 电 电 电 电 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The composition may be laminated, and the case may be made by blocking the Ta/TaN layer. Ta is the lower layer, and the upper layer of Cu is bonded to the upper layer to make a high-resistance hybrid yarn Γ °. The two barrier film is a medium containing a metal element, which can be formed only by a metal element, and other than the gold f70 element. Contains other elements than metals. The barrier film can contain only one type of material. • j*70 element can also contain more than 2 kinds of metal elements. When forming a barrier film, it has the ability to suppress conduction. The effect of diffusion of CFx, etc. Further, the barrier film has an effect of improving the adhesion between the conductive member and the interlayer insulating film. [0048] Next, Fig. 8 will be described. Fig. 8 shows a method of manufacturing the semiconductor device of the present invention. One step. Fig. 8 is a step of introducing a conductive member (7) after forming a barrier film in the via hole and the wiring trench. Here, the conductive member 10 is filled in the through hole and the wiring trench, and the conductive member is formed to cover the surface of the barrier film. The conductive member is preferably composed mainly of copper. The conductive member can achieve low resistance wiring by using copper. Conductive members except . Further, the main component herein may also mean a component in which the entire conductive member is set to have a ratio of about 50% or more. As the conductive member, a conventional method can be used. A sputtering method, an electrolytic plating method, an electroless plating method, or the like can be used. [_] Next, Figure 9 is explained. Fig. 9 shows a step of the method for fabricating the semiconductor device of the present invention. Fig. 9 shows a step of introducing the conductive member 10 and removing the conductive member and the barrier film to the extent that the mask cloud is exposed on the top surface. The removal of the conductive member and the barrier film, for example, ϋ, 13 200952119 ^ Che^Cal^nical polish 〇, i; =; set = the blown electric member is exposed to the atmosphere 'the surface of the conductive member i is exposed to the atmosphere, It is preferable to carry out the above steps in the transition state, and to control the surface oxidation. [0051] Specifically, as shown in FIG. 10 and FIG. u, the environment in which the substrate is blown is in a vacuum state, and the processing space 20 ς which is continuously passed through the side money step can be occupied by the enthalpy, The vacuum space of both sides of the space 21 is processed. In this manner, the semiconductor member is exposed to the atmosphere by the conductive member. Figure 10 shows the device, which is processed by the input of any true level. 传送 传送 她 她 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 The general-purpose container is composed of 3 。. On the other hand, the state of the device of the change-part _ is shown in the early 11th. FIG. 11 shows the dry-feeding module 26, the arm 25, the GV23, the TMS blowing space 2〇, and the transfer film. Forming space = Fig. 11 shows that for the semiconductor device located in the middle of the manufacturing step, after the TMS blowing step is performed in the first coffee door 2, the board is controlled by the transfer module which can be controlled to a reduced pressure atmosphere, and the second space 21 is blocked. The barrier film is formed. The arrow in the figure represents the order in which the semiconductor device located in the middle of the step is moved. First, the semiconductor device is moved into the space 20, and after blowing, the barrier film is formed in the space 21. During this step, It is desirable to maintain the vacuum state and transport the substrate. Further, in another method, the conductive member can be kept in a vacuum state by being transported within the hour after the TMS blowing treatment device and the barrier film forming device. To prevent surface oxidation. Again, in Figure 1 In the cases 0 and 11, the device for making the inside of the device vacuum may be any one. [0052] ~ 14 200952119 The semiconductor manufacturing device of the present invention can be manufactured by the above steps. Further, the above steps can be repeated as needed. Multilayer wiring is formed. [0053] The results of the experiment on the use of trimethyl sulfhydrane (TMS) gas for oxidized copper wiring are described in detail with reference to Figures 12 to 17. Figures 12 to 14 show The result of XPS analysis of the reduced copper oxide is the sample. The measurement conditions of Nos. 1 to 8 shown in Figs. 12 to 14 are as shown in the following Table 1. [0054] [Table 1]
No. XPS分析用樣本處理條件 ① STG 設定溫度300t:,H2 300sccnU200mTorr, 1800秒 ⑦ STG 設定溫度300°C,H2 300sccm,2000mTorr, 300秒 ②&③ STG 設定溫度300°C,TMS lSOsccm^Ar 1 OOsccm^OOOmTorr,1800秒 ④ STG 設定溫度300°C,TMS lSOsccm^Ar lOOsccm, 2000mTorr,30C^、 ⑤ STG 設定溫度300°C,TMS lSOsccir^Ar IOOsccii^ 2000mToiT, 600秒 ⑥ STG 設定溫度300°C,TMS 180sccm,Ar lOOsccm, 2000mTorr,1800秒 ⑧ 未處理 15 【0055】 200952119 二二處:二進表行== 虱虱進仃氧化銅之處理,於銅表面未檢測到飞 mr何處理之樣本處理條件⑧,檢測到銅表: 另-方面’圖13顯示於編號④〜⑧之樣本處理條件 XPS(Si 2P)分析之結果。位於圖13之上段列之5侧巾,顯 由檢測Si 2P光譜,測定可能附著於銅表面之^是否存在。其曰, 4個圖的-部分以圓圈包圍’觀察與此部分相關之資料,未檢測到 Si 2P光譜,可知各樣本表面不存在起因於TMS吹氣之&。 【0057】 ’、 XPS(0 Is)分 所述者相同。 圖14顯示於編號④、⑦及⑧之樣本處理條件, 析結果及XPS(Si2p)分析結果。結果與圖12及圖13 【0058】 其次說明圖15〜17。圖15〜17顯示將經過還原處理之氧化銅 作為樣本進行FT —IR分析之結果。圖15〜17所示編號①〜③之測 定條件,如以下表2所示。 “ 【0059】 【表2】No. XPS analysis sample processing conditions 1 STG set temperature 300t:, H2 300sccnU200mTorr, 1800 seconds 7 STG set temperature 300 ° C, H2 300sccm, 2000mTorr, 300 seconds 2 & 3 STG set temperature 300 ° C, TMS lSOsccm ^ Ar 1 OOsccm^OOOmTorr, 1800 seconds 4 STG Set temperature 300 °C, TMS lSOsccm^Ar lOOsccm, 2000mTorr, 30C^, 5 STG Set temperature 300°C, TMS lSOsccir^Ar IOOsccii^ 2000mToiT, 600 seconds 6 STG Set temperature 300°C , TMS 180sccm, Ar lOOsccm, 2000mTorr, 1800 seconds 8 untreated 15 [0055] 200952119 22: 2 table table == 虱虱 仃 仃 仃 仃 仃 , , , , , , , , , 未 未 未 未 未 未 未 未 未Treatment condition 8, a copper watch was detected: Another aspect 'Figure 13 shows the results of sample processing conditions XPS (Si 2P) analysis under Nos. 4-8. The 5 side flanks located in the upper row of Figure 13 show the detection of the Si 2 P spectrum and the presence or absence of a possible adhesion to the copper surface. Thereafter, the - part of the four graphs is surrounded by a circle. To observe the data relating to this portion, the Si 2 P spectrum was not detected, and it was found that there was no surface due to TMS blowing on each sample surface. [0057] ', XPS (0 Is) is the same as described above. Figure 14 shows the sample processing conditions at Nos. 4, 7, and 8, the results of the analysis, and the results of XPS (Si2p) analysis. Results and Figs. 12 and 13 [0058] Next, Figs. 15 to 17 will be described. Figures 15 to 17 show the results of FT-IR analysis of the reduced copper oxide as a sample. The measurement conditions of Nos. 1 to 3 shown in Figs. 15 to 17 are as shown in Table 2 below. " [0059] [Table 2]
No. FT—IR分析用樣本處理條件 ① STG 設定溫度300°C 1800秒 ②&③ STG 設定溫度300°C,TMS 180sccm,Ar 100sccm,2000mTorr,1800秒 -------_____ 註)STG意指基板載置台。 【0060】 200952119 光譜回^吸^诵,火後之吸收 後之吸收光譜之間,吸收値存有差 ,_1】 為 用之銅氧化物由於氣體回火而還原。 等,只要實施發:論該 當然均屬於本發明之權利範圍/丨”一以任思祕實施, (產業上利用性) φ ❹ [0062] 線:損;儘登:少對於通孔及配 原。 璧绝成之損害,且將經氧化之配線還 【圖式簡單說明】 :;«ΙΪΪ;ΐ;;ί-Γ,4 =知本; ί 於本發明半導體裝置之製造的一l ^ 果 圖12顯二έ於、^明半導體裝置之製造之另-ΐ造梦置 -以經過還原處理之氧化鱗樣本 圖13顯示以經過還原處理之氧化銅為樣本進行XPS分和 果 17 200952119 圖14顯示以經過還原處理之氧化銅為樣本進行XPS分析之結 果。 圖15顯示以經過還原處理之氧化銅為樣本進行FT —IR分析 之結果。 圖16顯示以經過還原處理之氧化銅為樣本進行FT —IR分析 之結果。 圖17顯示以經過還原處理之氧化銅為樣本進行FT —IR分析 之結果。 【主要元件符號說明】 1 基板 2 第1層間絕緣膜 3 導電構件 4 蝕刻阻擋膜 5 第2層間絕緣膜 6 罩蓋膜 7 通孔及配線溝 8 導電構件表面之一部分 9 阻障膜 10 導電構件 20 吹氣空間(空間)(處理空間) 21 阻障膜形成空間(處理空間) 22 真空處理空間No. FT-IR analysis sample processing conditions 1 STG set temperature 300 ° C 1800 seconds 2 & 3 STG set temperature 300 ° C, TMS 180sccm, Ar 100sccm, 2000mTorr, 1800 seconds -------_____ Note) STG It means a substrate mounting table. [0060] 200952119 The spectrum is back to sputum, and the absorption spectrum after absorption after the fire is poor, and the copper oxide used for the reduction is restored by gas tempering. Etc., as long as the implementation of the hair: on the course of the scope of the scope of the invention / 丨" one by the implementation of the secret, (industrial use) φ ❹ [0062] line: damage; Original. 璧 璧 之 , , , , , , , 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化Fig. 12 shows the second έ έ ^ ^ 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Figure 14 shows the results of XPS analysis using reduced copper oxide as a sample.Figure 15 shows the results of FT-IR analysis using reduced copper oxide as a sample. Figure 16 shows the reduced copper oxide as a sample. FT-IR analysis results Figure 17 shows the results of FT-IR analysis using reduced copper oxide as a sample. [Main component symbol description] 1 substrate 2 first interlayer insulating film 3 conductive member 4 etching barrier film 5 2 interlayer insulating film 6 Cover film 7 Through hole and wiring trench 8 Part of the surface of the conductive member 9 Barrier film 10 Conductive member 20 Air blowing space (space) (processing space) 21 Barrier film forming space (processing space) 22 Vacuum processing space
23 GV 25 臂 26 傳送模組 27 真空預備模組 28 裝載模組23 GV 25 Arm 26 Transfer Module 27 Vacuum Preparation Module 28 Load Module
29 裝載埠 FOUP 3029 Loading 埠 FOUP 30
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| CN102803552B (en) * | 2009-06-26 | 2015-06-24 | 东京毅力科创株式会社 | Plasma treatment method |
| US9340880B2 (en) | 2009-10-27 | 2016-05-17 | Silcotek Corp. | Semiconductor fabrication process |
| KR101790206B1 (en) | 2010-10-05 | 2017-10-25 | 실코텍 코포레이션 | Wear resistant coating, article, and method |
| US20120273948A1 (en) * | 2011-04-27 | 2012-11-01 | Nanya Technology Corporation | Integrated circuit structure including a copper-aluminum interconnect and method for fabricating the same |
| US11292924B2 (en) | 2014-04-08 | 2022-04-05 | Silcotek Corp. | Thermal chemical vapor deposition coated article and process |
| WO2017040623A1 (en) | 2015-09-01 | 2017-03-09 | Silcotek Corp. | Thermal chemical vapor deposition coating |
| CN107887323B (en) | 2016-09-30 | 2020-06-05 | 中芯国际集成电路制造(北京)有限公司 | Interconnect structure and method of making the same |
| KR102616489B1 (en) | 2016-10-11 | 2023-12-20 | 삼성전자주식회사 | Method for fabricating semiconductor device |
| CN108231659B (en) * | 2016-12-15 | 2020-07-07 | 中芯国际集成电路制造(北京)有限公司 | Interconnect structure and method of making the same |
| CN106783730B (en) * | 2016-12-28 | 2020-09-04 | 上海集成电路研发中心有限公司 | Method for forming air gap/copper interconnection |
| JP6441989B2 (en) | 2017-04-27 | 2018-12-19 | 株式会社Kokusai Electric | Semiconductor device manufacturing method, substrate processing apparatus, program, and recording medium |
| US11161324B2 (en) | 2017-09-13 | 2021-11-02 | Silcotek Corp. | Corrosion-resistant coated article and thermal chemical vapor deposition coating process |
| US20220235463A1 (en) * | 2019-05-20 | 2022-07-28 | Lam Research Corporation | SixNy AS A NUCLEATION LAYER FOR SiCxOy |
| WO2020252306A1 (en) | 2019-06-14 | 2020-12-17 | Silcotek Corp. | Nano-wire growth |
| US12473635B2 (en) | 2020-06-03 | 2025-11-18 | Silcotek Corp. | Dielectric article |
| US11978668B2 (en) | 2021-09-09 | 2024-05-07 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a via and methods of forming the same |
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| EP1077479A1 (en) * | 1999-08-17 | 2001-02-21 | Applied Materials, Inc. | Post-deposition treatment to enchance properties of Si-O-C low K film |
| JP2001185549A (en) * | 1999-12-24 | 2001-07-06 | Toshiba Corp | Method for manufacturing semiconductor device |
| KR100762863B1 (en) * | 2000-06-30 | 2007-10-08 | 주식회사 하이닉스반도체 | Copper metal wiring method using diffusion-proof titanium-silicon-nitrogen film |
| JP2002319618A (en) * | 2001-04-20 | 2002-10-31 | Anelva Corp | Method and apparatus for forming Cu film for wiring |
| JP2003045960A (en) * | 2001-08-01 | 2003-02-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP4293752B2 (en) * | 2002-02-28 | 2009-07-08 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP2003347299A (en) * | 2002-05-24 | 2003-12-05 | Renesas Technology Corp | Method for manufacturing semiconductor integrated circuit device |
| JP2004071956A (en) | 2002-08-08 | 2004-03-04 | Toshiba Corp | Method for manufacturing semiconductor device |
| JP4454242B2 (en) * | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| KR100912321B1 (en) * | 2003-12-04 | 2009-08-14 | 도쿄엘렉트론가부시키가이샤 | Method of cleaning semiconductor substrate conductive layer surface |
| US7229911B2 (en) * | 2004-04-19 | 2007-06-12 | Applied Materials, Inc. | Adhesion improvement for low k dielectrics to conductive materials |
| US7193325B2 (en) * | 2004-04-30 | 2007-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects |
| JP4473824B2 (en) * | 2005-01-21 | 2010-06-02 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US8211794B2 (en) * | 2007-05-25 | 2012-07-03 | Texas Instruments Incorporated | Properties of metallic copper diffusion barriers through silicon surface treatments |
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