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TW200943533A - A COMS device comprising an NMOS transistor with recessed drain and source areas and a PMOS transistor having a silicon/germanium material in the drain and source areas - Google Patents

A COMS device comprising an NMOS transistor with recessed drain and source areas and a PMOS transistor having a silicon/germanium material in the drain and source areas

Info

Publication number
TW200943533A
TW200943533A TW098106105A TW98106105A TW200943533A TW 200943533 A TW200943533 A TW 200943533A TW 098106105 A TW098106105 A TW 098106105A TW 98106105 A TW98106105 A TW 98106105A TW 200943533 A TW200943533 A TW 200943533A
Authority
TW
Taiwan
Prior art keywords
transistor
drain
source areas
silicon
recessed
Prior art date
Application number
TW098106105A
Other languages
English (en)
Inventor
Jan Hoentschel
Andy Wei
Uwe Griebenow
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200943533A publication Critical patent/TW200943533A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW098106105A 2008-02-29 2009-02-26 A COMS device comprising an NMOS transistor with recessed drain and source areas and a PMOS transistor having a silicon/germanium material in the drain and source areas TW200943533A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008011814A DE102008011814B4 (de) 2008-02-29 2008-02-29 CMOS-Bauelement mit vergrabener isolierender Schicht und verformten Kanalgebieten sowie Verfahren zum Herstellen derselben
US12/258,660 US20090218633A1 (en) 2008-02-29 2008-10-27 Cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silicon/germanium material in the drain and source areas

Publications (1)

Publication Number Publication Date
TW200943533A true TW200943533A (en) 2009-10-16

Family

ID=40936090

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098106105A TW200943533A (en) 2008-02-29 2009-02-26 A COMS device comprising an NMOS transistor with recessed drain and source areas and a PMOS transistor having a silicon/germanium material in the drain and source areas

Country Status (7)

Country Link
US (1) US20090218633A1 (zh)
KR (1) KR101148138B1 (zh)
CN (1) CN101971325B (zh)
DE (1) DE102008011814B4 (zh)
GB (1) GB2470523B (zh)
TW (1) TW200943533A (zh)
WO (1) WO2009108365A1 (zh)

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DE102008049725B4 (de) * 2008-09-30 2012-11-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg CMOS-Bauelement mit NMOS-Transistoren und PMOS-Transistoren mit stärkeren verformungsinduzierenden Quellen und Metallsilizidgebieten mit geringem Abstand und Verfahren zur Herstellung des Bauelements
DE102008054075B4 (de) * 2008-10-31 2010-09-23 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Abgesenktem Drain- und Sourcebereich in Verbindung mit einem Verfahren zur komplexen Silizidherstellung in Transistoren
DE102008064671B4 (de) * 2008-11-28 2011-03-10 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements mit einer Gatestruktur und Erhöhung der Integrität eines Gatestapels mit großem ε durch Schützen einer Beschichtung an der Gateunterseite während des Freilegens der Gateobseite
DE102009047314B4 (de) * 2009-11-30 2011-10-27 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Leistungssteigerung in Transistoren mit einem Metallgatestapel mit großem ε durch Reduzieren einer Breite von Versatzabstandshaltern
DE102009055438B4 (de) 2009-12-31 2014-10-16 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Höhere Integrität einer Gateelektrodenstruktur durch Anwenden eines Opferabstandshalters für die Deckschichtabtragung
KR101675388B1 (ko) * 2010-08-25 2016-11-11 삼성전자 주식회사 반도체 장치의 제조 방법
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US8669146B2 (en) 2011-01-13 2014-03-11 International Business Machines Corporation Semiconductor structures with thinned junctions and methods of manufacture
US8658506B1 (en) 2011-04-06 2014-02-25 Qualcomm Incorporated Method and apparatus for selectively improving integrated device performance
US8921177B2 (en) * 2011-07-22 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating an integrated circuit device
US8815736B2 (en) * 2011-08-25 2014-08-26 Globalfoundries Inc. Methods of forming metal silicide regions on semiconductor devices using different temperatures
US9093554B2 (en) * 2012-05-14 2015-07-28 Globalfoundries Inc. Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
KR101952119B1 (ko) 2012-05-24 2019-02-28 삼성전자 주식회사 메탈 실리사이드를 포함하는 반도체 장치 및 이의 제조 방법
US8735241B1 (en) * 2013-01-23 2014-05-27 Globalfoundries Inc. Semiconductor device structure and methods for forming a CMOS integrated circuit structure
US9508601B2 (en) * 2013-12-12 2016-11-29 Texas Instruments Incorporated Method to form silicide and contact at embedded epitaxial facet
US9324623B1 (en) 2014-11-26 2016-04-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device having active fins
DE102016203154B4 (de) * 2015-12-14 2017-09-28 Globalfoundries Inc. Verfahren zum Bilden einer Halbleitervorrichtungsstruktur
US9960084B1 (en) * 2016-11-01 2018-05-01 United Microelectronics Corp. Method for forming semiconductor device
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Also Published As

Publication number Publication date
DE102008011814B4 (de) 2012-04-26
KR101148138B1 (ko) 2012-05-23
WO2009108365A1 (en) 2009-09-03
GB2470523B (en) 2012-03-21
CN101971325B (zh) 2014-02-19
GB2470523A (en) 2010-11-24
DE102008011814A1 (de) 2009-09-10
KR20100129752A (ko) 2010-12-09
CN101971325A (zh) 2011-02-09
GB201014807D0 (en) 2010-10-20
US20090218633A1 (en) 2009-09-03

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