200941877 九、發明說明： 【發明所屬之技術領域】 本發明為一種電子裝置，特別是一種具有限電流電路 的電子裝置。 【先前技術】 習知適用於功率ic的限電流電路主要是藉由感應輸 出功率電晶體的電流，並轉換感應到的電流為電壓。當發 生過電流（over current)現象或是超載現象（over load) φ 時，透過一比較器比較該電壓與一預設的參考電壓以產生 一回授信號來控制輸出功率電晶體的閘極電壓。藉由控制 輸出功率電晶體的閘極電壓來達到限電流的目的。 【發明内容】 本發明的目的為提供一種結構簡單且可降低溫度與製 程對電晶體的影響的限電流電路。 本發明的一實施例提供一種具有限電流電路的電子裝 置，包括一功率電晶體、一第二電晶體、一壓降控制單元、 ❿一電流複製電路以及一緩衝裝置。該功率電晶體，具有一 源極、一汲極以及一閘極，其中該汲極耦接一電子裝置， 該源極耦接一電壓源。該第二電晶體，具有一第二源極、 一第二汲極以及一第二閘極，其中該第二汲極透過一電流 源耦接一地電位，該第二閘極耦接該功率電晶體的閘極。 該壓降控制單元，具有一第一端與一第二端，其中該第一 端接收一第一電壓，該第二端耦接該第二源極，壓降控制 單元調整致能限電流電路所需的第二電位差，相等於功率 5 200941877 電晶體輸出電流等於限電流值時的源極電位與閘極電位的 一第一電位差。第二電位差相等於第二電晶體的閘極電位 與該第一電壓的電位差。該電流複製電路，耦接該電壓源， 具有一第一電流輸出端與一第二電流輸出端，耦接該功率 電晶體的閘極與該第二閘極。該缓衝裝置，耦接該第一電 流輸出端與該地電位。 本發明的另一實施例提供一種具有限電流電路的電子 裝置，包括一功率電晶體以及一限電流電路。該功率電晶 Φ 體的一寬長比係根據該電子裝置的一最大承受電流所決 定。該限電流電路更包括一第二電晶體以及一壓降控制單 元。該第二電晶體，具有一第二源極、一第二汲極以及一 第二閘極，其中該第二汲極耦接一電流源，該第二閘極耦 接該功率電晶體的閘極。該壓降控制單元，具有一第一端 與一第二端，其中該第一端接收一第一電壓，該第二端耦 接該第二源極，該壓降控制單元調整致能限電流電路所需 的第二電位差，相等於功率電晶體輸出電流等於限電流值 ❿ 時的源極電位與閘極電位的一第一電位差。第二電位差相 等於第二電晶體的閘極電位與該第一電壓的電位差。 本發明的另一實施例提供一種限電流電路，耦接一功 率電晶體，該限電流電路包括包括一第二電晶體、一壓降 控制單元以及一電流複製電路。第二電晶體，具有一第二 源極、一第二汲極以及一第二閘極，其中該第二汲極透過 一電流源辆接一地電位，該第二閘極耦接該功率電晶體的 閘極。壓降控制單元，具有一第一端與一第二端，其中該 6 200941877 第一端接收一第一電壓，該第二端耦接該第二源極。電流 複製電路，耦接該電壓源，具有一第一電流輸出端，耦接 一缓衝裝置與一第二電流輸出端，耦接該第二閘極。當該 功率電晶體的閘源極電壓大於致能限電流電路所需的第二 電位差時，該電流複製電路被致能，並提升該功率電晶體 的閘極的電壓’使流經該功率電晶體的電流為一限電流值。 【實施方式】 第1圖為根據本發明之一種具有限電流電路的電子裝 φ 置的一實施例的示意圖。在本實施例中，主控制單元14 為電子裝置11的一部分，用以根據電子裝置11所需的電 流大小，控制功率電晶體Ml的閘極電壓。功率電晶體Ml， 具有一源極、一没極以及一閘極，其中該没極粞接電子裝 置11，該源極耦接第一電壓。在本實施例中，功率電晶體 Ml和主控制單元14的組合可能為一電源管理積體電路 (integrated circuit ’ 1C )、低壓降穩壓器（low dropout linear regulator，LD0)或是 AB 級放大器（class AB amplifier) ❿（）。第二電晶體M2，具有一第二源極、一第二汲極以及一 第二閘極，其中該第二汲極透過電流源18耦接一地電位， 該第二閘極耦接該功率電晶體Ml的閘極。壓降控制單元 17，具有一第一端與一第二端，其中該第一端耦接一第一 電壓VI，該第二端耦接該第二源極。該壓降控制單元17 用以調整致能限電流電路所需的第二電位差，大略相等於 功率電晶體輸出電流等於限電流值時的源極電位與閘極電 位的一第一電位差。第二電位差相等於第二電晶體的閘極 7 200941877 電位與該第一電壓的電位差。在本實施例中，壓降控制單 元17包括一個或複數個二極體。電流複製電路15，耦接 第一電壓，具有一第一電流輸出端與一第二電流輸出端， 其中該第二電流輸出端耦接該功率電晶體Ml的閘極與該 第二閘極。在本實施例中，主控制單元14為增加流經功率 電晶體Ml的電流，會將功率電晶體Ml的閘級電位下拉。 當電晶體Ml的閘級電位低於一預定電位或該第一電位差 大於致能限電流電路所需的第二電位差時，電流複製電路 φ 15被致能且第二電晶體M2被導通。電流複製電路15提升 功率電晶體Ml的閘極的電壓，並與主控制單元14取得平 衡，使功率電晶體Ml的閘級電位VG維持一預定值，如 此一來流經功率電晶體Ml的電流為一預定的限電流值。 在本實施例中，會先根據本電子裝置所能承受的一最 大電流值，來決定功率電晶體Ml的寬長比（W/L)。當 該功率電晶體Ml的閘源極電壓大於致能限電流電路所需 的第二電位差時，電流複製電路15被致能且第二電晶體 G M2被導通。電流複製電路15提升功率電晶體Ml的閘極 的電壓，並與主控制單元14達成平衡，使流經功率電晶體 Ml的電流為一預定的限電流值。 第2圖為根據本發明之一種具有限電流電路的電子裝 置的一實施例的示意圖。功率電晶體Μ1，具有一源極、一 汲極以及一閘極，其中該汲極耦接電子裝置21，該源極耦 接第一電壓VI。功率電晶體Ml和主控制單元23的組合 可能為一電源管理積體電路（integrated circuit，1C )、低 8 200941877 壓降穩壓器（low dropout linear regulator，LDO )或是 ❹ 級放大器（class AB amplifier)。第二電晶體M2,具有 第二源極、一第二汲極以及一第二閘極，其中該第二、友桠 透過電流源24耦接一地電位，該第二閘極耦接該功率 體Ml的閘極。壓降控制單元22，具有一第一端輿〜曰曰 端，其中該第一端耦接—第一電壓V1，該第二端輛 〜 二源極。該壓降控制單元22用以調整致能限電流電路= 的第一電位差’大略相等於功率電晶體輸出電流等: 流值時的源極電位與間極電位的一第一電位差。第二：電 差相等於第-電晶體的閘極電位與差立 在本實施例中，壓降控击丨„ — ^ 电位差。 負載元件或二極體，复士 电丨且 _ ^ x/rc 具中二極體可以由電晶體所形成。第 五電晶體M5’具有一笛 x第 極，其中該第五源極粞接五:極二第五汲極以及-第五閘 W搞笛-雷曰μ接第一電壓，該第五沒極麵接該第 及一第六閘極，其中‘、有源極、一第-汲極以 極輕接該第二閘極，^六源_接第—電壓，該第六沒 ^ 邊第六閘極耦接該第五閘極。 電阻R2、第四電# 16。$ 雜如第1圖中 的緩衝器16。第四電 汲極以及-第㈣括—第㈣極、一第四 該第四>及_接該該第四閘極耦接該第二沒極， 笛一〜过笛五及極。電阻尺2,具有一第一端與一 耦接該第四閘極。電容el耦接該第二 電阻的第一端與該地蛩 ^ 單元23為增加流經功率^間。。在本實施例中，主控制 车電晶體Ml的電流，會將功率電晶 9 200941877 體Ml的閘級電彳 -預定電位或該第一：拉。當電晶體M1的間級電位低於 二電位差時，第雷電位差大於致能限電流電路所需的第 fr、dr道 第〜電晶體M2被導通，此時第四曾 第 亦被導通。當第四 吁乐四電晶體M4 的問極被下拉到地被導\時，第五電晶體 六電晶體Μ6所形更㈣冑日日體Μ5與第 雪曰# λλ 成的電流鏡電路被致能。此時，备Mi ::體，極的電壓因受到第六電晶體= 單電晶體M1的閘極的電壓亦同時受到主控制 平衡，使^^最終功率電晶體M1的閘極的電麼會趨於 使抓、左該功率電晶體M1的電流為本電子 限電流值。 、且的一 第3圖為根據本發明之一種具有限電流電路的電子裝 置的另一實施例的示意圖。功率電晶體Ml，具有一源極、 一汲極以及一閘極’其中該汲極耦接電子裝置31，該源極 輕接第一電壓。在本實施例中，功率電晶體Ml和主控制 單兀33的組合可能為一電源管理積體電路（integrated ⑩ circuit ’ 1C )、低壓降穩壓器（l〇w dropout linear regulator， LDO)或是AB級放大器（class AB amplifier)。第二電晶 體M2’具有一第二源極、一第二汲極以及一第二閘極，其 中該第二汲極透過電流源32耦接一地電位，該第二閘極耦 接該功率電晶體Ml的閘極。第一電阻ΙΠ，具有一第一端 與一第二端，其中該第一端耦接於該第一電壓。第三電晶 體M3，具有一第三源極、一第三汲極以及一第三閘極，其 中該第三源極辆接該第一電阻R1的第二端，該第三汲極 200941877 與該第三閘極耦接該第二源極。第一電阻R1與第三電晶 體M3用以調整該第二電晶體M2的閘極電位與該第一電 壓的一第二電位差大略相等於該功率電晶體Ml的源極電 位與閘極電位的一第一電位差。在本實施例中，更包括至 少一個或複數個二極體耦接在該第三電晶體M3與該第二 電晶體M2之間，其中二極體可以由電晶體所形成。 第五電晶體M5，具有一第五源極、一第五汲極以及一 第五閘極，其中該第五源極耦接第一電壓，該第五汲極耦 φ 接該第五閘極。第六電晶體M6，具有一第六源極、一第六 汲極以及一第六閘極，其中該第六源極耦接第一電壓，該 第六汲極耦接該第二閘極，該第六閘極耦接該第五閘極。 一第一二極體，耦接該第一電阻的第二端與該第二電晶體 的源極。電阻R2、第四電晶體M4與電容C1形成如第1 圖中的緩衝器16。第四電晶體M4，包括一第四源極、一 第四汲極以及一第四閘極，其中該第四閘極耦接該第二汲 極，該第四汲極耦接該第五汲極。電阻R2,具有一第一端 ❹ 與一第二端，該第一端耦接該第四閘極。電容C1耦接該 第二電阻的第二端與該地電位之間。在本實施例中，主控 制單元33包括一控制器35以及一比較器34。控制器35 接收一控制信號Sc以產生一控制電壓Vc。比較器34根據 一參考電壓Vref與該控制電壓Vc來控制功率電晶體Ml的 閘極電壓VG。在本實施例中，主控制單元33為增加流經 功率電晶體Ml的電流，會將功率電晶體Ml的閘級電位 下拉。 11 200941877 當功率電晶體从1的問極電壓被透過主控制單元33下 拉（pulldown)至低於〆觸發點（triggerp〇int)時，第二 電晶體M2被導通，此時第四電晶體M4亦被導通。當第 四電晶體M4被導通時，第五電晶體M5的閘極被下拉而 導通，使得第五電晶體Μ5與第六電晶體M6所形成的電 流鏡電路被致能。此時功率電晶體Ml的閘極的電壓因受 到第六電晶體M6導通而提面’且功率電晶體Ml的閘極 的電壓亦同時受到主控制單元33控制，而最終功率電晶體 ❹Ml的閘極的電壓會趨於平衡，使使流經該功率 的電流為本電子裝置的一限電流值。 雖然本發明已以具體實施例揭露如上，然其僅為了易 於說明本發明之技術内容，而並非將本發明狹義地限定於 該實此例任何所屬技術領域巾具有通常知識者’在不脫離 發明之精神和範圍内，當可作些許之更動與潤飾，因此本 發明之保遵圍當视後附之申請專利範圍所界定者為準。 ❹ 12 200941877 【圖式簡單說明】 第1圖為根據本發明之一種具有限電流電路的電子裝 置的一實施例的示意圖。 第2圖為根據本發明之一種具有限電流電路的電子裝 置的一實施例的示意圖。 第3圖為根據本發明之一種具有限電流電路的電子裝 置的另一實施例的示意圖。 馨 【主要元件符號說明】 11、21、31〜電子裝置 12〜限電流電路 14、23、33〜主控制單元 15〜電流複製電路 16〜緩衝器 17、 22〜壓降調整單元 18、 24、32〜電流源 ❿ 34〜比較器 35〜控制器 13200941877 IX. Description of the Invention: [Technical Field] The present invention is an electronic device, and more particularly, an electronic device having a current limiting circuit. [Prior Art] A current-limiting circuit suitable for power ic is mainly used to induce a current of a power transistor and convert the induced current to a voltage. When an over current phenomenon or an over load φ occurs, the comparator compares the voltage with a predetermined reference voltage to generate a feedback signal to control the gate voltage of the output power transistor. . The current limit is achieved by controlling the gate voltage of the output power transistor. SUMMARY OF THE INVENTION An object of the present invention is to provide a current limiting circuit which is simple in structure and which can reduce the influence of temperature and process on a transistor. An embodiment of the invention provides an electronic device having a current limiting circuit, including a power transistor, a second transistor, a voltage drop control unit, a first current replica circuit, and a buffer device. The power transistor has a source, a drain, and a gate, wherein the drain is coupled to an electronic device, and the source is coupled to a voltage source. The second transistor has a second source, a second drain, and a second gate, wherein the second drain is coupled to a ground potential through a current source, and the second gate is coupled to the power The gate of the transistor. The voltage drop control unit has a first end and a second end, wherein the first end receives a first voltage, the second end is coupled to the second source, and the voltage drop control unit adjusts the enable current limiting circuit The required second potential difference is equal to the first potential difference between the source potential and the gate potential when the power output current of the transistor is equal to the current limit value. The second potential difference is equal to the potential difference between the gate potential of the second transistor and the first voltage. The current replica circuit is coupled to the voltage source and has a first current output terminal and a second current output terminal coupled to the gate of the power transistor and the second gate. The buffer device is coupled to the first current output terminal and the ground potential. Another embodiment of the present invention provides an electronic device having a current limiting circuit including a power transistor and a current limiting circuit. A width to length ratio of the power transistor Φ body is determined according to a maximum withstand current of the electronic device. The current limiting circuit further includes a second transistor and a voltage drop control unit. The second transistor has a second source, a second drain, and a second gate, wherein the second gate is coupled to a current source, and the second gate is coupled to the gate of the power transistor pole. The voltage drop control unit has a first end and a second end, wherein the first end receives a first voltage, the second end is coupled to the second source, and the voltage drop control unit adjusts the enable current limit The second potential difference required by the circuit is equal to a first potential difference between the source potential and the gate potential when the power transistor output current is equal to the current limit value ❿. The second potential difference phase is equal to the potential difference between the gate potential of the second transistor and the first voltage. Another embodiment of the present invention provides a current limiting circuit coupled to a power transistor, the current limiting circuit including a second transistor, a voltage drop control unit, and a current replica circuit. The second transistor has a second source, a second drain, and a second gate, wherein the second drain is connected to a ground potential through a current source, and the second gate is coupled to the power The gate of the crystal. The voltage drop control unit has a first end and a second end, wherein the first end of the 6 200941877 receives a first voltage, and the second end is coupled to the second source. The current replica circuit is coupled to the voltage source and has a first current output terminal coupled to a buffer device and a second current output terminal coupled to the second gate. When the gate voltage of the power transistor is greater than a second potential difference required by the enable current limiting circuit, the current replica circuit is enabled and boosts the voltage of the gate of the power transistor to flow through the power The current of the crystal is a current limit value. [Embodiment] Fig. 1 is a schematic view showing an embodiment of an electronic device having a current limiting circuit according to the present invention. In the present embodiment, the main control unit 14 is a part of the electronic device 11 for controlling the gate voltage of the power transistor M1 according to the current required by the electronic device 11. The power transistor M1 has a source, a gate, and a gate, wherein the gate is coupled to the electronic device 11, and the source is coupled to the first voltage. In this embodiment, the combination of the power transistor M1 and the main control unit 14 may be a power management integrated circuit (1C), a low dropout linear regulator (LD0) or a class AB amplifier. (class AB amplifier) ❿ (). The second transistor M2 has a second source, a second drain, and a second gate. The second drain is coupled to the ground potential through the current source 18, and the second gate is coupled to the power. The gate of the transistor M1. The voltage drop control unit 17 has a first end and a second end, wherein the first end is coupled to a first voltage VI, and the second end is coupled to the second source. The voltage drop control unit 17 is configured to adjust a second potential difference required for the enable current limiting circuit to be substantially equal to a first potential difference between the source potential and the gate potential when the power transistor output current is equal to the current limit value. The second potential difference is equal to the potential difference between the potential of the gate 7 200941877 of the second transistor and the first voltage. In the present embodiment, the voltage drop control unit 17 includes one or a plurality of diodes. The current replica circuit 15 is coupled to the first voltage and has a first current output terminal and a second current output terminal, wherein the second current output terminal is coupled to the gate of the power transistor M1 and the second gate. In the present embodiment, the main control unit 14 pulls down the gate potential of the power transistor M1 to increase the current flowing through the power transistor M1. When the gate potential of the transistor M1 is lower than a predetermined potential or the first potential difference is greater than the second potential difference required for the enable current limiting circuit, the current replica circuit φ 15 is enabled and the second transistor M2 is turned on. The current replica circuit 15 boosts the voltage of the gate of the power transistor M1 and balances with the main control unit 14 to maintain the gate potential VG of the power transistor M1 at a predetermined value, thus flowing through the power transistor M1. Is a predetermined current limit value. In this embodiment, the aspect ratio (W/L) of the power transistor M1 is determined according to a maximum current value that the electronic device can withstand. When the gate-source voltage of the power transistor M1 is greater than the second potential difference required for the enable current-limiting circuit, the current replica circuit 15 is enabled and the second transistor G M2 is turned on. The current replica circuit 15 boosts the voltage of the gate of the power transistor M1 and balances with the main control unit 14 so that the current flowing through the power transistor M1 is a predetermined current limit value. Figure 2 is a schematic illustration of an embodiment of an electronic device having a current limiting circuit in accordance with the present invention. The power transistor Μ1 has a source, a drain and a gate, wherein the drain is coupled to the electronic device 21, and the source is coupled to the first voltage VI. The combination of the power transistor M1 and the main control unit 23 may be a power management integrated circuit (1C), a low 8 200941877 low dropout linear regulator (LDO) or a ❹ stage amplifier (class AB). Amplifier). The second transistor M2 has a second source, a second drain, and a second gate. The second gate is coupled to the ground potential through the current source 24, and the second gate is coupled to the power. The gate of the body M1. The voltage drop control unit 22 has a first end 曰曰 曰曰 end, wherein the first end is coupled to the first voltage V1, the second end to the second source. The voltage drop control unit 22 is configured to adjust the first potential difference of the enable current limiting circuit = to be substantially equal to the power transistor output current or the like: a first potential difference between the source potential and the interpole potential. Second: the electrical difference is equal to the gate potential of the first transistor and the difference is in the present embodiment, the voltage drop is controlled by 丨 — — potential difference. The load component or diode, the rendezvous and the _ ^ x The /rc has a middle diode which can be formed by a transistor. The fifth transistor M5' has a flute x pole, wherein the fifth source is connected to five: the pole 2 fifth pole and the fifth gate W The flute-Thunder is connected to the first voltage, and the fifth pole is connected to the first and sixth gates, wherein the source pole and the first pole are extremely lightly connected to the second gate. The source_ is connected to the first voltage, and the sixth gate is coupled to the fifth gate. The resistor R2 and the fourth power #16. $ is similar to the buffer 16 in Fig. 1. The fourth power a pole 2 - a fourth (4) pole, a fourth fourth, and a fourth pole connected to the second pole, a flute 1 - a flute 5 and a pole. The first end is coupled to the fourth gate. The capacitor el is coupled to the first end of the second resistor and the ground unit 23 to increase the flow of power. In this embodiment, the main control The current of the car's electric crystal M1 will power晶 9 200941877 The gate of the body M1 - the predetermined potential or the first: pull. When the potential of the transistor M1 is lower than the two potential difference, the first potential difference is greater than the fr, dr required for the current limit circuit The channel - transistor M2 is turned on, and the fourth time is also turned on. When the fourth pole of the fourth ring transistor M4 is pulled down to the ground, the fifth transistor is formed by the sixth transistor Μ6. Further, (4) The current mirror circuit formed by the Japanese body Μ5 and the 曰雪曰# λλ is enabled. At this time, the voltage of the Mi:body is the body of the sixth transistor = the voltage of the gate of the single transistor M1. At the same time, it is balanced by the main control, so that the electric current of the gate of the final power transistor M1 tends to make the current of the power transistor M1 of the current and the left side be the electronic current limit value. A schematic diagram of another embodiment of an electronic device having a current limiting circuit according to the present invention. The power transistor M1 has a source, a drain and a gate, wherein the drain is coupled to the electronic device 31, the source Very lightly connected to the first voltage. In this embodiment, the power transistor M1 and the main control unit 33 The combination may be a power management integrated circuit (integrated 10 circuit '1C), a low dropout regulator (LDO) or a class AB amplifier. The second transistor M2' has a second source, a second drain, and a second gate, wherein the second drain is coupled to a ground potential through the current source 32, and the second gate is coupled to the gate of the power transistor M1. The first resistor ΙΠ has a first end and a second end, wherein the first end is coupled to the first voltage. The third transistor M3 has a third source, a third drain, and a first a third gate, wherein the third source is connected to the second end of the first resistor R1, and the third drain 200941877 is coupled to the second source to the third gate. The first resistor R1 and the third transistor M3 are used to adjust the gate potential of the second transistor M2 and a second potential difference of the first voltage to be substantially equal to the source potential and the gate potential of the power transistor M1. A first potential difference. In this embodiment, at least one or a plurality of diodes are coupled between the third transistor M3 and the second transistor M2, wherein the diodes may be formed by a transistor. The fifth transistor M5 has a fifth source, a fifth drain, and a fifth gate, wherein the fifth source is coupled to the first voltage, and the fifth drain is coupled to the fifth gate . The sixth transistor M6 has a sixth source, a sixth drain, and a sixth gate, wherein the sixth source is coupled to the first voltage, and the sixth drain is coupled to the second gate. The sixth gate is coupled to the fifth gate. a first diode is coupled to the second end of the first resistor and the source of the second transistor. The resistor R2, the fourth transistor M4 and the capacitor C1 form the buffer 16 as shown in Fig. 1. The fourth transistor M4 includes a fourth source, a fourth drain, and a fourth gate, wherein the fourth gate is coupled to the second drain, and the fourth drain is coupled to the fifth pole. The resistor R2 has a first end ❹ and a second end, and the first end is coupled to the fourth gate. The capacitor C1 is coupled between the second end of the second resistor and the ground potential. In the present embodiment, the main control unit 33 includes a controller 35 and a comparator 34. The controller 35 receives a control signal Sc to generate a control voltage Vc. The comparator 34 controls the gate voltage VG of the power transistor M1 in accordance with a reference voltage Vref and the control voltage Vc. In the present embodiment, the main control unit 33 pulls down the gate potential of the power transistor M1 to increase the current flowing through the power transistor M1. 11 200941877 When the gate voltage of the power transistor is pulled down from the main control unit 33 to below the trigger point (triggerp〇int), the second transistor M2 is turned on, and the fourth transistor M4 is turned on. Also turned on. When the fourth transistor M4 is turned on, the gate of the fifth transistor M5 is pulled down to be turned on, so that the current mirror circuit formed by the fifth transistor Μ5 and the sixth transistor M6 is enabled. At this time, the voltage of the gate of the power transistor M1 is raised by the sixth transistor M6, and the voltage of the gate of the power transistor M1 is simultaneously controlled by the main control unit 33, and the gate of the final power transistor ❹M1 is controlled. The voltage of the pole tends to be balanced so that the current flowing through the power is a current limit value of the electronic device. The present invention has been described above with reference to specific embodiments, but it is merely for ease of description of the technical contents of the present invention, and the present invention is not limited to the technical field of the present invention. In the spirit and scope of the invention, it is possible to make a few changes and refinements, and therefore the scope of the patent application scope of the invention is subject to the definition of the patent application. ❹ 12 200941877 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing an embodiment of an electronic device having a current limiting circuit according to the present invention. Figure 2 is a schematic illustration of an embodiment of an electronic device having a current limiting circuit in accordance with the present invention. Figure 3 is a schematic illustration of another embodiment of an electronic device having a current limiting circuit in accordance with the present invention. [Main component symbol description] 11, 21, 31~ electronic device 12~ current limiting circuit 14, 23, 33~ main control unit 15~ current copying circuit 16~ buffer 17, 22~ voltage drop adjusting unit 18, 24, 32~current source ❿ 34~ comparator 35~ controller 13