TW200945459A - Stacked semiconductor package and method for making the same - Google Patents

Abstract

The present invention relates to a stacked semiconductor package and a method for making the same. The stacked semiconductor package comprises a first package and a second package. The first package comprises a first wafer, at least one first chip, a first adhesive, a second redistribution layer and a plurality of second pads. The second redistribution layer is disposed on the second surface of the first wafer. The second package is stacked under the first package, and the second package is electrically connected to the first package. The second package comprises a second wafer, at least one second chip, a second adhesive, a third redistribution layer, a plurality of third pads, a fourth redistribution layer and a plurality of fourth pads. The third redistribution layer is disposed on the first surface of the second wafer. The fourth redistribution layer is disposed on the second surface of the second wafer. Whereby, the redistribution layers rearrange the layout of the first package and the second package, so that the flexibility of the stacked semiconductor package is increased.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure and a method of fabricating the same, and relates to a stacked semiconductor package structure and a method of fabricating the same. [Prior Art] Referring to Figure 1, a schematic diagram of a conventional stacked semiconductor package structure is shown. The conventional stacked semiconductor package structure 1 includes a first package and a second package 20. The first package 1 includes a first wafer, at least one first wafer 12, and a first adhesive 13. The first wafer 11 includes a first surface 111, a second surface U2, and at least one first through hole 113. The first through hole 113 penetrates through the first wafer u. The first wafer 12 is located in the first through hole 113. The first wafer 12 includes an active surface m, a back surface 122, and a plurality of first wafer via holes 123. The active surface 121 of the first wafer 12 is at the same level as the second surface 112 of the first wafer cassette. The first wafer vias 123 extend through the first wafer 12. The first adhesive 13 is used to fix the first wafer 12 in the first through hole 113. The second package 20 is electrically connected to the first package 10 through a plurality of first electrical connection elements μ. The second package 2 includes a second wafer 21, at least one second wafer 22, and a second adhesive 23. The second wafer 21 includes a first surface 211, a second surface 212, and at least one second through hole 213. The second through hole 213 penetrates the second wafer 21 . The second wafer 22 is located in the second through hole 21 3 . The second wafer 22 includes an active surface 221, a back surface 222, and a plurality of second wafer via holes 223. 129567.doc -6- 200945459 The active surface 221 of the second wafer 22 is at the same level as the second surface 212 of the second wafer 21. The second wafer vias 223 extend through the second wafer 22. The second adhesive 23 is used to fix the second wafer 22 in the second through hole 213. The disadvantages of the known stacked semiconductor package structure are as follows. The conventional stacked semiconductor package structure 1 is electrically connected to the active surface 121 of the first wafer 12 of the first wafer 11 and the second wafer 21 by using the first electrical connection elements 14 . The second wafers of the second wafer 22 pass through the vias 223. Therefore, the first package 1 and the second package 2 must have the same size and position of the wafers to pass through the first electrical connections. The components 14 are electrically connected, so that the stacked semiconductor package structure has more restrictions on the circuit layout, and lacks flexibility. Therefore, it is necessary to provide an innovative and progressive stacked semiconductor package structure and a method of fabricating the same to solve the above problems. SUMMARY OF THE INVENTION The present invention provides a stacked semiconductor package structure including a first package and a second package. The first package includes a first wafer, at least one first wafer, a first adhesive, a second redistribution layer, and a plurality of second contacts. The first wafer includes a first surface, a second surface, and at least one first through hole, the at least one first through hole extending through the first wafer. The at least one first wafer is located in the first through hole. The first wafer includes an active surface and a back surface, and the active surface of the first wafer is at the same level as the second surface of the first wafer. The first adhesive is used to fix the first wafer in the first through hole. 129567.doc 200945459 The first line redistribution layer is located on the second surface of the first wafer. The first and second contacts are located on the second line redistribution layer. The second package is electrically connected to the first package, and the second package is electrically connected to the first package. The second package includes a second wafer, at least one second wafer, and a second package. Two adhesives, a third line redistribution layer, a plurality of third contacts, a fourth line redistribution layer and a plurality of fourth contacts. The second wafer includes a first surface, a second surface, and at least one second through hole, and the at least one second through hole extends through the second wafer. The at least one second chip is located in the second through hole. The second chip includes an active surface and a back surface, and the active surface of the second wafer is in the same horizontal plane as the second surface of the second wafer. The second adhesive is used to fix the second wafer in the second through hole. The third line redistribution layer is located on the first surface of the second wafer. The third contacts are located on the third line redistribution layer. The fourth line redistribution layer is located on the second surface of the second wafer. The fourth contacts are located on the fourth line redistribution layer. The invention further provides a method for manufacturing a stacked semiconductor package structure, comprising the steps of: (a) providing a first wafer and a first carrier, the first wafer comprising a first surface and a second surface; a plurality of first through holes extending through the first wafer, the first carrier includes a support surface supporting the second surface of the first wafer; and placing a first wafer on the mother The first through hole includes an active surface and a back surface of the active surface of the first wafer facing the support of the first carrier and located on the second surface of the first wafer The same horizontal plane; (C) the first adhesive to fix the first wafer in the first through hole; (d) 129567.doc 200945459. The first carrier is removed, and a second carrier is provided, the second carrier Including a support surface supporting the first surface of the first wafer; (e) forming a second line redistribution layer and a plurality of second contacts on the second surface of the first wafer (f) removing the second carrier to form a first package; providing a second crystal The second wafer includes a first surface, a second surface, and a plurality of second through holes, the second through holes extending through the second wafer, and the third carrier includes a first carrier a support surface supporting the second surface of the φ second wafer; (h) placing a second wafer in each of the second through holes, wherein the second wafer includes an active surface and a back surface, The active surface of the second wafer faces the support surface of the third carrier and is at the same level as the second surface of the second wafer; (1) forming a second adhesive to fix the first wafer to In the second through hole: (1) forming a third line redistribution layer and a plurality of third contacts on the first surface of the second wafer; (k) removing the third carrier and providing a first a fourth carrier, the fourth carrier includes a ritual surface supporting the first surface of the second wafer; (1) forming a 帛4 line redistribution layer and a plurality of fourth contacts on the first wafer On the second surface; (m) removing the fourth carrier to form a second package; stacking and electrically connecting the The first package and the second package; and (4) performing a dicing step to form a plurality of stacked semiconductor package structures. Thereby, the circuit redistribution layer can reconfigure the circuit layout of the first package body and the second package body, so that the stacked semiconductor package structure has better flexibility in circuit layout. [Embodiment] Referring to Figs. 2 to 19, there is shown a schematic view of a first embodiment of a manufacturing method of the stacked semiconductor package structure of the present invention 129567.doc -9- 200945459. First, referring to Fig. 2, a first wafer 31 and a first carrier 32 are provided. The first wafer 31 includes a first surface 311, a second surface 312, and a plurality of first through holes 313. In the embodiment, the first wafer 31 further includes a plurality of first wafer via holes 314. The first through holes 313 penetrate the first wafer 31. In the embodiment, the first through-via vias 314 extend through the first wafer 31. The first carrier 32 includes a support surface 321' that supports the second surface 312 of the first wafer circle 31. In this embodiment, the first carrier 32 is a carrier wafer and is attached to the second surface 312 of the first wafer 3 i by a first colloid 33. However, in other applications, the first carrier 32 can also be a platform for a machine. Next, referring to FIG. 3, a first wafer 34 is placed in each of the first through holes 313. In this embodiment, the thickness of the first wafer 34 is different from the thickness of the first wafer 31, and only one wafer is placed in each of the first through holes 313. However, in other embodiments, A plurality of wafers can be placed in the first through hole 313 (as shown in Fig. 24). The first wafer 34 includes an active surface 341 and a back surface 342. The active surface 341 of the first wafer 34 faces the support surface 321 of the first carrier 32 and is at the same level as the first surface 312 of the first wafer 31. Next, referring to FIG. 4, a first adhesive 35 is formed to fix the first wafer 34 in the first through hole 3 13 . Next, referring to FIG. 5, in the embodiment, a polishing step is further included to simultaneously expose the back surface 342 of the first wafer 34 and the first surface 311 of the first wafer 31. Next, referring to FIG. 6, in this embodiment, a first circuit redistribution layer 36 and a plurality of 129567.doc •10-200945459 first contacts 37 are formed on the first wafer 3 a step on a surface 311, and the first contacts 37 are under the ball metal layer (under Bump)

Metallurgy). Referring next to FIG. 7, the first carrier 32 is removed and a second carrier 38 is provided. The second carrier 38 includes a surface 38m which is on the first surface 311 of the first wafer. The first line is re-published. In this embodiment, the second carrier 38 is a carrier wafer, and the first circuit redistribution layer 36 is attached to the first surface 3 of the first wafer 31 by using a first colloidal gel 39. . However, in other applications, the second carrier 38 can also be a platform for a machine. Referring next to FIG. 8, a second line redistribution layer 41 and a plurality of second contacts 42 are formed on the second surface 312 of the first wafer 31. In the embodiment, the first through-wafer vias 314 are electrically connected to the first-line redistribution layer 36 and the second-line redistribution layer 41, and the n (four) layers are under-ball metal layers. Next, referring to FIG. 9, the second carrier 38 is removed to form a first package body 30. The above process is overlaid to form a second package 50 (Fig. 17). First, referring to FIG. 1A, providing - a _ first day yen 5 丨 and a third carrier 52 » the =: ^ includes - the first surface 511, a second surface 512 and a plurality of n Π, #本# In the embodiment, the second wafer 51 further includes a plurality of first wafers. In the present embodiment, the second through holes 513 extend through the second crystal, and the second through holes 513 Dimensions and positions are equal to the first through-hole 331 (Fig. 2) in the actual (four), the wafer through the through hole through the second wafer & first 129567.doc 200945459 the second carrier 52 includes a support surface 521 that supports the second surface 512 of the second crystal circle. In this embodiment, the third carrier _ is a carrier wafer and is attached to the second surface 512 of the second wafer 51 by a third colloid 53. However, in other applications, the third carrier 52 can also be a platform for a machine. Next, referring to Figure 11, a second wafer 54 is placed in each of the second through holes 513. In this embodiment, the thickness of the second wafer 54 is different from the thickness of the second wafer 51. The second wafer 54 is the same as or different from the first wafer 34 (FIG. 3). In the embodiment, the first wafer 34 is a control wafer, and the second wafer 54 is a memory wafer. The size and footprint of the second wafer 54 are the same as or different from the first wafer 34. Only one wafer is placed in each of the second through holes 513. However, in other applications, a plurality of wafers may be placed in the second through holes 513. The second wafer 54 includes an active surface 541 and a back surface 542. The active surface 541 of the second wafer is oriented toward the support surface 521 of the third carrier 52 and at the same level as the second surface 512 of the second wafer 51. Next, referring to FIG. 12, a The second adhesive 55 is used to fix the second wafer 54 in the second through hole 513. Next, referring to FIG. 13, in the embodiment, a grinding step is further included to simultaneously expose the second wafer 54. The back surface 542 and the first surface 511 of the second wafer 51. Next, referring to FIG. 14, a third line redistribution layer 56 and a plurality of third contacts 57 are formed on the first surface of the second wafer 51. 511. In the present embodiment, the third contacts 57 are under the ball metal layer. Next, referring to Figure 15, the third carrier 52 is removed and a fourth load is provided 129567.doc •12· 200945459 The fourth carrier 58 includes a -cut surface 581 that is the third line redistribution layer 56 on the first surface 511 of the first dome 51. In this embodiment The fourth carrier 58 is a carrier wafer and is attached to the first surface 5 of the second wafer 51 by a fourth colloid. The second redistribution layer 56, while in other applications, the fourth support 58 may also be a machine of the internet.

Next, FIG. 16 forms a fourth line redistribution layer 61 and is connected to the second surface 512 of the second wafer 51. In the present embodiment, the second through-via vias 514 are electrically connected to the third circuit redistribution layer 56 and the fourth circuit redistribution layer 61, and the fourth contacts 62 are under the ball. Metal layer. Next, referring to Figure 17, the fourth carrier 58 is removed to form a second package 50. Next, referring to FIG. 18, the first package body 3 and the second package body 50 are stacked and electrically connected, wherein the position of the second through hole 513 can be aligned or not aligned with the position of the first through hole 313. In this embodiment, the first surface 511 of the second wafer 51 faces the second surface 312 of the first wafer 31, and the third contacts 57 pass through the plurality of first electrical connections. The component 4 is electrically connected to the second contacts 42. Finally, referring to Fig. 19, a dicing step is performed to form a plurality of stacked semiconductor package structures 2. Referring again to Figure 19, there is shown a schematic view of a first embodiment of a stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 2 includes a first package body 30 and a second package body 50. The first package body 3 includes a first wafer 31, at least one first wafer 34, a first adhesive 35, a second circuit redistribution layer 41, and a plurality of second contacts 42. In the present embodiment, the first cover 129567.doc -13- 200945459 package 30 further includes a first line redistribution layer 36 and a plurality of first contacts 37. The first wafer 31 includes a first surface 311, a second surface 312, and at least one first through hole 313. In this embodiment, the first wafer 31 further includes a plurality of first wafer via holes 314. The first through holes 313 penetrate the first wafer 31. In this embodiment, the first through-via vias 314 are passed through the first wafer 31 and electrically connected to the second trace redistribution layer 41. The first wafer 34 is located within the first through hole 3 i 3 .

The first wafer 34 includes an active surface 341 and a back surface 342. The active surface 341 of the first wafer 34 is on the same horizontal plane as the second surface 312 of the first wafer 31. The first adhesive 35 is used to fix the first wafer 34 in the first through hole 313. In this embodiment, the first line redistribution layer 36

Located on the first surface 31 of the first wafer 31 on a surface 311 of the first circuit redistribution layer 36. The first contacts are 37, and the first contacts 37 are under the ball metal layer. The second line redistribution layer 41 is located on the second surface of the first wafer 31. The second contacts 42 are located on the second circuit redistribution layer 41. In this embodiment, the second contacts 42 are under-ball metal layers. The second package 50 is stacked under the first package 3 (), and the second package is electrically connected to the first package 30. The second package 50 includes a second wafer 51, at least a second line redistribution layer 56, a plurality of third contacts 57 layers 61, and a plurality of fourth contacts 62. The wafer 54 , a second adhesive 55 , a fourth line redistribution, a second surface 512 and the second wafer 51 further include two through holes 513 extending through the second wafer 51 including a first surface 5 ιι One second through hole 513 is missing. In this embodiment, a plurality of second wafers are passed through the vias 514. These 129567.doc -14- 200945459 two wafers 51. In this embodiment, the second through holes 5丨3 are the same size, position and number as the first through holes 3 13 . In this embodiment, the second through-via vias 514 extend through the second wafer 51 and are electrically connected to the fourth trace redistribution layer 61. The second wafer 54 is located in the second through hole 513. The size and footprint of the second wafer 54 are the same as or different from the first wafer 34. The second wafer 54 includes an active surface 541 and a back surface 542. The active surface 541 of the second wafer cassette 54 is at the same level as the second surface 51 of the second wafer 51. The second adhesive 55 is used to fix the second wafer 54 to the second surface. Inside the through hole 513. The third line redistribution layer 56 is located on the first surface 511 of the second wafer 51. The third contacts 57 are located on the third line redistribution layer %. In the present embodiment, the third contacts 57 are under-ball metal layers, and the second contacts 42 are connected to the third contacts 57 through a plurality of first electrical connecting elements 4 . The fourth line redistribution layer 61 is located on the second surface 512 of the second wafer 51. The fourth contacts 62 are located on the fourth line redistribution layer 61. In the present embodiment, the fourth contacts 62 are under-ball metal layers. An advantage of the present invention is that the circuit layout layers 36, 41, 56, 61 can reconfigure the circuit layout of the first package body 30 and the second package body 5, so that the stacked semiconductor package structure 2 is in the circuit. The layout has better elasticity. Referring to Figure 20, there is shown a schematic view of a second embodiment of a stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 3 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is 129567.doc •15-200945459 only because the size of the second through hole 5 13 is different from the first through hole 313 ′ and the size of the second wafer 54 is different. On the first wafer 34. Referring to Fig. 21, there is shown a schematic view of a third embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 4 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is that the size and number of the second through holes 513 are different from those of the first through holes 313. In the present embodiment, a second through hole 513 is located between a first through hole 313, and the second wafer 54 is different in size from the first wafer 34. Referring to Fig. 22, there is shown a schematic view of a fourth embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 5 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is that the second package 50 is inverted such that the second surface 512 of the second wafer 51 © faces the second of the first wafer 31 . The surface 312 is such that the second contacts 42 are connected to the fourth contacts 62 through the first electrical connecting elements 4 . Referring to Figure 23, there is shown a schematic view of a fifth embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 6 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same elements are given the same reference numerals. The first embodiment of the present invention is different from the first embodiment in that the first wafer 34 further includes a plurality of first wafer via holes 343, and the second wafer 54 further includes a plurality of second wafer via holes 543. In the embodiment, the first wafer-through via 343 extends through the first wafer and is electrically connected to the second wiring redistribution layer 41. The second wafer vias 543 are through the substrate. The second wafer 54 is electrically connected to the fourth circuit layer 61. Referring to Figure 24', there is shown a schematic view of a sixth embodiment of the stacked semiconductor package structure of the present invention. The stacked φ-type semiconductor package structure 7 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same

The components are given the same number. The first embodiment of the present invention is different from the first embodiment in that the first package body 30 further includes a plurality of first wafer via holes 343 and at least one third wafer 43. In the present embodiment, the first wafer vias 343 are inserted through the first die 34 , and the third die 43 is disposed in the first through hole 313 and above the chip 34 . . The third wafer 43 includes an active surface 431 and a back surface 432. The active surface 431 of the third wafer 43 faces the back surface 342 of the first wafer, and the third wafer 43 passes through the plurality of first bumps. The first wafer 34 is electrically connected. In other applications, however, the back side 432 of the third wafer 43 faces the back side 342 of the first wafer 34. Referring to Figure 25', there is shown a schematic view of a seventh embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 8 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same elements are given the same reference numerals. The difference between this embodiment and the first embodiment is only that the second package 50 further includes at least one fourth wafer 63. In the present embodiment, the fourth wafer 63 is placed in the second through hole 513 and above the second wafer 54. The fourth wafer 63 includes an active surface 129567.doc -17-200945459 631 and a back surface 632. The back surface 632 of the fourth wafer 63 faces the back surface 542 of the second wafer 54 and the fourth wafer 63 The fifth knee 64 is attached to the second wafer 54. In other applications, however, the active surface 631 of the fourth wafer 63 is oriented toward the back side of the second wafer 54. Referring to Figure 26, a schematic diagram of an eighth embodiment of the stacked semiconductor package structure of the present invention is shown. The stacked semiconductor package structure 9 of the present embodiment is substantially the same as the stacked semiconductor package structure 2 of the first embodiment, wherein the same φ members are given the same reference numerals. The difference between this embodiment and the first embodiment is that only the stacked semiconductor package structure 9 further includes a third package body 70. In this embodiment, the third package body 70 is stacked under the second package body 5〇, and the third package body 7 is electrically connected to the second package body 50°. The third package body 70 The invention includes a third wafer 71, at least a fifth wafer 72, a third adhesive 73, a fifth circuit redistribution layer 74, a plurality of fifth contacts 75, a sixth circuit redistribution layer 76, and a plurality of The sixth junction. The third wafer 71 includes a first surface 711, a second surface 712, at least one third through hole 713, and a plurality of third wafer via holes 714. The third through hole 7 is penetrated through the third wafer 71. The third wafer vias 714 extend through the third wafer 71 and are electrically connected to the sixth line redistribution layer. The fifth wafer 72 is located in the third through hole 713. The fifth wafer 72 includes an active surface 721 and a back surface 722. The fifth wafer 72 is the same as or different from the first wafer "and the second wafer 54. The active surface 721 of the fifth wafer 72 is associated with the The second surface 712 of the third wafer 71 is located at the same horizontal plane. The third adhesive 73 is used to fix the fifth wafer 72 in the third through hole 713. The 129567.doc -18- 200945459 * fifth The circuit redistribution layer 74 is located on the first surface 711 of the third wafer 71. The fifth contacts 75 are located on the fifth circuit redistribution layer 71, and the fifth contacts 75 are under the ball metal. The fourth contact 62 is connected to the fifth contacts 75 through a plurality of second electrical connection elements 60. The sixth circuit redistribution layer 76 is located on the second surface of the third wafer 71. 712. The sixth contacts 77 are located on the sixth circuit redistribution layer 76, and the sixth contacts 77 are under the ball metal layer. φ However, the above embodiments are merely illustrative of the principle and function of the present invention. It is not intended to limit the invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the essence of the invention. The scope of the present invention should be as described in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional stacked semiconductor package structure; FIG. 2 to FIG. 19 are views showing the manufacture of a stacked semiconductor package structure of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 21 is a schematic view showing a third embodiment of a stacked semiconductor package structure of the present invention; FIG. 21 is a schematic view showing a third embodiment of the stacked semiconductor package structure of the present invention; 22 is a schematic view showing a fourth embodiment of the stacked semiconductor package structure of the present invention; FIG. 23 is a schematic view showing a fifth embodiment of the stacked 4-type semiconductor package structure of the present invention; and FIG. 24 is a view showing the stacked type cast package structure of the present invention. 196567.doc -19·200945459 of the sixth embodiment is not intended to be a schematic view of a seventh embodiment of the stacked semiconductor package structure of the present invention; and FIG. 26 shows an eighth embodiment of the stacked semiconductor package structure of the present invention. Schematic diagram.

Φ [Major component symbol description] 1 Conventional stacked semiconductor package structure 2 First embodiment of stacked semiconductor package structure of the present invention Second embodiment of stacked semiconductor package structure of the present invention 4 Stacked semiconductor package structure of the present invention Third Embodiment 5 A fourth embodiment of a stacked semiconductor package structure of the present invention A fifth embodiment of a stacked semiconductor package structure of the present invention is a sixth embodiment of the stacked semiconductor package structure of the present invention. Seventh Embodiment of Structure 9 Embodiment 8 of the stacked semiconductor package structure of the present invention 10 First package body 11 First wafer 12 First wafer 13 First adhesive 14 First electrical connection element 20 Second package 21 second wafer 22 first wafer 23 second adhesive 129567.doc •20- 200945459

30 first package 31 first wafer 32 first carrier 33 first colloid 34 first wafer 35 first adhesive 36 first line redistribution layer 37 first contact 38 second carrier 39 second colloid 40 first Electrical connection element 41 second line redistribution layer 42 second contact 43 third wafer 44 first bump 50 second package 51 second wafer 52 third carrier 53 third colloid 54 second wafer 55 second Adhesive 56 third line redistribution layer 57 third junction 58 fourth carrier 129567.doc -21- 200945459

59 fourth colloid 60 second electrical connection element 61 fourth line redistribution layer 62 fourth contact 63 fourth wafer 64 fifth colloid 70 third package 71 third wafer 72 fifth wafer 73 third adhesive 74 fifth line redistribution layer 75 fifth contact point 76 sixth line redistribution layer 77 sixth contact point 311 first surface 312 second surface 313 first through hole 314 first wafer through hole 321 support surface 341 active Face 342 Back 343 First wafer through hole 381 Branch surface 431 Active surface 129567.doc -22- 200945459 432 Back surface 511 First surface 512 Second surface 513 Second through hole 514 Second wafer through hole 521 Support surface 541 Active surface 542 Back surface 581 Branch surface 631 Active surface 632 Back surface 711 First surface 712 Second surface 713 Third through hole 714 Third wafer through hole 721 Active surface 722 Back surface 129567.doc -23-

Claims (1)

200945459 X. Patent Application Scope: A method for manufacturing a β-stacked semiconductor package structure includes: (4) a first wafer and a first carrier, the first wafer includes a surface, a second surface, and a plurality of a first through hole, the first through hole is through the first wafer, the first carrier includes a support surface supporting the second surface of the first wafer; _ (8) placing - the first wafer In each of the first through holes, the first wafer includes an active surface and a back surface, and the active surface of the first wafer faces the selected surface of the first carrier, and the first wafer The second surface is located at the same horizontal plane; (4) forming a ---adhesive to fix the first wafer in the first through-hole, (4) removing the first carrier' and providing a second carrier, the second carrier The body includes a support surface that cuts the first surface of the first wafer, and (4) a second wiring redistribution layer and a plurality of second contacts on the second surface of the first wafer; f) removing the second carrier to form a first package; (g) drawing a second wafer and - third a carrier, the second wafer includes a first surface, a second surface, and a plurality of second through holes, the first through holes extending through the second wafer. The third carrier includes a support surface. Supporting the second surface of the second wafer; (8) placing a second wafer in each of the second through holes, the second wafer including an active surface and a back surface, the active surface of the second wafer 129567.doc 200945459 is directed toward the support surface of the third carrier and at the same level as the second surface of the second wafer; (1) forming a second adhesive to fix the second wafer to the first In the two through holes; G) forming a second line redistribution layer and a plurality of third contacts on the first surface of the first wafer; ~ (k) removing the third carrier 'and providing - a fourth carrier, the fourth carrier includes a support surface supporting the first surface of the second wafer; (4) forming a fourth line redistribution layer and a plurality of fourth contacts to the second crystal On the second surface of the circle; ~ (m) removing the fourth carrier to form a second package; (8) stacking and electrically connecting Connecting the first package body and the second package body; and (4) cutting and cutting steps to form a plurality of stacked semiconductor package structures. ❹ 2· As in the method of claim 1, /, in the step (a) The first carrier is a carrier wafer or a thousand sub-human machine 0, in the step (4), the second carrier carrier is: a wafer or a platform of the machine 'this step (g In the third step, the wafer or the platform of the machine is carried. In the step (8), the carrier is a platform for carrying a wafer or a machine. 3. In the step (g), the second crystal layer further comprises a plurality of second wafer via holes, and the first and second rows of the wafers are passed through the second wafer, and the first day of the Japanese yen passes through the via hole system. Connect the line redistribution layer. (4) I line redistribution layer and the fourth I29567.doc 200945459 4. If the claim 1 is in the step (h), the first piece is contiguous with a plurality of second wafer through holes. The first cymbal is further included on the first day of the day. Μ second line redistribution layer and the fourth 5. According to the method of claim ,, the degree is different from the thickness of the first wafer: the thickness of the slab is different from 1 _2' In the step, the thickness of the second wafer of the second wafer. Reference 6. As in the case of claim 1, the soil, the, and the towel further include a grinding step after the step (4) to simultaneously expose the surface of the first month μ 7 . The back side of the 0 slice and the 7th of the first wafer, as in the method of claim 1, the method of the first, and the step (after the 0 further comprises forming a first line redistribution layer and a plurality of 笸-sites) a first contact on the first surface of the first wafer. The method of the first embodiment, wherein the first wafer further comprises a plurality of first wafer vias. a hole extending through the first wafer, the via holes being electrically connected to the first line redistribution layer and the second 9. The method of claim 7, wherein in the step (b), the method The first wafer further includes a first-wafer via hole extending through the first wafer, and the one of the wafer via holes is electrically connected to the first-line redistribution layer and the second-line redistribution layer. For example, in the method of claim 1, in the step (g), the size of the second through holes is different from the size of the first through holes. 11·If the method of claim 1 is used, Gan. In the step (h), the second wafer has a ruler 129567.doc 200945459 inch different from the first wafer. 12_ The method of claim item, wherein the step (1) And further comprising: a grinding step to simultaneously expose the back surface of the second wafer and the first surface of the second wafer. 13. The method of claim 1, wherein in the step (b), the coin is further disposed The wafer is disposed in the first through hole and on the first wafer, the third wafer includes an i-plane and a back surface. The back surface of the third wafer faces the back surface of the first wafer. The method of the present invention, wherein in the step (b), a third wafer is disposed in the first through hole and above the first wafer, the third wafer includes an active surface and a back surface, and the third The active surface of the wafer is oriented toward the back surface of the first wafer. 15. The method of claim 2, wherein the step (h) further places a fourth wafer in the second through hole and is located in the second Above the wafer, the fourth wafer includes an active surface and a back surface, the back surface of the fourth wafer facing the back surface of the second wafer. 16 (4) The method of claim 1 wherein the step (h) Depositing a fourth crystal in the second through hole and above the second wafer The fourth wafer includes an active surface and a back surface, and the active surface of the fourth wafer faces the back surface of the second wafer. 17. The method of claim 1, wherein in the step (4), the second transparent The position of the hole is not aligned with the position of the first through hole of the t. 18·If the π is the term r method 'where the position of each of the second through holes in the step (8) is between the two first through holes 19. The method of claim 1, wherein in the step (n), the face of the second wafer faces the second surface of the first wafer, and the first contacts are The second contacts are electrically connected. The second method of claim 1, wherein in the step (8), the first surface of the second wafer faces the second surface of the first wafer, and the fourth contacts are electrically The second contacts are connected sexually. 21. Method of requesting In the step (e), the second contacts are under the metal layer (Under Bump MeUllurgy), in the step (1), the third contacts are under the ball metal layer, the step (1) towel, the same The fourth contact is a metal layer under the ball. 22. The method of claim, wherein the step (4) further comprises: (f)): providing: a third wafer and a fifth carrier, the third wafer comprising a first surface, a second surface, and a plurality of a third through hole, the "three through hole through the fifth wafer 'the fifth carrier includes a - support surface' which supports the second surface of the third wafer; (m2) placement - fifth The fifth wafer includes an active surface and a back surface in each of the third through holes, the active surface of the fifth wafer facing the support surface of the fifth carrier, and the second wafer The second surface is located at the same horizontal plane; (m3) forming a third adhesive to fix the fifth wafer in the third through hole; (m4) forming a fifth line redistribution layer and a plurality of fifth contacts On the first surface of the third wafer; 129567.doc •5- 200945459 (m5) removing the fifth carrier and providing a sixth carrier, the sixth carrier including a support surface a first surface of the third wafer; (m6) forming a sixth line redistribution layer and a plurality of sixth contacts Of the second upper surface; and (M7) (iv) removing six support to form - a third step of the package and The step (n) is stacked and electrically connected to the first package, the second package, and the third package. The stacked semiconductor package structure includes: a first package, including a first wafer, a first surface, a second surface, and at least one first through hole, the at least one a first through hole is through the first wafer; at least one first wafer is located in the first through hole, the first chip includes an active surface and a back surface, the first, the first Ρ Η gt; The first surface of the first wafer is fixed in the first through hole; a first adhesive is fixed in the first through hole; a second circuit redistribution layer on the second surface of the first wafer; and a plurality of second contacts on the second circuit redistribution layer; and a second package stacked on the first package The first package is electrically connected to the first package. The second package includes: a second wafer, including a first surface, a second surface, and at least one second through hole. The at least one second through hole extends through the second wafer; 129567.doc -6 - 200945459 at least one second wafer </ RTI> in the second through hole, the first _ day and the sun month comprises an active surface and a back surface, the active surface of the second wafer is at the same level as the second surface of the first wafer; a second adhesive for fixing the second wafer in the second through hole; a second line redistribution layer on the first surface of the second wafer; Ο 24. φ 25. 26. a plurality of a third contact is located on the third line redistribution layer; a fourth line redistribution layer is located on the second surface of the second wafer; and a plurality of fourth contacts are located on the fourth line On the floor. The package structure of claim 23, wherein the second wafer further comprises a plurality of second wafer via holes extending through the second wafer, wherein the second wafer via holes are electrically connected to the second A three-line redistribution layer and the fourth circuit layer. The package structure of claim 23, wherein the mth portion includes a plurality of second wafer via holes extending through the second wafer, the second wafer via holes electrically connecting the third secret layer (4) and the Fourth line: cloth layer. The package structure of claim 23, wherein the first package further comprises a first line redistribution layer and a plurality of first contact points on the first surface of the first wafer. 27. 129567.doc 200945459 • The conduction-reduction connection connects the first-line redistribution layer and the second line is redistributed. 28. The package structure of claim 26, wherein the first wafer further comprises a plurality of first wafer vias extending through the first wafer, the first wafer vias being electrically connected to the first line The redistribution layer and the second circuit layer. 29. The package structure of claim 23, wherein the second contacts are connected to the third contacts via a plurality of (four)-electrical connection elements. 3. The package structure of claim 23, wherein the second contacts are connected to the fourth contacts through a plurality of first electrical connection elements. 3. The package structure of claim 23, wherein the thickness of the first wafer is different from the thickness of the first wafer, and the thickness of the second wafer is different from the thickness of the first wafer. 32. The package structure of claim 23, wherein the second through holes are sized differently than the first through holes. The package structure of claim 23, wherein the size of the second wafer is different from the first wafer. 34. The package structure of claim 23, wherein the first package further comprises a third wafer, Located in the first through hole and above the first wafer, the second wafer includes an active surface and a back surface, and the back surface of the third wafer faces the back surface of the first wafer. The package structure, wherein the first package further includes a third wafer, located in the first through hole and above the first wafer, the third wafer includes an active surface and a back surface, and the third wafer Active 129567.doc 200945459 The face is facing the back side of the first wafer. 36. 37. ❹ 38. 39. 40. ❹ 41. 42. The package structure of claim 23, wherein the second package further comprises a a fourth wafer is disposed in the second through hole and located on the second wafer. The fourth wafer includes an active surface and a back surface, and the back surface of the fourth wafer faces the back surface of the second wafer. The package structure of claim 23, wherein the The package further includes a fourth wafer located in the second through hole and located on the second wafer. The fourth wafer includes an active surface and a back surface, and the active surface of the fourth wafer faces the second The package structure of claim 23, wherein the position of the second through hole is not aligned with the position of the first through hole. The package structure of claim 23, wherein the position of the second through hole is located The package structure of claim 23, wherein the number of the second through holes is different from the number of the first through holes. The package structure of claim 23, wherein the second The contacts, the third contacts, and the fourth contacts are under-ball metal layers (Under, such as Metallurgy). The package structure of claim 23 further includes a third package stacked on the first The second package is electrically connected to the second package, the third package includes: a surface and at least a third wafer, including a first surface, a third through hole, At least one third through hole penetrating the third wafer The fifth wafer is located in the third through hole. The fifth wafer package 129567.doc -9·200945459 includes an active surface and a back surface, and the active surface of the fifth wafer and the second wafer The second surface is located at the same horizontal plane; a third adhesive is used to fix the fifth wafer in the third through hole; a fifth line redistribution layer is located on the first surface of the third wafer; a fifth contact is located on the fifth line redistribution layer; a sixth line redistribution layer is located on the second surface of the third wafer; and a plurality of sixth contacts are located on the sixth line On the floor. 129567.doc 10·