TW200945088A - Semiconductor intergrated circuit designing device, method for designing semiconductor intergrated circuit, computer program designing semiconductor intergrated circuit - Google Patents

Abstract

Provided for a semiconductor integrated circuit is a designing device that causes little increase in area, that can control a small delay in order to resolve a hold error, and that makes available formal verification and scan testing employed only in designing a conventional flip-flop circuit. Included are timing analysis means; FF (flip-flop circuit)-latch-circuit conversion means that refers to an analysis result by the timing analysis means, and that converts a flip-flop circuit at both ends of the node into two types of latch circuit comprised of a high latch circuit and a low latch circuit; latch destination determination means that selects a latch circuit to be fixed of the two types of latch circuits based on the location of the latch circuits on the circuit arrangement; and circuit information conversion means that converts circuit information of a latch circuit to be fixed into wiring information of a circuit to be converted.

Description

200945088 VI. Description of the Invention: [Technical Field of the Invention] [0001] Designed Design Apparatus (Design System) The present invention relates to the technical field of assisting a semiconductor integrated circuit. [Prior Art] [0002] Now::==:=3⁄4 Steps are actually larger or larger than the individual flip-flops 2=竿二=, the time difference between the clocks supplied by the circuit is I The delay between the flip-flops is not longer than a certain time value. The two-reverse 1T receives the previous clock signal data. This fault ^ is "protection" 贱 之 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Nakazawa and Hlr〇shi Nakamura, translation, Maruzen Co., pp. 356-358 (NAKAZAWA); Registered Patent Gazette No. 2677256 (^AKAMURA-D; Published Patent Gazette No. 2005_277909 (_1); Public Patent Gazette No. 2003-234643 (YOSHIKAWA); published patent publication No. 2005-026390 (ORITA); published patent publication No. 2-7188517 (TAKEYAMA); and published patent publication No. H〇9_〇〇8143 (NAKAMURA-2) ° [0003 According to NAKAZAWA's semiconductor integrated circuit design system (shown in Figure 12), it includes: semiconductor integrated circuit data, circuit delay measurement system, delay buffer insertion judgment system, and delay buffer insertion system, in which: circuit delay amount Test system 200945088, the Na signal is transmitted in the forward and reverse n circuit pairs, and the delay is transmitted to determine the delay buffer insertion that may cause the Ui to judge the delay of keeping the error, and the path is directly linked and not produced. The money road is used to solve the problem of keeping mistakes. The secret part of the 'insert-delay gate, [0004] shows) the package semiconductor integrated circuit design system (as shown in Figure 系统 judgment system, and _ electricity The road is inserted into the system, the circuit is delayed until the error is kept; the second is the second, and the system is designed by the semiconductor integrated circuit. 5 = semi-secret person, _ _ _ _ _ _ _ _ _ _ _ 1 It is recommended to use the design method of the question lock circuit. The problem of this method is H. The design method based on the synchronization of the positive and negative 11. YOSHIKAWA reveals: "If every positive and negative lock circuit, the positive and negative circuit circuit basis, and the latter 1 path The delay and the "clock cycle period, * 倾 录 录 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 ) 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正 正, and can increase the allowable maximum A logic delay time, and can be designed to be a secret design. ^ 5 200945088 [0007] ORITA states: "The signal line connection system 61 of the present embodiment includes: a logic design data memory unit 62 And storing the logic design data of the semiconductor device; the program s memory unit 63, storing the timing of analyzing the signal line to establish a new layer connection wiring pattern, etc.; the location wiring information memory unit 64, Information about the logic component, the location and the routing path; the timing information memory unit 65 stores timing analysis information about the signal propagation delay time of the signal line; the via hole information memory unit 66' is stored in different wiring layers And a layer hole information of the signal lines connected to each other through the via holes; the processing control unit 67 includes means for performing a connection processing of the series of signal lines; and the output device 69 is controlled by the input/output unit ^^8* And outputting the processing result; the input device 7〇, inputting the finger ❹=etc. to the process control unit 67, and the [the present invention] can provide a method for connecting the signal line, the signal line is generated enough between the logic elements The signal propagation delay time for timing control; and the system used to connect the signal lines. [0008] 〇, 'TAKEYAMA explains: "[A timing distribution device, which includes ·] in the = layer, the calculation, the complex timing allocation establishment unit, which is set corresponding to each of the complex design levels From the netlist information about the wiring pattern, the plural time series information database 'receives the block information about the circuit function, and can adjust the timing value generated by the delay element of the circuit to make the timing distribution. Output; and the inter-hierarchy cooperation manager (in her yer c〇Uab〇rati〇n_ager), which changes the timing of the complex number to establish the connection between each of the unit towels, and:: transmission/reception timing allocation The correction information of the value is added to/from the time series of the plural number. 』; and "[Time-series distribution device]' can change the influence range of the change when the timing specification is changed, thereby eliminating the error reference of the specification change. In addition, the combination of experimental wiring and actual wiring will facilitate a balance between improved planar configuration (fl〇〇r 仃 speed and improved accuracy). Furthermore, [timing distribution =] is sufficient: use hierarchical entities; establish dispersion The distributed design environment; in the top-down design, only the necessary parts are detailed; in a design team, the quality of the time series that was split during the test test is checked; 6 200945088 Forecast is implemented Problems during the period; and reduction of corrections.] [0009] At the same time, NAKAMURA-2 states: "Deferred optimization of the single-site insertion level _plus-. Insertion ^ 立 ^ Delay-limited signal path overlap frequency, and overlap The frequency 递 decreasing order shifts the scale _ to the touch, so that the LSI layout pattern of the synchronous sequential circuit borrows | ❹ affects the maximum delay time, and the calculation processing time can be reduced. It is sufficient to minimize the increase in the LSI layout pattern area of the step-by-step circuit. [0010] [Disclosure] [Problems to be Solved by the Invention] [0011] Method However, The above documents do not disclose any specific solutions for the following two questions [0012] 2 7 to keep the error, sometimes the circuit surface __^ = ^ process water circuit ===== cycle delay _ late question lock circuit In the case where the delay b circuit of the half cycle of the forward and reverse clocks is longer than the expected clock of 200945088 cycles [0014] ft with respect to the propagation signal between the flip-flop circuits, the device of the present invention The Qing + peak observation signal line has a small; i small delay to solve the error in the signal line (the delay value of the delay value). [0015] Set to: ===== The design of the road is installed on the circuit configuration and the circuit is equipped with the value of the positive and negative circuit. 'Cause == ask; ==; the road _ lock power 月 force month, refer to the analysis results of the time series analysis means, according to the relative Two & 200945088 lock circuit in the circuit configuration position and section input / output direction, and _ electric ^ = in the circuit configuration position signal in the circuit select the lightning to be fixed = set 'from two flashes The lock solution occurs at the point where the semi-guided Zhao ❹ 妍 妍 , , , , , , , , , , , , Road conversion function, reference iEiE^ fixed μ (four) (9) position on the circuit configuration 'select the circuit to be used by the circuit from the __ circuit · ^ secret Wei conversion Wei' which will be converted to the flash lock to be converted The wiring information of the circuit can be solved by a computer program or a method. The computer is designed to design the device. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ [0019] Regarding the propagation signal between the flip-flop circuits, the above-described invention realizes the design apparatus (design secret) of the broadcast body iii, and the design apparatus (design system) makes the signal line have less than the individual 9 200945088 [_] 杲In order to replace the above-mentioned considerations, the first beneficial effect of the early pure insertion-circuit element delay-in method and the flash lock circuit are plugged in, and the flip-flop circuit is only converted into a pair of latch circuits, Almost no addition. Compared with the adjustment method of the cut delay gate, in particular, in the future, when the wiring which has a large capacity due to miniaturization and the timing caused by the miniaturization of the components are not caused, it is expected that it is almost The replaced flip-flop circuit has the same area, and thus only utilizes [0021] The second beneficial effect of the present invention is to allow fine-tuning delay control based on the end point of the forward and reverser circuit. For example, the amount of flash delay is used as a solution to keep the error, and phase 2 is fixed by one. The present invention allows the use of = [0022] function means. And the hardware in the device according to the present invention is referred to as [0023] - the clock signal is input to the arbitrary signal, whereby the present invention is if the method of the present invention is Can also be applied to non-synchronous circuits, the dragon does not have f as CLK, but as the wheel of other circuits; ^ bucket start 5 and 疋 ^ tiger, and 200945088 [0024] Again, here use "circuit configuration position The representation, which represents the location of the schematic circuit configuration and the physical location on the layout. [Embodiment] Now, an embodiment of the present invention will be described. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. [First Embodiment] Referring to FIG. 1 'The semiconductor integrated circuit design system of the first embodiment of the present invention is a system (design device) supporting a semiconductor integrated circuit design, and the system (design device) includes six Function blocks and seven databases related to function blocks serve as functional structures. [0028] The above function block includes: a timing analysis function block 102; a flip-flop-latch-circuit conversion determination function block 104, which is connected to the timing analysis function block 102; and a latch circuit end point decision function block 1 〇5' is connected to the timing analysis function block ❹102; the flip-flop lock-circuit conversion function block 108' is connected to the flip-flop/flash lock_circuit conversion judgment function block 104; the latch circuit is moved to the function block 1〇9, The flash lock circuit end decision function block 105 is connected; and the circuit information conversion function block 112 is connected to the flip-flop_block lock_circuit conversion function block 108 and the latch circuit shift function block 109. [0029] In addition, the above database includes: a semiconductor integrated circuit data 101, which is connected to the timing analysis function block 102; a timing analysis data 103, and a timing analysis function block 1 and 2, a flip-flop-flash lock circuit conversion determination function block. 1〇4, and the flash lock circuit end point decision function block 105 is connected; the flip-flop-latch-circuit conversion data 106, and the forward and reverse 11 200945088-latch-circuit conversion judgment function block 104 and the flip-flop-latch The circuit switching function block 108 is connected; the latch circuit moves the data 1〇7, and is connected to the latch circuit end determining function block 105 and the latch circuit moving function block 109; the 'flash lock circuit element' and the circuit 110' and the circuit can be tested. The information conversion function block 112 is connected; the bypass mode (bypassm〇d latch circuit data 111' is connected with the circuit information conversion function block 112; the anti-hold-error semiconductor integrated circuit data 113, and the circuit information ^ The power change ^ block 112 is connected. [0030] These function blocks generally operate in the following manner. [0031]

The timing analysis function block 102 measures the propagation delay between the circuit elements of the semiconductor integrated circuit and the propagation delay between the flip-flop circuits. Specifically, the timing analysis function block 102: separately calculates the delay of the component gate of the adjacent circuit 3 and the delay of the wiring by using the timing analysis method; using the calculation result, analyzing the delay between the circuit component gates and the connected flip-flops The propagation delay value of the connection between the circuits; the operation delay position 'to make the gate level or the circuit block level (circuitbl〇cklevd

The position on the circuit configuration and the designation of the metric are used as timing analysis data. Here, the timing analysis method means element-level simulation, delay-level cascading, (9) 叻 simulation, post-layout simulation, 1 sinking (10), "^^ stationization (1), and the like, specifically, Use the Primeti tm TimeMillTM and SPICETM from Synopsys (USA) [0032] The flip-flop-flash lock-circuit conversion decision function block 104 determines the split into a high-flash lock circuit and a low-flash lock circuit with reference to the timing analysis resource=3. The flip-flop circuit. Specifically, δ, flip-flop-flash lock-circuit conversion judgment function block 1〇4 reference timing analysis data=3 to determine which flip-flop circuit should be converted into a latch circuit, by Pros and cons, the switch in the road locks the power conversion and the mobile job error although dd _). ^,, the forward and reverse - flash lock - circuit conversion judgment function block! 〇 4 specified signal delay = point, operation The front and rear flip-flops of this node, and the output flip-flop-flash lock-circuit conversion beaker, which specifies the flip-flop circuit to be converted into a latch circuit. ' 12 200945088 [0033] —^Latch circuit end point decision Function block 1〇5 reference timing analysis data 1〇3 to decide ^ The circuit and the lock should be mosquitoes, and the filaments are solidified = the flash lock circuit n. Specifically, the flip-flop circuit judged by the forward and reverse circuit conversion and break function block 104 has been latched. After the lock, the flash lock circuit end decision function block 105 determines which of the converted high lock circuit and the converted low flash lock circuit should be fixed, and operates the fixed latch circuit to determine that it is not fixed. The end of the so-lock circuit, and the (10) circuit is moved. The lock circuit end point decision function block 105 makes a decision so that the position on the circuit configuration does not cause a full touch delay. _Electric turn point mosquito square 1 〇5 ❹ The wiring delay value per unit distance is obtained in advance, and the wiring length [0034] to achieve the necessary delay time is calculated, and the position of the wiring length is determined in the circuit configuration. [0035] Actually in the flip-flop After being converted into a pair of latch circuits, the flip-flop-latch_, the function block 108 refers to the latched flip-flop data to determine the connection information of the circuit. Specifically, the flip-flop circuit has been converted into After the lock circuit, the operation of the flip-flop _ = lock-circuit conversion Wei block (10) can determine how the connection f signal should be 皮 闩 latch circuit move function block 109 reference latch circuit move data 1 〇 7 to semi-determined m 贞 circuit Mobile circuit connection. Specifically, the operation of the function block 109 can determine which latch circuit should be fixed or moved, and after the latch circuit to be moved has been moved, How to be changed. The raw shell circuit information conversion function block 112 uses the flip-flop_latch_circuit block 108 and the flash lock power, the result of the function block 1〇9, and as the solid moon;

The latch circuit can be measured r · · - Latch circuit data 111 f circuit design data 101. 13 200945088 Error semiconductor integrated circuit data, this data is thus output to the anti-holding error semi-conductor volume circuit design data. [0037] In addition, the database generally has the following constitution. [0038] The semiconductor integrated circuit data 101 is data capable of simulating the following items: a gate level net list; a hardware description language (HDL); and a library containing delayed data and processing data; Single-chip (one_Chip) or core-level (core-level) data; and delay data including up-to-wire (including the distribution of layout data, wiring capacity, etc.). ''

[0039] The timing analysis data 103 is the result of the timing analysis performed by the timing analysis function block 102. The time series analysis data 103 is information on the electric potential displacement of each node on the time axis. [0040] The flip-flop/interlock-circuit conversion data 1〇6 is to be divided by the flip-flop_flash lock_circuit determination function block 104 with reference to the timing analysis data 103. The latch circuit and the low latch circuit are determined. The result of the decision of the flip-flop circuit. ° Gate [0041] '

The latch circuit movement data 107 is a latch circuit end point determination function block 1〇5 which is determined by reference to the timing analysis data 103 regarding the high latch circuit and the low latch circuit, which one should be fixed, and the unfixed latch The result of the decision of the end point of the lock circuit. Specifically, the flash lock circuit moves data 1〇7 to include high and low lock power, position information on the circuit diagram, and coordinate information on the layout configuration; data I contains the delay time required to maintain the error and achieve this delay Wiring length information required for time. [0042] The testable latch circuit data 110 is a latch circuit library that has been fixed by the flip-flop _ latch _ J J 108 109 and is suitable for the latch test of the scan circuit. Testable 14 200945088 In order to generate anti-scale error turn _Wei Road data U3 [0043] Block circuit data 111 is a credit lock circuit with bypass mode, and to generate anti-hold error semiconductor integrated circuit data ιΐ3 2 # If there is a general intention to use the side during the period: then the circuit of this database will be ran. ^The door lock circuit ▲ No, [0044] Ϊ ί ί ί ί ί ( 四 四 四 四 四 四 四 四 四 四 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据Memory, semiconductor memory or any other party 104, flash lock circuit endpoint decision function block 1〇5, ❹ energy block 108, question lock circuit secret function block (10), and circuit turn ^ work =:, program _ It can be operated in the middle of the channel; the second spoon is transmitted to other memory devices. Database 电路 Circuit conversion data, flash lock circuit movement = road - shell material 110, bypass mode lock circuit data m, 10 type lock lock circuit data 113. Anti-holding error semiconductor product [0046] (d) In the embodiment of the Japanese embodiment, the semiconductor integrated circuit as shown in FIG. 2...the system is executed by the central processing unit 3 from the above-mentioned __ 5 of 15 200945088 (software) The functions of the functional blocks shown in Fig. 1 are realized. Next, the overall operation of the first embodiment according to the present invention will be described in detail with reference to the flowcharts of Figs. 1, 2, 3, and 4. First, as shown in FIG. 3, the timing analysis function block 102 uses an appropriate test pattern to calculate between the logic element gates before the semiconductor integrated circuit is fabricated, that is, during the design of the semiconductor integrated circuit. The propagation delay between the flip-flop circuits relative to the semiconductor integrated circuit design data 101; when manufacturing the semiconductor integrated circuit, the semiconductor integrated circuit design data 1 is the design data used. Next, the timing analysis function block 102 outputs the propagation delay (SA2) in the form of the timing analysis data 1〇3. The timing analysis function block 102 determines whether or not a hold error has occurred by referring to the propagation delay calculated between the respective logic element gates and between the respective flip-flop circuits (SA4). If no hold error occurs, the timing analysis function block 1〇2 terminates the timing analysis (gA6). [0050] If a hold error occurs, the flip-flop-latch-circuit conversion judgment function block 1〇4 stores the timing analysis result of the propagation delay information 1〇3 to determine the positive and negative circuit to be latched (SA8) ). The flip-flop-latch_circuit conversion judgment function block 1〇4 detects the node of the forward and reverse error, and decides that the positive [0051] error at the two ends of the node is pulled. Error (SA12). If there is a step ^sA8). $Function block 1_ towards the lock decision block, the end of the i-time analysis, the front and back flash lock circuit conversion judgment function party 16 200945088 [0052] (4) The function side _ for the occurrence of a hold error, positive and negative lock · electric · f keep error ( SA18). If it can block the timing analysis of the Zhejiang (s ^ door lock - circuit conversion judgment work [0053]

The error of the device occurs at the two ends of the node in the middle of the flip-flop. The positive and negative door locks are detected. The device-flash lock circuit conversion judgment function block 104 is implemented after the subsequent 104 ^ positive and negative marriage 'circuit conversion touch function side 2 = The device should be converted to a flash lock circuit, and the relevant information is output to the power conversion circuit 106. Furthermore, the flip-flop-question lock-circuit conversion 2 _flash lock-circuit conversion data 106' is when the flip-flop is turned. Circuit control method, such as replacement clock line and replacement signal [0054] When the lock-circuit conversion function block 1〇8 determines that it is to be converted into a flash lock, the latch circuit end decision function block 105 determines the desire The fixed latch circuit and the latch circuit to be moved, thereby determining the end point of the latch to be moved. The f-compensation end point decision function block 丨Q5 processes the flip-flop to be converted into the latch circuit in accordance with the flow chart shown in FIG. [0055] In other words, the flip-flop-latch_circuit conversion function block 1〇8 is determined by the flip-flop (SB2) to be converted into a latch. The latch circuit terminal decision function block 1〇5 retrieves the high latch circuit and the low latch circuit (SB4) converted from the flip-flop circuit. In the case of a flash lock, the position of the circuit on the circuit configuration is the input side of the node where the hold error occurs, and the flip-flop-circuit conversion function block 108 fixes the high latch circuit (SB6). [0056] 17 200945088 If the position of the latch circuit on the circuit configuration is the output side of the node where the error is held, the latch circuit end decision function block 105 fixes the position of the low latch circuit on the circuit configuration (SB8). [0057] If the position of the latch circuit in the circuit configuration is in the middle of the continuous hold error, the latch circuit end point decision function block 1〇5 uses the same latch circuit as the front and rear flip-flops. Fixed method (SB1〇). However, if the front and back of the positive and negative ^ have different fixed methods, the flash lock circuit end point determines the function block 1 〇 5 either of the fixed methods. [0058] In addition, the latch circuit end decision function block 105 moves the latch circuit to the opposite direction of the lock circuit - the circuit element (SB12). The circuit 'timing analysis function block 1G2 uses the appropriate measurement method to output the nose and output the logic between the logic element gates and between the respective flip-flop circuits as the timing analysis tilt 1G3 (SB14). Timing analysis function block failure 1 analysis f material 1G3 to determine whether a hold error _6). If ΐf holds 5 errors, the lock circuit end point decision function block 105 again moves the circuit element one by one in the opposite direction of the moving flash lock fixed latch circuit.

(ISB12) 〇 [0060] VIII hold error 'Flash lock circuit end point decision function block 105 terminates the sequence ^. Therefore the movement will be repeated until the error is resolved. Transfer correction energy minus 1 (35 production error correction circuit after moving after the replacement of the letter = road movement function block 1G9 in the attached circuit has been moved [0061] 'Figure 5, the forward and reverse circuit is from The circuit consists of inputting the output signal of the low-sound flash lock circuit and the signal input to the inverted clock signal to the gate ', the clock 仏 terminal (its clock signal terminal inputs the normal clock signal), 18 200945088 = , that is, the anti-n· is viewed and locked, and the Wei thief is in the order of the electric power, and then the positive and negative 116 are converted into the lock circuit of the lock circuit, which is fixed at the timing of the circuit configuration. The position, and the fixed ^ lock eve too -, u set. Therefore, it is possible to perform the test and scan test as before the latch circuit is switched. Here, the formal verification is verified by the flip-flop. The formal verification is to verify that the semiconductor product is used in the middle of the node between the flip-flop circuit and the positive-reverse device is only used to design the common flip-flop. Circuit [0062] The operating circuit is ❹ = during the test, the path „., such as: =: = positive; circuit 110: set and = ^ into the circuit before the phase ί, this can be like a positive and negative static circuit Before the information conversion function block 112, these processes are applicable to half 3 households, electricity, and 2 materials 1G1. In the circuit information conversion function, such as 1〇1 (refer to circuit change information 602). Electric information design data = more Semi-conductor fine circuit design: ===4= = words 'shown in the circuit block above the block of Figure 8, which is input from the AND circuit from the ψ ψ + + Λ, Han Power 200945088 correction is only increase - anti The input signal C, therefore, the 6 positive shirt is D'. Especially in the buffer circuit using the Ν() τ circuit, the number of NOT circuits is odd and the reverse is reversed, and the cymbal circuit is set to be the source of the error. Integrated circuit design data ι〇ι & contains: such as the circuit · the summary of the summary and its two touch #料; Turning Bureau (1_ lion; used to form: two bellows, and the text of the narration of the text; and the implementation of the idle level (_7-Hua-level (macro-level) functional description of the hardware description language (HDL , hardware "description language" information. However, in the case of the specially described HDL data, 'even the subtle description of the original operation error. Therefore, even if the text level is positive, it should be minimally affected by other functions. The method is carried out. Therefore, the flip-flop circuit that achieves the conversion to the (10) circuit is stored in the closest state to the file of the flash-lock circuit, and # downstream may share the same design. 】 Such a process can produce anti-holding error semiconductor integrated circuit design data using only a slight increase in area (due to the flip-flop-flash lock-circuit conversion) to protect against [0065] (Second embodiment) ❹ Now 'will explain According to a second embodiment of the present invention, Fig. 9 is a flip-flop-based circuit of a general clock gate father t. Propagation between the flip-flop 2 and the flip-flop 3 Delaying the short message, so that the circuit will have a In the conventional method, a delay gate having a large area and a delay of one-half a half of the total clock frequency are inserted here, but it is difficult to control the latch circuit. [0066] In the second embodiment of the present invention, the timing analysis function block 102 is obtained by combining the circuit component units in the flip-flop device and the flip-flop 2, and the positive and negative 20 200945088 < ί 2 = step = The reverse of the circuit of the inverter 4 is transmitted to the predetermined day Π (4) specific and the 5 reverse 3 circuit is after the clock input, straight: ^; ί: 3 --- ί-- 3Ϊ- 104 2 ; ❹ m, replaced with a simple lock circuit L1 and high _ circuit end point determined in the step of Figure 4), ask the lock circuit to be fixed; on the output / ΐί input side. Furthermore, since the flip-flop 3 is closer to the error-preserving 3, the 丄cap road U and the high-flash lock circuit Η2, the electric 峪 end point function block 1 〇 5 fixed L2 and recorded #am 〇, 里, the flip-flop 2 and which circuit in the flip-flop 3 should be used to solve the delay time required to keep the error. It is converted into a question lock circuit, and the low flash lock circuit L1 and the flip-flop 2 are extended to Τ2 (as shown in Fig. 10(8)), and can solve the problem that ^=2 times up to 10(b) 3 is converted into a flash lock circuit, and the communication time between the positive path 被 2 is extended to Τ3, and can be solved as shown in Fig. 10(c), positive and negative 5 § 2 months, no crying, no soil fcb ', Fallacy. Furthermore, :== and high_road coffee: ^=,, [0068] as shown in the figure, this operation makes the propagation delay between u and H2 longer than the propagation delay before the lock 21 200945088 conversion By this, the solution is like the conventional method, causing the increase of the area at this time, and not between the numbers), but when the flip-flop is converted to _^= corresponding to the increase by several times by the insertion. When the circuit is in time, the area under the gate will increase. [0069] During the conversion, since H1 and L2 are fixed, the same timing position of H1 six-t in the circuit configuration exists at the same timing position as that of the flip-flop 2. Therefore, H1 lies in the same value as the flip-flop 2 or the flip-flop 3 of the flip-flop 3. Therefore, the data held by the device has a combination circuit that is executed with the positive position information = positive and negative benefits are applied to the circuit configuration from the input to the outside of the flip-flop and the same manner as before the combination circuit is locked. The resulting scan test can be used to ask [0070]. The lock lock circuit L1AH2 can activate the function of the lock circuit, as shown in Fig. 6a^f, the lock function, and the bypass mode can be switched. The bypass mode flash lock circuit is equipped with the mold circuit. A selector signal is coupled to the selector circuit and used to perform a scan test to initiate the selector circuit for selection. Therefore, use the mode input energy. Then, the selector is implemented on the flash lock function or scans the test work signal to bypass the selector, and Η1: so that during the scan test period, the input operation period, Η1 and L2 operate as _5 can test the lock circuit' Make the scan counter-measurement _ the right ^=. Therefore, 彳 _ _ can try and then, as shown in Figure 6 (b), the spy pendulum through a latch circuit circuit, the red j circuit can also be configured to: can choose (any - circuit no scan positive and negative In the case of any flash-lock circuit, any function of the flash lock circuit and & ^_ case, we can choose between starting the latch circuit with this function [0072]. 2 is converted into L1 and also the movement of each L2 and H2, H2, the movement of the knife f f1, H1, the conversion of the flip-flop 3 into a long-term inverter is converted into a testable latch circuit or bypass 22 200945088 Mode The lock circuit only strives to achieve one that satisfies the following changes: 'As shown in circle 8. Therefore, the flip-flop circuit that converts to the positive-reverse converter and converts into the lock-lock circuit saves the error. If the target is changed, especially The layout can correct the grammar on the wrong design data and the circuit before the change. If you can get significantly different gentlemen's fruit, if the performance is inconsistent, the unresolved part is even ^, because ^ is based on text. The integration of the design data 2: In terms of avoiding: two == points can avoid new settings The error has a u (four) trace test; and the circuit ^ to = solve the 'implementation of the form verification and the scan lock circuit of the debris convert the 繊 flip-flop to [0074] (third embodiment) ❹ 接Referring to Fig. 11, Fig. 12, and Fig. 3, Qian Zhiyi, the Japanese and Japanese secrets, in the semiconductor integrated circuit design department, the flute-, the second embodiment of the conductor ship according to the present invention. FIG. 12 is a schematic diagram of a semi-computer according to the present invention. FIG. 12 is a second embodiment of the semiconductor integrated circuit design system for electronic, and the invention corresponds to FIG. 1 to FIG. 3 and shares the same number therein. Component: There is [0075] The example shows an example of a semiconductor integrated circuit design system, in which when Li Liling’s right-handed towel is used to solve the problem, the high- and low-flash (four) sets have multiple high-circuits. A library of multiple low-circuit circuits, = pure for inclusion in the semiconductor surface circuit design data 1 (), each program has a different gate width to implement fine-tuning of the timing in the timing analysis. 23 200945088 [0076 】 The most semiconductor integrated circuit design system, and the second real The block has a positive and negative L circuit. The function of the sturdy and sloping function is in the fanger road. It will determine the function of the flashing circuit end point decision function block (10). Ask the driving force of the lock (such as (four) degrees). Touch _ surgery = 贞 = = = _1 conversion drive force judgment function block 115 to determine. [0077] ❹ Ϊ Ϊ Ϊ Ζΐ 转换 转换 转换 转换 转换 转换 转换 转换The difference between the flow chart of the first and the third embodiment is the driving force selection of the setting_circuit after the Γ1 Γ Γ 上 上 上 上 选择 选择 选择 选择 选择 微 微 微 微 微 产业 产业 产业 产业 产业 产业 产业 产业 产业 产业 产业 产业 产业 产业The implementation of this day's money can be a person - turn _ body Wei, the body circuit only _ micro-area area and simple design method to solve the problem because the side delay between the pair is too small, resulting in "simple error" electricity, and solve various Claim. People squatting early, 仗【00**】 j has not been invented in all (4) Swiveling (4) circuits of the juice-making device (design system), its application is unlimited, ° [00** The description of the embodiments should be understood only to illustrate that the present embodiment of the invention should be considered as a singularity. Silk = read s sell instructions can be implemented in the absence of these specific details of the disk by the cover of the cover of the eve of the slamming ... ... 丄 贯 贯 下 与 与 申 申 申 申 申 申 申 申 申 申 申 申 ί ί ί ί ί ί ί ί ί ί ί ί ί ί The preferred embodiments and the accompanying drawings are to be understood as being in accordance with the embodiments of the present invention. The method of the transposed volume circuit design system of the first embodiment is a positive semiconductor integrated circuit design system according to the first embodiment of the present invention. The semiconductor integrated circuit design system of the first embodiment of the semiconductor integrated circuit design system at the time of the month ====== conductor_road design system; = circuit, lock circuit ==^= y _ Road design department for the change of Lang Qing 25 200945088 long for T3. Figure 10 (c) is a structural diagram of a circuit of a semiconductor integrated circuit design system according to a second embodiment of the present invention, which is based on a flip-flop circuit, in which the flip-flop 2 and the flip-flop 3 are both whitened. It is converted into a latch circuit, and the communication time between the low latch circuit [I and the high latch circuit Η2 is extended to Τ4. Figure 2 is a block diagram of a semiconductor integrated circuit design system in accordance with a third embodiment of the present invention. Figure 12 is a block diagram showing a semiconductor integrated circuit design system in accordance with a third embodiment of the present invention.

Figure 13 is a flow chart showing the steps of the flip-flop of the flip-flop of the semiconductor integrated circuit design system in accordance with the third embodiment of the present invention. Figure 14 is a flow diagram of a circuit delay resolution system for a related semiconductor integrated circuit design system. Figure 15 is a flow diagram of a circuit delay resolution system for a related semiconductor integrated circuit design system. [Main component symbol description] 3 CPU 5 Program memory 7 Library memory 9 Program memory 11 Bank memory 101 Semiconductor integrated circuit data 102 Timing analysis function block 103 Timing analysis data 104 Positive and negative device - Flash lock - Circuit Conversion Judgment Function Block 105 Latch Circuit Endpoint Decision Function Block 106 Rectifier - Flash Lock - Circuit Conversion Data 107 Latch Circuit Movement Data 108 Rectifier - Latch - Circuit Conversion Function Block 26 200945088 109 Latch Circuit Movement Function block 110 can test the latch circuit data 111 bypass mode latch circuit data 112 circuit information conversion function block 113 anti-hold error semiconductor integrated circuit data 115 flip-flop - flash lock - circuit conversion driving force judgment function block 6 〇 1 Text file circuit correction 602 Circuit change information SA2 Timing analysis SA4 whether there is a hold error❹

SA6 termination timing analysis error The flip-flops at both ends of the flip-flop are converted into the sense lock circuit SA10. The timing analysis of the input side flip-flops SA12 is there a hold error SA14 termination timing analysis SA16 timing analysis of the output side flip-flops SA18 there is a hold error SA20 termination timing analysis SA22 selects the latch drive force, the heart I is converted to the flash lock circuit positive and negative = the rear positive and negative 11 converted high __ circuit = device = = in the middle of continuous hold error 'Using the direction SB 12 opposite to the front and rear fixed lock circuits, the latch circuit to be moved is moved one by one. SB 14 Timing analysis SB16 is there a hold error SB 18 Termination timing analysis 27

Claims (1)

200945088 VII. Patent application scope: ^- Designing and setting up the volumetric circuit, 3 is mounted in the semiconductor integrated circuit, and the volumetric body circuit pack timing analysis means, including the design, including: ' "" Ή Ή , , , , , , , , , , , , , , , , , , , , , , 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点As a result, according to the signal of the position at the position of the circuit, the circuit information conversion means to be configured by the circuit is selected from the two lock circuit towels, and the wiring information to be fixed is replaced by the wiring information of the circuit to be converted. . The circuit of the circuit is changed to 2. The design of the semiconductor is as follows: = ί _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The location. -_贞电4.m profit range item 3 design semiconductor integrated circuit design device blowing; = point of the secret of the flip-flop circuit is converted into (four) circuit, the electric, Bessie conversion means the positive The lock circuit converted by the counter-latch-locking means is fixed on the circuit of the original forward-reverse H circuit; the position of the original flip-flop circuit in the circuit configuration. g 疋q 28 200945088, in the design device of the design semiconductor integrated circuit of the fourth application patent scope, although the test is fixed to the original flip-flop circuit in the circuit configuration with the latch circuit or In the low latch circuit, the circuit information conversion means is implemented as a testable latch circuit for describing the function of the inverter circuit; meanwhile, when the test is not fixed but is moved, the high flash lock circuit or the low voltage The electrical i-information conversion means performs a scan test via the flip-flop conversion method, and the lock-up circuit is a bypass mode lock circuit that acts to bypass the latch circuit. , ======================================================================================================= The node detects the error and indicates that the error has occurred. The two types of flash lock circuits of the analysis lock circuit are borrowed from the analysis function; the circuit is converted to include a high latch circuit and a low latch. Point determination function, refer to the analysis result of the timing analysis function, 29 200945088 For the position of the system lock on the circuit configuration and the node is placed in the direction of the circuit, and the question lock circuit is selected in the circuit with two flip circuits Fixed flash lock circuit; and data transfer;; r fixed circuit circuit resources (four) material depends on electricity (four) -, radiant converter electric 1 〇. If you apply for patent range 8 to design semiconductor products The method of the body circuit, which determines the function by the latching end point, and the positive and negative of the front and rear of the section (four) are as follows: The method for designing a semi-conducting hybrid circuit can be converted by the information of the circuit, and the circuit of the electric circuit is fixed at the position of ====1. For example, the method for designing a semiconductor integrated circuit of the patent application scope, by the circuit information conversion function, when the test is fixed on the position of the original flip-flop circuit, the 200945088 high-level circuit or The function of the cigarette lock circuit can test the latch circuit, and at the same time, the circuit has become a scanning flip-flop circuit. When the test is not fixed but is moved, the latch circuit is latched and latched via the flip-flop. Or the low latch circuit test, the latch circuit is similar to scanning the latch circuit before the bypass conversion function is switched. The work latch circuit is operated by the circuit to bypass the design device. The design includes a semiconductor integrated body, an electric power program, wherein the design device circuit allows the computer to execute the semiconductor integrated timing analysis function of the flip-flop circuit. Should contain the timing analysis data of the piano 7 value and detect the point of holding the input and output nodes of the second = 2; f wrong, and indicate that the flip-flop-latch-circuit conversion function of the hold error has occurred, I The inverter circuit is converted into, including high == relative ===: at; ===,; fruit, according to the position of the signal in the input/output direction of the circuit configuration position 1 the two _ circuits are selected to be The fixed circuit is replaced by the wiring of the circuit to be converted and the circuit information of the circuit to be solidified.