200933891 九、發明說明： .【發明所屬之技術領域】 • 本發明係關於一種薄膜電晶體基板及其製造方法，以 及一種金屬導線之佈線結構及其製造方法。 【先前技術】 目前，液晶顯示器逐漸取代傳統陰極射線管（Cath〇de Ray Tube，CRT)顯示器，而且，由於液晶顯示器具有輕、 ❾薄、體積小等特點，使其非常適合應用於桌上型電腦、筆 記型電腦、個人數位助理（Pers〇nal Digital心仏以卟 P D A)、便攜式電話、電視及多種辦公自動化與視聽設備 中。液晶面板係其主要元件，一般包括一薄膜電晶體基板、 一衫色濾光片基板及一夾於該薄膜電晶體基板與該彩色濾 光片基板之間之液晶層。 請參閱圖1，其係一種先前技術之薄膜電晶體基板之平 面示意圖。該薄膜電晶體基板1〇包括一顯示區U、一邊框 ❹區12及一積體電路區13。該顯示區η位於該薄膜電晶體基 板10之中央位置。該邊框區12位於該顯示區η之外圍。該 積體電路區13位於該邊框區12之下方。該邊框區12設置複 數金屬導線121，該積體電路區13設置至少一驅動晶片 131 ’該金屬導線121與該驅動晶片131之引腳（未標示）電連 接。 5青一併參閱圖2 ’其係圖1所示薄膜電晶體基板J 〇區域 A之放大示意圖。該薄膜電晶體基板1〇還包括位於該顯示 區11之複數閘極線111及複數資料線112，並由該複數閘極 200933891 線111及該複數資料線112構成之最小區域界定複數像素單 元110。該邊框區12之金屬導線121分別與該顯示區11之閘 極線111電連接，該驅動晶片131輸出之驅動訊號經由該金 屬導線121傳送至該閘極線111。 請一併參閱圖3，其係圖2所示薄臈電晶體基板10沿瓜-Π方向之剖面放大示意圖。該薄膜電晶體基板10進一步包 括一絕緣基底101、一閘極113、一閘極絕緣層102、一半導 體層103、一源極114、一汲極115及一像素電極116。該閘 極113設置於該顯示區11之絕緣基底101上，該金屬導線121 設置於該邊框區12之絕緣基底101上。該閘極絕緣層102覆 蓋該閘極113、該金屬導線121及該絕緣基底101。該半導體 層103設置於該閘極113對應之閘極絕緣層102表面。該源極 114及汲極115分別設置在該半導體層103表面及其邊緣之 閘極絕緣層102表面。該像素電極116設置於該像素單元110 對應之閘極絕緣層101表面，並與該汲極115電連接。 惟，該薄膜電晶體基板10之金屬導線121受到微影製程 之分辨率及製程環境中污染微粒之尺寸限制，各金屬導線 121之間必須要有一定間隔以避免產生短路。該間隔一般與 該金屬導線121之寬度相當。因此，該金屬導線121之佈線 結構需要較大的面積來實現，即在該薄膜電晶體基板10上 必須預留足夠之邊框區12以排佈該金屬導線121，導致對於 固定尺寸之該薄膜電晶體基板10無法進一步加大該顯示區 11之尺寸。 【發明内容】 200933891 有鑑於此，提供一種窄邊框之薄膜電晶體基板實為必 .要。 * 有鑑於此，提供一種窄邊框之薄膜電晶體基板之製造 方法實為必要。 有鑑於此，提供一種金屬導線之佈線結構實為必要。 有鑑於此，提供一種佈線結構之製造方法實為必要。 一種薄膜電晶體基板，其包括一絕緣基底、複數第一 ❹金屬導，、複數第二金屬導線及複數驅動線，於該絕緣基 底上界定一顯示區及一邊框區，該邊框區位於該顯示區之 外圍，該複數驅動線位於該顯示區，該第一金屬導線與該 第一金屬導線位於該邊框區並與該驅動線相連接，其中， 該邊框區進一步設置有複數絕緣牆，該複數絕緣牆等間距 排佈，該第一金屬導線位於該絕緣牆上，該第二金屬導線 位於該絕緣牆之間之絕緣基底上。 一種薄膜電晶體基板之製造方法，其步驟包括：提供一 ❹絕緣基底，其包括一顯示區及一邊框區，該邊框區位於該 顯不區之外圍；於該絕緣基底上沉積一絕緣層；在該絕緣 基底之邊框區形成複數絕緣牆，該絕緣牆等間距排列；於 該絕緣基底及該絕緣牆上沉積一第一金屬層；在該絕緣基 底之顯不區形成一閘極及一閘極線，且於該邊框區一併形 成一第一金屬導線及一第二金屬導線，該第—金屬導線位 於該絕緣牆表面，該第二金屬導線位於該絕緣牆間隔之絕 緣基底上。 一種薄膜電晶體基板之製造方法，其步驟包括：提供一 9 200933891 2緣基底’在該絕緣基底上定義-邊框區及-顯示區，該 .邊框區位於該顯示區之外圍；於該絕緣基底上沉積一第一 *金屬層；形成一閘極及一閘極線；於該閘極、該閘極線及 其一侧之絕緣基底上沉積一閘極絕緣層及一半導體層；形 成一半導體層圖案及複數絕緣牆，該半導體層圖案位於該 閘極對應之閘極絕緣層上，該絕緣牆位於該邊框區之絕緣 基底上，於該半導體層圖案、該絕緣牆、該閘極絕緣層及 〇該絕緣基底上沉積一第二金屬層；形成一源極、一没極、 複數第-金屬導線及第二金屬導線，該第—金屬導線位於 該絕緣牆上，該第二金屬導線位於該絕緣牆之間之絕緣基 底上。 一種金屬導線之佈線結構，其包括一基底、複數絕緣 牆、複數第一金屬導線及複數第二金屬導線。該絕緣牆等 間距排佈於該基底上，該第一金屬導線位於該絕緣牆:， 該第二金屬導線位於該絕緣牆之間之基底上。 ◎ 一種佈線結構之製造方法，其包括：提供一絕緣基底； 於該絕緣基底上沉積一絕緣層；於一道光罩製程形成複數 絕緣牆；於該絕緣牆及該絕緣基底上沉積一金屬層，於該 絕緣牆上形成一第一金屬導線，於該絕緣牆間隔之絕緣基 底上形成一第二金屬導線。 相較於先前技術’前述薄膜電晶體基板邊框區之相鄰 之第一金屬導線與第二金屬導線於垂直於該絕緣基底方向 以不同層設置方式實現絕緣，而並非在水平方向上實現絕 緣’可以大大減小該第一金屬導線與該第二金屬導線在水 200933891 平方向之間距。因此佈線結構之面積可大大減小，邊框區 . 之寬度亦可大大減小。 .【實施方式】 請參閱圖4,其係本發明薄膜電晶體基板之第一實施 方式之平面示意圖。該薄膜電晶體基板2〇包括一顯示區 21、一邊框區22及一積體電路區23。該顯示區21位於該 薄膜電晶體基板20之中央位置。該邊框區22位於該顯示 ❹區21之外圍。該積體電路區23位於該邊框區22之下方。 該邊框區22設置有複數第一金屬導線221及複數第二金屬 導線222，該第一金屬導線221與該第二金屬導線222高 低間隔排列分布並相互絕緣。該積體電路區23設置至少— 驅動晶片231。該第一金屬導線221及該第二金屬導線222 分別與該驅動晶片231之引腳電連接。 請一併參閱圖5 ’其係圖4所示該薄膜電晶體基板2〇 之區域B之放大示意圖。該薄膜電晶體基板20還包括位 ©於該顯示區21之複數閘極線211及複數資料線212,並由 該複數閘極線211及複數資料線212構成之最小區域界定 複數像素單元21〇。該邊框區22之第一金屬導線221經由 連接結構223與該顯示區21之閘極線211相連接，該第 二金屬導線222與該顯示區21之閘極線211直接連接。驅 動°孔被藉由該驅動晶片231輸出並經由該第一金屬導線 221及該第二金屬導線222傳送至該閘極線211。 睛一併參閱圖6，其係圖5所示之薄膜電晶體基板2〇 沿VI -VI方向之剖面放大示意圖。該薄膜電晶體基板2〇進 11 200933891 一步包括一絕緣基底201、複數絕緣牆220、一閘極213、 .一閘極絕緣層202、一半導體層圖案203、一源極214、一 汲_極215、一純化層204、一第一接觸孔a及一像素電極 « 216。該絕緣牆220設置於該邊框區22之絕緣基底201上， 該絕緣牆220為間隔之柱狀，且其寬度與其間距一致。該 第一金屬導線221設置於該絕緣牆220表面上，該第二金 屬導線222設置於該絕緣牆220間隔處之絕緣基底201 上。該閘極213設置於該顯示區21之絕緣基底201上。該 ®閘極絕緣層202覆蓋該第一金屬導線221、該第二金屬導 線222、該閘極213及該絕緣基底201。該半導體層圖案 203設置於該閘極213對應之閘極絕緣層202表面。該源 極214及汲極215分別設置在該半導體層圖案203表面及 其邊緣之閘極絕緣層202上。該鈍化層204覆蓋該邊框區 22之閘極絕緣層202，該顯示區21之源極214、汲極215 及其二側之閘極絕緣層202，並於該汲極215處形成一第 p —接觸孔a。該像素電極216設置於該顯示區21之鈍化層 204表面上，並藉由該第一接觸孔a與該汲極215電連接。 請一併參閱圖7，其係圖5所示之薄膜電晶體基板·20 沿Μ -W方向之剖面放大示意圖。該薄膜電晶體基板20進 一步包括一第二接觸孔b、一第三接觸孔c及一透明導電 連接層224,該第二接觸孔b、該第三接觸孔c及該透明導 電連接層224構成該連接結構223。該第二接觸孔b貫穿 該第一金屬導線221對應之閘極絕緣層202及鈍化層 204，並使部份該第一金屬導線221外露。該第二接觸孔c 12 200933891 貫穿該閘極線211對應之閘極絕緣層202及鈍化層204， . 並使部份該閘極線211外露。該透明導電連接層224藉由 該第二接觸孔b及第三接觸孔c將該第一金屬導線221與 * 該閘極線211電連接。 請一併參閱圖8至圖15。圖8係本發明薄膜電晶體基 板20製造方法之流程圖，圖9至圖15係該薄膜電晶體基 板20之製造方法之各主要步驟之示意圖。該薄膜電晶體基 板20之製造方法之主要步驟如下： θ (S20)形成絕緣牆220: 請一併參閱圖9,提供一絕緣基底201，該絕緣基底 201可以係玻璃、石英或者陶瓷等絕緣材質。在該絕緣基 底201上沉積一有機絕緣層（圖未示）。於第一道光罩製程 中，在該邊框區22形成該絕緣牆220。該絕緣牆220之剖 面為矩形圖案，二相鄰絕緣牆220之間距與該絕緣牆220 之寬度相等。 & (S21)形成閘極213、閘極線211、第一金屬導線221 及第二金屬導線222: 請一併參閱圖1〇，在該絕緣基底201及該絕緣牆220 上沉積一第一金屬層（圖未示）。該第一金屬層之材質可為 铭系金屬、钼、絡、组或銅。於第二道光罩製程中，分別 在該邊框區22形成該第一金屬導線221及該第二金屬導線 222，在該顯示區21形成該閘極213及該閘極線211。 該第一金屬導線221形成於該絕緣牆220上，該第二 金屬導線222形成於該絕緣牆220之間之絕緣基底201上 13 200933891 並與該閘極線211直接相連接（圖未示）。該絕緣牆220沿 . 垂直於該絕緣基底201方向之高度大於該第一金屬層之厚 度，使得該第一金屬導線221與該第二金屬導線222處於 » 不同層且相互絕緣。該第一金屬導線221與該第二金屬導 線222在沿水平方向為無間隔排列結構。 (522) 形成閘極絕緣層2〇2: 請一併參閱圖11，在該絕緣基底201、該閘極213、 該閘極線211、該第一金屬導線221及該第二金屬導線222200933891 IX. Description of the Invention: 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and a wiring structure of a metal wire and a method of manufacturing the same. [Prior Art] At present, liquid crystal displays are gradually replacing traditional cathode ray tube (CRT) displays, and because of their lightness, thinness and small size, liquid crystal displays are very suitable for desktop applications. Computers, notebooks, personal digital assistants (Pers〇nal Digital 仏 PDA), portable phones, televisions and a variety of office automation and audiovisual equipment. The liquid crystal panel is a main component, and generally includes a thin film transistor substrate, a shirt color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate. Please refer to Figure 1, which is a plan view of a prior art thin film transistor substrate. The thin film transistor substrate 1 includes a display area U, a bezel area 12, and an integrated circuit area 13. The display area η is located at a central position of the thin film transistor substrate 10. The bezel area 12 is located at the periphery of the display area n. The integrated circuit area 13 is located below the bezel area 12. The frame region 12 is provided with a plurality of metal wires 121, and the integrated circuit portion 13 is provided with at least one driving chip 131'. The metal wires 121 are electrically connected to pins (not shown) of the driving chip 131. 5 青一一 Refer to Fig. 2' is an enlarged schematic view of the thin film transistor substrate J 〇 region A shown in Fig. 1. The thin film transistor substrate 1 further includes a plurality of gate lines 111 and a plurality of data lines 112 located in the display area 11, and the minimum area formed by the plurality of gates 200933891 line 111 and the plurality of data lines 112 defines the plurality of pixel units 110. . The metal wires 121 of the frame region 12 are electrically connected to the gate lines 111 of the display area 11, and the driving signals outputted by the driving chips 131 are transmitted to the gate lines 111 via the metal wires 121. Please refer to FIG. 3 together, which is an enlarged cross-sectional view of the thin germanium transistor substrate 10 shown in FIG. 2 along the melon-Π direction. The thin film transistor substrate 10 further includes an insulating substrate 101, a gate 113, a gate insulating layer 102, a half conductor layer 103, a source 114, a drain 115, and a pixel electrode 116. The gate 113 is disposed on the insulating substrate 101 of the display area 11. The metal wire 121 is disposed on the insulating substrate 101 of the frame region 12. The gate insulating layer 102 covers the gate 113, the metal wiring 121, and the insulating substrate 101. The semiconductor layer 103 is disposed on the surface of the gate insulating layer 102 corresponding to the gate 113. The source electrode 114 and the drain electrode 115 are respectively disposed on the surface of the gate insulating layer 102 on the surface of the semiconductor layer 103 and its edge. The pixel electrode 116 is disposed on the surface of the gate insulating layer 101 corresponding to the pixel unit 110 and electrically connected to the drain 115. However, the metal wires 121 of the thin film transistor substrate 10 are limited by the resolution of the lithography process and the size of the contaminating particles in the process environment, and the metal wires 121 must be spaced apart to avoid short circuits. This spacing is generally equivalent to the width of the metal wire 121. Therefore, the wiring structure of the metal wire 121 needs to be realized by a large area, that is, a sufficient frame area 12 must be reserved on the thin film transistor substrate 10 to arrange the metal wire 121, resulting in the film being fixed for a fixed size. The crystal substrate 10 cannot further increase the size of the display region 11. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a thin-film thin-film transistor substrate. * In view of this, it is necessary to provide a method of manufacturing a thin film transistor substrate with a narrow bezel. In view of this, it is necessary to provide a wiring structure of a metal wire. In view of this, it is necessary to provide a method of manufacturing a wiring structure. A thin film transistor substrate comprising an insulating substrate, a plurality of first metal wires, a plurality of second metal wires and a plurality of driving lines, wherein a display area and a frame area are defined on the insulating substrate, the frame area is located on the display The plurality of driving lines are located in the display area, the first metal wire and the first metal wire are located in the frame area and are connected to the driving line, wherein the frame area is further provided with a plurality of insulating walls, the plurality The insulating walls are equally spaced, the first metal wire is located on the insulating wall, and the second metal wire is located on the insulating substrate between the insulating walls. A method for manufacturing a thin film transistor substrate, the method comprising: providing an insulating substrate comprising a display area and a frame area, the frame area being located at a periphery of the display area; depositing an insulating layer on the insulating substrate; Forming a plurality of insulating walls in the frame region of the insulating substrate, the insulating walls are equally spaced; depositing a first metal layer on the insulating substrate and the insulating wall; forming a gate and a gate in the visible region of the insulating substrate And a first metal wire and a second metal wire are formed in the frame region, the first metal wire is located on the surface of the insulating wall, and the second metal wire is located on the insulating substrate spaced apart from the insulating wall. A method for manufacturing a thin film transistor substrate, the method comprising the steps of: providing a 9 200933891 2 edge substrate defined on the insulating substrate - a frame region and a display region, the bezel region being located at a periphery of the display region; Depositing a first metal layer; forming a gate and a gate line; depositing a gate insulating layer and a semiconductor layer on the gate, the gate line and an insulating substrate on one side thereof; forming a semiconductor a layer pattern and a plurality of insulating walls, the semiconductor layer pattern is located on the gate insulating layer corresponding to the gate, the insulating wall is located on the insulating substrate of the frame region, the semiconductor layer pattern, the insulating wall, the gate insulating layer And depositing a second metal layer on the insulating substrate; forming a source, a gate, a plurality of first metal wires and a second metal wire, wherein the first metal wire is located on the insulating wall, and the second metal wire is located The insulating wall is insulated between the substrates. A wiring structure of a metal wire includes a substrate, a plurality of insulating walls, a plurality of first metal wires, and a plurality of second metal wires. The insulating walls are equally spaced on the substrate, and the first metal wires are located on the insulating wall: the second metal wires are located on the substrate between the insulating walls. ◎ A method for manufacturing a wiring structure, comprising: providing an insulating substrate; depositing an insulating layer on the insulating substrate; forming a plurality of insulating walls in a mask process; depositing a metal layer on the insulating wall and the insulating substrate, A first metal wire is formed on the insulating wall, and a second metal wire is formed on the insulating substrate spaced apart from the insulating wall. Compared with the prior art, the first metal wire and the second metal wire adjacent to the frame region of the aforementioned thin film transistor substrate are insulated in a different layer arrangement perpendicular to the direction of the insulating substrate, and not in the horizontal direction. The distance between the first metal wire and the second metal wire in the horizontal direction of the water 200933891 can be greatly reduced. Therefore, the area of the wiring structure can be greatly reduced, and the width of the frame area can be greatly reduced. [Embodiment] Please refer to Fig. 4, which is a plan view showing a first embodiment of a thin film transistor substrate of the present invention. The thin film transistor substrate 2 includes a display area 21, a bezel area 22, and an integrated circuit area 23. The display area 21 is located at a central position of the thin film transistor substrate 20. The bezel area 22 is located at the periphery of the display crotch area 21. The integrated circuit area 23 is located below the bezel area 22. The frame region 22 is provided with a plurality of first metal wires 221 and a plurality of second metal wires 222. The first metal wires 221 and the second metal wires 222 are arranged at a high interval and are insulated from each other. The integrated circuit region 23 is provided with at least a driving wafer 231. The first metal wire 221 and the second metal wire 222 are electrically connected to the pins of the driving chip 231, respectively. Referring to Fig. 5, an enlarged view of a region B of the thin film transistor substrate 2A shown in Fig. 4 is shown. The thin film transistor substrate 20 further includes a plurality of gate lines 211 and a plurality of data lines 212 in the display area 21, and a minimum area formed by the plurality of gate lines 211 and the plurality of data lines 212 defines the plurality of pixel units 21A. . The first metal wire 221 of the frame region 22 is connected to the gate line 211 of the display area 21 via a connection structure 223, and the second metal wire 222 is directly connected to the gate line 211 of the display area 21. The driving hole is outputted by the driving wafer 231 and transmitted to the gate line 211 via the first metal wire 221 and the second metal wire 222. Referring to Fig. 6, an enlarged cross-sectional view of the thin film transistor substrate 2A shown in Fig. 5 along the VI-VI direction is shown. The thin film transistor substrate 2 includes 11 an insulating substrate 201, a plurality of insulating walls 220, a gate 213, a gate insulating layer 202, a semiconductor layer pattern 203, a source 214, and a drain. 215, a purification layer 204, a first contact hole a and a pixel electrode «216. The insulating wall 220 is disposed on the insulating substrate 201 of the frame region 22, and the insulating wall 220 has a columnar shape with a width corresponding to the spacing thereof. The first metal wire 221 is disposed on the surface of the insulating wall 220, and the second metal wire 222 is disposed on the insulating substrate 201 at the interval of the insulating wall 220. The gate 213 is disposed on the insulating substrate 201 of the display area 21. The gate insulating layer 202 covers the first metal wire 221, the second metal wire 222, the gate electrode 213, and the insulating substrate 201. The semiconductor layer pattern 203 is disposed on the surface of the gate insulating layer 202 corresponding to the gate electrode 213. The source electrode 214 and the drain electrode 215 are respectively disposed on the surface of the semiconductor layer pattern 203 and the gate insulating layer 202 at the edge thereof. The passivation layer 204 covers the gate insulating layer 202 of the frame region 22, the source electrode 214 of the display region 21, the drain electrode 215 and the gate insulating layer 202 on both sides thereof, and forms a p-th layer at the drain electrode 215. - contact hole a. The pixel electrode 216 is disposed on the surface of the passivation layer 204 of the display region 21, and is electrically connected to the drain 215 through the first contact hole a. Please refer to FIG. 7 together, which is an enlarged cross-sectional view of the thin film transistor substrate 20 shown in FIG. 5 along the Μ-W direction. The thin film transistor substrate 20 further includes a second contact hole b, a third contact hole c and a transparent conductive connection layer 224. The second contact hole b, the third contact hole c and the transparent conductive connection layer 224 are formed. The connection structure 223. The second contact hole b penetrates the gate insulating layer 202 and the passivation layer 204 corresponding to the first metal wire 221, and exposes a portion of the first metal wire 221. The second contact hole c 12 200933891 penetrates the gate insulating layer 202 and the passivation layer 204 corresponding to the gate line 211, and exposes a portion of the gate line 211. The transparent conductive connection layer 224 electrically connects the first metal wire 221 and the gate line 211 via the second contact hole b and the third contact hole c. Please refer to Figure 8 to Figure 15 together. Fig. 8 is a flow chart showing a method of manufacturing the thin film transistor substrate 20 of the present invention, and Figs. 9 to 15 are schematic views showing major steps of a method of manufacturing the thin film transistor substrate 20. The main steps of the manufacturing method of the thin film transistor substrate 20 are as follows: θ (S20) forms an insulating wall 220: Referring to FIG. 9 together, an insulating substrate 201 is provided, which may be an insulating material such as glass, quartz or ceramic. . An organic insulating layer (not shown) is deposited on the insulating substrate 201. The insulating wall 220 is formed in the bezel area 22 during the first mask process. The insulating wall 220 has a rectangular cross section, and the distance between the two adjacent insulating walls 220 is equal to the width of the insulating wall 220. < (S21) forming a gate 213, a gate line 211, a first metal wire 221 and a second metal wire 222: Please refer to FIG. 1A together, depositing a first layer on the insulating substrate 201 and the insulating wall 220 Metal layer (not shown). The material of the first metal layer may be metal, molybdenum, complex, group or copper. In the second mask process, the first metal wire 221 and the second metal wire 222 are respectively formed in the frame region 22, and the gate electrode 213 and the gate line 211 are formed in the display region 21. The first metal wire 221 is formed on the insulating wall 220. The second metal wire 222 is formed on the insulating substrate 201 between the insulating wall 220 and is directly connected to the gate line 211 (not shown). . The height of the insulating wall 220 in the direction perpendicular to the insulating substrate 201 is greater than the thickness of the first metal layer, such that the first metal wire 221 and the second metal wire 222 are in different layers and are insulated from each other. The first metal wire 221 and the second metal wire 222 are arranged in a space-free arrangement in the horizontal direction. (522) Forming a gate insulating layer 2〇2: Please refer to FIG. 11 together, the insulating substrate 201, the gate electrode 213, the gate line 211, the first metal wire 221, and the second metal wire 222.
Q 上，用化學氣相沉積（Chemical Vapor Deposition，CVD)方 法形成一閘極絕緣層202，其材質為氮化矽（SiNx)。 (523) 形成半導體層圖案203: 請一併參閱圖12，在該閘極絕緣層202上形成一半導 體層（圖未示）。於第三道光罩製程中，在該閘極213對應 之閘極絕緣層202上形成一半導體層圖案203。 (524) 形成源極214及汲極215: P 請一併參閱圖13，在該閘極絕緣層202及該半導體層 圖案203上沉積一第二金屬層（圖未示）。該第二金屬層之 材質可為钽、銘合金、钥、銘或钥鶴合金。於第四道光罩 製程中，在該半導體層圖案203及其二側之閘極絕緣層202 表面形成一源極214及一汲極215。 (525) 形成鈍化層204及第一接觸孔a、第二接觸孔b、 第三接觸孔c: 請一併參閱圖14，在該閘極絕緣層202、該源極214 及該汲極215上沉積一鈍化層204。該鈍化層204之材質 14 200933891 為氧切或氮切。在該鈍化層咖上沉積—光阻層（圖才 第五道光罩對準該光阻層㈣，其中該道光罩為狽 J：科总顯#曝光後之光阻層，再以該剩餘光阻圖案為遽 罩對鈍化層204及閘極絕緣層2G2進行㈣，形成一第— 接觸孔a、一第二接觸孔b及一第三接觸孔。。In Q, a gate insulating layer 202 is formed by a chemical vapor deposition (CVD) method, and is made of tantalum nitride (SiNx). (523) Forming the semiconductor layer pattern 203: Referring to Fig. 12 together, a half conductor layer (not shown) is formed on the gate insulating layer 202. In the third mask process, a semiconductor layer pattern 203 is formed on the gate insulating layer 202 corresponding to the gate 213. (524) Forming the source 214 and the drain 215: P Referring to FIG. 13, a second metal layer (not shown) is deposited on the gate insulating layer 202 and the semiconductor layer pattern 203. The material of the second metal layer may be 钽, Ming alloy, key, Ming or key crane alloy. In the fourth mask process, a source 214 and a drain 215 are formed on the surface of the semiconductor layer pattern 203 and the gate insulating layer 202 on both sides thereof. (525) forming the passivation layer 204 and the first contact hole a, the second contact hole b, and the third contact hole c: Please refer to FIG. 14 together, the gate insulating layer 202, the source 214 and the drain 215 A passivation layer 204 is deposited thereon. The material of the passivation layer 204 14 200933891 is oxygen cut or nitrogen cut. Depositing a photoresist layer on the passivation layer (the fifth mask is aligned with the photoresist layer (4), wherein the photomask is a photoresist layer after exposure, and the remaining light is The resist pattern is a mask (4) for the passivation layer 204 and the gate insulating layer 2G2, and a first contact hole a, a second contact hole b and a third contact hole are formed.
❹ (S26)形成像素電極216及透明導電連接層224: 請一併參閱圖15,在該鈍化層2〇4上沉積一透明導電 層（圖未产示）。透明導電層可以為氧化銦錫（Indium❿⑽心 =〇)或氧化銦鋅（Indium Zinc 〇xide，Iz〇)。於第六道光罩 製程中’在該顯示區21形成一像素電極2i6及於該連接处 構223處形成—透明導電連接層224。該像素電極216 ^ 由該第-接觸孔a與該汲極215電連接，該透明導電連接 層224藉由該第二接觸孔b及第三接觸孔c將該第一金屬 導線221與該閘極線211電連接。 相較於先前技術，前述薄膜電晶體基板2〇之邊框區 22之第一金屬導線221與第二金屬導線222於垂直於該絕 緣基底201方向以不同層言史置方式實現絕緣，使相鄰之第 一金屬導線221與第二金屬導線222在水平方向之間距為 零，因此可將邊框區22之寬度減小一半，以形成窄邊框之 薄膜電晶體基板20。該薄膜電晶體基板2〇之製造方法在 原有製造薄膜電晶體的基礎之上加多一道光罩製程形成該 絕緣牆220即可完成。 相較於先前技術，該佈線結構之相鄰二導線於垂直於 該基底方向高低絕緣間隔設置’使其在水平方向之間距為 15 200933891 零，因此可將其需要之面積 古、土 H丄 ^ 償成』+ °該佈線結構之製造 方法可糟由一道光罩製程即可完成。 請巧圖16，錢本發㈣”晶録板之第二實施 方式之。卩伤平面放大示意圖。請一 时兩 併參閱圖17,其係圖16 所不之薄膜電晶體基板3〇沿xw_ 意圖。該薄膜電晶體基板3…構面結構示 9n々#诚，， 汉U之、，口構與該薄膜電晶體基板 ❹ 之目以，其區別主要在於邊框區32之絕緣牆320 極絕緣層3〇2之材質相㈤，該第—金屬導線321 及以第一金屬導線322之材質與該源極314 材質相同。 請-併參閱圖18,其係圖16所示之薄膜電晶體基板 30 /〇XVDI-XVni方向之剖面結構示意圖。該薄膜電晶體基 板30之絕緣牆320鄰近該閘極線311之末端為平緩延伸下 降之階梯狀，該第-金屬導線321位於其表面並直接與該 閘極線311電連接，較第一實施方式節省一連接結構。 ❹ 請一併參閱圖19至圖25。圖19係本發明薄膜電晶體 基板30之製造方法流程圖，圖2〇至圖乃係該薄膜電晶體 基板30之製造方法之各主要步驟之示意圖。該薄膜電晶體 基板30之製造方法之主要步驟如下： (530) 形成閘極313及閘極線311: 睛一併參閱圖20，提供一絕緣基底3〇1 ’在該絕緣基 底301上沉積一第一金屬層（圖未示）。於第一道光罩製裎 中’在該顯示區31形成一閘極313及一閘極線311。 (531) 形成閘極絕緣層302、半導體層303a: 16 200933891 請一併參閱圖21，在該絕緣基底301、該閘極313及 該閘極線311上沉積一閘極絕緣層302、—半導體層3〇3a 及一光阻層（圖未示）。 (S32)形成半導體層圖案303、絕緣牆320. ❹ ❹ 請一併參閱圖22,以一光罩對該光阻層進行曝光後顯 影，形成一預定圖案，其中該道光罩為狹縫光罩（圖未示）”。 對該半導體層303a及該閘極絕緣層302進行蚀刻，進而开〈 成該半導體層圖案303及該絕緣牆32〇，並移除該剩餘= 阻層。該絕緣牆320之剖面為矩形圖案，二相鄰絕緣牆 之間距與該絕緣牆220之寬度相等。該絕緣牆鄰近該 閘極線311之末端為平緩延伸下降之階梯狀，其沿垂直= 該絕緣基底301方向之高度逐漸降低並沿絕緣基^ 3叭之 方向延伸至該閘極線311邊緣。 汲極315、第一金屬導線321 (S33)形成源極314 第二金屬導線322: 請一併參閱圖23，在該半導 ,日叫求夂具二 閘極絕緣層302、絕緣牆320及絕緣基底3〇1上沉積一 二金屬層（圖未示）。於第三道光罩製程中形成—源極貝％ 一汲極315、一第一金屬導線321及一第二金屬導線幻 該第一金屬導線321位於該絕緣牆32〇上，該第二屬 線322形成於該絕㈣，之間距之絕緣基底上。該 牆320沿垂直於該絕緣基底3〇1方向之高度大於^ 屬導線322之厚度。該第一全厪道治/ 、-<禾一 i ^ ^ 、*導線位於該絕緣牆320 末知並與該閘極線311直接連接，該第二金屬導線與該 200933891 極線311(圖未示）直接連接。 * (S34)形成鈍化層3〇4及第一接觸孔d: • 請一併參閱圖24，在該源極314、汲極315及其二側 之閘極絕緣層302、該第一金屬導線321、該第二金屬導線 322沉積一鈍化層3〇4。於第四道光罩製程中形成一第一 觸孔d。 (S35)形成像素電極316: ❹ 味一併參閱圖25 ’在該鈍化層304上沉積一透明導電 層（圖未示）。於第五道光罩製程中，在該顯示區31形成— 像素電極316。該像素電極316籍由該第一接觸孔d與該 汲極315電連接。 在該第二實施方式之製造方法中，該邊框區32之絕緣 牆層與該顯示區31之閘極絕緣層3〇2 一併形成，並於形成 該半導體層圖案303時一併形成該絕緣牆320及其平緩延 伸下降階梯狀之末端。該第一金屬導線321及該第二金屬 〇導線322與該顯示區31之源極314及汲極315 —併形成， 並且該第一金屬導線321與該閘極線311直接連接。該第 二實施方式之製造方法較第一實施方式之製造方法少一道 光罩製程’減少製程成本。 本發明薄膜電晶體基板亦可具有多種變更設計，如： 在該第一實施方式中，該第一金屬導線221與該第二金屬 導線222可與該源極214及汲極215金屬層一併形成。該 第一實施方式之薄膜電晶體基板2〇之絕緣牆220之末端亦 可為一平緩延伸下降階梯狀結構，使該第一金屬導線221 18 200933891 與該閘極線211直接電連接。該第一金屬導線22ι及該第 .二金屬導線222亦可與除該閘極線211之外之資料線 .212、公共線（圖未示）等驅動線電連接。 綜上所述，本發明確已符合發明之要件，爰依法提出 專利申請。惟，以上所述者僅為本發明之較佳實施方式， 本發明之範圍並不以上述實施方式為限，舉凡熟悉本案技 藝之人士援依本發明之精神所作之等效修飾或變化，皆應 涵蓋於以下申請專利範圍内。 …❹ (S26) Forming the pixel electrode 216 and the transparent conductive connection layer 224: Referring to FIG. 15, a transparent conductive layer (not shown) is deposited on the passivation layer 2〇4. The transparent conductive layer may be indium tin oxide (Indium ❿ (10) core = 〇) or indium zinc oxide (Indium Zinc 〇 xide, Iz 〇). In the sixth mask process, a pixel electrode 2i6 is formed in the display region 21 and a transparent conductive connection layer 224 is formed at the connection structure 223. The pixel electrode 216 ^ is electrically connected to the drain 215 by the first contact hole a, and the transparent conductive connection layer 224 connects the first metal wire 221 and the gate through the second contact hole b and the third contact hole c The pole line 211 is electrically connected. Compared with the prior art, the first metal wire 221 and the second metal wire 222 of the frame region 22 of the thin film transistor substrate 2 are insulated in a direction perpendicular to the direction of the insulating substrate 201, so as to be adjacent. The distance between the first metal wire 221 and the second metal wire 222 in the horizontal direction is zero, so that the width of the frame region 22 can be reduced by half to form a thin-rimmed thin film transistor substrate 20. The manufacturing method of the thin film transistor substrate 2 can be completed by adding a mask process to the insulating film wall 220 based on the original film transistor. Compared with the prior art, the adjacent two wires of the wiring structure are disposed at a high and low insulation interval perpendicular to the direction of the substrate, so that the distance between them in the horizontal direction is 15 200933891 zero, so the area required for it can be made ancient, soil H丄^ The compensation method + ° The manufacturing method of the wiring structure can be completed by a mask process. Please refer to Figure 16, Qian Benfa (4)" The second embodiment of the crystal recording board. The plane of the scratched plane is enlarged. Please refer to Figure 17 for a while, which is the thin film transistor substrate of Figure 16 along the xw_ intent. The thin film transistor substrate 3 has a mesa structure, which is shown in the figure of 9n 々 诚 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The material phase (5) of the 3〇2, the material of the first metal wire 321 and the first metal wire 322 is the same as the material of the source electrode 314. Please refer to FIG. 18, which is the thin film transistor substrate 30 shown in FIG. Schematic diagram of the cross-sectional structure of the VXVDI-XVni direction. The insulating wall 320 of the thin film transistor substrate 30 is adjacent to the end of the gate line 311 in a stepped manner, and the first metal wire 321 is located on the surface thereof and directly The gate line 311 is electrically connected, which saves a connection structure compared with the first embodiment. ❹ Please refer to FIG. 19 to FIG. 25. FIG. 19 is a flowchart of a method for manufacturing the thin film transistor substrate 30 of the present invention, and FIG. Each of the manufacturing methods of the thin film transistor substrate 30 The main steps of the method for manufacturing the thin film transistor substrate 30 are as follows: (530) forming a gate 313 and a gate line 311: Referring to FIG. 20 together, an insulating substrate 3〇1' is provided in the insulation. A first metal layer (not shown) is deposited on the substrate 301. A gate 313 and a gate line 311 are formed in the display region 31 in the first mask structure. (531) Forming a gate insulating layer 302, semiconductor layer 303a: 16 200933891 Please refer to FIG. 21, a gate insulating layer 302, a semiconductor layer 3〇3a and a photoresist are deposited on the insulating substrate 301, the gate 313 and the gate line 311. a layer (not shown). (S32) forming a semiconductor layer pattern 303 and an insulating wall 320. ❹ ❹ Referring to FIG. 22 together, the photoresist layer is exposed and developed by a photomask to form a predetermined pattern. The reticle is a slit reticle (not shown). The semiconductor layer 303a and the gate insulating layer 302 are etched, and the semiconductor layer pattern 303 and the insulating wall 32 are opened, and the remaining = resist layer is removed. The insulating wall 320 has a rectangular cross section, and the distance between two adjacent insulating walls is equal to the width of the insulating wall 220. The end of the insulating wall adjacent to the gate line 311 has a stepped shape which gradually descends, and gradually decreases in height in the direction of the vertical direction of the insulating substrate 301 and extends in the direction of the insulating substrate to the edge of the gate line 311. The drain 315 and the first metal wire 321 (S33) form the source 314. The second metal wire 322: Please refer to FIG. 23 together. In the semiconductor, the second gate insulating layer 302 and the insulating wall 320 are A two metal layer (not shown) is deposited on the insulating substrate 3〇1. Formed in the third mask process - a source of a gate 315, a first metal wire 321 and a second metal wire phantom the first metal wire 321 is located on the insulating wall 32, the second line 322 is formed on the insulating substrate (4). The height of the wall 320 in a direction perpendicular to the insulating substrate 3〇1 is greater than the thickness of the ^ wire 322. The first full 厪 / / , - lt; 禾 i ^ ^ , * wire is located at the end of the insulating wall 320 and directly connected to the gate line 311, the second metal wire and the 200933891 pole line 311 (Figure Not shown) Direct connection. * (S34) forming a passivation layer 3〇4 and a first contact hole d: • Please refer to FIG. 24 together, the source 314, the drain 315 and the gate insulating layer 302 on both sides thereof, the first metal wire 321. The second metal wire 322 is deposited with a passivation layer 3〇4. A first contact hole d is formed in the fourth mask process. (S35) Forming the pixel electrode 316: As shown in Fig. 25', a transparent conductive layer (not shown) is deposited on the passivation layer 304. In the fifth mask process, a pixel electrode 316 is formed in the display region 31. The pixel electrode 316 is electrically connected to the drain 315 via the first contact hole d. In the manufacturing method of the second embodiment, the insulating wall layer of the frame region 32 is formed together with the gate insulating layer 3〇2 of the display region 31, and the insulating layer is formed together when the semiconductor layer pattern 303 is formed. The wall 320 and its gradual extension descend to the stepped end. The first metal wire 321 and the second metal wire 322 are formed together with the source 314 and the drain 315 of the display area 31, and the first metal wire 321 is directly connected to the gate line 311. The manufacturing method of the second embodiment is one less than the manufacturing method of the first embodiment, and the process cost is reduced. The thin film transistor substrate of the present invention may also have various modified designs, such as: in the first embodiment, the first metal wire 221 and the second metal wire 222 may be combined with the source 214 and the drain 215 metal layer. form. The end of the insulating wall 220 of the thin film transistor substrate 1 of the first embodiment may also be a gently extending and descending stepped structure, so that the first metal wire 221 18 200933891 is directly electrically connected to the gate line 211. The first metal wire 22i and the second metal wire 222 may also be electrically connected to a driving line such as a data line .212 or a common line (not shown) other than the gate line 211. In summary, the present invention has indeed met the requirements of the invention, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application. ...
19 200933891 【圖式簡單說明】 .圖1係先前技術薄膜電晶體基板之平面示意圖。 .圖2係圖1區域A之局部放大示意圖。 圖3係圖2沿線Π - Π[之剖面示意圖。 圖4係本發明薄膜電晶體基板之第一實施方式之平面示意 圖。 圖5係圖4區域Β之局部放大示意圖。 ❹圖6係圖5所示之薄膜電晶體基板沿線之剖面結構示 意圖。 圖7係圖5所示之薄膜電晶體基板沿線之剖面結構示 意圖。 圖8係圖5所示之薄膜電晶體基板製造方法之流程圖。 圖9至圖15係圖5所示之薄膜電晶體基板之製造方法之各 主要步驟之不意圖。 圖16係本發明薄膜電晶體基板之第二實施方式之局部平 ^ 面示意圖。 圖17係圖16所示之薄膜電晶體基板沿線χ w _ χ训之剖面 結構示意圖。 圖18係圖16所示之薄膜電晶體基板沿線χ观_ χ观之剖面 結構示意圖。 圖19係圖16所示之薄膜電晶體基板製造方法之流程圖。 圖20至圖25係圖16所示之薄膜電晶體基板之製造方法之 各主要步驟之示意圖。 【主要元件符號說明】 20 200933891 薄膜電晶體基板 20 顯不區 21、31 邊框區 22、32 積體電路區 23 驅動晶片 231 像素單元 210 、 310 閘極線 211 、 311 資料線 212 ' 312 閘極 213 、 313 源極 214 、 314 汲極 215 、 315 像素電極 216 、 316 絕緣踏 220 ' 320 第一金屬導線 221 ' 321 第二金屬導線 222 、 322 連接結構 223 透明導電連接層 224 絕緣基底 201 、 301 閘極絕緣層 202 、 302 半導體層圖案 203 、 303 半導體層 303a 鈍化層 204、304 第一接觸孔 a、d 第二接觸孔 b 第三接觸孔 c ❹ 2119 200933891 [Simplified illustration of the drawings] Fig. 1 is a schematic plan view of a prior art thin film transistor substrate. Figure 2 is a partial enlarged view of the area A of Figure 1. Figure 3 is a schematic cross-sectional view of Figure 2 along line Π - Π [. Figure 4 is a plan view showing a first embodiment of the thin film transistor substrate of the present invention. Figure 5 is a partial enlarged view of the area 图 of Figure 4. Fig. 6 is a cross-sectional view showing the structure of the thin film transistor substrate shown in Fig. 5. Fig. 7 is a cross-sectional view showing the structure of the thin film transistor substrate shown in Fig. 5. FIG. 8 is a flow chart showing a method of manufacturing the thin film transistor substrate shown in FIG. 9 to 15 are not intended to be the main steps of the method of manufacturing the thin film transistor substrate shown in Fig. 5. Figure 16 is a partial plan view showing a second embodiment of the thin film transistor substrate of the present invention. Figure 17 is a cross-sectional view showing the structure of the thin film transistor substrate shown in Figure 16 along the line w _ χ. Fig. 18 is a cross-sectional view showing the structure of the thin film transistor substrate shown in Fig. 16 taken along the line. Figure 19 is a flow chart showing a method of manufacturing the thin film transistor substrate shown in Figure 16. 20 to 25 are schematic views showing the main steps of the method of manufacturing the thin film transistor substrate shown in Fig. 16. [Main component symbol description] 20 200933891 Thin film transistor substrate 20 display area 21, 31 Border area 22, 32 Integrated circuit area 23 Drive wafer 231 Pixel unit 210, 310 Gate line 211, 311 Data line 212 ' 312 Gate 213, 313 source 214, 314 drain 215, 315 pixel electrode 216, 316 insulation step 220 '320 first metal wire 221 '321 second metal wire 222, 322 connection structure 223 transparent conductive connection layer 224 insulation substrate 201, 301 Gate insulating layer 202, 302 semiconductor layer pattern 203, 303 semiconductor layer 303a passivation layer 204, 304 first contact hole a, d second contact hole b third contact hole c ❹ 21