200933844 六、發明說明： 【發明所屬之技術領域】 本發明係關於晶圓級封裝（WLP，wafer level package) 之結構’更特別地係有關於具有晶粒接收穿孔 (through-hole)形成於基底（substrate)中之扇出（fan-out)晶 圓級封裝，以改善可靠度及縮減元件尺寸。 【先前技術】 在現今半導體元件的領域中，其元件的密度持續地增 ®加而元件尺寸卻又不斷縮減。因此，業界對於如此高密度 元件的封裝或互連（interconnecting)技術要求亦相對增 加，以因應上述之情勢。在傳統的覆晶接合（flip_chip attachment)方法中，封裝用之焊錫凸塊（s〇lderbumps)陣列 係形成於晶粒（die)之表面上。焊錫凸塊之形成可經由使用 一焊錫複合材料透過一焊錫罩幕（s〇lder mask)以製造出期 望之知錫凸塊圖案。晶片封裝之功能包括電力分配、信號 ❹分配、熱發散、保護及支撐等功能。當半導體元件日趨複 雜時，傳統封裝技術，例如導線架封裝（lead加则 package)、軟質基底封裝（flex package)、硬質基底封裝⑺ package)技術，已無法滿足含有高密度元件的小型晶片 (chip)之製造需求。 00 此外，由於傳統封裝技術須先將晶圓&成個別的晶 粒’再分別封裝每-晶粒，因此採用上述技術之製造程序 相當耗時。由於積體電路之發展料晶片封裝技術甚矩， 因此隨著電子產品之尺寸的要求，封裝技術亦然。基於上 2 200933844 述理由，現今封裝技術之趨勢係朝向球閘陣列（BGA，ball grid array)、覆晶式球閘陣列（FC-BGA，flip-chip ball grid array)、晶片尺寸封裝（CSP，chip scale package)、以及晶 圓級封裝邁進。「晶圓級封裝」係代表整體的封裝及晶圓上 所有互連結構（interconnections)以及其他製程步驟皆於晶 片（晶粒）切割（singulation)前完成。一般而言，完成所有組 裝程序或封裝程序之後，其個別的半導體封裝會自一具有 複數個半導體晶粒的晶圓分離。故此，晶圓級封裝具有極 ® 小的尺寸並伴隨極佳的電性性質。 晶圓級封裝（WLP)技術係為一種先進之封裝科技，藉 由此技術，其晶粒係在晶圓上進行製造與測試，然後晶圓 會再經過切割（dicing)使之分離以組裝在表面黏著線 (surface-mount line)上。由於晶圓級封裝技術係利用整體晶 圓作為一物件，而非利用單一的晶片或晶粒，因此在進行 劃線切割（scribing)步驟前，封裝及測試皆已完成；再者， ❹因為晶圓級封裝係為如此先進之技術以致於打線（wire bonding)、黏晶（die mount)、及底部填膠(under-fill)等步驟 皆可省略。藉由使用晶圓級封裝技術，製造所需之成本及 時間皆可縮減，且所得之晶圓級封裝結構可與晶粒相當； 因此，此技術可滿足電子元件微型化之需求。 雖然晶圓級封裝（WLP)技術具備上述優點，但仍存在 一些問題影響晶圓級封裝技術之接受度。舉例而言，晶圓 級封裝結構之材料與母板（PCB，printed circuit board，印 刷電路板）材料間熱膨脹係數（CTE，Coefficient of Thermal 200933844200933844 VI. Description of the Invention: [Technical Field] The present invention relates to a structure of a wafer level package (WLP), and more particularly to having a through-hole formed on a substrate. Fan-out wafer-level packaging in (substrate) to improve reliability and reduce component size. [Prior Art] In the field of semiconductor components today, the density of components is continuously increased and the component size is continuously reduced. Therefore, the industry's requirements for packaging or interconnection technology for such high-density components are relatively increased to cope with the above situation. In a conventional flip-chip attachment method, solder bump arrays for packaging are formed on the surface of a die. Solder bumps can be formed by using a solder composite through a solder mask to create a desired tin bump pattern. The functions of the chip package include power distribution, signal distribution, heat dissipation, protection and support. When semiconductor components become more and more complex, traditional packaging technologies, such as lead package (package), flexible package, and hard package (7) package, are unable to meet small wafers with high-density components. ) Manufacturing needs. 00 In addition, the manufacturing process using the above technique is quite time consuming because conventional packaging techniques require the wafer & individual granules to be individually packaged separately. Due to the development of integrated circuits, wafer packaging technology is very popular, so with the size requirements of electronic products, packaging technology is also the same. Based on the reasons of the previous 2 200933844, the trend of today's packaging technology is toward ball grid array (BGA), flip-chip ball grid array (FC-BGA), chip size package (CSP, Chip scale package), as well as wafer level packaging. Wafer-level packaging represents the entire package and all interconnects on the wafer and other process steps are completed prior to wafer (slice) singulation. In general, after completing all of the assembly or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. As a result, wafer-level packages are extremely small and have excellent electrical properties. Wafer-level packaging (WLP) technology is an advanced packaging technology in which the die is fabricated and tested on a wafer, which is then diced to separate it for assembly. On the surface-mount line. Since wafer-level packaging technology uses an integrated wafer as an object rather than a single wafer or die, packaging and testing are completed before the scribing step; further, because of the crystal The round-scale package is such an advanced technology that the steps of wire bonding, die mounting, and under-filling can be omitted. By using wafer-level packaging technology, the cost and time required for manufacturing can be reduced, and the resulting wafer-level package structure can be comparable to the die; therefore, this technology can meet the needs of miniaturization of electronic components. While wafer level packaging (WLP) technology has these advantages, there are still some issues that affect the acceptance of wafer level packaging technology. For example, the coefficient of thermal expansion between the material of the wafer-level package structure and the printed circuit board (PCB) (CTE, Coefficient of Thermal 200933844
Expansion)之差異為影響此結構機械不穩定性之另一關鍵 因素。美國專利第6,271，469號中所揭露之封裝即為其中 一種會遭遇熱膨脹係數不匹配問題之設計，這是因為一般 的先前技術是使用模封材料（molding compound)來封住石夕 晶粒。眾所周知，矽材料之熱膨脹係數為2.3，但模封材 料之熱膨脹係數則約為40-80。此種配置會造成晶片位置 在製程中移位，此位移係導因於模封材料及介電層材料之 固化溫度較高，且互連接塾（interconnecting pads)產生位移 會進而導致良率及效能之問題。由於環氧類樹脂（ep〇Xy resin)之特性’若其固化溫度接近或超過玻璃轉換溫度 (Tg ’ glass transition temperature) ’ 在溫度循環（temperature cycling)期間晶片亦不易回復至其原本位置。由此可知先前 之結構封裝係無法進行大尺寸之處理，且需花費較高之製 造成本。 此外，一些技術需要晶粒直接形成於基底之上表面。 ❹誠如所知者，半導體晶粒之接墊（pads)經由重布層（rdL， redistribution layer)所參與之重布製程而形成一區域陣列 類型中之複數個金屬接墊。上述增層（build-up)將增加封裝 尺寸。因此，封裝厚度亦為增加。這將可能與縮減晶片尺 寸之需求相衝突。 再者’先前之技術須歷經複雜之製程才得以形成面板 式（“Panel” type)封裝。此製程需要模製工具（mold t00i)以 進行封裝（encapsulation)及注入模封材料。由於加熱固化材 料所造成之翹曲（warp)使得控制晶粒表面及模封材料於相 4 200933844 同高度變得不易，因此可能需要化學機械研磨法（CMP， Chemical Mechanical Polishing)以研磨粗縫之表面。製造成 本因而增加。 因此，本發明係提供一種扇出晶圓級封裝（FO-WLP， fan-out wafer level packaging)結構，其具有良好的熱膨脹 係數（CTE)功效及縮減尺寸以克服前述問題，並提供較佳 的基板級（board level)溫度循環可靠度測試。 【發明内容】 ❹ 本發明之目的係為提供一種扇出晶圓級封裝，其具有 良好的熱膨脹係數效能及縮減尺寸。 本發明之另一目的係在於提供一種扇出晶圓級封裝， 其具有晶粒接收穿孔之基底（substrate)以改善可靠度及縮 減元件尺寸。 本發明係揭露一種封裝結構，包含：一基底，具有晶 粒接收穿孔、一電性連接穿孔結構、以及基底上表面上之 第一接觸墊（contact pad);至少一晶粒’配置於晶粒接收穿 ❿ 孑L之内；一圍繞（核心黏著’ core paste adhesion)材料’形 成於晶粒之下以及填入晶粒側邊與晶粒接收穿孔侧邊之間 的空隙；一介電層，形成於晶粒及基底之上；一重布層 (RDL，redistribution layer)，形成於介電層之上且麵合至 第一接觸墊；一絕緣底座（isolating base)，具有黏著材料且 形成於重布層之上；以及第二接觸墊，形成於基底之下表 面並且耦合至電性連接穿孔結構。 上述基底（substrate)之材質包括環氧類樹脂（epoxy)中 200933844 的環氧樹脂黏合玻璃纖維（ERBGF，epoxy resin bonded glass fabric) FR4 (Flame Resistant 4)、FR5、雙馬來醢亞胺 -三氮雜苯樹脂（BT，Bismaleimide triazine)、石夕、印刷電路 板（PCB，printed circuit board)材質、玻璃、或陶究。此外， 基底之材質亦可包括合金或金屬；以基底之熱膨脹係數與 其母板（PCB，熱膨脹係數約為14-17)相近為較佳。上述介 電層之材質包括彈性介電層、感光層、矽氧類介電層 (silicone dielectric based layer)、石夕氧烧聚合物（SINR， 〇 siloxane polymer)層、聚醯亞胺（PI，polyimides)層、或石夕 氧樹脂（silicone resin)層。 【實施方式】 本發明更深入之詳述將透過以下本發明中較佳之實施 例與圖示進行描述。然而，應理解者為本發明中所有之較 佳實施例僅為例示之用，並非用以限制，因此除文中明確 描述之實施例及較佳實施例外，本發明亦可廣泛地應用在 $ 其他實施例中，且本發明之範疇明顯係非受限，但以「申 請專利範圍」中所述為準。 本發明係揭露一種扇出晶圓級封裝（FO-WLP，fan-out wafer level packaging)結構，其中包含基底（substrate) 2， 此基底具有預設終端金屬接觸墊3形成於其上以及一預先 形成於其内之晶粒接收穿孔（through-hole) 4。一晶粒係配 置於基底之晶粒接收穿孔之内且以核心材質（core paste)黏 著，例如以彈性核心材質填入晶粒邊緣與晶粒接收穿孔側 壁之間之空隙及/或晶粒之下。感光材質係選擇性地塗布於 6 200933844 B曰粒及預先形成之基底上（包含核心材質區域）。上述感光 材質係以彈性材質為較佳。 圖一a及圖一 b係為本發明一實施例中之扇出晶圓級 封裝之剖面圖。如圖一 a所示，扇出晶圓級封裝之結構包 含基底2,此基底具有終端金屬接觸墊3(以供有機基底之 用）以及形成於其内之晶粒接收穿孔4以接收晶粒6。晶粒 接收穿孔4之形成係自基底之上表面穿過基底而至基底之 ❹下表面。晶粒接收穿孔4係預先形成於基底2之内。核心 材質21係塗布於晶粒6下表面之下，因此可密封及保護晶 粒6。核心材質21亦再填入晶粒6邊緣與晶粒接收穿孔4 側壁之間之空隙（填入空隙間之材質與填入晶粒背面之材 質可為不同）。導電層24係塗布於晶粒接收穿孔4之侧壁 以藉由核心材質21而增進矽晶粒與基底間之黏著力。 晶粒6係配置於基底2上之晶粒接收穿孔4之内。誠 如所知者，在晶粒6上形成金屬接墊（接合墊，b〇nding pads) ❹10。在晶粒6及基底2上表面之上形成一感光層或介電層 12。藉由微影（lithography)製程或曝光及顯影製程使複數個 開口形成於介電層12之中。複數個開口係分別對準金屬接 墊或輸出入接墊（I/O pad) 10、及基底上表面上之第一終端 金屬接觸墊 3。重布層（RDL，redistribud〇n laye〇 14，、亦 稱為導電線路（conductive trace)，形成於介電層12之上， 其係藉由移除覆蓋於介電層12上之所選區域的金屬層（種 子層）而形成，其中重布層14與晶粒6透過輸出入（1/〇)接 墊10及第一終端金屬接觸墊3而保持電性連接。基底2 200933844 更包含形成於基底之中的電性連接穿孔22<J在電性連接穿 孔22之上形成第一終端金屬接觸墊3。導電材質係再填入 電性連接穿孔22以和預先形成之基底2電性連接。第二終 知接墊18係位於基底2之下表面且位於電性連接穿孔Μ 之下，並藉由電性連接穿孔22而耦合至基底2之第—終端 金屬接觸墊3。切割線（scribe line) 28係界定於封裝單元之 間以經由切割使每一單元分離，可選擇無介電層塗布於切 ❹割線上。具有黏著材料26之絕緣底座（is〇iating base) 27 係藉由真空面板接合製程而覆蓋於重布層14之上。多重辦 層（重布層）經由重複上述步驟可易於製作。在本發明中， 由於在晶粒上預先形成保護層（passivati〇n layer)以及有機 基底材質之應用，可無須亦或選擇性地形成介電層12 (圖 一 b中），因此重布層14可形成在基底及晶粒之表面上。 圖一 b中’在絕緣底座27中形成開口 29以及曝露重布層 之焊錫金屬接墊可更進一步連接至另一半導體元件封襞或 ❹被動元件以形成堆疊（stacking)結構。 介電層及核心材質係作為一緩衝區域以於溫度循環 (temperature cycling)時吸收晶粒6與基底2間之熱機械應 力，此應力係由於介電層12及核心材質之彈性性質所造 成。此前述之構造係構成平面柵格陣列（LGa，Land grid array)式封裝。 圖二係為本發明之另一替代實施例，導電球2〇形成於 第二終端接墊18之上。此構造即為球閘陣列（BGA)式封 裝。其它部分則與圖一 a相似，故不在此贅述。在本實施 200933844 例中，終端接墊18可於球閘陣列式封裝中作為球底金屬 (UBM，under ball metal)。複數個金屬接觸墊3形成於基 底2上表面之上並耦合至重布層14。 基底2之材質以有機基底為較佳，如環氧類樹脂中的 環氧樹脂黏合玻璃纖維（FR5)、聚醯亞胺（ρι)、雙馬來醯亞 胺-三氮雜苯樹脂（BT)、或具有已定義穿孔之印刷電路板 (PCB)、或疋有預姓刻電路（pre_etching)之銅金屬。其熱膨 脹係數（CTE)與其母板（PCB)相同為較佳。具有高玻璃轉換 溫度（Tg)之有機基底以環氧類樹脂FR5或Βτ基底為較 佳。銅金屬（熱膨脹係數約為16)亦可使用。玻璃、陶瓷、 矽皆可用作基底之材料。彈性核心材質係由矽氧橡膠 (silicone rubber)與彈性樹脂材料所構成。 環氧樹脂類有機基底（FR5、BT)之熱膨脹係數（χ/γ方 向）約為16,利用玻璃材質之晶片重布工具之熱膨脹係數 約為5-8，因此FR5、ΒΤ基底在製程溫度循環下不易返回 ❹其原本位置（一旦溫度接近玻璃轉換溫度時），而晶圓級封 裝（WLP)之技術需要些許高溫製程，此將導致晶圓級封裝 面板形式中之晶粒位移。 上述基底（substrate)可為圓形，如晶圓形態，其直徑可 為200公厘（mm)、300公厘或更長。此基底亦可呈長矩形， 如面板（Panel)形式。晶粒接收穿孔4係預先形成於基底2 =内。切割線28係界定於封裝單元之間以經由切割使每一 f元刀離叫參照圖二，上半部係描述在重布層堆疊製程 月IJ之面板形晶圓，基底2包含複數個預先形成之晶粒接收 200933844 穿孔4以及電性連接穿^丨” 醫¥孔22°在電性連接穿孔22之上形 成第:終端金屬接觸墊3。導電㈣係再填人連接穿孔（已 預先形成），因而建構出電性連接穿孔22之構造。 本發明之實施例中，介電層12以石夕氧類介電材料為 主所製作之彈性介電材料為較佳，其中包㈣氧烧聚合物 (SINR * sdoxane polymers) ^ ^(Dow Corning) WL5000The difference in Expansion is another key factor affecting the mechanical instability of this structure. The package disclosed in U.S. Patent No. 6,271,469 is one of which is subject to the problem of thermal expansion coefficient mismatch, since the conventional prior art uses a molding compound to seal the stone. It is well known that the thermal expansion coefficient of the tantalum material is 2.3, but the thermal expansion coefficient of the mold material is about 40-80. This configuration causes the wafer position to shift during the process. This displacement is due to the higher curing temperature of the molding material and the dielectric layer material, and the displacement of the interconnecting pads leads to yield and efficiency. The problem. Due to the characteristics of the epoxy resin (ep〇Xy resin), if the curing temperature approaches or exceeds the glass transition temperature (Tg' glass transition temperature), the wafer does not easily return to its original position during temperature cycling. It can be seen from the prior art that the structural package cannot be processed in a large size and requires a high cost. In addition, some techniques require that the grains be formed directly on the surface of the substrate. As is well known, the pads of the semiconductor die form a plurality of metal pads in an area array type via a redistribution process in which the redistribution layer (rdL) is involved. The above build-up will increase the package size. Therefore, the package thickness is also increased. This will likely conflict with the need to reduce the size of the wafer. Furthermore, the prior art has to undergo a complex process to form a "Panel" type package. This process requires a molding tool (mold t00i) for encapsulation and injection molding. The warp caused by heating the solidified material makes it difficult to control the grain surface and the molding material at the same height as the phase 3 200933844, so CMP (Chemical Mechanical Polishing) may be required to grind the coarse seam. surface. Manufacturing costs are thus increased. Accordingly, the present invention provides a fan-out wafer level packaging (FO-WLP) structure having good thermal expansion coefficient (CTE) efficiency and reduced size to overcome the aforementioned problems and to provide a preferred Board level temperature cycle reliability test. SUMMARY OF THE INVENTION The object of the present invention is to provide a fan-out wafer level package which has good thermal expansion coefficient performance and reduced size. Another object of the present invention is to provide a fan-out wafer level package having a substrate for receiving a via of a die to improve reliability and reduce component size. The present invention discloses a package structure comprising: a substrate having a die receiving via, an electrically connected via structure, and a first contact pad on the upper surface of the substrate; at least one die disposed in the die Receiving a hole 孑L; a surrounding (core paste adhesion) material is formed under the die and filling a gap between the side of the die and the side of the die receiving perforation; a dielectric layer, Formed on the die and the substrate; a redistribution layer (RDL) formed on the dielectric layer and surfaced to the first contact pad; an isolating base having an adhesive material and formed on the weight Above the cloth layer; and a second contact pad formed on the lower surface of the substrate and coupled to the electrically connected perforated structure. The material of the above substrate includes epoxy resin bonded glass fabric (FRB) FR4 (Flame Resistant 4), FR5, and bismaleimide-three in 200933844 epoxy resin (epoxy). Azabenzene resin (BT, Bismaleimide triazine), Shi Xi, printed circuit board (PCB), glass, or ceramics. In addition, the material of the substrate may also include an alloy or a metal; preferably, the thermal expansion coefficient of the substrate is similar to that of the mother substrate (PCB, thermal expansion coefficient of about 14-17). The material of the dielectric layer includes an elastic dielectric layer, a photosensitive layer, a silicone dielectric based layer, a SINR (〇 siloxane polymer) layer, and a polyimine (PI, A polyimides layer, or a layer of a silicone resin. DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in more detail with reference to the preferred embodiments of the present invention. However, it should be understood that the preferred embodiments of the present invention are intended to be illustrative only and not limiting, and the invention may be applied to other applications in addition to the embodiments and preferred embodiments as specifically described herein. In the examples, the scope of the invention is obviously not limited, but the scope of the patent application is subject to the specification. The present invention discloses a fan-out wafer level packaging (FO-WLP) structure, comprising a substrate 2 having a predetermined terminal metal contact pad 3 formed thereon and a pre-form The crystal grains formed therein receive through-holes 4. A die is disposed in the die receiving via of the substrate and adhered by a core paste, for example, an elastic core material fills the gap between the edge of the die and the sidewall of the die receiving via and/or the die under. The photosensitive material is selectively applied to 6 200933844 B particles and a preformed substrate (including core material regions). The above photosensitive material is preferably an elastic material. 1a and 1b are cross-sectional views of a fan-out wafer level package in accordance with an embodiment of the present invention. As shown in FIG. 1a, the structure of the fan-out wafer level package comprises a substrate 2 having a terminal metal contact pad 3 (for an organic substrate) and a die receiving via 4 formed therein for receiving the die 6. The formation of the die receiving vias 4 is from the upper surface of the substrate through the substrate to the underlying surface of the substrate. The die receiving vias 4 are formed in advance within the substrate 2. The core material 21 is applied under the lower surface of the die 6, so that the crystal 6 can be sealed and protected. The core material 21 is also filled with a gap between the edge of the die 6 and the sidewall of the die receiving via 4 (the material between the voids may be different from the material filled in the back of the die). The conductive layer 24 is applied to the sidewall of the die receiving via 4 to enhance the adhesion between the germanium die and the substrate by the core material 21. The die 6 is disposed within the die receiving via 4 on the substrate 2. As is known, a metal pad (bonding pad, b〇nding pads) is formed on the die 6. A photosensitive layer or dielectric layer 12 is formed over the upper surface of the die 6 and the substrate 2. A plurality of openings are formed in the dielectric layer 12 by a lithography process or an exposure and development process. The plurality of openings are respectively aligned with the metal pads or the I/O pads 10, and the first terminal metal contact pads 3 on the upper surface of the substrate. A redistribution layer (RDL), also known as a conductive trace, is formed over the dielectric layer 12 by removing selected regions overlying the dielectric layer 12. The metal layer (seed layer) is formed, wherein the redistribution layer 14 and the die 6 are electrically connected through the input/output (1/〇) pad 10 and the first terminal metal contact pad 3. The substrate 2 200933844 further includes formation The electrical connection vias 22 < J in the substrate form a first terminal metal contact pad 3 over the electrical connection vias 22. The conductive material is refilled with electrical connection vias 22 to electrically connect with the pre-formed substrate 2 The second terminal mat 18 is located on the lower surface of the substrate 2 and under the electrical connection via Μ, and is coupled to the first terminal metal contact pad 3 of the substrate 2 by electrically connecting the vias 22. A scribe line 28 is defined between the package units to separate each unit by cutting, and a non-dielectric layer can be selected for coating on the cutting line. An insulating base having an adhesive material 26 is The vacuum panel bonding process covers the redistribution layer 14 The multiple layer (re-layer) can be easily fabricated by repeating the above steps. In the present invention, since the protective layer (passivati〇n layer) and the organic substrate material are formed on the die, it is not necessary or optional. The dielectric layer 12 is formed (Fig. 1b), so that the redistribution layer 14 can be formed on the surface of the substrate and the crystal grains. In Fig. 1b, the opening 29 and the solder for exposing the redistribution layer are formed in the insulating base 27. The metal pad can be further connected to another semiconductor device package or a passive device to form a stacking structure. The dielectric layer and the core material serve as a buffer region for absorbing the crystal grains 6 during temperature cycling. The thermo-mechanical stress between the substrate and the substrate 2 is due to the elastic properties of the dielectric layer 12 and the core material. The foregoing structure constitutes a planar grid array (LGa) package. In another alternative embodiment of the present invention, the conductive balls 2 are formed on the second terminal pads 18. This configuration is a ball gate array (BGA) package. The other portions are similar to those of FIG. In this example, in the example of 200933844, the terminal pads 18 can be used as a ball metal (UBM) in a ball grid array package. A plurality of metal contact pads 3 are formed on the upper surface of the substrate 2 and Coupling to the redistribution layer 14. The material of the substrate 2 is preferably an organic substrate, such as epoxy resin bonded glass fiber (FR5), polyimine (ρι), and bismaleimide in the epoxy resin. Triazabenzene resin (BT), or a printed circuit board (PCB) with defined perforations, or copper metal with pre-etching. The coefficient of thermal expansion (CTE) is preferably the same as its mother board (PCB). An organic substrate having a high glass transition temperature (Tg) is preferably an epoxy resin FR5 or Βτ substrate. Copper metal (a coefficient of thermal expansion of about 16) can also be used. Glass, ceramics, and tantalum can be used as the material of the substrate. The elastic core material is composed of silicone rubber and elastic resin material. The thermal expansion coefficient (χ/γ direction) of the epoxy-based organic substrate (FR5, BT) is about 16, and the thermal expansion coefficient of the wafer re-distribution tool using glass is about 5-8, so the FR5 and the ruthenium substrate are cycled at the process temperature. It is not easy to return to its original position (when the temperature is close to the glass transition temperature), while the wafer level package (WLP) technology requires a little high temperature process, which will result in grain displacement in the wafer level package panel form. The above substrate may be circular, such as a wafer form, and may have a diameter of 200 mm (mm), 300 mm or more. The substrate can also be in the form of a long rectangle, such as a panel. The die receiving via 4 is formed in advance in the substrate 2 =. The cutting line 28 is defined between the package units to make each f-knife away from each other via cutting. Referring to FIG. 2, the upper half describes the panel-shaped wafer in the redistribution layer processing process, and the substrate 2 includes a plurality of advances. The formed die receives the 200933844 perforation 4 and the electrical connection. The hole 22° is formed on the electrical connection perforation 22: the terminal metal contact pad 3. The conductive (four) refilling the connection perforation (pre-formed) Therefore, the structure of electrically connecting the through holes 22 is constructed. In the embodiment of the present invention, the dielectric layer 12 is preferably an elastic dielectric material mainly made of a diarrhea-based dielectric material, wherein the package (4) is oxy-fired. SINR * sdoxane polymers ^ ^(Dow Corning) WL5000
系列、及其間之組成。另一實施例中，介電層係由包含聚 醯亞胺（PI，P〇lyimides)或石夕氧樹脂（siHc_⑽⑻之材料所 製成。此材料以感光層為較佳以簡化製程。 本發明之-實施财，彈性介電層係為—種熱膨脹係 數大於100 (百萬分之一/每攝氏溫度，卯之材料，伸 長率（elongation rate)約為40% (以3〇 5〇%為較佳），且此種 材料之硬度係介於塑膠與橡膠之間。彈性介電層12之厚度 端視重布層/介電層介面於溫度循環測試期間所累積之應 力而決定。 本發明之一實施例中，絕緣底座27之材質以環氧樹 脂、FR4、FR5、聚醯亞胺（PI)、矽氧橡膠（siHc〇ne rubber)、 或雙馬來醯亞胺-三氮雜苯樹脂（BT)為較佳，而絕緣底座 27下之黏著材料26係為一種具有彈性且吸濕性小於〇 5% 之材質以作為一緩衝區域，於正常操作時吸收熱應力及防 止溼氣進入晶粒之主動區域以提供最高可靠度。 圖四係描述承載面板晶圓（已重布晶粒6與基底2)之 玻璃載體（carrier)工具40。黏著材料42，如（雙面）紫外線 膠帶（UV tape) ’係形成於玻璃載體工具4〇之周邊區域。 200933844 在實施例中上述載體工具可由與面板形狀相同之玻璃 所製成。而晶粒接收穿孔構造將不會形成於上述基底之邊 緣5圖四之下半部係描述此玻璃載體工具與上述面板（晶 粒”基底）之結合。此面板將與此玻璃載體黏合，在製程中 此玻璃載體將黏著及托住上述面板。 圖五係七田述具有晶粒接收穿孔4之基底之俯視圖。基 底之邊緣區域50不具有晶粒接收穿孔，其於晶圓級封裝 ❹（WLP)中用以黏合玻璃載體。待晶圓級封裝完成之後，基 底2將自上述玻璃載體分離，意即圖五中虛線之内部區域 將由切割製程以完成封裝之切割（singulati〇n)。 圖六係描述與熱膨脹係數（CTE)相關聯之主要部分。 矽晶粒（熱膨脹係數約為2 3)係封裝於此封裝結構中。fr5 或BT (雙馬來醯亞胺-三氮雜苯樹脂，tdazine) 有機環氧樹脂類材料（熱膨脹係數約為14_16)係用作基底 之材質，且其熱膨脹係數與其印刷電路板（pCB)或母板相 Ο同B曰粒與基底間之空間（空隙）係以核心材質填入（以彈性 核心材質為較佳）以吸收熱機械應力，此應力係由於晶粒與 環氧類樹脂FR5、BT基底間之熱膨脹係數不匹配 (mismatching)所導致。此外，介電層12包含彈性材質以吸 收晶粒接墊與上述基底間之應力。重布層金屬係為銅金合 金且熱膨脹係數約為16，與印刷電路板（PCB)及有機基底 相同’而導電凸塊（bump)之凸塊底金屬（UBM，Under-Bump Metallization)18係位於基底之終端金屬接觸墊3之上。印 刷電路板（PCB)之金屬區（land)60為銅組成金屬，銅金屬之 11 200933844 熱膨脹係數約為16與PCB之熱膨脹係數匹配。由前述可 知，本發明可提供良好的熱膨脹係數（CTE)解決方案（XZY 方向完全匹配）以利於晶圓級封裝（WLP)。 在上述增層之下（PCB及基底）的熱膨脹係數匹配之問 題明顯已由本發明所提供之方案所解決，且在基板級條件 下，基底上之終端接觸墊（焊錫凸塊（solderbumps)/焊錫球） 將不會於χ/γ方向產生熱應力，因此提供較佳之可靠度， ❹而彈性介電層係用以吸收z方向之應力。晶片邊緣與基底 穿孔側壁間之空間（空隙）可填入彈性介電材質以吸收機械 /熱應力。 本發明之一實施例中，重布層之材料包含鈦/銅/金合 金或鈦/銅/鎳/金合金；重布層之厚度係介於2至15微米 ni)之間。鈦銅合金與晶種金屬層皆以濺鍍技術形成，而銅 金合金或銅/鎳/金合金則以電鍍（electr〇plating)技術形 成；利用電鍍製程以形成重布層可使其具有足夠厚度與較 φ好之機械性質，以耐受溫度循環期間熱膨脹係數不匹配的 現象。金屬接墊之材質可為鋁或銅或兩者之組合。如果扇 出晶圓級封裝（FO-WLP)結構分別採用矽氧烷聚合物（SINR) 與銅作為其彈性介電層與重布層，則根據應力分析（未圖 示）’累積於重布層/介電層介面之應力將會降低。 如圖一至圖二所示’重布層自晶粒扇出且向下與第二 終端接墊連接。此與習知技術不同，本發明中基底已預先 形成之晶粒接收穿孔4以接收晶粒6，因此可減少封裝之 厚度。習知技術係違反減少晶粒封裝厚度之原則。本發明 12 200933844 之封裝與先前技術相比可達較薄之厚度。再者，上述基底 已=封裝前預先準備。晶粒接收穿孔4亦預先決定。因此， 產量可較先前大幅提升。本發明係揭露一種扇出晶圓級封 裝，其具有縮減之厚度及良好的熱膨脹係數（cte)匹配效 能。 本發明包含準備一基底（以有機基底為佳，如pR4、 FR5、BT、PI)以及形成於基底上表面之上的金屬接觸塾和 基底下表面的金屬連接穿孔。晶粒接收穿孔之尺寸每邊較 晶粒大100微米（#m/side)。而上述基底之厚度則較晶粒略 厚使其得以保護晶粒之背部。 重布層（導、線1’選擇性製程）形成於已加工之矽晶圓 上，如果輸出入（I/O)金屬接墊之節距於面板型之光微影 (photolithography)製程中太緊（小），則可改善製程中之良 率。下一步驟係藉由背部研磨以研磨晶圓至所欲之厚度。 隨後，上述晶圓透過切割製程以分離晶粒。 © 其後本發明之製程包括提供一晶粒重布（對準）工具 (以玻璃材貝為佳）’具有對準圖案⑽即则价p⑽咖)形成 於其上。然後，已具有圖案之黏膠係印刷於此工具上（用以 黏〇 BS粒之表面與基底），接著，利用具有覆晶⑺0 Chip) 功能之取置精細對準系統（pick and place行此aUgnment system)將目標晶粒在此工具上進行重布至所欲之節距。圖 案黏膠係將晶片（主動表面側）黏合於此工具上。隨後，上 述基底（具有晶粒接收穿孔）係黏結於晶粒重布工具之圖案 黏膠上，之後再將彈性核心材質印刷在晶粒與上述基底穿 200933844 孔的側壁間之空間（空隙）以及晶粒之背面。最好能使晶粒 之主動表面、核心材質、與基底保持在同一水平高度。接 著’固化步驟係用以固化核心材質並透過紫外線膠帶（uv tape)黏結玻璃載體。面板接合機（panel b〇nder)係用以將玻 璃載體接合至基底上及晶粒背面。待真空接合後，再經由 除去圖案黏膠（亦可使用溶劑、熱、或紫外線等）將上述晶 粒重布工具與面板晶圓分離。 Ο 當晶粒於基底（面板底座）上完成重布後，即進行一淨 化程序，其係藉由濕洗及/或乾洗方法清理晶粒表面。下一 步驟係將介電材料塗布於面板表面。其後，進行微影 (lithography)製程以打開接觸窗（via)(金屬接觸墊）及鋁接 合墊及/或切割線（scribe nne)(此為選擇性）。下一步驟為電 漿淨化程序以清理穿孔（via h〇les)表面以及鋁接合塾。濺鍍 鈦/銅合金以作為種子金屬層，接著光阻劑係塗布於種子金 屬層上以形成重布金屬層之圖案。之後，施以電鍍形成銅 ❹金合金或銅/鎳/金合金以作為重布層金屬，隨後去除上述 光阻及金屬濕式银刻（wet etching)以形成重布層金屬線 路。下一步驟係接合具有黏著材料之絕緣底座（is〇lating base)於重布層上，及/或打開重布層之焊錫金屬接墊以更進 一步包含至另一封裝元件或被動元件（選擇性）之互連 (interconnection)。 在面板下側上之第二終端接墊上印出焊錫球配置或焊 錫膏（solder paste)後’進行焊錫球側之熱迴銲（heat re_fl〇w) 步驟（球閘陣列式封裝，BGA)。絕緣底座頂端之頂端標記 200933844 可由雷射形成。最後執行測試。面板晶圓級之最後測試係 利用垂直探測卡（probe card)來實現；藉由打開重布層的焊 錫金屬接墊上之絕緣底座，探測接墊（probing pads)可形成 於晶粒電路侧之上。測試後，基底進行切割而使得封農分 離成個別單元。其後，上述封裝係個別取出及放置於托盤 (tray)或膠帶（tape)及捲盤（reel)上。 本發明之優點包含： 上述形成面板式晶圓之製程簡單且易於控制面板表面 之粗Μ度。其面板（黏結晶粒）厚度易於控制且可排除製程 中由於玻璃載體所產生晶粒位移之問題。射出成型工具 (injection mold tool)係可省略且亦無翹曲因此無需化學機 械研磨（CMP，Chemical Mechanical Polishing)。面板型晶 圓易於藉由具有增層（build-up)製程之晶圓級封裴製程中 來處理。 基底已於封裝前預先準備了預先形成之晶粒接收穿 ❹孔、電性連接金屬穿孔、以及終端金屬接觸墊（用於有機基 底）；晶粒接收穿孔之尺寸較晶粒每邊大1〇〇微米（二 m/side);其可藉由填人彈性核心材質以吸收熱應力而作為 應力釋放緩衝區域，此應力係由於♦晶粒與基底（fr5、BT) 間之熱膨脹係數不匹配所導致。由於應用簡易製程以形成 增層於晶粒表面及基底之上，封襄之產量可因而提升（製造 2期時間縮短）。而在晶粒之主動表面上形成終端金屬接觸 塑*。 。本發明中，彈性 晶粒配置製程即與現下之製程相同 15 200933844 核心材質（樹脂、環氧類樹脂、石夕氧橡勝等）係填入晶粒邊 緣與晶粒接收穿孔側壁間之空隙以作為熱應力釋放緩衝區 域，其後進行真空熱固化步驟。在面板式晶圓之製程中， 熱膨脹係數（CTE)不匹配之問題已由使用較低且接近石夕晶 粒熱膨脹係數之玻璃載體而克服。僅有石夕氧介電材質（以石夕 氧烷聚合物（SINR)為較佳）塗布於主動表面及基底（以 FR4、FR5、或BT為較佳）表面為選擇性製程。接觸墊係由 ❹光罩幕（photo mask)製程㈣，其僅由於在介電層（sinr) 為感光層以打開接觸開口。晶粒黏著材質（圍繞之核心材質） 係印刷於晶粒之背面以及與基底間之空隙。在本發明中， 其封裝級與基板級之可靠度皆較以往為佳，特別^對於基 板級溫度循環測試，這是因為基底與印刷電路母板 之熱膨脹係數相同所致，因此製程中焊錫凸塊/焊錫球上不 會爻到任何熱機械應力；先前於溫度循環期間進行之失效 模式基板測試（即焊錫球碎裂）已不明顯。其成本低廉且製 ❹程簡易。亦可易於形成多重晶片封裝。 對熟悉此領域技藝者，本發明雖以較佳實施例闡明如 上，然其並非用以限定本發明之精神。在不脫離本發明之 精神與範圍内所作之修改與類似的配置，均應包含在下述 之申請專利範圍内，此範圍應覆蓋所有類似修改與類似結 構，且應做最寬廣的詮釋。 【圖式簡單說明】 圖一 a及圖一 b係為本發明中形成扇出晶圓級封裝 (FO-WLP)構造（平面栅格陣列（LGA)式封裝）之剖面圖。 16 200933844 圖二係為本發明中形成扇出晶圓級封裝構造（球閘陣 列（BGA)式封裝）之剖面圖。 圖二係為本發明中基底之剖面圖。 圖四係為本發明中基底與玻璃載體結合之剖面圖。 圖五係為本發明中基底之俯視圖。 圖六係為本發明中半導體元件封裝於基板級溫度循環 測試時之說明圖。 【主要元件符號說明】 ❹1元件封裝 21核心材質The series, and the composition of the room. In another embodiment, the dielectric layer is made of a material comprising polyimine (PI, P〇lyimides) or a stone oxide resin (siHc_(10)(8). This material is preferably a photosensitive layer to simplify the process. The implementation of the elastic dielectric layer is a thermal expansion coefficient greater than 100 (one millionth / per liter temperature, 卯 material, elongation rate is about 40% (at 3 〇 5 〇 Preferably, the hardness of the material is between the plastic and the rubber. The thickness of the elastic dielectric layer 12 is determined by the stress accumulated during the temperature cycling test by the redistribution layer/dielectric layer interface. In one embodiment, the insulating base 27 is made of epoxy resin, FR4, FR5, polyimine (PI), silicone rubber, or bismaleimide-triazabenzene. Resin (BT) is preferred, and the adhesive material 26 under the insulating base 27 is a material having elasticity and hygroscopicity of less than 〇 5% as a buffer region for absorbing thermal stress and preventing moisture from entering during normal operation. The active area of the die provides the highest reliability. Figure 4 depicts the bearing surface A glass carrier carrier 40 for the wafer wafer (replaced with the die 6 and the substrate 2). The adhesive material 42, such as a double-sided UV tape, is formed in the peripheral region of the glass carrier tool 4 200933844 In the embodiment, the carrier tool may be made of the same shape as the panel, and the die receiving perforation structure will not be formed on the edge of the substrate. 5 The lower half of FIG. 4 describes the glass carrier tool and the above. A combination of a panel (grain" substrate. The panel will be bonded to the glass carrier, and the glass carrier will adhere and hold the panel during the process. Figure 5 is a top view of the substrate having the die receiving perforations 4. The edge region 50 does not have a die receiving via, which is used to bond the glass carrier in a wafer level package (WLP). After the wafer level packaging is completed, the substrate 2 is separated from the glass carrier, that is, in FIG. The inner area of the dashed line will be cut by the cutting process to complete the encapsulation (Singulati〇n). Figure 6 shows the main part associated with the coefficient of thermal expansion (CTE). The number is approximately 2 3) is packaged in this package structure. fr5 or BT (bismaleimide-triazabenzene resin, tdazine) organic epoxy resin material (coefficient of thermal expansion is about 14_16) is used as the substrate Material, and its thermal expansion coefficient is the same as its printed circuit board (pCB) or motherboard. The space between the B particles and the substrate (void) is filled with core material (preferably with elastic core material) to absorb the thermomechanical Stress, which is caused by mismatching of thermal expansion coefficients between the grains and the epoxy resin FR5, BT substrate. In addition, the dielectric layer 12 contains an elastic material to absorb the stress between the die pad and the substrate. . The redistribution metal is a copper-gold alloy with a thermal expansion coefficient of about 16, which is the same as a printed circuit board (PCB) and an organic substrate. The bump-bump metallization (UBM) of the bump is 18 series. Located on the terminal metal contact pad 3 of the substrate. The metal layer 60 of the printed circuit board (PCB) is made of copper, and the copper metal 11 200933844 has a thermal expansion coefficient of about 16 to match the thermal expansion coefficient of the PCB. As can be seen from the foregoing, the present invention provides a good coefficient of thermal expansion (CTE) solution (XZY direction perfect match) to facilitate wafer level packaging (WLP). The problem of matching the coefficient of thermal expansion under the above-mentioned build-up (PCB and substrate) has been clearly solved by the solution provided by the present invention, and at the substrate level, the terminal contact pads (solder bumps/solders) on the substrate The ball will not generate thermal stress in the χ/γ direction, thus providing better reliability, while the elastic dielectric layer is used to absorb the stress in the z direction. The space (void) between the edge of the wafer and the sidewall of the perforation of the substrate can be filled with an elastic dielectric material to absorb mechanical/thermal stress. In one embodiment of the invention, the material of the redistribution layer comprises titanium/copper/gold alloy or titanium/copper/nickel/gold alloy; the thickness of the redistribution layer is between 2 and 15 microns ni). Both the titanium-copper alloy and the seed metal layer are formed by sputtering techniques, while the copper-gold alloy or the copper/nickel/gold alloy is formed by electroplating (electr〇plating); the use of an electroplating process to form a redistribution layer is sufficient The mechanical properties of thickness and better than φ to withstand the phenomenon that the coefficient of thermal expansion does not match during temperature cycling. The material of the metal pad may be aluminum or copper or a combination of the two. If the fan-out wafer level package (FO-WLP) structure uses sodium siloxane polymer (SINR) and copper as its elastic dielectric layer and redistribution layer, it is accumulated according to stress analysis (not shown). The stress of the layer/dielectric layer interface will be reduced. As shown in Figures 1 to 2, the redistribution layer is fanned out from the die and connected downwardly to the second terminal pad. This is in contrast to the prior art in which the pre-formed die of the substrate receives the vias 4 to receive the die 6, thereby reducing the thickness of the package. Conventional technology violates the principle of reducing the thickness of the die package. The package of the invention 12 200933844 can be made thinner than the prior art. Furthermore, the above substrate has been prepared in advance before packaging. The die receiving via 4 is also predetermined. As a result, production can be significantly higher than before. The present invention discloses a fan-out wafer level package having a reduced thickness and a good coefficient of thermal expansion (cte) matching. The present invention comprises preparing a substrate (preferably an organic substrate such as pR4, FR5, BT, PI) and metal connection vias formed on the metal contact pads and the lower surface of the substrate over the upper surface of the substrate. The size of the grain receiving perforations is 100 microns (#m/side) larger on each side than the grains. The thickness of the substrate is slightly thicker than the grain to protect the back of the die. The redistribution layer (guide, line 1' selective process) is formed on the processed germanium wafer if the pitch of the input/output (I/O) metal pads is too large in the panel type photolithography process. Tight (small) can improve the yield in the process. The next step is to grind the wafer to the desired thickness by back grinding. Subsequently, the wafer is passed through a dicing process to separate the dies. © The process of the present invention thereafter comprises providing a die re-alignment (alignment) tool (preferably as glass bakelite) having an alignment pattern (10), i.e., a p(10) coffee formed thereon. Then, the patterned adhesive is printed on the tool (for bonding the surface of the BS grain to the substrate), and then using the fine alignment system with the function of flip chip (7)0 Chip) (pick and place) aUgnment system) Re-lay the target die on the tool to the desired pitch. The pattern adhesive adheres the wafer (active surface side) to the tool. Subsequently, the substrate (having a die receiving perforation) is adhered to the pattern adhesive of the die resurfacing tool, and then the elastic core material is printed on the space (void) between the die and the sidewall of the substrate through the hole of 200933844 and The back side of the die. Preferably, the active surface of the die, the core material, and the substrate are maintained at the same level. The curing step is then used to cure the core material and bond the glass carrier through a UV tape. A panel bunder is used to bond the glass carrier to the substrate and to the back side of the die. After the vacuum bonding, the above-mentioned crystal re-disposing tool is separated from the panel wafer by removing the pattern adhesive (solvent, heat, or ultraviolet rays may also be used). Ο When the die is finished on the substrate (panel base), a cleaning process is performed, which cleans the surface of the die by wet cleaning and/or dry cleaning. The next step is to apply a dielectric material to the surface of the panel. Thereafter, a lithography process is performed to open a via (metal contact pad) and an aluminum bond pad and/or a scribe nne (this is optional). The next step is a plasma cleaning process to clean the vias and aluminum joints. A titanium/copper alloy is sputtered as a seed metal layer, and then a photoresist is applied to the seed metal layer to form a pattern of the redistributed metal layer. Thereafter, electroplating is carried out to form a copper-gold alloy or a copper/nickel/gold alloy as a redistribution metal, followed by removal of the above-mentioned photoresist and metal wet etching to form a redistribution metal line. The next step is to bond an insulating base having an adhesive material to the redistribution layer, and/or to open the redox layer of the solder metal pad to further include to another package component or passive component (optional) ) interconnection. After the solder ball arrangement or the solder paste is printed on the second terminal pad on the lower side of the panel, the solder reheating step (ball reel type package, BGA) is performed. The top mark of the top of the insulating base 200933844 can be formed by laser. Finally perform the test. The final test of the panel wafer level is achieved by using a vertical probe card; by opening the insulating base on the redistributed solder metal pad, the probing pads can be formed on the side of the die circuit. . After the test, the substrate is cut to separate the agricultural components into individual units. Thereafter, the package is individually taken out and placed on a tray or tape and reel. Advantages of the present invention include: The above-described process for forming a panel wafer is simple and easy to control the roughness of the panel surface. The thickness of the panel (adhesive crystal grain) is easy to control and the problem of grain displacement due to the glass carrier in the process can be eliminated. The injection mold tool can be omitted without warping and thus does not require chemical mechanical polishing (CMP). The panel type wafer is easily handled by a wafer level sealing process with a build-up process. The substrate has been pre-formed with pre-formed die receiving vias, electrically connected metal vias, and termination metal contact pads (for organic substrates); the size of the die receiving vias is 1 inch larger than each side of the die. 〇micron (two m/side); it can be used as a stress relief buffer by filling the elastic core material to absorb thermal stress, which is due to the mismatch between the thermal expansion coefficients between the die and the substrate (fr5, BT). resulting in. Due to the application of a simple process to form a build-up on the surface of the die and on the substrate, the yield of the seal can be increased (the manufacturing period is shortened). A terminal metal contact is formed on the active surface of the die. . In the present invention, the elastic grain arranging process is the same as the current process. 15 200933844 The core material (resin, epoxy resin, shihe oxygen rubber, etc.) is filled in the gap between the edge of the die and the sidewall of the die receiving perforation. As a thermal stress relief buffer region, a vacuum heat curing step is then performed. In the fabrication of panel wafers, the problem of mismatch in coefficient of thermal expansion (CTE) has been overcome by the use of glass carriers that are relatively low in thermal expansion coefficient. Only the Si Xi oxygen dielectric material (preferably using a sulphuric acid polymer (SINR)) is applied to the active surface and the substrate (preferably FR4, FR5, or BT) is a selective process. The contact pads are formed by a photomask process (four) which is opened only by the dielectric layer (sinr) being the photosensitive layer to open the contact opening. The die attach material (the core material surrounding it) is printed on the back side of the die and the space between the die and the substrate. In the present invention, the reliability of the package level and the substrate level is better than before, especially for the substrate-level temperature cycle test, because the thermal expansion coefficient of the substrate and the printed circuit mother board is the same, so the solder bump in the process No thermo-mechanical stress is applied to the block/solder ball; the failure mode substrate test (ie, solder ball chipping) previously performed during the temperature cycle is not apparent. The cost is low and the manufacturing process is simple. It is also easy to form a multi-chip package. The invention is not limited to the spirit of the invention as set forth in the preferred embodiments. Modifications and similar configurations made within the spirit and scope of the invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1a and FIG. 1B are cross-sectional views showing a fan-out wafer level package (FO-WLP) structure (planar grid array (LGA) type package) in the present invention. 16 200933844 Figure 2 is a cross-sectional view showing a fan-out wafer level package structure (BGA array package) in the present invention. Figure 2 is a cross-sectional view of the substrate of the present invention. Figure 4 is a cross-sectional view showing the bonding of a substrate to a glass carrier in the present invention. Figure 5 is a top plan view of the substrate of the present invention. Fig. 6 is an explanatory view showing the semiconductor element package in the substrate temperature cycle test of the present invention. [Main component symbol description] ❹1 component package 21 core material
2基底 3第一終端金屬接觸墊 4晶粒接收穿孔 5基底之邊緣 6晶粒 10金屬接墊（接合墊，輸 12介電層或感光層 14重布層（導電線路) 18第二終端接墊 20導電球 22電性連接穿孔 24導電層 26黏著材料 2 7絕緣底座 28切割線 29開口 40玻璃载體 42黏著材料 50基底之邊緣區域 6〇印刷電路板之金屬區 61印刷電路板（母板） 172 substrate 3 first terminal metal contact pad 4 die receiving perforation 5 substrate edge 6 die 10 metal pads (bond pad, 12 dielectric layer or photosensitive layer 14 redistribution layer (conductive line) 18 second terminal connection Pad 20 conductive ball 22 electrically connected perforation 24 conductive layer 26 adhesive material 2 7 insulating base 28 cutting line 29 opening 40 glass carrier 42 adhesive material 50 edge area of the substrate 6 〇 printed circuit board metal area 61 printed circuit board (mother Board) 17