200931599 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種非揮發性記憶體及其製作方法，尤指一種 SONOS型記憶體結構。 【先前技術】 非揮發性記憶體由於具有不因電源供應中斷而造成儲存資料 ❹遺失之特性，因此被廣泛使用。而依照單元記憶胞儲存之資料位 元數，又可區分為單一位元儲存(single_bitstorage)非揮發性記憶 體’例如某些氮化物唯讀記憶體(nitride read-only-memory，簡稱為 NROM)、傳統金屬-氧化石夕化石夕_氧化石夕_石夕型 (metal-oxide-nitride-oxide-silicon’ 簡稱為 MONOS)記憶體或傳統矽 -氧化石夕-氮化♦氧化碎-石夕型(silicon-oxide-nitride-oxide-silicon，簡 稱為SONOS)記憶體，與雙位元儲存(dual-bit storage)非揮發性記憶 體’例如分離編程虛擬接地(split program virtual ground) SONOS型 (簡稱為SPVG SONOS)記憶體或分離編程虛擬接地(split program virtual ground) MONOS (簡稱為 SPVG MONOS)型記憶體，其中 SPVG SONOS型記憶體與SPVG MONOS型記憶體之單元記憶胞 由於可儲存二位元之資訊，因此相較於一般單一位元儲存非揮發 性s己憶體可儲存更大量的資訊，已逐漸成為非揮發性記憶體之主 流。200931599 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a non-volatile memory and a method of fabricating the same, and more particularly to a SONOS-type memory structure. [Prior Art] Non-volatile memory is widely used because it has a characteristic that stored data is not lost due to power supply interruption. According to the number of data bits stored in the unit memory cell, it can be divided into a single bit storage (single_bitstorage) non-volatile memory, such as some nitride read-only-memory (NROM). , traditional metal - oxidized stone 化 石 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Silicon-oxide-nitride-oxide-silicon (SONOS) memory, with dual-bit storage non-volatile memory, such as split program virtual ground SONOS type ( Abbreviated as SPVG SONOS) memory or split program virtual ground MONOS (referred to as SPVG MONOS) type memory, in which SPVG SONOS type memory and SPVG MONOS type memory unit memory cells can store two bits The information of Yuan, therefore, can store a larger amount of information than the general single-bit storage of non-volatile suffixes, and has gradually become the mainstream of non-volatile memory.
請參考第1圖與第2圖，第1圖與第2圖為一習知SPVG 200931599 _ SONOS型記憶體之示意圖，其中第！圖為習知spvGs〇N〇s型 §己憶體進行編程(pr〇gramming)操作時之示意圖第2圖為習知 SPVGSONOS型記憶體進行抹除(erasing)操作時之示意圖，且於 第1圖與第2圖中僅顯示出單一記憶胞。如第j圖所示，s削 SONOS型記憶體1〇係形成於一 P型摻雜井σ wdl)l2上其主要 包含有-選擇閘極(select gate)14，以及二N型之埋入式位元線 (bmied bit line)位於選擇閘極結構14相對侧邊之p型摻雜井12 ❹内，分別作為汲極16與源極18。選擇閘極結構14與p型摻雜井 12之間包含有一閘極絕緣層2〇，而選擇閘極結構14上方則包含 有一頂蓋層22。此外，選擇閘極結構14之侧壁依序包含有一底氧 化石夕層24、一氮化石夕層26與一頂氧化石夕層28，其中氮化石夕層％ 係用來作為捕捉電子或電洞的儲存媒介。另外，頂氧化碎層28之 上方則包含有一字元線30。 如第1圖所示’SPVGSONOS型記憶體1〇於進行編程操作時 ® 係利用源極侧邊注入(source-side injection)機制，其電壓操作為對 予元線30施加一高正電壓，如6至9V之電壓，對選擇閘極結構 14施加一低正電壓’如IV’對源極18則施加一正電壓，如4.5V， 並使P型摻雜井12與汲極16之電壓維持在〇v。在此狀況下，穿 越選擇閘極結構14下方通道(channel)之電子會被捕捉並被侷陷於 位於源極18之一侧之氮化矽層26内(如圖中之箭號所示），藉此改 變成不同之啟始電壓(threshold voltage)，以達到儲存資料之功能。 此外，透過類似之反向電壓操作即可將電子侷陷於汲極16之一側 7 200931599 之氮化矽層26内’以儲存另一位元之資料，形成雙位元儲存記憶 體。 如第2圖所示，當spvgs〇n〇s；型記憶體10於進行抹除操 作時係利用帶對帶電洞注入(ban(j_t〇_band hot hole injection)機制， 其電壓操作為對字元線30施加一高 負電壓，如-6至-9V之電壓， 對源極18則施加一正電壓，如4 5v，將選擇閘極結構14之電壓 ❹低於啟始電壓’並使P型摻雜井12與沒極16之電壓維持在0V。 在此狀況下P型摻雜井12中之電洞會注入源極18之一侧之氮化 石夕層26内並中和編程操作時侷陷於氮化石夕層26内之電子，達到 資料抹除之作用。此外，侷陷於汲極16之一側之氮化矽層26内 之電子亦可利用類似之電壓操作加以中和。 請參考第3圖至第7圖，第3圖至第7圖為一傳統製作SPVG SONOS型記憶體之方法示意圖，其中第3圖至第6圖為部分記憶 ❿胞之剖面示意圖，而第7圖則為SPVG S0N0S型記憶體之外觀示 恩圖。如第3圖所示，首先提供一半導體基底1〇〇，並於半導體基 底100中形成至少一 p型摻雜井102，接著再於卩型摻雜井1〇2 表面形成複數個選擇閘極結構1〇4,且各選擇閘極結構1〇4由下至 上依序包含有一閘極絕緣層106、一選擇閘極1〇8與一頂蓋層11〇。 如第4圖所示，接著於半導體基底1〇〇與選擇閘極結構1〇4之 表面全面沉積一材料層（圖未示），並利用一回蝕刻製程，全面性地 200931599 2糊歧材制’直至於各轉_結構說趣 牲側壁子結構112，並___之錄牲侧壁子結構112間 之P型摻雜井⑽以形成—開σ 114。隨後進行一離子佈植製程， 經由各開口 m於ρ型摻雜井㈣分卿成—ν型摻雜區. 作為埋入式位TL線之用。另外於形成Ν雜雜⑽後，可進行 -驅入_e-in)製程’以使_摻雜區116狀換質擴散。 〇 *第5圖所示★後去除各選擇閘極結構ίο讀]壁之犧牲侧壁 ^結構112，並於P型摻料1G2、獅祕結構1G4與N型推雜 區116之表面形成-複合介電層118，作為捕捉電子之儲存媒介。 其中，複合介電層118為一氧化石夕_氮化矽_氧化矽(〇N〇)介電層， 其包含有一底氧化矽層120、氮化矽層122以及一上氧化矽層124。 最後如第6圖與第7圖所示，於複合介電層118之表面全 面沉積一導電層(圖未示）’並利用一微影暨蝕刻製程定義出複數個 ❹平行並與選擇閘極結構104正交之字元線126，完成傳統SPVG SONOS型記憶體之製作。Please refer to FIG. 1 and FIG. 2, and FIG. 1 and FIG. 2 are schematic diagrams of a conventional SPVG 200931599 _ SONOS type memory, wherein the first! The figure is a schematic diagram of the conventional spvGs〇N〇s type § 己 体 进行 programming (pr〇gramming) operation. FIG. 2 is a schematic diagram of the conventional SPVGSONOS type memory performing erasing operation, and is in the first Only a single memory cell is shown in the figure and in FIG. As shown in the figure j, the s-cut SONOS-type memory 1 is formed on a P-type doping well σ wdl)l2, which mainly includes a -select gate 14 and a buried type N The bmied bit line is located in the p-type doping well 12 of the opposite side of the selected gate structure 14 as the drain 16 and the source 18, respectively. A gate insulating layer 2 is included between the gate structure 14 and the p-type doping well 12, and a cap layer 22 is included above the gate structure 14. In addition, the sidewall of the gate structure 14 is selected to include a bottom oxide layer 24, a nitride layer 26 and a top oxide layer 28, wherein the nitride layer is used as a capture electron or electricity. The storage medium of the hole. Additionally, a top line 30 is included above the top oxidized layer 28. As shown in Fig. 1, the 'SPVGSONOS type memory 1' uses a source-side injection mechanism when the program operation is performed, and the voltage operation is to apply a high positive voltage to the pre-element 30, such as A voltage of 6 to 9V applies a low positive voltage to the selected gate structure 14 'IV' to apply a positive voltage to the source 18, such as 4.5V, and maintains the voltage of the P-type well 12 and the drain 16 In 〇v. Under this condition, electrons passing through the channel below the gate structure 14 are captured and trapped in the tantalum nitride layer 26 on one side of the source 18 (shown by the arrow in the figure). Thereby changing to a different threshold voltage to achieve the function of storing data. In addition, through a similar reverse voltage operation, the electron can be trapped in the tantalum nitride layer 26 on one side of the drain 16 (200931599) to store another bit of data to form a dual bit storage memory. As shown in Fig. 2, when spvgs〇n〇s; type memory 10 is used for erasing operation, it uses a band-to-band hole injection (ban(j_t〇_band hot hole injection) mechanism, and its voltage operation is a pair of words. The line 30 applies a high negative voltage, such as a voltage of -6 to -9V, and applies a positive voltage to the source 18, such as 4 5v, which will select the voltage of the gate structure 14 below the starting voltage 'and P The voltage of the doping well 12 and the non-polarity 16 is maintained at 0 V. In this case, the holes in the P-type doping well 12 are injected into the nitride layer 26 on one side of the source 18 and neutralized during programming operation. The electrons trapped in the nitride layer 26 can be erased by the data. In addition, the electrons trapped in the tantalum nitride layer 26 on one side of the drain 16 can be neutralized by a similar voltage operation. Fig. 3 to Fig. 7, Fig. 3 to Fig. 7 are schematic diagrams showing a conventional method for fabricating SPVG SONOS type memory, wherein Fig. 3 to Fig. 6 are schematic diagrams showing a section of a memory cell, and Fig. 7 is a diagram of Fig. 7 For the appearance of the SPVG S0N0S type memory, as shown in Figure 3, first provide a semiconductor substrate 1 〇〇, and semi-conducting At least one p-type doping well 102 is formed in the substrate 100, and then a plurality of selective gate structures 1〇4 are formed on the surface of the germanium-type doping well 1〇2, and the respective selected gate structures 1〇4 are sequentially arranged from bottom to top. A gate insulating layer 106, a select gate 1〇8 and a cap layer 11〇 are included. As shown in FIG. 4, a surface is deposited on the surface of the semiconductor substrate 1〇〇 and the selected gate structure 1〇4. Material layer (not shown), and using an etching process, comprehensively 200931599 2 paste dissimilar material system 'until each turn _ structure said interesting side wall substructure 112, and ___ recorded side wall substructure 112 P-type doping wells (10) to form - open σ 114. Subsequently, an ion implantation process is performed, through each opening m, the p-type doping well (4) is divided into a -v-type doped region. As a buried bit For the TL line, in addition to the formation of the Ν (10), the _e-in process can be performed to diffuse the _doped region 116. 〇*Fig. 5 shows the structure of the selected gate structure after removing the selected gate structure. The structure is formed on the surface of the P-type dopant 1G2, the lion structure 1G4 and the N-type dummy region 116. The composite dielectric layer 118 acts as a storage medium for capturing electrons. The composite dielectric layer 118 is a oxidized yttrium-yttria-ytterbium oxide (ITO) layer comprising a bottom yttrium oxide layer 120, a tantalum nitride layer 122, and an upper yttrium oxide layer 124. Finally, as shown in FIG. 6 and FIG. 7, a conductive layer (not shown) is deposited on the surface of the composite dielectric layer 118 and a plurality of ❹ parallel and selected gates are defined by a lithography and etching process. The structure 104 orthogonal character line 126 completes the production of the conventional SPVG SONOS type memory.
然而’由於傳統之複合介電層係為連續結構，會完整地覆蓋 到選擇閘極結構’且傳統選擇閘極結構上方製作一頂蓋層，因此 傳統方法需另行製作内連接線來控制選擇閘極的電壓。這不但會 大幅增加SPVG SONOS型記憶體的佈局面積，也導致SPVG SONOS型記憶體之製作過程更為繁複。再者，傳統SPVG SONOS 200931599 ‘型記憶體需於選擇間極結構之側壁製作犧牲側壁子，因此也增加 了製程上的複雜度。此外’不論是在進行編程操作時或是進^抹〇 除操作時，傳統方法皆須同時控制SPVG s〇N〇s型記憶體之字元 線、選擇閘極結構、源極的施加電壓，並使p型摻雜井與没極之 電壓維持在特定賴下，使得SPVG SONOS型記麵之操作過程 較為複雜。有鐘於此，申請人乃根據此等缺點及依據多年從事半 導體產業之相酸驗，悉心觀察且研究之，而提出改良之本發明， ❹以知:升SONOS型記憶體之可靠度與良率。 【發明内容】 因此本發明之主要目的為提供一種s〇N〇s型記憶體，以解決 習知技術無法克服之難題。 本發明提供一種具有分離式電荷擷取側壁子之記憶體，其包 含有一半導體基底、複數個不相接觸之選擇閘極結構、複數個不 相接觸之電荷擷取侧壁子與複數條字元線。半導體基底包含有至 少一位於半導體基底表面之第一導電型式摻雜井與複數個位於第 導電型式摻雜井中之第二導電型式摻雜區。選擇閘極結構位於 第一導電型式摻雜區之間，排列成至少一行。各選擇閘極結構包 3有一设置於第一導電型式摻雜井上之閘極介電層與一設置於閘 極介電層上之閘極導電層。前述電荷擷取側壁子位於選擇閘極結 構之相對二侧壁的表面。各字元線直接接觸各閘極導電層之上表 200931599 之提供铺作具有分離式電荷擷取側壁子之記憶體 ^法。首先’提供—半導體基底。轉體基底包含有至少-位 換基底中的第—導電型式摻料。之後，於第—導電型式 =形=數個不相接觸之條狀結構。各條狀結構包含有 2置於第-導電型式摻雜井上之閘極介電層與-設置於問極介 =層上之_導電層。接著，於各條狀結構之姆二侧壁表面形 ❹t別-電荷娜側壁子，再進行一離子佈植製程，利用各條狀 =構以及各電荷擷取健子作為縣，於各條狀結躺之第-導 S式播雜井中分別形成—第二導電型式摻雜區。然後，於第二 導電型式摻雜區上形成一閘極間介電層。其後於半導體基底上全 2成V電層’直接接觸閘極導電層表面。隨後餘刻導電層與 條狀結構^導電層成為複數個不相接觸且與各第二導電型式摻 ，、品交之子元線並使各條狀結構成為複數個選擇閉極結構。 ® 為讓本發明之上述目的、特徵、ί«版田& 们賊、和優點能更明顯易懂，下文 特牛較佳實施方式’並配合所_式，作詳細說明如下。然而如 下之較佳實施方式細式健參考與說_，並_來對本發明 加以限制者。 【實施方式】 本發明可細於私記結财，例如SPVG S0N0S記情 體、SPVGMO刪記憶體、單次可程式記憶體(〇_e - 11 200931599 programming memory，OTP)、多次可程式記憶體(mu]ti_time programming memoIy，MTP)、埋入式單次可程式記憶斷咖_ one-time programming memory > eOTP) 〇 樹第8圖至第15圖，第8圖至第15圖為本發明第一較 佳實施例製作SPVG SONGS型記麵之方法示_，其_為清楚 麵本發明之特徵，第8圖至第1G酸第12圖至第Μ圖為部分 ❹ 記憶胞之剖面示意圖，而第！；!圖與第15圖則為部分spvG犯漏 型記憶體之外觀示意圖。需注意的是圖式僅以說明為目的，並未 依照原尺寸侧。如第8 首先提供—料縣底200，並 利用-圖案化簡未示於财)與—離子佈植製程(未示於圖中)於 半導體基底200中形成至少__ p剂接汹^ 制你―、⑽ 摻齡2G2。接著，姻熱氧化 製矛或/儿積製程於P型摻雜井202表面形成一層介 =電層表面沉積-層導電層齡朴再於導電層心二 層與條f健。之後對前述導電 232。各條狀結構232^ 形成複數個不相接觸之條狀結構 門極暮' 了至上依序包含有一閘極介電層206與- ㈣極導電㈣可作為啊_S型記 導=介電層2〇6可以包含有氧化石夕層等之絕緣 所構成。 2〇8可以為多晶石夕層或金屬層等導電材料 如第9圖所示 接著可先於半導體基底勘與條狀結構 232 32 200931599 '之表面=面/儿積一第一氧化梦層220，覆蓋於條狀結構232之側 -f。接著，於料體基底200上全面形成-第-氮化石夕層222，覆 蓋於第氧化石夕層220表面。之後，對第一氮化石夕層222斑第一 f化石夕層220進行一第一侧製程，暴露出條狀結構232 ^間極 導電層208與位於條狀結構232間之半導體基底2〇〇，留下位於條 狀…構232側壁的第一氧化石夕層22〇與第一氮化石夕層從。如第 10圖所示’接著可對第一氮切層222進行一氧化製程，以使第 ❹-減^ 222的外表面氧化形成一第二氧化補224，藉此於各 條狀…構232之相對二麵表面形成分別—具有〗形結構的電荷掏 取侧壁子212 ’作為電子之儲存媒介。需注意蚊，本發明之電荷 操取側壁子212可暴露出各條狀結構232之間極導電層2〇8的上 表面’以使閘極導電層2〇8得以直接電連接後續形成的字元線。 於其他實施例中，本發明亦可於半導體基底2〇〇上全面沉積 第一氧化石夕層（圓未示）’覆蓋於第一氮化石夕層222表面，再對第 -氧化石夕層進行-第二侧製程’暴露出條狀結構232之閘極導 電層208與位於條狀結構232間之半導體基底2〇〇,留下位於第一 氮化矽層222表面的第二氧化矽層224，藉此形成電荷擷取側壁子 212。 在本實施例中，電荷擷取側壁子212可為一氧化矽_氮化矽_ 氧化矽(ΟΝΟ)複合結構，包含有一第一氧化矽層22〇、第一氮化矽 層222以及一第二氧化石夕層224。然而其它複合介電廣，例如氮化 13 200931599 石夕-氧化石夕(NO)介電層、氧化石夕_氮化石夕(〇N^介電層、si〇2/Ta2〇5、However, 'because the traditional composite dielectric layer is a continuous structure, it will completely cover the selected gate structure' and a cap layer is formed above the conventional gate structure. Therefore, the traditional method needs to make an internal connection line to control the selection gate. Extreme voltage. This will not only greatly increase the layout area of SPVG SONOS type memory, but also make the production process of SPVG SONOS type memory more complicated. Furthermore, the traditional SPVG SONOS 200931599 ‘type memory needs to make the sacrificial sidewalls on the sidewalls of the inter-polar structure, thus increasing the complexity of the process. In addition, the traditional method must simultaneously control the word line of the SPVG s〇N〇s type memory, select the gate structure, and apply the voltage of the source, whether during the programming operation or when the erase operation is performed. Maintaining the p-type doping well and the voltage of the immersion to a specific level makes the operation of the SPVG SONOS type surface more complicated. In view of these shortcomings and based on the shortcomings of the semiconductor industry for many years, the applicant has carefully observed and studied, and proposed the improved invention. rate. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a s〇N〇s type memory to solve the problem that the prior art cannot overcome. The invention provides a memory having a separate charge extraction sidewall, comprising a semiconductor substrate, a plurality of non-contacting selective gate structures, a plurality of non-contacting charge extraction sidewalls and a plurality of characters line. The semiconductor substrate includes at least one first conductivity type doping well on the surface of the semiconductor substrate and a plurality of second conductivity type doping regions in the first conductivity type doping well. The gate structure is selected between the first conductive type doped regions and arranged in at least one row. Each of the selected gate structures 3 has a gate dielectric layer disposed on the first conductivity type doping well and a gate conductive layer disposed on the gate dielectric layer. The charge extraction sidewalls are located on the surface of the opposite sidewalls of the selected gate structure. Each word line is in direct contact with each of the gate conductive layers. Table 200931599 provides a memory method with a separate charge extraction sidewall. First, 'provide' a semiconductor substrate. The rotating substrate comprises a first conductive type of admixture in at least a displaced substrate. Thereafter, in the first conductivity type = shape = several strip structures that are not in contact. Each strip structure comprises a gate dielectric layer disposed on the first conductive type doping well and a conductive layer disposed on the dielectric layer. Then, on the surface of the two side walls of each strip structure, the surface of the two side walls is shaped, and the side wall of the charge is carried out, and then an ion implantation process is performed, and each strip is used as a county, and each strip is used as a county. A second conductive type doped region is formed in the first-guided S-type wells in which the lie is lying. Then, an inter-gate dielectric layer is formed on the second conductive type doped region. Thereafter, the entire surface of the gate conductive layer is directly contacted on the semiconductor substrate by 2 volts. Then, the conductive layer and the strip structure are electrically connected to a plurality of sub-line lines which are not in contact with each other and are mixed with each of the second conductive patterns, and each strip structure is a plurality of selective closed-pole structures. In order to make the above objects, features, and vocabulary and advantages of the present invention more comprehensible, the following description of the preferred embodiments of the present invention will be described in detail below. However, the following preferred embodiments are in the form of a reference to the present invention. [Embodiment] The present invention can be more convenient for private accounting, such as SPVG S0N0S syllabus, SPVGMO storing memory, single-time programmable memory (〇_e - 11 200931599 programming memory, OTP), multiple programmable memory Body (mu]ti_time programming memoIy, MTP), embedded one-time programmable memory _ one-time programming memory > eOTP) eucalyptus 8th to 15th, 8th to 15th DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first preferred embodiment of the invention produces a SPVG SONGS type of recording method _, which is a clear feature of the present invention, and FIG. 8 to FIG. 1G acid 12th to Μth is a schematic view of a partial 记忆 memory cell And the first! Fig. 15 and Fig. 15 are schematic diagrams showing the appearance of a partial spvG leaky memory. It should be noted that the drawings are for illustrative purposes only and are not in accordance with the original dimensions. For example, the eighth material is provided at the bottom of the county, and the at least __p agent is formed in the semiconductor substrate 200 by using an -ion implantation process (not shown). You --, (10) age 2G2. Then, the aroma-oxidation spear or / or entanglement process forms a layer on the surface of the P-type doping well 202. The surface layer of the electrical layer is deposited - the layer of the conductive layer is at the level of the second layer of the conductive layer and the strip. The conductive 232 is then applied to the foregoing. Each strip structure 232^ forms a plurality of strip-shaped gate electrodes which are not in contact with each other. The top layer sequentially includes a gate dielectric layer 206 and - (four) pole conductive (four) can be used as a _S type register = dielectric layer 2〇6 may be composed of an insulation such as a oxidized stone layer. 2〇8 may be a conductive material such as a polycrystalline layer or a metal layer, as shown in Fig. 9, which may be preceded by a semiconductor substrate and a strip structure 232 32 200931599 'surface = face / child product - first oxidation dream layer 220, covering the side -f of the strip structure 232. Next, a -d-nitridene layer 222 is formed on the material substrate 200 to cover the surface of the oxidized stone layer 220. Thereafter, a first side process is performed on the first nitride layer 220 of the first nitride layer 222 to expose the strip structure 232 and the interlayer conductive layer 208 and the semiconductor substrate 2 between the strip structures 232. , leaving the first oxidized layer of 侧壁 位于 位于 构 构 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇. As shown in FIG. 10, the first nitrogen cut layer 222 may be subjected to an oxidation process to oxidize the outer surface of the second germanium-reducing layer 222 to form a second oxidation allowance 224, thereby forming a strip shape 232. The opposite two-sided surface forms a charge-collecting sidewall sub-212' having a separate structure as a storage medium for electrons. It is necessary to pay attention to mosquitoes. The charge-operating sidewalls 212 of the present invention may expose the upper surface of the pole conductive layer 2〇8 between the strips 232 so that the gate conductive layer 2〇8 can be directly electrically connected to the subsequently formed word. Yuan line. In other embodiments, the present invention may also deposit a first layer of the oxidized stone layer (circular not shown) on the surface of the semiconductor substrate 2 to cover the surface of the first layer of nitride layer 222, and then the layer of the first layer of oxidized stone. Performing a second side process 'excepting the gate conductive layer 208 of the strip structure 232 and the semiconductor substrate 2 between the strip structures 232 leaving a second layer of tantalum oxide on the surface of the first tantalum nitride layer 222 224, thereby forming a charge extraction sidewall 212. In this embodiment, the charge extraction sidewall 212 may be a yttria-yttria-yttrium oxide (yttrium oxide) composite structure, including a first tantalum oxide layer 22, a first tantalum nitride layer 222, and a first The dioxide layer 224. However, other composite dielectrics are widely used, such as nitriding 13 200931599 Shi Xi - Oxide Xi (NO) dielectric layer, oxidized stone Xi _ nitride 夕 (〇 N ^ dielectric layer, si 〇 2 / Ta 2 〇 5,
Sl02/Ta2〇5/Si〇2、Si〇2/SrTi03、Si02/BaSrTi02、Sl02/Ta2〇5/Si〇2, Si〇2/SrTi03, Si02/BaSrTi02,
Si02/SrTi03/Si02、Si02/SrTi03/BaSrTi02、Si02/Hf205/Si02 等， 均可視需要而應用作為電子之儲存媒介。 之後，如第11圖所示，進行一自對準之離子佈植製程，利用 各條狀結構232以及各電荷擷取側壁子212作為遮罩，於各條狀 ❹結構232間之P型摻雜井202中分別形成一 摻雜區216，作 為記憶體之源極/汲極與埋入式位元線之用。另外，於形成^^型摻 雜區216後，可進行一驅入(drive-in)製程，以使N型掺雜區216Si02/SrTi03/SiO2, SiO2/SrTi03/BaSrTi02, SiO2/Hf205/SiO2, etc., can be applied as a storage medium for electrons as needed. Thereafter, as shown in FIG. 11, a self-aligned ion implantation process is performed, and each strip structure 232 and each charge extraction sidewall 212 are used as a mask, and P-type doping between each strip structure 232 is performed. A doped region 216 is formed in the well 202 to serve as a source/drain and a buried bit line of the memory. In addition, after the formation of the doping region 216, a drive-in process can be performed to make the N-doped region 216
内之摻質擴散。值得注意的是，本實施例係以形式之spVG NOS型^己憶體為例5兑明本發明之方法，因此係於半導體基底 200中形成P型摻雜井202與]^型摻雜區216，若因產品需求或其 他叹汁考量而欲製作之SpVG s〇N〇s型記憶體係為型式， ❾則僅需於半導體基底200中利用不同摻質形成N型摻雜井與P型 換雜區即可。 值得注意的是，本發明亦可於製備閘極導電層2〇8之後，先 形成:襯氧化層伽饮0硫)（圖未示）。再於襯氧化層表面依序沉 氧化石夕層、一氮化石夕層與另一氧化石夕層，並利用襯氧化層(圖 不)作為回蝕刻製程之蝕刻停止層，形成電荷擷取侧壁子212。 ^構成電荷娜侧壁子2丨2之材料，則可視襯氧化層(圖未示)之有 無’選用蝕刻選擇比較高的組合。此外，襯氧化層亦可用來作為Ν 200931599 型摻雜區216之離子佈植製程的犧牲層(sacriflcial layer)，以保護N 型摻雜區216表面之晶格結構。 如第12圖所示，隨後於半導體基底2〇〇上全面形成一介電層 (圖未不）’覆蓋於條狀結構232與㈣摻雜區216上，再對此介 電層進行-回_或化學機械研磨等之平坦化餘，直到暴露出 條狀結構232之閘極導電層2〇8，以於N型換雜區216上形成一 ❹閘極間；I電層234。其後如第13圖所示，於半導體基底細上全 面形成-導電層236 ’如-多晶石夕層、一金屬石夕化物或一金屬層， 直接接觸閘極導電層的表面，再於導電層说上形成一圖案 化遮罩244此圖案化遮罩244具有複數個不相接觸之條狀開口(未 示於圖中），且各條狀開口與條狀結構232正交。 接著如第14 ®與第15圖所示，以圖案化遮罩244作為侧 遮罩’對導電層236與條狀結構232進行一侧製程，直到各條 ❹狀結構2W成為複數個不相接觸之選擇閘極結構2〇4，並使導電層 236成為複數個不相接觸且與各N型摻雜區216正交之字元線 24〇其巾該飯刻製程可以去除導電層236未被圖案化遮罩撕 所遮蔽之部分’以及條狀結構232未被圖案化遮罩撕所遮蔽之 部分，而可以留下部分未被圖案化遮罩撕戶斤遮蔽之電荷娜側 壁子212其後，去除圖案化遮罩244，完成本實施例spvGS〇n〇s 型記憶體之製作。 15 200931599 值得注意的是，於本發明之其他實施例中，形成選擇閘極結 構204之蝕刻製程也可能會暴露出位於電荷擷取側壁子212下方 之半導體基底200’甚至是直接蚀刻掉未被圖案化遮罩244所遮蔽 之電荷擷取側壁子212，使得位於同一行的二個選擇閘極結構2〇4 的電荷擷取側壁子212彼此不相連接。請參考第16圖與第17圖， 第16圖繪示的是本發明第二較佳實施例SPVGSONOS型記憶體 之立體示意圖，而第Π圖繪示的是本發明第三較佳實施例SpVG ❹ SONOS型記憶體之立體示意圖。如第16圖所示，姓刻製程使得 電荷擷取侧壁子212暴露出位於其下方之半導體基底2〇〇，因此位 於同一行的二個選擇閘極結構204的電荷擷取側壁子212彼此不 相連接。如第17圖所示’蝕刻製程係完全去除未被圖案化遮罩244 所遮蔽之電荷擷取側壁子212。 另需注意的是，於本發明之第一、第二較佳實施例中，電荷 擷取側壁子212係為一種氧化矽-氮化矽_氧化矽(〇N〇)的複合結 β構’驗其他實補巾，電荷齡觀子也可以為-種氧化石夕遗 化石夕氧化石夕-氮化梦(ΟΝΟΝ)的複合結構。請參考第18圖至第19 圖’其繪不的是本發明第四較佳實施例製作電荷掏取侧壁子之方 法示意圖’其中相同的元件或部位沿用相同的符號來表示。如第 18圖所示’首先提供-半導體基底2〇〇，半導體基底綱中包含 有至少- Ρ型摻雜井2〇2,且半導體基底2〇〇上包含有與複數個條 狀結構232。各條狀結構232由下至上依序包含有一閑極、 206與一閘極導電層2〇8。 16 200931599 第-半導體基底與條狀結構232之表面依序沉積一 第氧切層220與-第一氮化石夕層如，再對第 與第-氧切層22G進行—第—綱μ ^ 蝕刻製程，暴露出條狀結構232 之閘極導電層與位於條狀結構232間 位於條狀結構232側壁的第_氧 導體基底200留下 夕層220與第一氮化梦層222。 如第19圖所示，接著可對第一氮化石夕層222進行-氧化製 =二第—_ 222的外表面氧化形成一第二氧賴 程於it制用—氮化製程，錢沉積製程與一_製 氧賴224物成—層第：氮切請，藉此 ^各條狀結構232之相對二側壁表面形成分別一具幻形結構的電 側壁子312。需注意的是’本發明之電荷擷取側壁子312 2露出各條狀結構232之間極導電層的上表面，以使間極 導電層208得以電連接後續形成的字元線。 於其他實施例中，本發明亦可於半導體基底·上全面沉積 化石夕層(圖未示），覆蓋於第—氮化石夕層迎表面，再於半 化^上全面沉積—第二氮切層（圖未示），覆蓋於第二氧 化石夕層表面。之後，對第二氮切層與第二氧切層進行一第二 程’暴露紐狀結構说之__⑽與位於條狀結 構232間之半導體基底·，留下位於第—氮化石夕層222表面的第 二氧切層224與位於第二氧切層说表面第二氮切層242 , 17 200931599 藉此形成電荷擷取侧壁子312。 另外，本發明之電荷擷取側壁子也可以具有L形結構。請參 考第20圖至第21圖，其繪示的是本發明第五較佳實施例製作電 荷操取侧壁子之方法示意圖，其中相同的元件或部位沿用相同的 符號來表示。如第20圖所示，首先提供一半導體基底2〇〇，半導 體基底200中包含有至少一 P型摻雜井2〇2，且半導體基底2〇〇 〇上包含有複數個條狀結構232。各條狀結構232由下至上依序包含 有閘極"電層206與一閘極導電層208。接著，於半導體基底 200與條狀結構232之表面依序沉積一第一氧化矽層22〇、一第一 氣化石夕層222、一第二氧化石夕層224與一第二氮化石夕層2幻。 接著如第21圖所示’對第二氮化石夕層242、第二氧化石夕層 故、第-氮化料222與第一氧化销22〇進行一餘刻製程，暴 露祕狀結構232之_導電層與位於條狀結構沈間之半 導體基底200,並留下位於條狀結構232 層挪、第一氣化石夕層222、第二氧化梦層224與第二第氮二夕 242，藉此形成一具有L形結構的電荷擷取側壁子。旦中，電 荷娜侧壁子412可暴露出各條狀結構况之間極導電層、綱的 上表面，以使閘極導電層得以電連接後續形成的字元線。 由上述可知’本發明製作記髓之方法，可直接利用於間極 過程中所形成之條狀結構與電荷摘取側壁子作為佈植遮罩來 18 200931599 •進行-自對準之離子佈植製程，以形成記舰所需之_推雜區 (亦為記憶體之源極/汲極與埋入式位元線）。再者，本發明之選擇 閉極可直接與字元線電連接，無須再另行製作選擇触與字元線 之間的連線結構，因此不但有效地縮小了記,紐的佈局面積，也 可以有效地簡化記憶體之製作過程。此外，根據本發明所製作出 之记憶體結構，記憶體的操作過程也會更為簡易。如此一來，不 但可以提高積體電路的積集度，更可以增加產品的良率與運 ® 能。 卩上所述僅為本發狀較佳實關，驗本㈣申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知SPVG SONOS型記憶體進行編程操作時之示意圖。 B第2圖為習知SPVGS〇N〇Ss記憶體進行抹除操作時之示意圖。 第3圖至第7圖為一傳統製作spvGS〇N〇s型記憶體之方法示意 圖。 第8圖至第15圖為本發明第一較佳實施例製作spvGs〇N〇s型 記憶體之方法示意圖。 第16圖繪示的是本發明第二較佳實施例spvG s〇N〇s型記憶體 之立體示意圖。 第π圖繪示的是本發明第三較佳實施例spvGs〇N〇s型記憶體 之立體示意圖。 19 200931599 第18圖至第19圖繪示的是本發 側壁子之方法示意圖。 月第四較佳實施例製作電荷擷取 第20圖至第21圖繪示的是本發明第 侧壁子之方法示意圖。 五較佳實施例製作電荷擷取The dopant inside diffuses. It should be noted that, in this embodiment, the spVG NOS type of the memory is taken as an example 5, and the method of the present invention is formed. Therefore, the P-type doping well 202 and the ^-type doping region are formed in the semiconductor substrate 200. 216. If the SpVG s〇N〇s type memory system is to be produced due to product demand or other sighing considerations, the ❾ is only required to form N-type doping wells and P-type replacements in the semiconductor substrate 200 by using different dopants. Miscellaneous areas can be. It should be noted that the present invention can also be formed after the preparation of the gate conductive layer 2〇8: the lining oxide layer is scented to 0 sulphur (not shown). Then, the oxidized stone layer, the nitriding layer and the other oxidized stone layer are sequentially deposited on the surface of the lining oxide layer, and the etch-stop layer is formed by using the lining oxide layer (not shown) as an etch-etching layer to form a charge extraction side. Wall 212. ^ The material constituting the charge side wall member 2丨2 can be visually selected as the oxide layer (not shown). In addition, the lining oxide layer can also be used as a sacriflcial layer of the ion implantation process of the 31200931599 type doping region 216 to protect the lattice structure of the surface of the N-type doping region 216. As shown in FIG. 12, a dielectric layer (not shown) is then formed on the semiconductor substrate 2' to cover the strip structure 232 and the (4) doped region 216, and then the dielectric layer is subjected to - back _ or chemical mechanical polishing or the like, until the gate conductive layer 2 〇 8 of the strip structure 232 is exposed to form a gate between the NMOS gates 216; the I electrical layer 234. Thereafter, as shown in FIG. 13, a conductive layer 236' such as a polycrystalline layer, a metal lithium or a metal layer is formed on the semiconductor substrate finely, directly contacting the surface of the gate conductive layer, and then A patterned mask 244 is formed on the conductive layer. The patterned mask 244 has a plurality of strip openings (not shown) that are not in contact with each other, and each strip opening is orthogonal to the strip structure 232. Then, as shown in the 14th and 15th, the patterned mask 244 is used as a side mask to perform one side process on the conductive layer 236 and the strip structure 232 until the strip-shaped structures 2W become a plurality of non-contacts. The gate structure 2〇4 is selected, and the conductive layer 236 is formed into a plurality of word lines 24 that are not in contact with each other and orthogonal to the N-type doping regions 216. The conductive layer 236 can be removed. The portion of the patterned mask tear-shadowed portion and the portion of the strip-like structure 232 that is not covered by the patterned mask tear can leave a portion of the charge side wall 212 that is not obscured by the patterned mask. The patterned mask 244 is removed to complete the fabrication of the spvGS〇n〇s type memory of this embodiment. 15 200931599 It is noted that in other embodiments of the invention, the etch process that forms the select gate structure 204 may also expose the semiconductor substrate 200' under the charge extraction sidewall 212 even directly etched away. The charge shielded by the patterned mask 244 draws the sidewalls 212 such that the charge extraction sidewalls 212 of the two select gate structures 2〇4 located in the same row are not connected to each other. Please refer to FIG. 16 and FIG. 17, FIG. 16 is a perspective view of a second preferred embodiment of the present invention, and FIG. 16 is a perspective view of a second preferred embodiment of the present invention.立体 Stereoscopic diagram of SONOS type memory. As shown in FIG. 16, the surname process causes the charge extraction sidewall 212 to expose the semiconductor substrate 2 below it, so that the charge extraction sidewalls 212 of the two selective gate structures 204 in the same row are mutually Not connected. As shown in Fig. 17, the etching process completely removes the charge extraction sidewalls 212 that are not masked by the patterned mask 244. It should be noted that, in the first and second preferred embodiments of the present invention, the charge extraction sidewall 212 is a composite structure of yttrium oxide-yttria-yttria (〇N〇). In the case of other actual patches, the charge age can also be a composite structure of the oxidized stone eve fossilized oxidized stone eve-nitriding dream (ΟΝΟΝ). Referring to Figures 18 through 19, there is shown a schematic diagram of a method for fabricating a charge-trapping sidewall in accordance with a fourth preferred embodiment of the present invention, wherein the same elements or portions are denoted by the same reference numerals. As shown in Fig. 18, the semiconductor substrate 2 is first provided, and the semiconductor substrate includes at least a germanium-type doping well 2〇2, and the semiconductor substrate 2 includes a plurality of strip structures 232. Each strip structure 232 includes a dummy electrode 206 and a gate conductive layer 2〇8 from bottom to top. 16 200931599 The surface of the first semiconductor substrate and the strip structure 232 is sequentially deposited with an oxygen cut layer 220 and a first nitride layer, and then the first and the oxygen cut layer 22G are subjected to a first-order μ ^ etching. The process exposes the gate conductive layer of the strip structure 232 and the first oxygen conductor substrate 200 located on the sidewall of the strip structure 232 between the strip structures 232 to leave the layer 220 and the first nitride layer 222. As shown in FIG. 19, the first surface of the first nitride layer 222 can be oxidized to form the second surface of the second layer to form a second oxygen-reducing process. Forming a layer with a 制 氧 赖 224 : 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 。 。 。 。 。 。 。 。 。 。 相对 相对 相对It is to be noted that the charge-trapping sidewalls 312 2 of the present invention expose the upper surface of the pole-conducting layer between the strips 232 such that the inter-polar conductive layer 208 is electrically connected to the subsequently formed word lines. In other embodiments, the present invention can also deposit a fossil layer (not shown) on the semiconductor substrate, covering the surface of the first layer of the nitride layer, and then depositing it on the semi-chemical layer. A layer (not shown) covers the surface of the second oxidized stone layer. Thereafter, the second nitrogen cut layer and the second oxygen cut layer are subjected to a second pass 'exposed beam structure __(10) and the semiconductor substrate between the strip structures 232, leaving the first layer of the nitride layer 222. The second oxygen cut layer 224 of the surface and the second nitrogen cut layer 242, 17 200931599 on the second oxygen cut layer surface thereby form a charge extraction sidewall 312. In addition, the charge extraction sidewall of the present invention may also have an L-shaped structure. Referring to FIG. 20 to FIG. 21, there is shown a schematic diagram of a method for fabricating a power source to operate a side wall according to a fifth preferred embodiment of the present invention, wherein the same elements or portions are denoted by the same reference numerals. As shown in Fig. 20, a semiconductor substrate 2 is first provided. The semiconductor substrate 200 includes at least one P-type doping well 2〇2, and the semiconductor substrate 2 includes a plurality of strip structures 232 thereon. Each strip structure 232 includes a gate "electrode layer 206 and a gate conductive layer 208 sequentially from bottom to top. Next, a first yttrium oxide layer 22, a first gasification layer 222, a second oxidized stone layer 224 and a second nitriding layer are sequentially deposited on the surface of the semiconductor substrate 200 and the strip structure 232. 2 magic. Then, as shown in FIG. 21, 'the second nitride layer 242, the second oxidized layer, the first nitride material 222 and the first oxidation pin 22 〇 are subjected to a process of etching to expose the secret structure 232. _ conductive layer and semiconductor substrate 200 located between the strip structure, and left in the strip structure 232 layer, the first gasification layer 222, the second oxidized dream layer 224 and the second nitrogen eve 242, borrowed This forms a charge extraction sidewall having an L-shaped structure. In the case, the electro-Hoina sidewall 412 can expose the pole conductive layer and the upper surface between the strips to allow the gate conductive layer to electrically connect the subsequently formed word lines. It can be seen from the above that the method of making the marrow in the present invention can directly utilize the strip structure formed in the interpole process and the charge extraction sidewall as the implantation mask. 18 200931599 • Performing-self-aligned ion implantation The process is to form the whispering zone required for the ship (also the source/drain and buried bit lines of the memory). Furthermore, the selective closed pole of the present invention can be directly connected to the word line, and there is no need to separately make a connection structure between the touch and the word line, thereby effectively reducing the layout area of the note and the button. Effectively simplify the process of making memory. Further, according to the memory structure fabricated by the present invention, the operation of the memory is also simpler. In this way, not only can the integration of the integrated circuit be increased, but also the yield and operation of the product can be increased. The above description is only for the purpose of the present invention, and the equal changes and modifications made in the scope of the patent application (4) shall fall within the scope of the present invention. [Simple description of the diagram] Fig. 1 is a schematic diagram of a conventional SPVG SONOS type memory for programming operation. Figure 2B is a schematic diagram of the conventional SPVGS〇N〇Ss memory erase operation. Fig. 3 to Fig. 7 are schematic diagrams showing a conventional method of fabricating spvGS〇N〇s type memory. 8 to 15 are schematic views showing a method of fabricating a spvGs〇N〇s type memory according to a first preferred embodiment of the present invention. Figure 16 is a perspective view showing a spvG s〇N〇s type memory of a second preferred embodiment of the present invention. Fig. π is a perspective view showing a spvGs〇N〇s type memory of a third preferred embodiment of the present invention. 19 200931599 Figures 18 to 19 show schematic views of the method of the side wall of the present invention. The fourth preferred embodiment of the invention is used to make charge extraction. Figs. 20 to 21 are schematic views showing the method of the first side wall of the present invention. Five preferred embodiments for making charge extraction
【主要元件符號說明】 10 SPVG SONOS型記憶體 14 選擇閘極 18 源極 22 頂蓋層 26 氮化石夕層 30 字元線 102 P型摻雜井 106 閘極絕緣層 110頂蓋層 ❹114開口 118複合介電層 122氮化石夕層 126字元線 202 P型摻雜井 206閘極介電層 212 電荷操取侧壁子 220第一氧化珍層 12 16 20 24 28 1〇〇 104 108 112 116 120 124 2〇〇 204 208 216 222 p型摻雜井 及極 閘極絕緣層 底氧化石夕層 頂氧化石夕層 半導體基底 選擇閘極結構 選擇閘極 犧牲侧壁子結構 N型摻雜區 底氧化矽層 頂氧化石夕層 半導體基底 選擇閘極結構 閘極導電層 N型摻雜區 第一氮化石夕層 20 200931599 224 第二氧化矽層 232 條狀結構 234 閘極間介電層 236 導電層 240 字元線 242 第二氮化矽層 244 圖案化遮罩 312 電荷擷取側壁子 412 電荷擷取側壁子 ❹ ❹ 21[Main component symbol description] 10 SPVG SONOS type memory 14 Select gate 18 Source 22 Top cover layer 26 Nitride layer 30 Word line 102 P type doping well 106 Gate insulating layer 110 Top layer 114 Opening 118 Composite dielectric layer 122 nitride layer 126 word line 202 P type doping well 206 gate dielectric layer 212 charge operation side wall 220 first oxide layer 12 16 20 24 28 1〇〇 104 108 112 116 120 124 2〇〇204 208 216 222 p-type doping well and pole gate insulating layer bottom oxide oxide layer top oxide oxide layer semiconductor substrate selection gate structure selection gate sacrificial sidewall substructure N-doped region bottom Yttrium oxide layer top oxide oxide layer semiconductor substrate selection gate structure gate conductive layer N-type doped region first nitride layer 110 200931599 224 second hafnium oxide layer 232 strip structure 234 inter-gate dielectric layer 236 conductive Layer 240 Character Line 242 Second Tantalum Layer 244 Patterned Mask 312 Charge Capture Sidewall 412 Charge Capture Sidewall ❹ ❹ 21