200939605 九、發明說明： .【發明所屬之技術領域】 本發明涉及一種電壓轉換器，尤其涉及一種具有較少 功率損耗之電壓轉換器。 【先前技術】 隨著科技之發展及社會之進步，電子產品之種類越來 越多，電子產品中之積體電路之集成程度也越來越高°而 多數之電子產品需要對其施加一穩定直流電壓以使其工 〇作。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a voltage converter, and more particularly to a voltage converter having less power loss. [Prior Art] With the development of technology and the advancement of society, there are more and more types of electronic products, and the integration of integrated circuits in electronic products is getting higher and higher. Most electronic products need to be stabilized. The DC voltage is used to make it work.
電壓轉換器主要用來將輸入之直流電壓，作電壓位元 准之調節，並使其穩定於所設定之一電壓值’其利用驅動 上橋及下橋功率元件之切換而產生脈波，此脈波經過電感 電容組成之低通濾波器後產生穩定之直流電壓，以供給各 種電子產品，具體請參閱Volkan Kursun等人2004年於IEEE 系統中發表之 “ HIGH INPUT VOLTAGE STEP-DOWN DC-DC CONVERTERS FOR INTEGRATION IN A LOW o VOLTAGE CMOS PROCESS” 一文。 電子產品，特別是可檇式電子裝置，如手機、手提電 腦、個人數位助理等等’無不以獲得更長之使用時間為發 展方向’其待機時間之長短直接反映了產品之品質。而電 壓轉換器於輕載模式（Light Load Mode)下之效率之高低決 定了電子產品待機時間之長短，輕載效率越高，待機時間 越長。而電壓轉化器於輕載模式下之轉換效率是決定其輕 載效率之重要因素。 7 200939605 普通之電壓轉換器輕載模式下轉換效率較低，因此極 大地影響了電子產品之待機時間及其品質。 【發明内容】 下面將以實施例說明一種電壓轉換器，該電壓轉換器 效率損耗較低。The voltage converter is mainly used to adjust the input DC voltage as a voltage bit and stabilize it at a set voltage value, which generates a pulse wave by switching between the upper bridge and the lower bridge power component. The pulse wave is passed through a low-pass filter composed of an inductor and a capacitor to generate a stable DC voltage for supply to various electronic products. For details, please refer to "High INPUT VOLTAGE STEP-DOWN DC-DC CONVERTERS" published by Volkan Kursun et al. FOR INTEGRATION IN A LOW o VOLTAGE CMOS PROCESS". Electronic products, especially portable electronic devices, such as mobile phones, portable computers, personal digital assistants, etc., all have a longer life time as the development direction. The length of the standby time directly reflects the quality of the product. The efficiency of the voltage converter in Light Load Mode determines the length of the electronic product's standby time. The lighter load efficiency is higher and the standby time is longer. The conversion efficiency of the voltage converter in light load mode is an important factor in determining its light load efficiency. 7 200939605 Ordinary voltage converters have low conversion efficiency in light load mode, thus greatly affecting the standby time and quality of electronic products. SUMMARY OF THE INVENTION A voltage converter having a low efficiency loss will be described below by way of example.
種電壓轉換器，其包括一個脈寬調變控制晶片，一 上橋電曰曰體’一下橋電晶體，一低通濾波器，該上橋電晶 ❹體之源極f連接至—輸人電塵，其沒極與該下橋電晶體之 $極相連接，其相連接之處定義為第—節點，該下橋電晶 =源極接地，該第—節‘點進—步電連接至該低通滤波器 f n入端，該低通滤波器之輸出端作為該電壓轉換器之輸 出端，該脈寬調變控制晶片上設置有BOOT引腳’ PHASE 引腳，UGATE 引腳，LGATT? η丨 η»· 引腳，Vcc引腳以及GND引 3 腳，該脈寬調變控制晶片進行工作以驅動 =上=體和該下橋電晶體，該脈寬調變控制晶片内包 ❹括-電源管理器’ 一第一驅動器，一 控制邏輯電路以及一電流源，該電源管 Ζ 接至該脈寬調變控制晶片之Vee引 s 1入&電運 cc 5丨腳，通過該Vcc引腳盥 -外接電壓相連接，其輸出端輪出—控制 控 制邏輯電路以使該間極控制邏輯電路之第 二： 第一脈衝訊號，其第二輸出端輪出一 則 器:Γ控制邏輯電路之第-輸出端電 第二驅動器之輸入端，以分別輪 电連接至以 ，出該第一脈衝訊號及該第 8 200939605 二脈衝訊號以分別驅動該第一驅動器及第二驅動器，該第 .一驅動器之正電壓端子電連接至該脈寬調變控制晶片之 BOOT引腳，該第一驅動器之負電壓端子電連接至該脈寬調 * 變控制晶片之PHASE引腳，該第一驅動器之輸出端電連接 至該脈寬調變控制晶片之UGATE引腳，該第二驅動器之正 電壓端子電連接至該脈寬調變控制晶片之Vcc引腳以與該 外接電壓相連接，該第二驅動器之負電壓端子電連接至該 脈寬調變控制晶片之GND引腳以使其接地，該第二驅動器 ®之輸出端電連接至該脈寬調變控制晶片之LGATE引腳，該 電流源與一第一二極體之負極相連接，該連接之處定義為 第三節點，該第一二極體之正極接地，該外接電壓電連接 至一第二二極體之正極，該第二二極體之負極電連接至一 第一電容之一端，該連接之處定義為第四節點，該第一電 容之另一端電連接至該第一節點，該脈寬調變控制晶片之 BOOT引腳電連接至該第四節點，其PHASE引腳電連接至 a該第一節點，其UGATE引腳電連接至該上橋電晶體之閘 極，其LGATE引腳電連接至該下橋電晶體之閘極，其中， 該脈寬調變控制晶片内還進一步包括一第一電阻，該第一 電阻之一端電連接至該第三節點，其另一端電連接至該脈 寬調變控制晶片之PHASE引腳，以使該脈寬調變控制晶片 之PHASE引腳作為一多功能引腳，且該脈寬調變控制晶片 内還進一步包括一電感電流感測器，一計數步階電流產生 器，一振盪器，一第一比較器以及一第二比較器，該電感 電流感測器之輸入端電連接至該第三節點，其輸出端電連 9 200939605 接至該計數步階電流產生器之輸入端，該計數步階電流產 ，生器之輸出端電連接至該振盪器之輸入端，該振盪器之輸 ,出端電連接至該第二比較器之反向輸入端，該第一比較器 之正向輸入端電連接至一參考電壓，其反向輸入端電連接 一回饋電壓，該第一比較器之輸出端電連接至該第二比較 器之正向輸入端，該第二比較器之輸出端電連接至該閘極 控制邏輯電路，該電感電流感測器，計數步階電流產生器， ❹振盈器’第一比較器，第二比較器，電流源，以及該第一 電阻’下橋電晶體組成了一個輕載效率改善電路。 優選之’該低通滤波器包括一電感及一電容，該電感 之一端作為該低通濾波器之輸入端，其電連接至該第一節 點，該電感之另一端電連接至該電容之一端，其連接之處 疋義為第二節點，其作為該低通濾波器之輸出端，該電容 之另一端接地。 。優選之，該電感電流感測器之輸入端通過一控制開關 ❹電連接至該第二節點，該控㈣襲受該祕控制邏輯電 路第-輸出端所輸出第二脈衝訊號之控制，以使該電感電 流感測器與下橋電晶體同步工作。 優選之，該回饋電廢為該電虔轉換器之輸出端所輸出 優選之該電壓轉換器進—步包括—第二電阻與一第 ς =該第二電阻之一端電連接至該電壓轉換器之輸出 ί為=電連接至該第三電阻之-端，該連接之處定 ρ‘’該第：電阻之另—端接地，該回饋電座為 200939605 該第五節點處之電歷。 • 優選之，該電源管理器為一起始重置電路，其輸出一 .上電重定訊號至該閘極控制邏輯電路以使該閘極控制邏輯 電路之第一輸出端輸出一第一脈衝訊號，其第二輸出端輸 出一與該第一脈衝訊號相反之第二脈衝訊號，。 相較於先前技術，本發明之電壓轉換器採用輕載效率 改善電路降低該電壓轉換器於輕載模式時上橋電晶體及下 ◎橋電晶體之切換頻率，從而減少效率損耗，使採用該電壓 轉換器之電子裝置可具有更長之待機時間，且其利用該脈 寬調變控制晶片上之PHASE引腳作為多功能引腳以形^輕 載效率改善電路，其並沒有增加該脈寬調變控制晶 腳數。 【實施方式】 下面結合附圖將對本發明實施例作進一步之詳細說 日月。 、’。 ❹ 請參閱圖1，本發明實施例所提供之一種電壓轉換器 100,該電壓轉換器100包括一脈寬調變控制器200，串聯 於一輸入電壓Vin及接地電位GND之間之一上橋電晶體 110及一下橋電晶體120，及一低通濾波器13〇，該低通濾 波器130之輸入端連接至該上橋電晶體11〇與該下橋電晶 體120之間，該低通濾波器13〇之輸出端作為該電壓轉換 器100之輸出端Vout以輸出一穩定之電壓值。 該上橋電晶體110之源極電連接至該輸入電壓，其 /及極與該下橋電晶體120之没極相連接，該相連接之處定 11 200939605 義為第一節點A，該下橋電晶體120之源極接地。該低通 . 濾波器130之輸入端電連接至該第一節點A。該低通濾波 . 器130可由一電感L及一電容C所組成，該電感L之一端 作為該低通濾波器130之輸入端，該電感L之另一端與該 電容C之一端相電連接，該連接之處定義為第二節點B， 該電容C之另一端接地，該第二節點B作為該電壓轉換器 100之輸出端Vout。 該脈寬調變控制晶片200上設置有複數基本引腳，其 ®包括BOOT引腳，PHASE引腳，UGATE引腳，LGATE引 腳，Vcc引腳以及GND引腳。通過這些基本引腳，該脈寬 調變控制晶片200進行工作以分別驅動該上橋電晶體110 以及該下橋電晶體120，使該電壓轉換器100進行工作。 該脈寬調變控制器200包括一電源管理器210, 一閘極 控制邏輯電路220，一第一驅動器230，一第二驅動器240 以及一電流源250。 q 該電源管理器210之輸入端電連接至該脈寬調變控制 晶片200之Vcc引腳，通過該Vcc引腳電連接至一外接電 壓Vcc，該脈寬調變控制晶片200被致能後，該電源管理器 210之輸出端輸出一控制訊號至該閘極控制邏輯電路220 以使其開始工作。優選之，該電源管理器210為一個起始 重置電路（Power on Reset，P0R)。 該閘極控制邏輯電路220之第一輸出端電連接至該第 一驅動器230之輸入端，以輸出一第一脈衝訊號Vcl至該 第一驅動器230。該閘極控制邏輯電路220之第二輸出端電 12 200939605 連接至該第二驅動器240之輸入端，以輸出一第二脈衝訊 號Vc2至該第二驅動器240。該第一脈衝訊號Vcl與該第 二脈衝訊號Vc2為一對互反之訊號。該第一驅動器230與 該第二驅動器240分別為一放大器。 該第一驅動器230之正電壓端子電連接至該脈寬調變 控制晶片200之BOOT引腳上，其負電壓端子電連接至該 脈寬調變控制晶片200之PHASE引腳上，其輸出端電連接 至該脈寬調變控制晶片200之UGATE引腳上。 該第二驅動器240之正電壓端子電連接至該脈寬調變 控制晶片200之Vcc引腳上，其通過該Vcc引腳與一外接 電壓Vcc相連接。該第二驅動器240之負電壓端子電連接 至該脈寬調變控制晶片200之GND引腳上，其通過該GND 引腳使該第二驅動器240之負電壓端子接地。（為了表示方 便，圖1中僅將該脈寬調變控制晶片200中之第二驅動器 240之負電壓端子電連接至該GND引腳，而該脈寬調變控 制晶片200中之其他電子元件需要接地時，均採用直接接 地之形式進行體現，惟，本領域普通技術人員可理解的是， 該脈寬調變控制晶片200中需要接地之電子元件均是電連 接至該GND引腳，通過該GND引腳使其接地）。該第二驅 動器240之輸出端電連接至該脈寬調變控制晶片200之 LGATE引腳。 該電流源250反接一第一二極體251後接地，即該電 流源250與該第一二極體251之負極相連接，該相連接之 處定義為第三節點C，該第一二極體251之正極接地。 13 200939605 該外接電壓Vcc進一步地電連接至一第二二極體151 . 之正極，該第二二極體151之負極與一第一電容152之一 .端相連接，該連接之處定義為第四節點D，該第一電容152 之另一端電連接至該第一節點A。 該脈寬調變控制晶片200之BOOT引腳電連接至該第 四節點D，其UGATE引腳電連接至該上橋電晶體110之閘 極，其PHASE引腳電連接至該第一節點A，其LGATE引 腳電連接至該下橋電晶體120之閘極。 ® 該脈寬調變控制晶片200内還進一步設置一第一電阻The voltage converter comprises a pulse width modulation control chip, an upper bridge electric body 'a lower bridge transistor, a low pass filter, and the source f of the upper bridge electric crystal body is connected to the input The electric dust has a poleless connection with the pole of the lower bridge transistor, and the junction is defined as a first node, the lower bridge is a source grounded, and the first node is a point-in-step connection. The input end of the low-pass filter is used as an output end of the low-pass filter, and the pulse width modulation control chip is provided with a BOOT pin 'PHASE pin, UGATE pin, LGATT η丨η»· pin, Vcc pin and GND pin 3, the pulse width modulation control chip works to drive = upper body and the lower bridge transistor, the pulse width modulation control chip package - a power manager 'a first driver, a control logic circuit and a current source, the power supply tube is coupled to the Vee of the pulse width modulation control chip, and the cc 5 pin is passed through the Vcc Pin 盥 - external voltage is connected, its output is turned out - control logic is controlled to make the pole The second logic circuit: the first pulse signal, the second output end of which is rotated by a device: the first output terminal of the control logic circuit is electrically connected to the input end of the second driver, respectively, to be electrically connected to the a pulse signal and the 8th 200939605 two-pulse signal respectively driving the first driver and the second driver, wherein a positive voltage terminal of the first driver is electrically connected to a BOOT pin of the pulse width modulation control chip, the first The negative voltage terminal of the driver is electrically connected to the PHASE pin of the pulse width modulation control chip, and the output end of the first driver is electrically connected to the UGATE pin of the pulse width modulation control chip, and the positive voltage of the second driver The terminal is electrically connected to the Vcc pin of the pulse width modulation control chip to be connected to the external voltage, and the negative voltage terminal of the second driver is electrically connected to the GND pin of the pulse width modulation control chip to be grounded. The output of the second driver® is electrically connected to the LGATE pin of the pulse width modulation control chip, and the current source is connected to the negative pole of a first diode, and the connection is defined as a third node, the first The anode of the diode is grounded, the external voltage is electrically connected to the anode of a second diode, and the cathode of the second diode is electrically connected to one end of a first capacitor, and the connection is defined as a fourth node. The other end of the first capacitor is electrically connected to the first node, the BOOT pin of the pulse width modulation control chip is electrically connected to the fourth node, and the PHASE pin is electrically connected to the first node, and the UGATE is The galvanic pin is electrically connected to the gate of the upper bridge transistor, and the LGATE pin is electrically connected to the gate of the lower bridge transistor, wherein the pulse width modulation control chip further includes a first resistor, the first One end of the resistor is electrically connected to the third node, and the other end thereof is electrically connected to the PHASE pin of the pulse width modulation control chip, so that the PHASE pin of the pulse width modulation control chip is used as a multi-function pin, and The pulse width modulation control chip further includes an inductor current sensor, a step current generator, an oscillator, a first comparator and a second comparator, the input of the inductor current sensor The terminal is electrically connected to the third node, The output terminal 9 200939605 is connected to the input end of the counting step current generator, the counting step current is generated, and the output end of the generator is electrically connected to the input end of the oscillator, and the output of the oscillator is output. Connected to the inverting input of the second comparator, the positive input of the first comparator is electrically connected to a reference voltage, the inverting input is electrically connected to a feedback voltage, and the output of the first comparator is electrically Connected to the forward input of the second comparator, the output of the second comparator is electrically connected to the gate control logic circuit, the inductor current sensor, the step current generator, the ❹ oscillator The first comparator, the second comparator, the current source, and the first resistor 'lower bridge transistor form a light load efficiency improving circuit. Preferably, the low pass filter comprises an inductor and a capacitor, one end of the inductor serving as an input of the low pass filter, electrically connected to the first node, and the other end of the inductor is electrically connected to one end of the capacitor The connection is defined as the second node, which serves as the output of the low-pass filter, and the other end of the capacitor is grounded. . Preferably, the input end of the inductor current sensor is electrically connected to the second node through a control switch, and the control (4) is controlled by the second pulse signal outputted by the first output terminal of the secret control logic circuit, so that The inductor current sensor operates in synchronization with the lower bridge transistor. Preferably, the feedback power is outputted to the output of the power converter, preferably the voltage converter further comprises: a second resistor and a second resistor = one end of the second resistor is electrically connected to the voltage converter The output ί is = electrically connected to the end of the third resistor, and the connection is ρ'' the first: the other end of the resistor is grounded, and the feedback base is the electrical calendar at the fifth node of 200939605. Preferably, the power manager is a start reset circuit, and outputs a power-on reset signal to the gate control logic circuit to output a first pulse signal to the first output end of the gate control logic circuit. The second output terminal outputs a second pulse signal opposite to the first pulse signal. Compared with the prior art, the voltage converter of the present invention uses a light load efficiency improving circuit to reduce the switching frequency of the upper bridge transistor and the lower bridge transistor in the light load mode, thereby reducing the efficiency loss, thereby adopting the The electronic device of the voltage converter can have a longer standby time, and the PHASE pin on the pulse width modulation control chip is used as a multi-function pin to form a light load efficiency improving circuit, which does not increase the pulse width. Modulation control the number of pins. [Embodiment] Hereinafter, embodiments of the present invention will be further described in detail with reference to the accompanying drawings. , '. Referring to FIG. 1 , a voltage converter 100 is provided in an embodiment of the present invention. The voltage converter 100 includes a pulse width modulation controller 200 connected in series between an input voltage Vin and a ground potential GND. The transistor 110 and the lower bridge transistor 120, and a low pass filter 13A, the input end of the low pass filter 130 is connected between the upper bridge transistor 11A and the lower bridge transistor 120, the low pass The output of the filter 13 is used as the output terminal Vout of the voltage converter 100 to output a stable voltage value. The source of the upper bridge transistor 110 is electrically connected to the input voltage, and the / and the pole are connected to the pole of the lower bridge transistor 120. The phase connection is determined as the first node A, and the next node The source of the bridge transistor 120 is grounded. The low pass. The input of the filter 130 is electrically coupled to the first node A. The low-pass filter 130 can be composed of an inductor L and a capacitor C. One end of the inductor L serves as an input end of the low-pass filter 130, and the other end of the inductor L is electrically connected to one end of the capacitor C. The connection is defined as the second node B, the other end of which is grounded, and the second node B serves as the output Vout of the voltage converter 100. The pulse width modulation control chip 200 is provided with a plurality of basic pins including ® BOOT pin, PHASE pin, UGATE pin, LGATE pin, Vcc pin and GND pin. Through these basic pins, the pulse width modulation control chip 200 operates to drive the upper bridge transistor 110 and the lower bridge transistor 120, respectively, to operate the voltage converter 100. The pulse width modulation controller 200 includes a power manager 210, a gate control logic circuit 220, a first driver 230, a second driver 240, and a current source 250. q The input end of the power manager 210 is electrically connected to the Vcc pin of the pulse width modulation control chip 200, and is electrically connected to an external voltage Vcc through the Vcc pin, and the pulse width modulation control chip 200 is enabled. The output of the power manager 210 outputs a control signal to the gate control logic circuit 220 to cause it to start operating. Preferably, the power manager 210 is a Power on Reset (P0R). The first output of the gate control logic circuit 220 is electrically coupled to the input of the first driver 230 to output a first pulse signal Vcl to the first driver 230. The second output terminal 12 200939605 of the gate control logic circuit 220 is connected to the input terminal of the second driver 240 to output a second pulse signal Vc2 to the second driver 240. The first pulse signal Vcl and the second pulse signal Vc2 are a pair of signals opposite to each other. The first driver 230 and the second driver 240 are respectively an amplifier. The positive voltage terminal of the first driver 230 is electrically connected to the BOOT pin of the pulse width modulation control chip 200, and the negative voltage terminal thereof is electrically connected to the PHASE pin of the pulse width modulation control chip 200, and the output end thereof Electrically connected to the UGATE pin of the pulse width modulation control chip 200. The positive voltage terminal of the second driver 240 is electrically connected to the Vcc pin of the pulse width modulation control chip 200, and is connected to an external voltage Vcc through the Vcc pin. The negative voltage terminal of the second driver 240 is electrically connected to the GND pin of the pulse width modulation control chip 200, and the negative voltage terminal of the second driver 240 is grounded through the GND pin. (For convenience of illustration, only the negative voltage terminal of the second driver 240 in the pulse width modulation control wafer 200 is electrically connected to the GND pin in FIG. 1, and the pulse width modulation control other electronic components in the wafer 200 When the grounding is required, the direct grounding is used. However, those skilled in the art can understand that the electronic components in the pulse width modulation control chip 200 that need to be grounded are electrically connected to the GND pin. This GND pin is grounded). The output of the second driver 240 is electrically coupled to the LGATE pin of the pulse width modulation control chip 200. The current source 250 is connected to the first diode 251 and grounded, that is, the current source 250 is connected to the negative electrode of the first diode 251, and the phase connection is defined as the third node C, the first two The anode of the polar body 251 is grounded. 13 200939605 The external voltage Vcc is further electrically connected to the positive pole of a second diode 151. The cathode of the second diode 151 is connected to one end of a first capacitor 152, and the connection is defined as The fourth node D, the other end of the first capacitor 152 is electrically connected to the first node A. The BOOT pin of the pulse width modulation control chip 200 is electrically connected to the fourth node D, the UGATE pin is electrically connected to the gate of the upper bridge transistor 110, and the PHASE pin is electrically connected to the first node A. The LGATE pin is electrically connected to the gate of the lower bridge transistor 120. ® a further resistor is further disposed in the pulse width modulation control chip 200
Rocset，其一端電連接至該第三節點C，另一端電連接至該 脈寬調變控制晶片200之PHASE引腳，使該脈寬調變控制 晶片200之PHASE引腳作為一多功能引腳，以擴展該脈寬 調變控制晶片200之功能。 該脈寬調變控制晶片200内還進一步設置一電感電流 感測器261 (Inductor Current Sense)，一計數步階電流產生 ❹器 262(Counter & Current Step)，一 振盪器 263，一 第一比 較器264以及一第二比較器265。 該電感電流感測器261之輸入端電連接至該第三節點 C，通過第一電阻Rocset以感測該脈寬調變控制晶片200 之PHASE引腳上之電壓，該電感電流感測器261之輸出端 電連接至該計數步階電流產生器262之輸入端，該計數步 階電流產生器262之輸出端電連接至該振盪器263之輸入 端，該振盪器263之輸出端電連接至該第二比較器265之 反向輸入端。 200939605 該第一比較器264之正向輸入端電連接至一參考電壓 .Vref，其反向輸入端電連接至一回饋電壓，該回饋電壓對應 • 於該電壓轉換器100之輸出端Vout所輸出之電壓。於本實 施例中，該電壓轉換器100之輸出端Vout進一步串聯一第 二電阻161及一第三電阻162後接地，該第二電阻161與 第三電阻162之連接之處定義為第五節點E，將該第五節點 E處之電壓Vfb作為該回饋電壓。當然可理解之是，該電 壓轉換器100之輸出端Vout所輸出之電壓也可作為回饋電Rocset, one end of which is electrically connected to the third node C, and the other end is electrically connected to the PHASE pin of the pulse width modulation control chip 200, so that the PHASE pin of the pulse width modulation control chip 200 is used as a multi-function pin To expand the function of the pulse width modulation control chip 200. An inductor current sensor 261 (Inductor Current Sense) is further disposed in the pulse width modulation control chip 200, and a counter current generator 262 (Counter & Current Current), an oscillator 263, a first The comparator 264 and a second comparator 265. The input end of the inductor current sensor 261 is electrically connected to the third node C, and the voltage on the PHASE pin of the pulse width modulation control chip 200 is sensed by the first resistor Rocset, the inductor current sensor 261 The output of the oscillator step current generator 262 is electrically connected to the input of the oscillator 263, and the output of the oscillator 263 is electrically connected to the input terminal of the counter step current generator 262. The inverting input of the second comparator 265. 200939605 The forward input terminal of the first comparator 264 is electrically connected to a reference voltage .Vref, and the inverting input terminal is electrically connected to a feedback voltage corresponding to the output of the voltage converter 100. The voltage. In this embodiment, the output terminal Vout of the voltage converter 100 is further connected in series with a second resistor 161 and a third resistor 162, and is grounded. The connection between the second resistor 161 and the third resistor 162 is defined as a fifth node. E. The voltage Vfb at the fifth node E is used as the feedback voltage. Of course, it can be understood that the voltage outputted by the output terminal Vout of the voltage converter 100 can also be used as the feedback power.
該第一比較器264之輸出端電連接至該第二比較器 265之正向輸入端，該第二比較器265之輸出端電連接至該 閘極控制邏輯電路220之一輸入端。 優選之，該電感電流感測器261之輸入端通過一控制 開關266電連接至該第三節點C，以感測該脈寬調變控制 晶片200之PHASE引腳上之電壓。該控制開關266接受該 0閘極控制邏輯電路220之第二輸出端所輸出之第二脈衝訊 號Vc2之控制，以使該電感電流感測器261與該下橋電晶 體120同步工作。 該電感電流感測器261，計數步階電流產生器262，振 盪器263，第一比較器264，第二比較器265，第一電阻 Rocset，下橋電晶體120及電流源250組成一個輕載效率改 善電路，用以改善該電壓轉換器100於輕載模式下之效率。 該電壓轉換器100之工作原理為：當該脈寬調變控制 晶片200被致能後，該電源管理器210發出控制訊號，使 15 200939605 該閘極控制邏輯電路220工作以使其第一輸出端發出第一 . 脈衝訊號Vcl，第二輸出端發出第二脈衝訊號Vc2。該第一 .脈衝訊號Vcl及第二脈衝訊號Vc2分別透過該第一驅動器 230及第二驅動器240輸出至該脈寬調變控制晶片200之 UGATE引腳及LGATE引腳，並分別傳輸至該上橋電晶體 110及下橋電晶體120之閘極以控制切換該上橋電晶體110 及該下橋電晶體120。 由於該第一脈衝訊號Vcl與該第二脈衝訊號Vc2為一 ®對互為相反之訊號，因此，當上橋電晶體110導通時，該 下橋電晶體120截止；當上橋電晶體110截止時，該下橋 電晶體120導通。 當該上橋電晶體110導通，下橋電晶體120截止時， 該輸入電壓Vin通過上橋電晶體110對該電感L及電容C 所組成之低通濾波器130進行充電；當該上橋電晶體110 截止，下橋電晶體120導通時，該低通濾波器130通過下 0橋電晶體120進行放電。於該低通濾波器130充放電之過 程中，該電壓轉換器100產生輸出電流I，並將該輸入電壓 Vin轉換成一個穩定之電壓，並通過該電壓轉換器100之輸 出端Vout輸出。 由於本發明之電壓轉換器100還包括由電感電流感測 器261，計數步階電流產生器262，振盪器263，第一比較 器264，第二比較器265，電流源250，第一電阻Rocset以 及下橋電晶體120組成之一輕載效率改善電路，因此當該 下橋電晶體120導通時，該電流源250，第一電阻Rocset 16 200939605 以及導通之下橋電晶體120組成一回路。由於該電感電流 . 感測器261通過該控制開關266電連接至第三節點C，而 .該控制開關266受該閘極控制邏輯電路220之第二輸出端 所輸出之第二脈衝訊號Vc2之控制，因此當下橋電晶體120 導通時，該控制開關266閉合，該電感電流感測器261通 過該第一電阻Rocset偵測脈寬調變控制器200之PHASE 引腳上之電流，即偵測判斷該電流源250，第一電阻Rocset 以及導通之下橋電晶體120所組成回路中之電流。 ® 該計數步階電流產生器262通過電感電流感測器261 所輸出之訊號判斷是否持續地產生輕載電流，如持續地產 生輕載電流，則表示該電壓轉換器100持續地處於輕載模 式下，此時，該計數步階電流產生器262產生一電流至該 振盪器263中，以降低該振盪器263之輸出頻率，其輸出 頻率通過第二比較器265輸出至該閘極控制邏輯電路220 以降低其輸出之第一脈衝訊號Vcl及第二脈衝訊號Vc2之 ❹頻率，從而降低了該上橋電晶體110及下橋電晶體120之 切換頻率，減少由於該上橋電晶體110及下橋電晶體120 之切換而造成之效率損耗，使採用該電壓轉換器100之電 子裝置可具有更長之待機時間。 且本發明之電壓轉換器100是利用該脈寬調變控制晶 片200上之PHASE引腳作為多功能引腳從而形成了由電感 電流感測器261，計數步階電流產生器262，振盪器263， 第一比較器264，第二比較器265，第一電阻Rocset，下橋 電晶體120及電流源250所組成之輕載效率改善電路，其 17 200939605 並不需要設置額外之多功能引腳來形成該輕載效率改善電 . 路。 . 相較於先前技術，本發明之電壓轉換器100採用輕载 效率改善電路降低該電壓轉換器100於輕載模式時上橋電 晶體110及下橋電晶體120之切換頻率，從而減少效率損 耗，使採用該電壓轉換器100之電子裝置可具有更長之待 機時間，且其利用該脈寬調變控制晶片200上之PHASE引 ❹腳作為多功能引腳以形成輕載效率改善電路，其並沒有增 加該脈寬調變控制晶片200之引腳數。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 示意圖。 【主要元件符號說明】 t壓轉換器 100 脈寬調變控制晶片 200 上橋電晶體 110 下橋電晶體 120 低*通濾波器 130 電源管理器 210 〇 圖1係本發明實施例所提供之一種電壓轉換器之電路 18 200939605 閘極控制邏輯電路 220 . 第一驅動器 230 . 第二驅動器 240 電流源 250 第一二極體 251 第二二極體 151 第一電容 152 電感電流感測器 261 ®計數步階電流產生器 262 振盪器 263 第一比較器 264 第二比較器 265 第二電阻 161 第三電阻 162 控制開關 266 Ο 19An output of the first comparator 264 is electrically coupled to a forward input of the second comparator 265, and an output of the second comparator 265 is electrically coupled to an input of the gate control logic 220. Preferably, the input of the inductor current sensor 261 is electrically coupled to the third node C via a control switch 266 to sense the voltage on the PHASE pin of the pulse width modulation control chip 200. The control switch 266 receives the control of the second pulse signal Vc2 outputted by the second output terminal of the 0 gate control logic circuit 220 to synchronize the inductor current sensor 261 with the lower bridge transistor 120. The inductor current sensor 261, the counting step current generator 262, the oscillator 263, the first comparator 264, the second comparator 265, the first resistor Rocset, the lower bridge transistor 120 and the current source 250 form a light load. A efficiency improvement circuit for improving the efficiency of the voltage converter 100 in a light load mode. The voltage converter 100 operates on the principle that when the pulse width modulation control chip 200 is enabled, the power manager 210 sends a control signal to enable the 15th control circuit 220 to operate to make its first output. The first pulse signal Vcl is issued, and the second output signal Vc2 is outputted by the second output terminal. The first pulse signal Vcl and the second pulse signal Vc2 are respectively output to the UGATE pin and the LGATE pin of the pulse width modulation control chip 200 through the first driver 230 and the second driver 240, and are respectively transmitted to the UGATE pin and the LGATE pin. The gates of the bridge transistor 110 and the lower bridge transistor 120 control the switching of the upper bridge transistor 110 and the lower bridge transistor 120. Since the first pulse signal Vcl and the second pulse signal Vc2 are mutually opposite signals, when the upper bridge transistor 110 is turned on, the lower bridge transistor 120 is turned off; when the upper bridge transistor 110 is turned off; When the lower bridge transistor 120 is turned on. When the upper bridge transistor 110 is turned on and the lower bridge transistor 120 is turned off, the input voltage Vin is charged by the upper bridge transistor 110 to the low pass filter 130 composed of the inductor L and the capacitor C; when the upper bridge is charged When the crystal 110 is turned off and the lower bridge transistor 120 is turned on, the low pass filter 130 is discharged through the lower 0 bridge transistor 120. During the charging and discharging of the low pass filter 130, the voltage converter 100 generates an output current I, converts the input voltage Vin into a stable voltage, and outputs it through the output terminal Vout of the voltage converter 100. Since the voltage converter 100 of the present invention further includes an inductor current sensor 261, a step current generator 262, an oscillator 263, a first comparator 264, a second comparator 265, a current source 250, and a first resistor Rocset. And the lower bridge transistor 120 is composed of a light load efficiency improving circuit. Therefore, when the lower bridge transistor 120 is turned on, the current source 250, the first resistor Rocset 16 200939605, and the underlying bridge transistor 120 form a loop. Because of the inductor current, the sensor 261 is electrically connected to the third node C through the control switch 266, and the control switch 266 is received by the second pulse signal Vc2 outputted by the second output terminal of the gate control logic circuit 220. Control, so when the lower bridge transistor 120 is turned on, the control switch 266 is closed, and the inductor current sensor 261 detects the current on the PHASE pin of the pulse width modulation controller 200 through the first resistor Rocset, that is, detecting The current source 250, the first resistor Rocset, and the current in the loop formed by the bridge transistor 120 are determined. The counting step current generator 262 determines whether the light load current is continuously generated by the signal output from the inductor current sensor 261. If the light load current is continuously generated, it indicates that the voltage converter 100 is continuously in the light load mode. At this time, the counting step current generator 262 generates a current into the oscillator 263 to lower the output frequency of the oscillator 263, and the output frequency thereof is output to the gate control logic circuit through the second comparator 265. 220 to reduce the frequency of the first pulse signal Vcl and the second pulse signal Vc2 of the output, thereby reducing the switching frequency of the upper bridge transistor 110 and the lower bridge transistor 120, reducing the upper bridge transistor 110 and the lower The loss of efficiency caused by the switching of the bridge transistor 120 allows the electronic device employing the voltage converter 100 to have a longer standby time. The voltage converter 100 of the present invention uses the PHASE pin on the pulse width modulation control chip 200 as a multi-function pin to form an inductor current sensor 261, which counts the step current generator 262, and the oscillator 263. The first comparator 264, the second comparator 265, the first resistor Rocset, the lower bridge transistor 120 and the current source 250 constitute a light load efficiency improving circuit, and the 17 200939605 does not need to set an additional multi-function pin. Forming the light load efficiency improves the electricity. Compared with the prior art, the voltage converter 100 of the present invention uses a light load efficiency improving circuit to reduce the switching frequency of the upper bridge transistor 110 and the lower bridge transistor 120 when the voltage converter 100 is in the light load mode, thereby reducing efficiency loss. The electronic device using the voltage converter 100 can have a longer standby time, and the PHASE pin on the pulse width modulation control chip 200 is used as a multi-function pin to form a light load efficiency improving circuit. The number of pins of the pulse width modulation control chip 200 is not increased. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. [Simple description of the diagram] Schematic. [Main component symbol description] t-voltage converter 100 pulse width modulation control chip 200 upper bridge transistor 110 lower bridge transistor 120 low-pass filter 130 power manager 210 FIG. 1 is a kind of embodiment provided by the present invention Circuit of Voltage Converter 18 200939605 Gate Control Logic Circuit 220 . First Driver 230 . Second Driver 240 Current Source 250 First Diode 251 Second Diode 151 First Capacitor 152 Inductor Current Detector 261 ® Count Step current generator 262 oscillator 263 first comparator 264 second comparator 265 second resistor 161 third resistor 162 control switch 266 Ο 19