200939350 九、發明說明： 【發明所屬之技領域】 本發明係關於一種晶圓之銅勢表面處理方法，特別是關於 一種藉由在一晶圓之銅墊的上方形成一層緊密結合之錫層，以 供直接做為或選擇接合更小尺寸金屬凸塊的晶圓之銅墊表面 處理方法。 【先前技術】 近年來，高效能、高積集度、低成本、輕薄短小一直為長 久以來電子產品設計製造上所追尋之目標。為了達成上述目 標，積體電路封裝技術也跟著朝向微型化、高密度化發展，其 中常見的封裝技術包含雙列直插式封裝①加丨In_line Package ’ DIP)、四方扁平封裝(guadFlatPack , 、四方形 扁平無引腳封裝(Quad Hat No-lead，QFN)、針聊陣列式構裝 (Pin Grid Array ’ PGA)、球格陣列式構裝毋沾 GridAlTay，BGA) 及晶片尺寸級構裝(Chip-Scale Package，CSP)等。以BGA或 PGA封裝構造為例，其係在一多層電路基板之上表面利用打 線技術(Wire Bonding ’ WB)或覆晶技術(FlipChip , FC)固設至 少一晶片，並在其下表面固設數個銲球㈣如匕,。特別是’ 由於BGA或PGA封裝構造能以堆疊(stack die)方式或鄰接 (side-by-side)方式進一步整合數個晶片於同一封裝體中，因此 有利於構成具多功能的系統級封裝(|§3^61111111^(±&鮮，8正）， 200939350 - 是以成為近年來發展迅速之晶片構裝技術。另一方面，CSP封 - 裝構造則是能整合數個晶片至同一晶片中，以構成具多功能的 系統單晶片封裝(System On Chip，SOC)，故亦為發展迅速之 另一晶片構裝技術。+上所述，不論是BGA、PGA或CSP等 先進封裝技術皆會使用到覆晶技術(Flip Chip，FC)，以便在一 b曰片之下表面固設數個凸塊(s〇lder bump)。因此，覆晶技術亦 成為先進封裝技術成敗與否之關鍵因素之一。 ❹ 舉例而言，中華民國專利公告第5214〇6號則公開一種「凸 塊形成製程」’其包含下列步驟：提供一晶圓，具有數個銲墊； 於該晶圓之表面依序形成一黏著層、一阻障層及一沾錫層；定 義該沾錫層及該阻障層’以形成複數個球底金屬層_州圖 案，並暴露出該黏著層；形成數個銲料層圖案於該球底金屬層 圖案之表面，去除暴露出之該黏著層；以及進行回焊使各該銲 料層圖案形成-凸塊。上述黏著層材質選自鉻、銅、銘、欽其 中之，上述阻障層材質選自鈦鱗合金、鈦、錄飢合金、鉻銅 合金其中之一；及上述沾錫層材質選自銅、鎳、鈀、金、銀及 始其:之-。在製程完絲，該·之銲墊(缝)上依序存在 該黏著層、阻障層、沾錫層及銲料凸塊之疊層構造。 再者’中華民國專利公告第1257136號則公開一種「晶圓 級封裝之凸塊製造方法」，其包含下列步驟：提供一晶圓，其 上形成數條切割道、一保護層及數個銲墊；形成一導電層於該 200939350 _ _上，料與鱗墊紐連接_人該切割道 ;形成一 . $阻層於該導電層上；_化該光阻層於該銲整上方形成數個 露出該導電層之開口丨並於輝塾以外之區域形成數個未露出該 導電層之開口，以及形紐個凸塊於該些銲墊上方之該些開口 以連接該導電層。上料電層之材質係選自欽、鈦鶴合金、銘、 錦叙合金、錦、銅及鉻的其中之一；或是，欽/錦叙合金/銅或 在呂/鎳鈒合金/銅之三層結構；或為欽/銅二層結構，亦可為銘/ ❹ 鈦她合金/銅之四層結構。在製程完成後，該晶圓之銲雜 墊)上依序存在該導電層(一至四層)及鮮料凸塊之叠層構造。 另外，中華民國專利公告第⑵則號則公開一種r降低 晶圓上金屬凸塊表面姆度之方法」，其包含下列步驟：提供 -晶圓’具有-主動面；形成—金屬層於該晶圓之該主動面； 形成-光阻層於該金屬層，該光阻層係形成有數個開口以顯露 該金屬層；形成數個金屬凸塊於該光阻層之開口該金屬凸塊 D 係具有數個顯露於該光阻層之接合面；研磨該金屬凸塊之接合 面，以降低其表面粗糙度；在研磨之後’移除該光阻層；以及 在移除該光阻層之後’蝕刻該金屬凸塊，以消除該接合面之研 磨痕跡。上述金屬層係選自單一金屬或合金組成之複合金屬 層，亦即UBM結構。在製程完成後，該晶圓之銲墊(銘整)上 依序存在該金屬層(單一層或複合層)及銲料凸塊之疊層構造。 除此之外，相關於覆晶(Flip Chip，FC)及凸塊底金屬層 200939350 (Under Bump Metallurgy，UBM)之先前技術尚有中華民國專利 . 公告第556293號「凸塊製程」、第1221334號「凸塊製程」、 第1225698號「晶圓級封裝凸塊製程」及第1239578號「凸塊 製程」等。在製程完成後，該晶圓之鋒塾(銘塾)上依序亦皆存 在該凸塊底金屬層(複合層)及録料凸塊之疊層構造。 另一方面，相對摩於封裝技術之發展，半導體晶圓製程技 術亦朝微小化邁進。特別是，在0.13微米級晶圓技術進展至 © 9〇奈米級晶圓技術期間，链製程將逐漸被銅製程取代，以往 晶圓表面上所形成之鋁墊(A1 pad)突然變成銅墊(Cu pad)。此種 先進製程趨勢的演變立刻面臨到一技術問題，亦即這使得原本 應用於晶圓鋁墊之各種習用凸塊底金屬層（Under Bump200939350 IX. Description of the Invention: [Technical Field] The present invention relates to a copper surface treatment method for a wafer, and more particularly to a method for forming a tightly bonded tin layer over a copper pad of a wafer. A copper pad surface treatment method for wafers that are directly used or selected to bond smaller size metal bumps. [Prior Art] In recent years, high performance, high integration, low cost, light weight and shortness have been the goals pursued in the design and manufacture of electronic products for a long time. In order to achieve the above objectives, integrated circuit packaging technology is also moving towards miniaturization and high density. Common packaging technologies include dual in-line package 1 plus In_line Package ' DIP), quad flat package (guadFlatPack , , 4 Quad Flat No-lead (QFN), Pin Grid Array 'PGA, Grid Array GridAlTay, BGA) and Chip Size Package (Chip) -Scale Package, CSP), etc. Taking a BGA or PGA package structure as an example, at least one wafer is fixed on a surface of a multi-layer circuit substrate by wire bonding (WB) or flip chip technology (FlipChip, FC), and is fixed on the lower surface thereof. Set a few solder balls (four) such as 匕. In particular, 'BGA or PGA package construction can further integrate several wafers in the same package in a stack die or side-by-side manner, thus facilitating the formation of a multi-functional system-in-package ( |§3^61111111^(±&Fresh, 8 positive), 200939350 - It is a wafer fabrication technology that has developed rapidly in recent years. On the other hand, the CSP package-mounting structure can integrate several wafers to the same wafer. In order to form a multi-functional system on-chip (SOC), it is also a rapidly developing wafer fabrication technology. In addition, advanced packaging technologies such as BGA, PGA or CSP Flip Chip (FC) will be used to fix a number of bumps on the surface of a b-chip. Therefore, flip chip technology has become the key to the success or failure of advanced packaging technology. One of the factors. ❹ For example, the Republic of China Patent Publication No. 5214-6 discloses a "bump forming process" which includes the steps of providing a wafer having a plurality of pads; on the surface of the wafer Forming an adhesive layer and a barrier layer in sequence a tin-plated layer; defining the tin-plated layer and the barrier layer to form a plurality of ball-bottom metal layer-state patterns and exposing the adhesive layer; forming a plurality of solder layer patterns on the surface of the ball-bottom metal layer pattern And removing the exposed adhesive layer; and performing reflow soldering to form each of the solder layers to form a bump. The adhesive layer material is selected from the group consisting of chromium, copper, Ming and Qin, and the barrier layer material is selected from titanium scale alloy. One of titanium, hunger alloy, chrome-copper alloy; and the above-mentioned tin-plated material is selected from the group consisting of copper, nickel, palladium, gold, silver, and the like: - in the process of finishing the wire, the solder pad (seam The laminated structure of the adhesive layer, the barrier layer, the tin-plated layer, and the solder bumps is sequentially present. Further, the 'Mounting Patent Publication No. 1257136 discloses a method for manufacturing a bump of a wafer-level package, The method comprises the steps of: providing a wafer on which a plurality of dicing streets, a protective layer and a plurality of solder pads are formed; forming a conductive layer on the 200939350 _ _, which is connected with the scale pad _ the cutting channel; Forming a resist layer on the conductive layer; _forming the photoresist layer on the soldering layer Forming a plurality of openings 露出 exposing the conductive layer and forming openings in the region other than the illuminating layer, and opening the openings above the pads to connect the conductive layers The material of the feeding layer is selected from one of Qin, Titanium alloy, Ming, Jinxu alloy, brocade, copper and chromium; or, Qin / Jin Xu alloy / copper or in Lu / nickel bismuth alloy / The three-layer structure of copper; or the two-layer structure of Qin/Copper, or the four-layer structure of Ming/❹Titanium alloy/copper. After the process is completed, the conductive pad on the wafer is sequentially present. Layer (one to four layers) and laminated structure of fresh bumps. In addition, the Republic of China Patent Publication No. (2) discloses a method for reducing the surface roughness of a metal bump on a wafer, which comprises the steps of: providing a wafer with an active surface; forming a metal layer on the crystal Forming a photoresist layer on the metal layer, the photoresist layer is formed with a plurality of openings to expose the metal layer; forming a plurality of metal bumps at the opening of the photoresist layer Having a plurality of bonding faces exposed to the photoresist layer; grinding the bonding surface of the metal bumps to reduce surface roughness thereof; 'removing the photoresist layer after polishing; and after removing the photoresist layer' The metal bump is etched to eliminate the abrasive trace of the joint. The above metal layer is selected from a composite metal layer composed of a single metal or alloy, that is, a UBM structure. After the process is completed, the metal pad (single layer or composite layer) and the solder bump stack structure are sequentially present on the pad of the wafer. In addition, the prior art related to Flip Chip (FC) and bump bottom metal layer 200939350 (Under Bump Metallurgy, UBM) still has the Republic of China patent. Announcement No. 556293 "Bumping Process", No. 1221334 No. "Bumping Process", No. 1225698 "Wafer Level Package Bumping Process" and No. 1239578 "Bumping Process". After the process is completed, the front edge of the wafer is also sequentially deposited on the bump metal layer (composite layer) and the recording bump. On the other hand, compared to the development of packaging technology, semiconductor wafer processing technology is also moving toward miniaturization. In particular, during the 0.13 micron wafer technology advancement to the 9 〇 nanometer wafer technology, the chain process will gradually be replaced by the copper process. The aluminum pad (A1 pad) formed on the surface of the wafer suddenly becomes a copper pad. (Cu pad). The evolution of this advanced process trend immediately faced a technical problem, which led to the use of various bump bump metal layers (Under Bump) that were originally applied to wafer aluminum pads.
Metallurgy，UBM)因金屬冶金相容性問題而不再完全適用於下 —世代的晶_墊上。再者，由於上述f用凸塊底金屬層通常 需要減金屬層，·導致其製程較為繁複，且生產成本亦相 © 馳高。另外，亦有必要思考要藉由何種先進技術，以進一步 縮小日曰圓銅墊上之凸塊尺寸，以便相對減少凸塊間距藉此提 高覆晶晶片在單位面積中可佈局之凸塊總量。 是故’確實有必要提供一種晶圓之銅塾表面處理方法，以 解決習知技術所存在的缺陷。 【弩明内容】 本發明之主要目的在於提供—種晶圓之銅墊表面處理方 200939350 其係在-晶圓上暫時全面性形成—金屬薄層，並選擇利用 • 化學浸鑛之方式形成—錫層於銅墊上方，進領化凸塊製程/ 構造及降低製程成本。 本發月之-人要目的在於提供—種晶圓之鋼塾表面處理方 法’其係㈣金屬薄層選擇以化學浸财式置換成—錫層，兮 錫層置換-晶圓之銅整表面一部份之銅，因而得到緊密結合於 銅塾表面之錫層，進而增加凸塊結合強度。 ❹、本發明之另—目㊣在於提供-種晶bj之銅墊表面處理方 法’其係在-晶圓之銅塾表面上方形成—緊密結合之錫層，以 =直接做為小尺寸之她，進而降低凸塊間距、提高凸塊佈局 进度及符合環保法規無鉛標準。 、本發明之再—目的在於提供—種晶圓之銅絲面處理方 去其係在-晶圓之銅墊表面上方形成一緊密結合之錫層，以 卿軸—頻合無崎料之凸塊進祕供無鉛覆晶技術及 ^ 符合雜法規無錯標準。 、為達上述之目的，;本發明提供—種晶圓之銅塾表面處理方 、、其匕3 .提供一晶圓，其表面具有數個銅墊；在該晶圓之 於5面形成金屬薄層’以電性連接所有該銅墊；形成一光阻層 ^屬薄層上’並圖案化該光阻層，以形成數個開口裸露該 鋼塾上之金屬薄層；化學浸錢處理該開口内之金屬薄層，將該 鋼塾上之金屬薄層置換成—錫層；去除該光阻層；以及，去除 200939350 - 未受該錫層遮蔽之金屬薄層。 • 接著，在該晶圓切割成數個晶片後，該錫層可直接做為小 尺寸之凸塊，以供媒介結合該晶片至一基板上，進而構成一 BGA或PGA封裝構造。或者，在該晶圓切割成數個晶片後， 賴層可直接做為小&寸之凸塊，且該晶片可直接使用做為一 CSP封裝構造。 再者’在本發明另一實施例之晶圓之銅墊表面處理方法 ❹ t ’於去除該光阻層的步驟之前，另可選擇包含：形成-銲料 層於該開口内之錫層上。接著，於去除該光阻層及去除未受該 錫層遮蔽之金屬薄層的步驟之後，另包含：對該銲料暑進行回 焊，以形成一金屬凸塊。 另外’在本發明再一實施例之晶圓之銅墊表面處理方法 中’於去除未受該錫層遮蔽之金屬薄層的步驟之後，另可進一 #包含：形成另-光阻層於該晶圓上，並圖案化該另一光阻 ® 層’以形成數個開口裸露該銅塾上之錫層；在該開口内形成一 銲料層，去除該另一光阻層；以及，對該銲料層進行回焊，以 形成數個金屬凸塊。 i 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更明顯易 K，下文將特舉本發明較佳實施例，並配合所附圖式，作詳細 說明如下。 200939350 根據本發明之晶圓之銅墊表面處理方法，其主要包含下列 步驟：提供一晶圓1，其表面具有數個銅墊u ;在該晶圓2之 表面形成-金屬薄層2 ’以電性連接所有該銅墊u :形成一光 阻層3於該金屬薄層2上，並圖案化該光阻層3，以形成數個 開口 3!裸露該銅墊1:1上之金屬薄層2 ;在該開口 31内形成 -錫層4 ;去除該轉層3 ;以及’去除未受該錫層*遮蔽之 金屬薄層2。本發明係可依需求選擇藉由下述第一至第三實施 例之任一種方式進行該晶圓之銅墊表面處理方法，該第一至第 三實施例係分別作詳駟說明如下。 請參照第1至7醇所示，本發明第一實施例之晶圓之銅墊 表面處理方法主要包含下列步驟：提供L，其表面具有 數個銅墊11，在該晶圓i之表面形成一金屬薄層2，以電性連 接所有該_ 11 ;形成—光阻層3於該金屬薄層2上，並圖 案化該光阻層3，以形成數個開D 31裸露該銅墊n上之金屬 薄層2 Mb學浸鑛處理該開口 31内之金屬薄層2，將該銅塾 上之金屬薄層2置換成-錫層4 ;去除該光阻層3 ;以及， 去除未受該錫層4遮蔽之金屬薄層2。 請參照第1圖所示，本發明第一實施例之晶圓之銅塾表面 處理方法第—步驟係：提供該晶圓丨，其表面具有數個銅塾 在本步驟中，該晶圓丨較佳係選自碎晶圓且該晶圓！係 選擇使用G.18微雜下之銅製程進行加王，以便在該晶圓！ 200939350 - 之表面形成數個該銅墊* n(Cu pad)及銅線路(未緣示）。接著， ， 該晶圓1之表面進一步形成一保護層12，且圖案化該保護層 12 ’以定義數個開口 (未標示）’藉此裸露該銅墊u及包埋該銅 線路。該保護層12埤常選自氧化矽或氮化矽等絕緣材質。 叫參照第2圖所示，本發明第一實施例之晶圓之銅墊表面 處理方法第—步驟係.在該晶圓〗之表面形成該金屬薄層2， 以電性連接所有該銅墊11。在本步驟中，本發明較佳在真空 ❹ 狀態下選擇利用濺鍍(sputtering deposition)、蒸鍍(evap〇rati〇n deposition)或無電鍍(咖ctr〇Iess platin祕理該晶圓！之表面， 娜賴金屬薄層2,該金屬騎2之厚度較佳㈣在〗奈米 (nm)至1微米(um)之間’特別是在5奈米至奈米之間最 佳是在10奈米至_奈米之間。該金屬薄層2之厚度必需適 當控制’賴後續咖化學賴方式將其魏置換成該錫層 4。再者’該金屬薄層2之材質較佳選自能被錫置換之金屬， ❹.銅’翻以在製程中暫時性且全雜的雜連接所有該銅 墊1其目的在於用以克服在後續進行化學浸鏟時，因該晶 圓1之内部f路(未繪示)造成各銅塾U之電位不相同的問題， 以確保能在所有之銅墊Η上形成一致厚度的錫層4。 凊參照第3及4圖所示，本發明第—實施例之晶圓之銅塾 表面處理方法第三步驟係：形成該光阻層3於該金屬薄層2 上並圖案化該光阻層3 ’以形成數個該開口 31裸露該銅墊 12 200939350 • 11上之金屬薄層2。在本步驟中’本發0月較佳選擇藉由塗佈液 . 態光阻(Photoresist)或黏貼乾膜(dryfilm)而形成該光阻層3,且 其係可取材自負型光阻或正型光阻。接著，本發明係利用一般 曝光顯影方式對該光，層3進行圖案化製程，以形成數個該開 口 ’該開口 31對應於該鋼塾„之位置，因而可裸露該銅 墊11上之金屬薄層2。 請參照第5及5A ®所示’本發明第—實施例之晶圓之銅 ❹ 録面處理方法第四步驟係：化學浸錄處理該開口 31内之金 屬薄層2 ’將該銅塾Η上之金屬薄層2置換成一錫層4。在本 步驟中，該化學浸鍍方式較佳係選自具有置換性之電錄方式， 特别疋化學浸錫製紅(ImmersionTinProcess)。該化學浸鑛處理 之電鑛液係較佳以該錫電鑛液為主，例如氯化錫(SnCl2)加上錯 合劑(C〇mplexagent)之電鑛液’其中該錯合劑較佳可選自硫腺 (ThiG_)。藉此’由於該電難巾之_子肢漸置換該金 ❹ 屬薄層2之銅，因而沈積形成該錫層4，且最後該μ 2 之銅將完全被錫置換取代。值得注意的是，如第：二 該晶圓1之銅墊11表面的-部份鋼亦可能被錫所置換取代， 因而形成一祕面ΐη緊密結合該錫層4。該錫層4之高度(厚 度)較佳控齡_絲㈣至⑽微物m)之間特別是在 〇·1微米至75微米之間，最佳是在i微米至％微米之間。再 者’該錫層4之材質除了選自錫之外，亦可選自其他無轉 13 200939350 • 料，例如錫銀合金或錫銀銅合金等。 . 請參照第6圖所示，本發明第-實施例之晶圓之銅墊表面 ^方法第五步驟係？去除該光阻層3。在本步驟中，可利用 般顯衫方式去除該光阻層3。當該光阻層3選自光阻乾膜 時，則亦可直接撕除之。在去除該光阻層3後，將裸露該錫層 4以及未受該錫層4遮蔽之金屬薄層2。 凊參照第7圖所示，本發明第一實施例之晶圓之銅墊表面 ❹ 處理方法第六步驟係：絲未受該_ 4遮蔽之金屬薄層2。 在本步驟巾’本發明較佳翻適當之磁彳液以選擇性姓刻去 除該金屬薄層2之銅，但不雜刻該錫層4。再者，在本發明_ 之其他實施例t ’亦可另以形成光阻、曝光、顯影等步驟在該 錫層4上形成另一光阻層做為一遮蔽層(未喻示），但曝露未受 該錫層4遮蔽之金屬薄看2，以便利用侧液姓刻去除該金屬 薄層2之銅。接著，再利用顯影液去除該錫層4上之另一光阻 ❹層。 。藉由上述第-至第六步驟，本發明第一實施例即可在該晶 圓1之銅墊11上形成緊密結合之該錫層4 ’且該錫層4可直 接做為小尺寸之凸塊。在完成本發明第一實施例之晶圓之銅墊 表面處理方法後’接著可將該晶圓1切割成數個晶片（未緣 示），該晶片可利用該錫層4(小尺寸之凸塊)媒介結合至一基板 (未緣不)上，進而構成—BGA或PGA封裝構造。或者，在該 200939350 日日圓1切割成數個晶片（未繪示)後，隨即直接使用做為一 csp 封裝構造。由於該踢層4定義之凸塊尺寸相對較小，故有利於 進-步縮減銅墊間距、降低凸塊間距，及提高單位面積中之凸 塊佈局&、度。㈤時，亦能符合RqHS及等目際環保法 規對無鉛標準的要求。 -月參照第1至5及8至11圖所示，本發明第二實施例之晶 圓之銅墊表面處理方”相似於本發明第—實施例，但該第二 實施例之晶圓之銅墊表面處理方法係包含下列步驟：提供一晶 圓1 ’其表面具有數個銅墊U;在該晶圓丄之表面形成一金屬 薄層2 ’以電性連接所有該銅塾u 形成一光阻層3於該金屬 薄層2上’並随化該光阻層3，㈣成數烟口 y裸露該 鋼整11上之金屬薄層2 ;化學浸錢處理該開口 31内之金屬薄 層2，將該銅墊n上之金屬薄層2置換成一錫層4 ;形成一焊 料層5於· 口 31狀顯4上；去_絲層3 ;去除未 又該錫層4遮蔽之金屬薄層2;以及，對該銲料層5進行回焊， 以形成一金屬凸塊5,。 相較於該第-較佳實施例，該第二較佳實施例較佳係形成 較厚之該光阻層3，使該光阻層3之開口 31具有較大空間， 以便在形成該錫層4之後，尚能進一步形成該銲料層5。該銲 料層5係可選用印刷、電鑛或蒸錢等方式形成在該開口 31内 之錫層4上，其中該電鍵方式可選自有電電錄(dectr〇piating) 15 200939350 或無電電鑛(electrolessplating)等方式。該銲料層5之材質較佳 選自無錯焊料，例如錫、錫銀合金或錫銀銅合金等，且其材質 及熔點可相同或相異於該錫層4之材質及熔點。惟，依實際需 求，該銲料層5之材質仍可選自含鉛焊料，例如錫錯合金等。 該銲料層5經回焊後形成該金屬凸塊5,，該金屬凸塊5,之高 度(厚度)較佳控制在5微米(um)至300微米(um)之間，特別是 在10微米至250微米之間’最佳是在20微米至200微米之間。 Φ 藉由上述第一至第八步驟，本發明第二實施例即可在該晶 圓1之銅墊11上形成緊密結合之該錫層4，並藉由該錫層4 一 進一步形成該金屬凸塊5’。在完成本發明第二實施例之晶圓之 銅墊表面處理方法後，接著可將該晶圓丨切割成數個晶片（未 緣示）’該晶片可利用該金屬凸塊5’媒介結合至一基板(未繪示） 上，進而構成一 BGA或PGA封裝構造。或者，在該晶圓工 切割成數個晶片（未繪示)後’隨即直接使用做為一 Csp封裝構 ❹ 造。由於該錫層4及金屬凸塊5,仍具相對較小之尺寸，故亦有 利於進一步縮減銅墊朗距、降低凸塊間距，及提高單位面積中 之凸塊佈局密度。同時，亦能符合及weee等國際環 保法規對無錯標準的要求。 清參照第1至7友12至16圖所示，本發明第三實施例之 晶圓之銅墊表面處理方法係相似於本發明第一實施例，但該第 二實施例之晶圓之銅墊表面處理方法係包含下列步驟：提供一 16 200939350 曰 fMl ί Ββ ，其表面具有數個銅墊I〗；在該晶圓1之表面形成一金 屬薄層2，以電性連接所有該銅墊η ;形成—光阻層3於該金 屬薄層2上’並圖案化該光阻層3，以形成數侧口 31裸露 ^鋼墊11上之金屬薄層2 ;化學浸鍵處理該開口 31内之金屬 薄層2 ’將該銅墊u木之金屬薄層2置換成一錫層4，·去除該 ^層3 ,去除未受_錫層4遮蔽之金屬薄層2 ;形成另一光Metallurgy, UBM) is no longer fully applicable to the next generation of crystal-mats due to metallurgical compatibility issues. Furthermore, since the above-mentioned bump bottom metal layer generally requires a metal layer reduction, the process is complicated, and the production cost is also high. In addition, it is also necessary to consider what advanced technology to further reduce the size of the bumps on the round copper pads to reduce the bump spacing and thereby increase the total number of bumps that can be laid out in the unit area of the flip chip. . Therefore, it is indeed necessary to provide a copper beryllium surface treatment method for wafers to solve the defects of the prior art. [Contents of the invention] The main purpose of the present invention is to provide a copper pad surface treatment party for the wafer 200939350. The system is temporarily formed on the wafer - a thin layer of metal, and is selected to be formed by chemical leaching. The tin layer is above the copper pad to advance the bump process/configuration and reduce process cost. The purpose of this month is to provide a method for the surface treatment of steel wafers. (4) The thin layer of metal is replaced by a chemical immersion method into a tin layer, and the tin layer is replaced by a copper surface. A portion of the copper thus obtains a tin layer that is tightly bonded to the surface of the copper matte, thereby increasing the bond strength of the bump. ❹, the other object of the present invention is to provide a copper pad surface treatment method of the seed crystal bj, which is formed on the surface of the copper beryllium of the wafer - a tightly bonded tin layer, to directly use her as a small size , in turn, reduce the bump spacing, improve the bump layout progress and meet the environmental protection standards lead-free standards. A further object of the present invention is to provide a copper wire surface treatment of a wafer to form a tightly bonded tin layer on the surface of the copper pad of the wafer, which is a convex-frequency and non-baked material. Block into the secret for lead-free flip chip technology and ^ meet the standards of error-free standards. For the above purposes, the present invention provides a copper beryllium surface treatment method for a wafer, and a crucible for providing a wafer having a plurality of copper pads on its surface; and forming a metal on the surface of the wafer The thin layer 'electrically connects all the copper pads; forming a photoresist layer on the thin layer' and patterning the photoresist layer to form a plurality of openings to expose the thin metal layer on the steel crucible; chemical immersion treatment a thin metal layer in the opening, replacing the thin metal layer on the steel crucible with a tin layer; removing the photoresist layer; and removing 200939350 - a thin metal layer not covered by the tin layer. • Next, after the wafer is diced into a plurality of wafers, the tin layer can be directly used as a small-sized bump for the medium to bond the wafer to a substrate to form a BGA or PGA package structure. Alternatively, after the wafer is diced into a plurality of wafers, the lamella layer can be directly used as a small & inch bump, and the wafer can be directly used as a CSP package structure. Further, in the silicon pad surface treatment method of the wafer according to another embodiment of the present invention, before the step of removing the photoresist layer, the method further comprises: forming a solder layer on the tin layer in the opening. Then, after the step of removing the photoresist layer and removing the thin metal layer not covered by the tin layer, the method further comprises: reflowing the solder to form a metal bump. In addition, in the method for treating a copper pad surface of a wafer according to another embodiment of the present invention, after the step of removing the thin metal layer not covered by the tin layer, another method may further include: forming a further photoresist layer. And patterning the other photoresist layer ' on the wafer to form a plurality of openings to expose a tin layer on the copper bead; forming a solder layer in the opening to remove the other photoresist layer; and, The solder layer is reflowed to form a plurality of metal bumps. [Embodiment] The above and other objects, features, and advantages of the present invention will become more apparent. 200939350 A copper pad surface treatment method for a wafer according to the present invention, which mainly comprises the steps of: providing a wafer 1 having a plurality of copper pads u on its surface; forming a thin metal layer 2 on the surface of the wafer 2 Electrically connecting all the copper pads u: forming a photoresist layer 3 on the metal thin layer 2, and patterning the photoresist layer 3 to form a plurality of openings 3! Exposed the copper pads 1:1 thin metal Layer 2; a tin layer 4 is formed in the opening 31; the layer 3 is removed; and 'the thin metal layer 2 not covered by the tin layer* is removed. In the present invention, the copper pad surface treatment method of the wafer can be selected by any of the following first to third embodiments, and the first to third embodiments are respectively described in detail below. Referring to the first to seventh alcohols, the copper pad surface treatment method of the first embodiment of the present invention mainly comprises the following steps: providing L having a plurality of copper pads 11 on the surface thereof, forming a surface on the wafer i a metal thin layer 2 electrically connecting all of the _11; forming a photoresist layer 3 on the metal thin layer 2, and patterning the photoresist layer 3 to form a plurality of openings D 31 to expose the copper pad The metal thin layer 2 Mb is immersed to treat the thin metal layer 2 in the opening 31, the metal thin layer 2 on the copper enamel is replaced by the tin layer 4; the photoresist layer 3 is removed; and the removal is not The tin layer 4 is covered by a thin metal layer 2. Referring to FIG. 1 , a first step of the copper beryllium surface treatment method of the wafer according to the first embodiment of the present invention is: providing the wafer crucible having a plurality of copper crucibles on the surface thereof, the wafer crucible Preferably, it is selected from the group of wafers and the wafer! The system chooses to use the G.18 micro-disintegration copper process to add the king to the wafer! 200939350 - The surface forms several copper pads * n (Cu pad) and copper lines (not shown). Next, a surface of the wafer 1 is further formed with a protective layer 12, and the protective layer 12' is patterned to define a plurality of openings (not labeled) to thereby expose the copper pad u and embed the copper line. The protective layer 12 is usually selected from insulating materials such as tantalum oxide or tantalum nitride. Referring to FIG. 2, the copper pad surface treatment method of the first embodiment of the present invention is the first step of forming a thin metal layer 2 on the surface of the wafer to electrically connect all the copper pads. 11. In this step, the present invention preferably selects sputtering surface deposition, evaporation (evap〇rati〇n deposition) or electroless plating in a vacuum crucible state. , Nalai metal thin layer 2, the thickness of the metal ride 2 is better (four) between the〗 〖Nano (nm) to 1 micron (um) 'especially between 5 nm to nano-optimal is in 10 Between rice and _ nanometer. The thickness of the thin metal layer 2 must be appropriately controlled to replace the Wei with the tin layer 4. The material of the metal thin layer 2 is preferably selected from The metal replaced by tin, ❹.copper' turns over the temporary and fully miscellaneous miscellaneous connections in the process. All of the copper pads 1 are designed to overcome the internal f of the wafer 1 during subsequent chemical dip shovel. The road (not shown) causes the problem that the potentials of the respective copper bismuth U are different, so as to ensure that a uniform thickness of the tin layer 4 can be formed on all the copper pads. 凊 Referring to Figures 3 and 4, the present invention is the first The third step of the copper beryllium surface treatment method of the wafer of the embodiment is: forming the photoresist layer 3 on the metal thin layer 2 and patterning the light Layer 3' exposes a plurality of metal openings 12 on the copper pad 12 200939350 • 11 to form a plurality of openings 31. In this step, the present invention is preferably selected by a coating liquid photoresist (Photoresist) or The photoresist layer 3 is formed by sticking a dry film, and the film is made of a self-negative photoresist or a positive photoresist. Next, the present invention performs a patterning process on the light and the layer 3 by a general exposure development method. To form a plurality of the openings 'the opening 31 corresponds to the position of the steel 塾 „, so that the thin metal layer 2 on the copper pad 11 can be exposed. Please refer to the fifth embodiment of the present invention as shown in the fifth and fifth versions. The fourth step of the copper plaque recording method of the wafer is: chemical thinning treatment of the thin metal layer 2 in the opening 31' to replace the thin metal layer 2 on the copper enamel with a tin layer 4. In this step, Preferably, the chemical immersion plating method is selected from the group consisting of a replaceable electro-recording method, in particular, Immersion Tin Process. The electro-mineral system of the chemical leaching treatment is preferably based on the tin-electric ore liquid. For example, tin chloride (SnCl2) plus the wrong agent (C〇mplexagent) of the electric mineral liquid' which is wrong Preferably, the agent may be selected from the group consisting of sulfur glands (ThiG_), whereby the tin layer 4 is deposited and formed by the gradual replacement of the copper of the metal layer 2 by the sub-limb of the electric napkin, and finally the μ 2 Copper will be completely replaced by tin replacement. It is worth noting that, as in the second: the part of the surface of the copper pad 11 of the wafer 1 may also be replaced by tin, thus forming a secret surface ΐη tightly bonding the tin layer 4. The height (thickness) of the tin layer 4 is preferably between ages _ silk (4) to (10) micro-objects m), especially between 微米 1 micrometer to 75 micrometers, most preferably between 1 micrometer and 1 micrometer. . Further, the material of the tin layer 4 may be selected from other materials, such as tin-silver alloy or tin-silver-copper alloy, in addition to tin. Please refer to FIG. 6 , the fifth step of the method for the surface of the copper pad of the wafer of the first embodiment of the present invention. The photoresist layer 3 is removed. In this step, the photoresist layer 3 can be removed by a conventional shirting method. When the photoresist layer 3 is selected from a photoresist dry film, it can also be directly removed. After the photoresist layer 3 is removed, the tin layer 4 and the thin metal layer 2 which is not shielded by the tin layer 4 are exposed. Referring to Fig. 7, the sixth step of the copper pad surface ❹ processing method of the wafer according to the first embodiment of the present invention is as follows: the metal thin layer 2 which is not shielded by the -04. In the present step, the preferred magnetic sputum of the present invention removes the copper of the thin metal layer 2 with a selective surname, but does not etch the tin layer 4. Furthermore, in another embodiment t of the present invention, another photoresist layer may be formed on the tin layer 4 as a shielding layer (not shown) by forming a photoresist, exposure, development, and the like, but The exposed metal that is not shielded by the tin layer 4 is thinned 2 to remove the copper of the thin metal layer 2 by the side liquid. Next, another photoresist layer on the tin layer 4 is removed by a developer. . With the above-mentioned first to sixth steps, the first embodiment of the present invention can form a tightly bonded tin layer 4' on the copper pad 11 of the wafer 1, and the tin layer 4 can be directly used as a small-sized convex. Piece. After the copper pad surface treatment method of the wafer of the first embodiment of the present invention is completed, the wafer 1 can be subsequently cut into a plurality of wafers (not shown), and the wafer can utilize the tin layer 4 (small-sized bumps) The medium is bonded to a substrate (not edged) to form a BGA or PGA package structure. Alternatively, after the Japanese yen 1 is cut into several wafers (not shown) on the 200939350, it is directly used as a csp package structure. Since the size of the bump defined by the kick layer 4 is relatively small, it is advantageous to further reduce the copper pad pitch, reduce the bump pitch, and improve the bump layout & degree in the unit area. (5) It also meets the requirements of the RqHS and other environmental protection laws for lead-free standards. Referring to Figures 1 to 5 and 8 to 11 of the present invention, the copper pad surface treatment side of the wafer according to the second embodiment of the present invention is similar to the first embodiment of the present invention, but the wafer of the second embodiment is The copper pad surface treatment method comprises the steps of: providing a wafer 1 ′ having a plurality of copper pads U on its surface; forming a thin metal layer 2 ′ on the surface of the wafer raft to electrically connect all the copper 塾 u to form a wafer The photoresist layer 3 is disposed on the thin metal layer 2 and conforms to the photoresist layer 3, and (4) the metal thin layer 2 on the steel 11 is exposed to the plurality of vents y; the metal thin layer in the opening 31 is chemically immersed in the opening 31 2, the metal thin layer 2 on the copper pad n is replaced by a tin layer 4; a solder layer 5 is formed on the port 31; the wire layer 3 is removed; and the metal layer not covered by the tin layer 4 is removed. Layer 2; and reflowing the solder layer 5 to form a metal bump 5. Compared to the first preferred embodiment, the second preferred embodiment preferably forms a thicker light. The resist layer 3 has a large space for the opening 31 of the photoresist layer 3, so that the solder layer 5 can be further formed after the tin layer 4 is formed. The tin layer 4 in the opening 31 is formed by printing, electrowinning or steaming, wherein the key mode can be selected from the group consisting of electric circuit recording 15 200939350 or electroless plating. The material of the solder layer 5 is preferably selected from the group consisting of a solder, such as tin, tin-silver alloy or tin-silver-copper alloy, and the material and melting point thereof may be the same or different from the material and melting point of the tin layer 4. The material of the solder layer 5 may still be selected from a lead-containing solder, such as a tin-stagger alloy, etc. The solder layer 5 is reflowed to form the metal bump 5, and the height (thickness) of the metal bump 5 is higher. Preferably controlled between 5 micrometers (um) and 300 micrometers (um), especially between 10 micrometers and 250 micrometers, preferably between 20 micrometers and 200 micrometers. Φ by the first to eighth steps described above In the second embodiment of the present invention, the tin layer 4 is tightly bonded on the copper pad 11 of the wafer 1, and the metal bump 5' is further formed by the tin layer 4. After the copper pad surface treatment method of the wafer of the second embodiment, the wafer defect can be subsequently cut into several crystals. A wafer (not shown) can be bonded to a substrate (not shown) by the metal bump 5' to form a BGA or PGA package structure. Alternatively, the wafer can be cut into a plurality of wafers ( It is not directly used as a Csp package structure. Since the tin layer 4 and the metal bump 5 still have a relatively small size, it is also advantageous for further reducing the copper pad pitch and reducing the convexity. Block spacing, and increase the density of the bump layout in the unit area. At the same time, it can also meet the requirements of the international environmental protection regulations such as weee for the error-free standard. The third paragraph of the present invention is shown in Figures 1 to 7 The copper pad surface treatment method of the wafer of the embodiment is similar to the first embodiment of the present invention, but the copper pad surface treatment method of the wafer of the second embodiment comprises the following steps: providing a 16 200939350 曰fMl ί ,β, The surface has a plurality of copper pads I; a thin metal layer 2 is formed on the surface of the wafer 1 to electrically connect all the copper pads η; forming a photoresist layer 3 on the metal thin layer 2' and pattern The photoresist layer 3 is formed to form a plurality of side ports 31 exposed a thin metal layer 2 on the pad 11; chemical thinning treatment of the thin metal layer 2 in the opening 31' to replace the thin metal layer 2 of the copper pad with a tin layer 4, removing the layer 3, removing the untreated layer _ tin layer 4 shaded metal thin layer 2; form another light
θ 6於該Baj|} ί上’雌案傾光阻層6，以形成數個開口 裸露該銅塾11上'錫層4;在該開口 61内形成—銲料層7; “I光阻層^，以尋，對該_料層7進行回焊，以形成數個 金屬凸.塊7,..。. 相較於該第-較佳實施例，該第三較佳實施例係進一步在 本發明第-實施例之第六步驟後增加第七至第十步驟，以形成 較厚之該光阻層6，使該光闕6提供數個開口 &，以便進一 步在該錫層4上形成轉料層7。本發明係可選擇藉由塗佈液 態光阻或黏貼乾膜而形成該光阻層卜再者該轉層7係可 選用印刷、電賴驗等方式形成在關口 61内之錫層4上， 其中該駿方式可選自有電魏(d吻plating)或無電静 (咖福eSS_ng财式。該銲料層7較佳選自論焊料例 如錫、錫銀合金或錫銀銅合金等，且其材質及麟可相同或相 異於該錫層4讀歧魅。惟，依實際絲，該銲料層7之 材質仍可選自含鉛焊料，例如·合鱗。鱗制7經回焊 17 200939350 ▲ 後職該金屬凸塊7’ ’該金屬凸塊7,之高度(厚度)較健制在 . 10微米(11111)至300微米(um)之間，特別是在20微米至250微 米之間，最佳是在30微米至200微米之間。 藉由上述第一至第十步驟，本發明第三實施例即可在該晶 圓1之銅墊11上形成緊岔結合之該錫層4，並藉由該錫層4 進一步形成該金屬凸塊7，。在完成本發明第三實施例之晶圓之 銅塾表面處理方法後’接著可將該晶圓i切割成數個晶片（未 © 繪示）’該晶片可利用該金屬凸塊7’媒介結合至一基板(未繪示） 上，進而構成一 BGA或PGA封裝構造。或者，在該晶圓！ 切割成數個晶片（未繪示)後，隨即直接使用做為一 Csp封裝構 造。由於該錫層4及金屬凸塊7,仍具相對較小之尺寸，故亦有 利於進一步縮減銅墊間距、降低凸塊間距，及提高單位面積中 之凸塊佈局密度。同時，亦能符合r〇Hs及WEEE等國際環 保法規對無鉛標準的妻求。 G 如上所述，相較於習用凸塊底金屬層(UBM)因金屬冶金相 容性問題而不再完全適用於下一世代的晶圓銅墊上，且由凸塊 底金屬層長出之凸塊亦具有凸塊尺寸過大等缺點，第7、u及 16圖之本發明藉由先在該晶圓丨上暫時全面性形成該金屬薄 層2’接著再將該金屬薄層2進一步化學浸鍍置換成該錫層4， 因而使該錫層4直接緊密結合至該晶圓丨之銅墊u表面上， 其確實可有效簡化凸塊製程、降低製程成本、增加凸塊結合強 18 200939350 • 度、降低凸額距、提高凸塊佈局密度及符合環保法規無錯標 準。 ^ » 雖然本伽已以較佳實施例揭露，财並_以限制本發 明’任何熟習此項技藝之人士，在不脫離本發明之精神和範圍 内’當可作各種更動與修飾，因此本發明之保護範圍當視後附 之申請專利範圍所界定者為準。 q 【圖式簡單說明】 第1圖：本發明第一實施例之晶圓之銅墊表面處理方法第一步 驟之示意圖。 第2圖.本發明第一實施例之晶圓之銅塾表面處理方法第一步 驟之示意圖。 第3及4圖：本發明第一實施例之晶圓之銅墊表面處理方法第 三步驟之示意圖。 0 第5及5A圖：本發明第一實施例之晶圓之銅墊表面處理方法 第四步驟之示意圖及局部放大圖。 第6圖：本發明第一實施例之晶圓之銅墊表面處理方法第五步 驟之示意圖。 第7圖：本發明第一實施例之晶圓之銅墊表面處理方法第六步 驟之示意圖。 第8、9、10及11圖··本發明第二實施例之晶圓之銅墊表面處 理方法第五至第八步部之示意圖。 19 200939350 第12、13、14、15及16圖：本發明第三實施例之晶圓之銅墊 表面處理方法第七至第十步驟之示意圖。 【主要元件符號說明】 1 晶圓 11 銅墊 111 粗糖面 12 保護層 2 金屬薄層 3 光阻層 31 開口 4 錫層 5 銲料層 5, 金屬凸塊 6 光阻層 61 開口 7 銲料層 7, 金屬凸塊 ❹ 20θ 6 on the Baj|} ' 'female tilting photoresist layer 6 to form a plurality of openings to expose the 't tin layer 4 on the copper plaque 11; forming a solder layer 7 in the opening 61; "I photoresist layer For retrieving, the layer 7 is reflowed to form a plurality of metal bumps. The seventh preferred embodiment is further in comparison with the first preferred embodiment. The seventh step to the tenth step are added after the sixth step of the first embodiment of the present invention to form a thicker photoresist layer 6, so that the aperture 6 provides a plurality of openings & for further on the tin layer 4. The transfer layer 7 is formed. In the present invention, the photoresist layer can be formed by coating a liquid photoresist or a dry film, and the layer 7 can be formed in the gate 61 by printing, electric inspection or the like. On the tin layer 4, the manner of the spring may be selected from the group consisting of electric solder (d kiss plating) or no electric static (the solder layer 7 is preferably selected from solders such as tin, tin silver alloy or tin silver). Copper alloy, etc., and the material and the lining may be the same or different from the tin layer 4. However, depending on the actual wire, the material of the solder layer 7 may still be selected from lead-containing solder, for example, scales. 7 reflowed 17 200939350 ▲ After the metal bump 7' 'the metal bump 7, the height (thickness) is more robust between 10 microns (11111) to 300 microns (um), especially at 20 Between micrometers and 250 micrometers, preferably between 30 micrometers and 200 micrometers. With the first to tenth steps described above, the third embodiment of the present invention can form a closeness on the copper pad 11 of the wafer 1. The tin layer 4 is bonded, and the metal bump 7 is further formed by the tin layer 4. After the copper beryllium surface treatment method of the wafer of the third embodiment of the present invention is completed, the wafer i can be subsequently cut. A plurality of wafers (not shown) can be bonded to a substrate (not shown) by using the metal bumps 7' to form a BGA or PGA package structure. Alternatively, the wafer can be cut into several numbers. After the wafer (not shown), it is directly used as a Csp package structure. Since the tin layer 4 and the metal bump 7 still have a relatively small size, it is also advantageous for further reducing the copper pad pitch and reducing the convexity. Block spacing, and increase the bump layout density per unit area. At the same time, it can also meet r〇Hs and W International environmental regulations such as EEE are for the lead-free standard. G As mentioned above, compared to the conventional bump metallization layer (UBM), it is no longer fully applicable to the next generation of wafer copper pads due to metal metallurgical compatibility problems. And the bumps which are grown by the bottom metal layer of the bump also have the disadvantages that the bump size is too large, and the invention of the seventh, u and 16 forms the thin metal layer 2 by temporarily forming the metal layer on the wafer stack. 'The metal thin layer 2 is further chemically etched and replaced with the tin layer 4, so that the tin layer 4 is directly and tightly bonded to the surface of the copper pad u of the wafer, which can effectively simplify the bump process, Reduce process costs, increase the strength of bumps and joints, reduce the crown distance, increase the density of bump layout, and comply with environmental standards. ^ 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本The scope of the invention is defined by the scope of the appended claims. q [Simple description of the drawings] Fig. 1 is a schematic view showing the first step of the surface treatment method for the copper pad of the wafer according to the first embodiment of the present invention. Fig. 2 is a schematic view showing the first step of the method for treating the matte surface of the wafer of the first embodiment of the present invention. 3 and 4 are schematic views showing the third step of the surface treatment method for the copper pad of the wafer according to the first embodiment of the present invention. 0 and 5A are diagrams showing a fourth step of the method for processing the copper pad of the wafer according to the first embodiment of the present invention and a partial enlarged view. Fig. 6 is a view showing the fifth step of the surface treatment method for the copper pad of the wafer according to the first embodiment of the present invention. Fig. 7 is a view showing the sixth step of the surface treatment method for the copper pad of the wafer according to the first embodiment of the present invention. Figs. 8, 9, 10 and 11 are schematic views showing the fifth to eighth steps of the copper pad surface treatment method of the wafer according to the second embodiment of the present invention. 19 200939350 Figures 12, 13, 14, 15 and 16 are schematic views of the seventh to tenth steps of the copper pad surface treatment method of the third embodiment of the present invention. [Main component symbol description] 1 wafer 11 copper pad 111 coarse sugar surface 12 protective layer 2 metal thin layer 3 photoresist layer 31 opening 4 tin layer 5 solder layer 5, metal bump 6 photoresist layer 61 opening 7 solder layer 7, Metal bumps ❹ 20