200939183 TW 24449twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種信號相位校正，且特別是有關於 一種相位校正電路以及内嵌該相位校正電路之顯示驅動 器。 【先前技術】 一般會隨著製程、環境、經過路徑的不同等等因素產 φ 生不同的信號偏移。信號偏移會衍生出設定時間（setup time)與保持時間（holdtime)問題。圖丨八是說明信號路 徑。圖1B是說明圖1A中信號時序關係。請同時參照圖 1A與圖1B，信號源（發送器11〇)透過信號路徑將 信號（時脈CLK10與資料D10 )傳送給接收器13〇。因此， 接收器130可以依據所接收之時脈CLK1〇與資料D1〇，而 輸出對應之時脈CLK11與資料D11給下一級電路（未繪 示）。 時脈CLK10與資料D10在傳輸過程中可能會使信號 ® 2移。圖1B是說明資料D11的傳輸發生信號偏移，使得 貝料mi之轉態時間點相當接近時脈CLKU之上升緣。 =時脈clkii之上升緣出現在資料D11傳輸所需的設 間内，因此下一級電路(未繪示)將在時脈（^反11之上 =緣錯誤地取樣了資料D11，此即為設定時間問題。另外， 右在時脈CLK11上升緣後的保持時間不夠長，將會導致保 持時間問題。 5 TW 24449twf.doc/n 200939183 圖2A是說明利用固定延遲緩衝器來修正信號偏移之 傳統系統方塊圖。圖2B是說明圖2A中信號時序關係。具 有固定延遲時間之延遲緩衝器240被用來延遲時脈CLKll 之時序而產生時脈CLK12，以消除信號偏移的問題。然 而，固定的延遲緩衝器無法隨著製程變異與電壓等等變因 而彈性修正信號的偏移。 【發明内容】 本發明提供-種相位校正電路，可以自我_隨製程 變異與工作電壓變化，彈性選擇所需要延遲時間，以將晶 片内部數位信號的延遲偏移所造成的設定時間“Mu time )與保持時間（h〇id time )問題予以修正。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal phase correction, and more particularly to a phase correction circuit and a display driver in which the phase correction circuit is embedded. [Prior Art] Generally, different signal offsets are generated depending on factors such as process, environment, and path. Signal offsets can cause problems with setup time and holdtime. Figure VIII shows the signal path. Figure 1B is a diagram showing the timing relationship of signals in Figure 1A. Referring to FIG. 1A and FIG. 1B simultaneously, the signal source (transmitter 11A) transmits the signal (clock CLK10 and data D10) to the receiver 13A through the signal path. Therefore, the receiver 130 can output the corresponding clock CLK11 and the data D11 to the next stage circuit (not shown) according to the received clock CLK1 〇 and the data D1 。. Clock CLK10 and data D10 may shift signal ® 2 during transmission. Fig. 1B is a diagram showing the signal shift of the transmission of the data D11, so that the transition time point of the material mi is quite close to the rising edge of the clock CLKU. = The rising edge of the clock clkii appears in the setup required for the data D11 transmission, so the next level circuit (not shown) will sample the data D11 incorrectly on the clock (^反11 = edge). Set the time problem. In addition, the hold time after the rising edge of the clock CLK11 is not long enough, which will cause the hold time problem. 5 TW 24449twf.doc/n 200939183 Figure 2A illustrates the use of a fixed delay buffer to correct the signal offset. The conventional system block diagram. Fig. 2B is a diagram illustrating the timing relationship of the signal in Fig. 2A. The delay buffer 240 having a fixed delay time is used to delay the timing of the clock CLK11 to generate the clock CLK12 to eliminate the problem of signal offset. The fixed delay buffer cannot elastically correct the offset of the signal as the process variation and the voltage change. [Invention] The present invention provides a phase correction circuit that can self-select with process variation and operating voltage variation, and elastic selection. A delay time is required to correct the set time "Mu time" and the hold time (h〇id time) caused by the delay offset of the internal digital signal of the wafer.
、本發明提供一種顯示驅動器，内後相位校正電路，可 =隨製程變異與卫作電壓變化彈性地選擇所需要延遲 間，以將接收器的延遲偏移予以修正。 為解決上述問題，本發明提出一種相位校正電路 3校it:相位校正電路包括樣本產生器、相位調 生i n⑪暫存早70、檢測單元以及最佳化單元。樣本產 接樣本以及資料樣本給目標電路。相_整器 料調整時;與^ 調ΪΪ ’Hi資料。旋轉暫存單元提供控制資料給相位 相位ί預定時序改變控制資料。檢測單元耦接至 位關Π輸出用 ^、，〇果。取佳化單元耦接至檢測單元與 6 200939183 TW 24449twf.doc/n 用以依據檢測結果，紀錄該旋轉暫存單元 =====料，以從中擇—做為校正控制資料， ^校正控制#料給相位調整器。 正電路麵示驅動器，包括接收器以及相位校 收外部所提供之信號。相位校正電路内 不鶴器，用以嫌接收ϋ。相位校JE電路包括樣 o :整器、旋轉暫存單元、檢測單元以及最 Γ位調整產收生 === 與 ，料給相位調整器，並依據預定時序改供 :測:元難相位調整器，用以檢測第二==資 : 係’以輸出檢測結果。最佳:單:輕 接至檢測皁兀與旋轉暫存單元，用以依 :暫存單元所輸出之各種控制資料，以從中擇 並且㈣_暫存單元輸出校正控制資料給相 本發明相位校正電路利用洛屯丨s % 出，並依據檢測結果祕選擇所需要延遲_ 之^ 以動祕正因延遲偏移所造成的設定時間與保持時 為讓本發明之上述特徵和優點能更明顯易懂 舉較佳實關’並配合所關式，作詳細朗如下。、 7 200939183 Γλν 24449twf.doc/n 【實施方式】 圖3是依照本發明實施例說明一種内嵌有相位校正電 路之積體電路方塊圖。在此是以顯示驅動器300代表說明 内喪有相位校正電路之積體電路。顯示驅動器300包含介 面電路(interface circuit) 310 以及通道(channel) 340，以接 收來自發送器200的信號’並且驅動顯示面板(未繪示）。 介面電路310包括接收器320以及相位校正電路 330。舉例來說’接收器32〇利用低擺幅差動訊號傳輸 (reduced swing differential signaling，RSDS)或是其他信 號傳輸介面接收來自發送器200的信號。若有需要，接收 器320亦將所接收之信號格式轉換為顯示驅動器3〇〇内部 之佗號格式。相位校正電路330包括樣本產生器331、副 本接收器（replicate receiver) 336、副本相位調整器(repiicate phase adjuster) 332、相位調整器337、旋轉暫存單元335、 檢測單元333以及最佳化單元334。相位校正電路330接 收目標電路(例如接收器320)所輸出之時脈與資料，並調整 時蜂與資料二者之間的相位關係，以輸出經調整後的時脈 與資料給下一級電路（例如通道340)。 副本接收器336之電路設計可以和接收器32〇相同， 而副本相位調整器332二者之電路設計可以與相位調整器 337相同。由於副本接收器336和接收器32〇均配置在顯 示驅動器300内，亦即二者是由相同.製程所製造出來的， 因此二者之特性（包含信號之延遲偏移）幾乎相同。換句 200939183 rw 24449twf.doc/n 話說田|J本接收器336與副本相位調整器332可以分別視 為接收器320與相位調整器337之副本。 在板正階段，樣本產生器331產生時脈樣本以及資料 樣本^本接收器336。副本接收器Μ6便依據時脈樣本 収資料樣本而輸出第—時脈與第_#料給副本相位調整 器。副本相位調整器3幻依旋轉暫存單元335所提供 ，控制資料調整第一時脈與第一資料二者之間的相位關 ❹ ^以輸出第二時脈與第二資料。旋轉暫存單元335依據 預疋B夺序產生控制資料，並且提供控制資料給副本相位調 整器33^與相位調整器337。檢測單元333雛至副本相 位調整斋332。檢測單元333檢測第二時脈與第二資料二 者之間的相位關係，以輸出檢測結果。最佳化單元334耦 接至檢測單元333與旋轉暫存單元奶。依據檢測單元姐 之檢測結果，最佳化單元334紀錄旋轉暫存單元335所輸 出之各種控制資料，以從中擇一做為校正控制資料，並乂 ，制旋轉暫存單元335輸出校正控制資料給副本相位調整 器332與相位調整器337。相位校正電路33〇之詳細實 方式容後詳述。 '' 要注意的是’内嵌有相位校正電路的積體電路之實施 =式並不限於上述實施例。例如，圖4是依照本發明另一 ^施例說明内嵌有相位校正電路之積體電路方塊圖。在此 是以顯示驅動器400代表說明内嵌有相位校正電路之積體 電路。顯示驅動器400包括介面電路410以及通道44〇 , 9 200939183 TW 24449twf.doc/n 以接收來自發送器200的信號，並且驅動顯示面板(未绔 示）。 曰 ❹ 參 介面電路410包括接收器420以及相位校正電路 430。舉例來說，接收器420利用RSDS或是其他信號傳輸 介面接收來自發送器200的信號。若有需要，接收器42〇 亦了以將所接收之#號格式轉換為顯示驅動器内部所 需之其他信號格式。相位校正電路43〇内嵌於顯示驅動哭 4〇〇,用以調校目標電路(例如接收器420)。相位校正電ς 430包括樣本產生器431、相位調整器432、旋轉暫存單元 435、檢測單元433以及最佳化單元434。在顯示驅動器4〇〇 内部，相位校正電路430接收接收器42〇所輸出之時脈盥 貧料，並婦時脈與資料二者之_相位關係，以輸出經 調整後的時脈與資料給下一級電路（例如通道44〇)。 在校正階段，選擇器436將會輸出樣本產生器431所 產生的時脈樣本以及資料樣本給接收器420。接收器42〇 便依據時脈樣本以及資料樣本*輸出第—時脈與第一資料 ^相^調整器432。相位調整器432接收接收器420所輪 出之第—時脈與第-資料，並依旋轉暫存單元奶所提供 :控制；料調整第-時脈與第-資料二者之間的相位關 箱出第二時脈與第二資料。旋轉暫存單元435依據 仏、改變控㈣料，並且提健师料給相位調整器 拾前Λ單元433祕至相位調整器432。檢測單元433 測^果*7,與ϊί*資料二者之間的相位關係，以輸出檢 ’、、、°攻佳化單兀434耦接至檢測單元433與旋轉暫存 rw 24449twf.doc/nThe present invention provides a display driver, an internal post-phase correction circuit that can flexibly select the required delay with process variation and servo voltage variation to correct the delay offset of the receiver. In order to solve the above problems, the present invention proposes a phase correction circuit 3: the phase correction circuit includes a sample generator, a phase adjustment i n11 temporary storage 70, a detection unit, and an optimization unit. The sample is sampled and the data sample is given to the target circuit. Phase _ 器 ’ Hi data adjustment. The rotation temporary storage unit provides control data to the phase phase ί predetermined timing change control data. The detection unit is coupled to the position and output with ^, and the result. The optimisation unit is coupled to the detection unit and 6 200939183 TW 24449twf.doc/n for recording the rotation temporary storage unit ===== according to the detection result, to select from - as the correction control data, ^ correction control #料给相调调器. The positive circuit displays the driver, including the receiver and the signal provided by the phase to the outside of the phase. In the phase correction circuit, there is no crane to use it. The phase calibration JE circuit includes the sample o: the whole device, the rotary temporary storage unit, the detection unit, and the most clamped adjustment production and output === and the material is supplied to the phase adjuster, and is supplied according to the predetermined timing: measurement: meta difficulty phase adjustment For detecting the second == capital: system ' to output the detection result. The best: single: lightly connected to the detection saponin and rotary temporary storage unit, according to: the various control data output by the temporary storage unit, to select from and (4) _ temporary storage unit output correction control data to the phase correction circuit of the invention Use the 屯丨 % % out, and select the required delay according to the detection result. The set time and the retention time caused by the delay offset are more obvious and easy to understand. Let's take a better look and use the details. 7 200939183 Γλν 24449twf.doc/n [Embodiment] FIG. 3 is a block diagram showing an integrated circuit in which a phase correction circuit is embedded in accordance with an embodiment of the present invention. Here, the display driver 300 represents an integrated circuit in which a phase correction circuit is described. The display driver 300 includes an interface circuit 310 and a channel 340 to receive a signal ' from the transmitter 200' and drive a display panel (not shown). The interface circuit 310 includes a receiver 320 and a phase correction circuit 330. For example, the receiver 32 receives the signal from the transmitter 200 using reduced swing differential signaling (RSDS) or other signal transmission interface. Receiver 320 also converts the received signal format to an apostrophe format within display driver 3, if desired. The phase correction circuit 330 includes a sample generator 331, a replica receiver 336, a rephasing phase adjuster 332, a phase adjuster 337, a rotation temporary storage unit 335, a detection unit 333, and an optimization unit 334. . The phase correction circuit 330 receives the clock and data output by the target circuit (for example, the receiver 320), and adjusts the phase relationship between the bee and the data to output the adjusted clock and data to the next-stage circuit ( For example, channel 340). The circuit design of replica receiver 336 can be the same as receiver 32, and the circuit design of both replica phase adjuster 332 can be the same as phase adjuster 337. Since the replica receiver 336 and the receiver 32 are both disposed in the display driver 300, i.e., both are manufactured by the same process, the characteristics of the two, including the delay offset of the signals, are almost the same. In other words, 200939183 rw 24449twf.doc/n The field receiver 336 and the replica phase adjuster 332 can be regarded as replicas of the receiver 320 and the phase adjuster 337, respectively. In the positive phase of the board, the sample generator 331 generates a clock sample and a data sample receiver 336. The replica receiver Μ6 outputs the first-time clock and the _# material to the replica phase adjuster according to the time-sample sample. The copy phase adjuster 3 is provided by the magic rotation register unit 335, and the control data adjusts the phase relationship between the first clock and the first data to output the second clock and the second data. The rotation temporary storage unit 335 generates control data in accordance with the pre-order B reorder, and supplies control data to the replica phase adjuster 33 and the phase adjuster 337. The detecting unit 333 is adapted to the copy phase adjustment 332. The detecting unit 333 detects a phase relationship between the second clock and the second data to output a detection result. The optimization unit 334 is coupled to the detection unit 333 and the rotary temporary storage unit milk. According to the detection result of the detecting unit sister, the optimizing unit 334 records various control data output by the rotation temporary storage unit 335 to select one as the correction control data, and the rotation temporary storage unit 335 outputs the correction control data to Copy phase adjuster 332 and phase adjuster 337. The detailed embodiment of the phase correction circuit 33 is described in detail later. '' It is to be noted that the implementation of the integrated circuit in which the phase correction circuit is embedded is not limited to the above embodiment. For example, FIG. 4 is a block diagram showing an integrated circuit in which a phase correction circuit is embedded in accordance with another embodiment of the present invention. Here, the integrated circuit in which the phase correction circuit is embedded is represented by the display driver 400. The display driver 400 includes an interface circuit 410 and a channel 44, 9 200939183 TW 24449twf.doc/n to receive signals from the transmitter 200 and to drive a display panel (not shown). The interface circuit 410 includes a receiver 420 and a phase correction circuit 430. For example, receiver 420 receives signals from transmitter 200 using RSDS or other signal transmission interfaces. If desired, the receiver 42 is also operative to convert the received ## format to other signal formats required within the display driver. The phase correction circuit 43 is embedded in the display drive to adjust the target circuit (e.g., receiver 420). The phase correction power 430 includes a sample generator 431, a phase adjuster 432, a rotation temporary storage unit 435, a detection unit 433, and an optimization unit 434. Inside the display driver 4, the phase correction circuit 430 receives the clock-depleted material outputted by the receiver 42 and the phase relationship between the clock and the data to output the adjusted clock and data. The next level of circuitry (such as channel 44〇). During the correction phase, the selector 436 will output the clock samples generated by the sample generator 431 and the data samples to the receiver 420. The receiver 42 outputs the first-time clock and the first data ^ adjuster 432 according to the clock sample and the data sample *. The phase adjuster 432 receives the first-clock and the first data that the receiver 420 rotates, and provides the control according to the rotation of the temporary storage unit milk: control; adjusts the phase relationship between the first-clock and the first-data The second clock and the second data are out of the box. The rotation temporary storage unit 435 changes the control (four) material according to 仏, and the controller supplies the phase adjuster to the front stage unit 433 to the phase adjuster 432. The detecting unit 433 measures the phase relationship between the data *7 and the data, and outputs the detection ', , , and the attack unit 434 to the detecting unit 433 and the rotating temporary storage rw 24449twf.doc/ n
200939183 據檢測單元Μ3之檢測結果，最佳化單元糾 一做為所輸出之各種控制資料，以從中擇 正=;==制旋轉暫存單元4_校 才目,校正電路330及/或43〇的操作將以圖5說明之。 ^之相位校正電路用以調校目標電路52〇。以圖3之實 言杳目標電路520可以視為圖3之副本接收器说。 ，之只施例而言’目標電路52〇可以視為圖4之接收 器 420 〇 ▲請參照® 5,此相位校正電路包括樣本產生器531、相 整器532、檢測單元533、最佳化單元534卩及旋轉暫 存單元奶’其可以分別視為圖3之樣本產生器别、副本 相位，整器332、檢測單元333、最佳化單元334以及旋轉 暫存單元335 ’也可以分別視為圖4之樣本產生器43卜相 位調整器432、檢測單元433、最佳化單元434以及旋轉暫 存單元435。 口圖6是依照本發明實施例說明圖5相位校正電路之信 唬時序圖。請同時參照圖5與圖6，樣本產生器531產生 時脈樣本rs__clk以及資料樣本rs_data給目標電路52〇。時 脈樣本rs—elk以及資料樣本rs一data經過目標電路520内部 之“號路徑後，可能會使時脈樣本rs—clk及/或資料樣本 fs__data發生信號偏移。 方疋轉暫存單元535 &供控制資料DC_con[n:l]給相位 調整器532，並依據預定時序改變控制資料DC_con[n:1]。 24449twf.doc/n 200939183 例如，假設n=6 (即控制資料DC—con[n:l]有6位元），則 旋轉暫存單元535可以依序輸出控制資料DC_con[n:l]為 000001b、000010b、000100b、001000b、010000b、100000b、 000001b、000010b、…等。若以10進位表示，則控制資料 DC_con[n:l]依據預定時序改變為卜2、4、8、16、32、1、 2 ' ° 相位調整器532可以接收目標電路520所輸出之第一 ❹ 時脈test_clk與第一資料test_data，並依控制資料 DC_con[n: 1]調整第一時脈 test_clk 與第一資料 test__data 二 者之間的相位關係，以輸出第二時脈clk__delay與第二資料 data—delay。在一實施例中，假設相位調整器532不改變第 一時脈 test_clk 之相位（亦即 test_clk = clk_delay )，且依 控制資料DC—con[n: 1 ]調整第一資料test_data之相位來做 為第二資料data—delay。若控制資料DC_con[n:l] = 1，則 相位調整器532所輸出之第二資料data_delay譬如為圖6 之波形data—delay⑴，若控制資料DC—con[n:l] = 2 (即 O 〇〇〇〇l〇b)，則相位調整器532所輸出之第二資料data_delay 譬如為圖6之波形data_delay(2)。以此類推，若控制資料 DC_con[n:l] = 32 (即l〇〇〇〇〇b)，則相位調整器532所輸 出之第二資料data一 delay譬如為圖 ό之波形 data—delay(32)。 檢測單元533耦接至相位調整器532以便接收第二時 脈elk—delay與第二資料data_delay。檢測單元533檢測第 二時脈elk一delay與第二資料data—delay二者之間的相位關 12 200939183 TW 24449twf.doc/n 係，以輸出檢測結果detect—result。在此假設檢測單元533 是依據第二時脈Clk一delay (本實施例中等同於第一時脈 test—elk之相位）之上升緣來取樣第二資料data—dday。因 此’若控制資料DC_con[n:l] = 2，則檢測單元533所取樣 之第二資料data—delay (即圖6之波形data—delay(2))為 「〇」，若控制資料DC—con[n:l] = 8，則檢測單元533所 取樣之第二資料data一delay (即圖6之波形data_delay(8)) ❹ 為「lj。依據樣本產生器531所產生之時脈樣本rs_clk 以及資料樣本rs—data二者之相位關係，檢測單元533所取 樣之第二資料data_cielay理應為「1」。因此檢測單元533 了以依據所取樣之第二資料data_delay來判斷相位調整器 532之調整結果是否適當，並依據上述判斷輸出檢測結果 detect—result。 最佳化單元534耦接至檢測單元533與旋轉暫存單元 535，用以依據檢測結果detect—resuit，紀錄旋轉暫存單元 535所輸出之各種控制資料Dc__c〇n[n:l]，以從中擇一做為 © 校正控制資料，並且控制旋轉暫存單元535輸出此一校正 控制^料給相位調整器532。例如，旋轉暫存單元535所 輸出之控制資料DC—con[n:l]依循1、2、4、8、16、32、1、 2.··之次序不斷變換。最佳化單元534透過檢測結果 detect—result可以判斷出當控制資料DC—con[n:l]為4、8、 16時’相位調整器532之調整結果是適當的。因此，最佳 化單元534可以從4、8、16中擇一做為校正控制資料（例 如選擇中間值「8」），並且藉由信號〇ptimal_signal控制 13 200939183 rw 24449twf.doc/n 旋轉暫存單元535輪出校正控制資料「8」（即DC_con[n:l] 001000b)給相位調整器532。因此，相位調整器532可 以依校正㈣資料「8」（控職料沉—⑽㈣）調整目 標電路520所輸出之第一時脈池與第一資料㈣―她 二者之間的相位關係，以輸出第二時脈dk—制町盘第二資 料她-她〆參照圖6之與data delay⑻之波形）'。 圖7A是依照本發明說明圖5中樣本產生器531之實 施範例。樣本產生器531可以包括器71〇、樣本單元 720以及差一動介面單元73〇。振i器71〇提供時脈樣本池 給樣本早％ 72〇。樣本單元72G依射脈樣本g—池輸出時 脈樣本P_clk與資料樣本p_data給差動介面單元73〇。差 ^面單元730將樣本單元，所輸出_雜本p—他 〃、二料樣本p_data轉換成時脈樣本rs—以及資料樣 rs—data。在此樣本單元72〇可能包含延遲器π。、此實施200939183 According to the detection result of the detecting unit Μ3, the optimization unit corrects as various output control data to select from the positive ==== system to rotate the temporary storage unit 4_ calibration, correction circuit 330 and/or 43 The operation of 〇 will be illustrated in Figure 5. The phase correction circuit is used to calibrate the target circuit 52A. In the actual state of Figure 3, the target circuit 520 can be considered as the replica receiver of Figure 3. For example, the 'target circuit 52' can be regarded as the receiver 420 of FIG. 4 〇 ▲ please refer to the ® 5, the phase correction circuit includes the sample generator 531, the phase sequencer 532, the detection unit 533, and optimization. The unit 534 and the rotating temporary storage unit milk can be regarded as the sample generator, the copy phase, the whole device 332, the detecting unit 333, the optimizing unit 334, and the rotating temporary storage unit 335' of FIG. 3, respectively. The sample generator 43 of FIG. 4 includes a phase adjuster 432, a detection unit 433, an optimization unit 434, and a rotation temporary storage unit 435. Port 6 is a timing chart illustrating the phase correction circuit of Fig. 5 in accordance with an embodiment of the present invention. Referring to FIG. 5 and FIG. 6, the sample generator 531 generates the clock sample rs__clk and the data sample rs_data to the target circuit 52A. After the clock sample rs_elk and the data sample rs_data pass through the "number path" inside the target circuit 520, the clock sample rs_clk and/or the data sample fs__data may be signal-shifted. & control data DC_con[n:l] is given to the phase adjuster 532, and the control data DC_con[n:1] is changed according to a predetermined timing. 24449twf.doc/n 200939183 For example, suppose n=6 (ie, control data DC-con [n:l] has 6 bits), then the rotation temporary storage unit 535 can sequentially output the control data DC_con[n:l] to 000001b, 000010b, 000100b, 001000b, 010000b, 100000b, 000001b, 000010b, ..., etc. In the case of 10 bits, the control data DC_con[n:l] is changed to 2, 4, 8, 16, 32, 1, 2 '° according to a predetermined timing. The phase adjuster 532 can receive the first output of the target circuit 520. The clock test_clk and the first data test_data, and according to the control data DC_con[n: 1] adjust the phase relationship between the first clock test_clk and the first data test__data to output the second clock clk__delay and the second data data -delay. In one embodiment, the phase is assumed The whole device 532 does not change the phase of the first clock test_clk (ie, test_clk = clk_delay), and adjusts the phase of the first data test_data according to the control data DC_con[n: 1 ] as the second data data-delay. The control data DC_con[n:l] = 1, the second data data_delay output by the phase adjuster 532 is as the waveform data_delay(1) of FIG. 6, if the control data DC_con[n:l] = 2 (ie O 〇 〇〇〇l〇b), the second data data_delay output by the phase adjuster 532 is, for example, the waveform data_delay(2) of Fig. 6. By analogy, if the control data DC_con[n:l] = 32 (ie, l〇 〇〇〇〇b), the second data data-delay outputted by the phase adjuster 532 is as the waveform data_delay (32). The detecting unit 533 is coupled to the phase adjuster 532 to receive the second clock. The elk_delay and the second data data_delay. The detecting unit 533 detects a phase relationship between the second clock elk-delay and the second data data-delay 12 200939183 TW 24449twf.doc/n, to output a detection result detect- Result. It is assumed here that the detecting unit 533 samples the second data data_dday according to the rising edge of the second clock Clk_delay (the phase equivalent to the first clock test_elk in this embodiment). Therefore, if the control data DC_con[n:l] = 2, the second data data_delay (i.e., the waveform data_delay(2) of Fig. 6) sampled by the detecting unit 533 is "〇", if the control data DC- Con[n:l] = 8, the second data data-delay sampled by the detecting unit 533 (ie, the waveform data_delay(8) of FIG. 6) ❹ is “lj. The clock sample rs_clk generated according to the sample generator 531. And the phase relationship between the data samples rs_data, and the second data data_cielay sampled by the detecting unit 533 is supposed to be "1". Therefore, the detecting unit 533 determines whether the adjustment result of the phase adjuster 532 is appropriate according to the sampled second data data_delay, and outputs a detection result detect_result according to the above judgment. The optimization unit 534 is coupled to the detection unit 533 and the rotation temporary storage unit 535 for recording the various control data Dc__c〇n[n:l] output by the rotation temporary storage unit 535 according to the detection result detect_resuit. Alternatively, the correction control data is used, and the control rotation register unit 535 outputs the correction control to the phase adjuster 532. For example, the control data DC_con[n:l] output by the rotation temporary storage unit 535 is continuously changed in the order of 1, 2, 4, 8, 16, 32, 1, 2.. The optimization unit 534 can determine through the detection result detect_result that the adjustment result of the phase adjuster 532 is appropriate when the control data DC_con[n:l] is 4, 8, or 16. Therefore, the optimization unit 534 can select one of the 4, 8, and 16 as the correction control data (for example, select the intermediate value "8"), and control the signal by the signal 〇ptimal_signal 13 200939183 rw 24449twf.doc/n The unit 535 rotates the correction control data "8" (i.e., DC_con[n:l] 001000b) to the phase adjuster 532. Therefore, the phase adjuster 532 can adjust the phase relationship between the first clock pool outputted by the target circuit 520 and the first data (four) and her according to the corrected (4) data "8" (the control device sinks - (10) (4)). Output the second clock dk - the second information of the system - she - she will refer to Figure 6 and the data delay (8) waveform) '. Figure 7A is a diagram showing an exemplary embodiment of the sample generator 531 of Figure 5 in accordance with the present invention. The sample generator 531 may include a device 71, a sample unit 720, and a difference-motion interface unit 73. The vibrator 71 provides the clock sample pool to the sample as early as 72 〇. The sample unit 72G outputs the clock sample P_clk and the data sample p_data to the differential interface unit 73 according to the pulse sample g-pool. The difference face unit 730 converts the sample unit, the output_mixed p-the other, the two-sample p_data into the clock sample rs- and the data sample rs-data. The sample unit 72〇 may contain a delay π. This implementation
It太樣本單元720是將時脈樣本o'cik直接輸出做為時 ’細㈣雜本G_dk触㈣請 貝料樣本p_data。 然而，樣本單元720的實施方式並不限於此。例如， 圖7B是依照本發明說明圖5中樣本產生器531之另—The It too sample unit 720 uses the clock sample o'cik as the direct output as the 'fine (four) miscellaneous G_dk touch (four) please the sample p_data. However, the embodiment of the sample unit 720 is not limited thereto. For example, FIG. 7B illustrates another example of the sample generator 531 of FIG. 5 in accordance with the present invention.
=例。在此實施例中，樣本單元72〇可能包Z 22。樣本單元72〇是將時脈樣本。—dk直接輸出做為= ^本p—data，並且將時脈樣本〇_处通過延遲器7 ^ 時脈樣本p clk。 彳文為 TW 24449twf.doc/n 200939183 上述差動介面單元730可以將樣本單元720所輪出的 時脈樣本p clk與資料樣本p—data轉換成符合低擺幅差動 訊號傳輸（reduced swing differential signaling, RSDS)戋 是其他信號傳輸介面之信號。當然，差動介面單元73〇亦 可能被省略’使得樣本產生器531將樣本單元720所輪出 的％脈樣本p一elk與資料樣本p_data直接輸出做為時脈樣 本rs—elk以及資料樣本rS_data。 圖8是依照本發明說明圖5中差動介面單元730之實 施範例。差動介面單元730包括反相器810與820，以及 電阻 811、812、813、814、815、816、821、822、823、 824、825與826。反相器810之輸入端接收時脈樣本p_clk， 而反相器820之輸入端接收資料樣本p—data。電阻8u_813 串聯於時脈樣本1)_(2也與接地電壓之間，其中電阻812與 813之間的共同接點耦接參考電壓VDC，而電阻811與 之間的共同接點可以輸出信號rs—c。電阻814 816串聯於 反相器810之輸出端與接地電壓之間，其中電阻815與816 ❹ 之間的共同接點麵接參考電壓VDC，而電阻814與815之 間的共同接點可以輪出信號rs—cB。信號rs—c與信號rs_cs 即為差動介面單元730所輸出之時脈樣本rs—dk。另外， 電阻821-823串聯於資料樣本p—data與接地電壓之間，其 中電阻822與823之間的共同接點耦接參考電壓VDC，而 電阻821與822之間的共同接點可以輸出信號^。電阻 824-826串聯於反相器820之輸出端與接地電壓之間，其 中電阻825與826之間的共同接點柄接參考電壓VDC，而 15 200939183 -TW 24449twf.doc/n 電阻824與825之間的共同接點可以輪出信號rs—dB。信 號rs一d與信號rs—dB即為差動介面單元73〇所輸出之資& 樣本 rs__data。 ' 延續前述範例之假設，在此亦假設控制資料 DC_COn[n:l]為6位元資料（即DC_c〇n[6:1])。圖$是依 照本發明說明圖5中相位調整器532之實施範例。相位調 整器532包括延遲選擇器900,用以接收目標電路52〇所 ❹ 輸出之第一資料test一data，並依該控制資料DCLc〇n[6:1] 延遲第一資料test_data，以輸出為第二資料data—delay。在 本實施例中，相位調整器532是將目標電路52〇所輸出之 第一時脈test一dk直接輸出做為第二時脈dk_delay，並且 透過延遲選擇器900調整目標電路520所輸出第一資料 test—data之才目位。 請參照圖9 ’延遲選擇器900包括延遲單元串以及開 關92卜922、923、924、925、926。延遲單元串由延遲單 元911、912、913、914、915及916相互串接所形成。其 ❹ 中，延遲單元串之第一個延遲單元911之輸入端接收目標 電路520所輸出第一資料test_data。開關921之第一端接 收第一資料 test_data。開關 922、923、924、925 與 926 之 第一端分別耦接至延遲器912-915之輸出端。開關921-926 之第二端相互連接以便輸出第二資料data_delay。開關 921-926分別受控於控制資料DC_con[6:l]之其中一個位元 (即 DC—con[l]、DC_con[2]、DC_con[3]、DC-C〇n[4]、 DC_con[5]或 DC_con[6])，而使開關 921-926 其中之一導 16 TW 24449twf.doc/n 200939183 通，以輸出第二資料data_delay。因此，藉由控制資料 DC—con[6:l]可以調整第一資料data—delay與第二時脈 clk_delay二者之間的相位關係。 相位調整器532之實施方式不應被限定為圖9所示， 所屬領域具有通常知識者亦可以其他方式實現相位調整器 532。例如’將延遲選擇器改耦接於第一時脈test-dk與第 二時脈clk_delay之間，使得延遲選擇器依控制資料 DC—con[6:l]延遲目標電路所輸出之第一時脈test—dk，以 獲得第二時脈clk_delay。另外’亦可將第一資料test_data 直接輸出做為第二資料data_delay。 圖10是依照本發明說明圖5中檢測單元533之實施範 例。在本實施例中’檢測單元533包括正反器1〇1〇以及比 較器1020。正反器1〇1〇依據第二時脈clk—delay閂鎖第二 資料data—delay。比較器1〇2〇檢查正反器1010所閂鎖之 資料是否正確’以輸出檢測結果detect_result。依據前述樣 本產生器531所產生之時脈樣本rs—clk以及資料樣本 rs_data一者之相位關係，比較器1〇2〇可以比較正反器1〇1〇 所閂鎖之第二資料data_delay是否為「1」。因此檢測單元 533可以依據所閂鎖之第二資料data_delay來判斷相位調 整益532之調整結果是否適當，並依據上述判斷輸出檢測 結果 detect_result。 上述比較器1020可以及閘（未繪示）實施之。其中， 及閘之第一輸入端耦接至正反器1010之輸出端，及閘之第 二輸入端接收一邏輯值（在此為邏輯「丨」），而其輸出端 17 200939183 TW 24449twf.doc/n 輸出檢測結果detect_result。當然，上述比較器1〇2〇之實 施方式並不限於此。 本發明之實施方式並不限於上述所示。例如，圖11 是依據本發明說明另一種相位校正電路之實施範例。圖i i 所示之實施方式類似於圖5之實施範例，因此不再贅述相 同部分。與圖5之實施範例相較，圖η之檢測單元113〇 疋依據第一時脈clk_delay與第二資料data_delay二者之間 的相位關係，更輸出樣本設定信號setupjresult給樣本產生 器1110;以及樣本產生器111〇更依據樣本設定信號 setup—result調整資料樣本rs一data之相位。例如，當樣^ 設定信號setup_result為邏輯「〇」時，樣本產生器111〇 所產生之時脈樣本rs—clk以及資料樣本rs—data之相位關係 是符合系統本身所設定之設定時間（setuptime)關係；當 樣本設定信號setup一result為邏輯「丨」時，樣本產生器〗11〇 ^f生之時脈樣本rS-Clk以及資料樣本rs-data之相位關係 是符合系統本身所設定之保持時間（h〇ldtime)關係。 「在此假設樣本設定信號setup—result之初始值為邏輯 〇」，此時為「設定時間」測試模式。由於樣本設定信號 一Iesult為邏輯「0」，樣本產生器1110產生符合系統 °又疋時間」關係之時脈樣本rs_clk以及資料樣本 rs—data。時脈樣本rs—他以及資料樣本rs—_經過目標電 路520 ί產生第—時脈teSt-dk與第—資料test—data。旋 轉暫單元535輸出循環的控制資料DC_eGn[n:l]給相位 調整盗532。相位調整器532受控制資料Dc—麵_]的控 18 200939183 TW 24449twf.doc/n =，以決定第二時脈clk〜delay與第二資料她 Γ間。檢測單元1叫貞測第二時脈他―_；與第二Ϊ 1恤一制吵一者之間的相位關係' ’以判定可否問鎖到正 確=料。隨著控制資料DC—c〇n[n:1]的改變，當檢測單 ^本—到正確_树，檢測單元_更輪出 ^又疋油etup—result為邏輯「!」給樣本產生器ιΐι〇， ❹ 此時=位校j路將開始進行「保持時間」測試。 當樣本設定信號setup_result為邏輯「i」，此時為 ，時間」測試模式。由於樣本設定信號，⑽此為邏輯 1 士」，樣本產生HUH)產生符合系統「保持時間」關係 之哺樣本rS 一 clk以及資料樣本rs—_。旋轉暫存單元奶 輸出循環的控制資料DC—con㈣給相位調整器532。相位 調整器532受控制資料Dc—c〇n[n:1]的控制，以決定第二 時脈dk—delay與第二資料data_dday的延遲時間。檢測單 兀113(H貞測第二時脈clk—dday與第二資料心㈣二 者之間的她關係’以判定可否⑽到正確的資料。 當檢測單元1130第-次閃鎖到正確的資料時，檢測單 凡1130輸出檢測結果detect—resuit由邏輯「〇轉變為 輯「!」’使得最佳化單元534内部計數器計數4= 最佳化單元534内部暫存器會記錄此時的控制資料 DC—Con[n:l]之值。之後’最佳化單元534不再隨著檢測結 果detect—result改變其内部暫存器之值。 旋轉暫存單元535會循觀改變控制資料Dc—c吵⑴ 之值。當控制資料DC_c〇n[n: 1 ]改變狀態時，檢測單元1 i3〇 19 TW 24449twf.doc/n 200939183 所輸出的檢測結果detect_result會由邏輯「1」轉變為邏輯 「0」’然後再依據是否閂鎖到正確資料來決定是否再次將 檢測結果detect—result由邏輯「〇」轉變為邏輯「丨」。因 此當檢測單元1130連續偵測到第二時脈dk一delay與第二 資料data_delay二者之間的相位關係足以閂鎖到正確資料 時’隨著控制資料DC_con[n:l]的循環改變，檢測結果 detectjesult亦會呈現「〇」、Μ」、「〇」、「！」的變 ❹ 化。最佳化單元534内部計數器亦會計數檢測結果 detect—result的變化，直到檢測結果detect—result保持邏輯 「〇」。因此，最佳化單元534内部計數器所記錄之值即為 通過偵測的控制資料DC_con[n: 1 ]筆數。 由於旋轉暫存單元535會循環地改變控制資料 DC_con[n:l]之值，因此當控制資料DC_c〇n[n:1^值再一 次輪迴至相同於最佳化單元534内部暫存器所記錄之值 N* ’由於表佳化單元534内部計數器所記錄之值即為通過 偵測的控制資料DC一con[n:l]筆數，因此當控制資料 ❹ D^-con[n:l]再改變「最佳化單元534内部計數器之值/2」 -人時’最佳化單元534藉由信號〇ptimal_signal控制旋轉 暫存單元535保持所輸出之控制資料Dc_C0n[n:i]而不再 循環改變。 _ 若以圖6為例，當控制資料DC_con[n:l]之值為4時， 檢測單兀1130第一次閂鎖到正確的資料。於是，檢測單元 ^130輸出檢測結果detectjresult由邏輯「〇」轉變為邏輯 1」，使得最佳化單元534内部計數器計數一次，同時最 20 TW 24449twf.doc/n 200939183 佳化單元534内部暫存器會記錄此時的控制資料 DC—c〇n[n:l]之值為4。接下來當控制資料DC_con[n:1]= 8、16時，檢測結果detect_result為邏輯「1」。當控制資 料DC_C〇n[n:l] = 32時，檢測結果detect—似此為邏輯 「0」。此表示控制資料DC_con[iKl] = 4、8、16等三筆資 料可以使相位調整器532輸出適當相位關係，所以此時最 佳化單元534内部計數器所記錄之值即為3。旋轉暫存單 元535會循環地改變控制資料Dc—c〇n[n:1]之值，當控制 資料DC_con[n:l]再一次改變為4時（相同於最佳化單元 534内部暫存器所記錄之值），因此最佳化單元534從控 制資料DC_con[n:l]=4起算’等控制資料DC—c〇n[n:1]再改 變「3/2」次時（相當於將最佳化單元534内部計數器之計 數值右移1位元，因此3/2=1) ’亦即當控制資料Dc—c〇n㈣ 再一次改變為8時，最佳化單元534藉由作號 Optimal一signal控制旋轉暫存單元535保持輸出控制資料 DC—con[n:l]為8而不再循環改變。 圖12是依據本發明說明圖u中樣本產生器ιιι〇之實 施範例。樣本產生器1110包括振盪器121〇一延遲器 1220、第二延遲器1230以及切換器124〇。振盪器12楛 供時脈樣本rs—clk。第一延遲器122〇與第二延遲器123〇 各自接收並延遲時脈樣本rs_clk。切換器124〇依據樣本設 定信號setup—result之控制，選擇將第一延遲器122〇與第 二延遲器1230二者之一的輸出做為資料樣本^ 21 200939183 TW 24449twf.doc/n 考量系統信號規格，亦可配置信號轉換電路於樣本產 生器1110中。例如，圖13是依據本發明說明圖u中樣本 ^生器1110之另一實施範例。樣本產生器ηι〇包括振盪 器1210、第一延遲器122〇、第二延遲器123〇、切換器124〇 以及差動介面單元1310。振盪器121〇提供原始時脈 p_dk。第一延遲器1220與第二延遲器123〇各自接收並延 遲原始時脈p_dk。切換器1240依據樣本設定信號 ❹ setuP-result之控制，選擇將第一延遲器1220與第二延遲 器1230 一者之一的輸出做為原始資料p_data。差動介面單 元1310可以將原始時脈p_clk與原始資料p—data分別轉換 為差動模式之時脈樣本rS-Clk與資料樣本rs_data。上述時 脈樣本rs_clk與資料樣本rs_data可以是符合低擺幅差動訊 號傳輸（reduced swing differential signaling，RSDS)或是 其他信號傳輸介面之信號。圖8所示之電路亦可以做為差 動介面單元1310之實施範例。 圖14是依照本發明說明圖η中檢測單元113〇之實施 〇 範例。在本實施例中’檢測單元1130包括正反器1410以 及比較器1420。正反器1410依據第二時脈cik_delay閂鎖 第二資料data_delay。比較器1420檢查正反器1410所閂 鎖之資料是否正確，以輸出檢測結果detect_result以及樣 本設定信號setup—result。依據前述樣本產生器1110所產 生之時脈樣本rs_clk以及資料樣本rS-data二者之相位關 係，比較器1420可以比較正反器141〇所閂鎖之第二資料 data一delay是否為「1」。因此檢測單元U30可以依據所 22 rw 24449twf.doc/n ❹= example. In this embodiment, sample unit 72〇 may include Z 22 . The sample unit 72 is a clock sample. -dk direct output as = ^ this p-data, and pass the clock sample 〇_ through the delay 7 ^ clock sample p clk.彳文为TW 24449twf.doc/n 200939183 The above differential interface unit 730 can convert the clock sample p clk and the data sample p_data rotated by the sample unit 720 into a low-swing differential signal transmission (reduced swing differential). Signaling, RSDS) is the signal of other signal transmission interfaces. Of course, the differential interface unit 73 may also be omitted 'so that the sample generator 531 directly outputs the % pulse sample p_elk and the data sample p_data rotated by the sample unit 720 as the clock sample rs_elk and the data sample rS_data. . Figure 8 is a block diagram showing an embodiment of the differential interface unit 730 of Figure 5 in accordance with the present invention. The differential interface unit 730 includes inverters 810 and 820, and resistors 811, 812, 813, 814, 815, 816, 821, 822, 823, 824, 825, and 826. The input of the inverter 810 receives the clock sample p_clk, and the input of the inverter 820 receives the data sample p_data. The resistor 8u_813 is connected in series with the clock sample 1)_(2 is also connected to the ground voltage, wherein the common contact between the resistors 812 and 813 is coupled to the reference voltage VDC, and the common contact between the resistor 811 and the output signal rs —c. The resistor 814 816 is connected in series between the output of the inverter 810 and the ground voltage, wherein the common contact between the resistors 815 and 816 面 is connected to the reference voltage VDC, and the common contact between the resistors 814 and 815 The signal rs_cB can be rotated. The signal rs_c and the signal rs_cs are the clock samples rs_dk output by the differential interface unit 730. In addition, the resistors 821-823 are connected in series between the data sample p-data and the ground voltage. The common contact between the resistors 822 and 823 is coupled to the reference voltage VDC, and the common contact between the resistors 821 and 822 can output a signal ^. The resistors 824-826 are connected in series with the output of the inverter 820 and the ground voltage. Between the resistors 825 and 826, the common contact handle is connected to the reference voltage VDC, and 15 200939183 - TW 24449twf.doc / n The common contact between the resistors 824 and 825 can rotate the signal rs - dB. A d and the signal rs-dB is the differential interface unit 73 The resource & sample rs__data. 'Continue the assumption of the foregoing example, here also assume that the control data DC_COn[n:l] is 6-bit data (ie DC_c〇n[6:1]). Figure $ is in accordance with the present invention An example of the implementation of the phase adjuster 532 in Fig. 5. The phase adjuster 532 includes a delay selector 900 for receiving the first data test data output by the target circuit 52, and according to the control data DCLc〇n[6 The first data test_data is delayed to output the second data data_delay. In this embodiment, the phase adjuster 532 directly outputs the first clock test dk outputted by the target circuit 52〇 as the first data. The second clock is dk_delay, and the target data of the first data test_data output by the target circuit 520 is adjusted by the delay selector 900. Referring to FIG. 9 'the delay selector 900 includes the delay unit string and the switch 92 922, 923, 924 , 925, 926. The delay unit string is formed by the delay units 911, 912, 913, 914, 915 and 916 being connected in series with each other. In the middle, the input end of the first delay unit 911 of the delay unit string receives the target circuit 520 Output the first data test_data. Switch 92 The first end of 1 receives the first data test_data. The first ends of the switches 922, 923, 924, 925 and 926 are respectively coupled to the outputs of the delays 912-915. The second ends of the switches 921-926 are connected to each other for output. The second data data_delay. The switches 921-926 are respectively controlled by one of the control data DC_con[6:l] (ie, DC_con[l], DC_con[2], DC_con[3], DC-C〇n[4], DC_con [5] or DC_con[6]), and one of the switches 921-926 leads 16 TW 24449twf.doc/n 200939183 to output the second data data_delay. Therefore, the phase relationship between the first data data-delay and the second clock clk_delay can be adjusted by controlling the data DC_con[6:l]. The embodiment of the phase adjuster 532 should not be limited to that shown in Figure 9, and the phase adjuster 532 can be implemented in other ways as is known in the art. For example, the delay selector is coupled between the first clock test-dk and the second clock clk_delay, so that the delay selector delays the first output of the target circuit according to the control data DC_con[6:l]. Pulse test_dk to obtain the second clock clk_delay. In addition, the first data test_data can also be directly output as the second data data_delay. Figure 10 is a diagram showing an embodiment of the detecting unit 533 of Figure 5 in accordance with the present invention. In the present embodiment, the detecting unit 533 includes a flip-flop 1〇1〇 and a comparator 1020. The flip-flop 1〇1〇 latches the second data data_delay according to the second clock clk_delay. The comparator 1〇2〇 checks whether the data latched by the flip-flop 1010 is correct ’ to output the detection result detect_result. According to the phase relationship between the clock sample rs_clk and the data sample rs_data generated by the sample generator 531, the comparator 1〇2〇 can compare whether the second data data_delay latched by the flip-flop 1〇1〇 is "1". Therefore, the detecting unit 533 can determine whether the adjustment result of the phase adjustment benefit 532 is appropriate according to the latched second data data_delay, and output the detection result detect_result according to the above judgment. The comparator 1020 can be implemented by a gate (not shown). The first input terminal of the gate is coupled to the output terminal of the flip-flop 1010, and the second input terminal of the gate receives a logic value (here, logic "丨"), and the output terminal 17 200939183 TW 24449twf. Doc/n outputs the detection result detect_result. Of course, the implementation of the above comparator 1 is not limited to this. Embodiments of the invention are not limited to the above. For example, Figure 11 illustrates an embodiment of another phase correction circuit in accordance with the present invention. The embodiment shown in Fig. i i is similar to the embodiment of Fig. 5, and therefore the same portions will not be described again. Compared with the embodiment of FIG. 5, the detecting unit 113 of the image n outputs a sample setting signal setupjresult to the sample generator 1110 according to the phase relationship between the first clock clk_delay and the second data data_delay; The generator 111 adjusts the phase of the data sample rs_data according to the sample setting signal setup_result. For example, when the sample setup signal setup_result is logical "〇", the phase relationship between the clock sample rs_clk and the data sample rs_data generated by the sample generator 111 is in accordance with the set time set by the system itself (setuptime). Relationship; when the sample setting signal setup-result is logical "丨", the phase relationship between the sample generator 〇11〇^f clock sample rS-Clk and the data sample rs-data is in accordance with the retention time set by the system itself. (h〇ldtime) relationship. "Assuming that the initial value of the sample setting signal setup_result is logic 〇", this is the "set time" test mode. Since the sample setting signal - Iesult is logic "0", the sample generator 1110 generates the clock sample rs_clk and the data sample rs_data in accordance with the system ° and time relationship. The clock sample rs-he and the data sample rs__ generate the first-time clock teSt-dk and the first data test-data through the target circuit 520 ί. The rotation temporary unit 535 outputs the loop control data DC_eGn[n:l] to the phase adjustment thief 532. The phase adjuster 532 is controlled by the control data Dc_face_] 18 200939183 TW 24449twf.doc/n = to determine the second clock clk~delay and the second data. The detecting unit 1 is called to measure the second time pulse __; the phase relationship '' between the second one and the second one to determine whether the lock can be correctly corrected. With the change of the control data DC_c〇n[n:1], when detecting the single-book-to the correct_tree, the detection unit_ turns round and the oil eup_result is logical "!" to the sample generator Ϊ́ΐι〇, ❹ At this point, the school will begin the “hold time” test. When the sample setting signal setup_result is logic "i", this time is the "time" test mode. Due to the sample setting signal, (10) this is logic 1", the sample produces HUH) to generate the sample rS- clk and the data sample rs__ in accordance with the "hold time" relationship of the system. Rotating the temporary unit milk output control data DC_con (4) to the phase adjuster 532. The phase adjuster 532 is controlled by the control data Dc_c〇n[n:1] to determine the delay time of the second clock dk_delay and the second data data_dday. The detection unit 113 (H measures the relationship between the second clock clk_dday and the second data heart (4) to determine whether it is possible (10) to the correct data. When the detection unit 1130 is flashed to the correct In the case of data, the detection unit 1130 outputs the detection result detect-resuit from the logical "〇 to ""!" so that the optimization unit 534 internal counter counts 4 = the optimization unit 534 internal register will record the control at this time The value of the data DC_Con[n:l]. Then the 'optimization unit 534 no longer changes the value of its internal register with the detection result detect-result. The rotation temporary storage unit 535 will change the control data Dc. c. The value of (1). When the control data DC_c〇n[n: 1 ] changes state, the detection result detect_result output by the detection unit 1 i3〇19 TW 24449twf.doc/n 200939183 will be changed from logic "1" to logic " 0"' then decides whether to change the detection result_result from logical "〇" to logic "丨" again according to whether it is latched to the correct data. Therefore, when the detecting unit 1130 continuously detects the second clock dk-delay And the second data data_delay The phase relationship between the two is sufficient to latch the correct data. 'With the loop of the control data DC_con[n:l], the detection result detectjesult will also show the changes of "〇", Μ", "〇", "!" The internal counter of the optimization unit 534 also counts the change of the detection result detect-result until the detection result detect_result remains logical "〇". Therefore, the value recorded by the internal counter of the optimization unit 534 is detected. Controls the number of data DC_con[n: 1 ]. Since the rotation temporary storage unit 535 cyclically changes the value of the control data DC_con[n:l], when the control data DC_c〇n[n:1^ value is again rotated to the same The value recorded by the internal register of the optimization unit 534 is N*' because the value recorded by the internal counter of the table optimization unit 534 is the number of control data DC_con:[n:l], so when The control data ❹ D^-con[n:l] then changes the value of the internal counter of the optimization unit 534/2. The "optimization unit 534" controls the rotation temporary storage unit 535 to maintain the output by the signal 〇ptimal_signal. Control data Dc_C0n[n:i] without rectification _ If we take Figure 6 as an example, when the value of the control data DC_con[n:l] is 4, the detection unit 1130 latches to the correct data for the first time. Then, the detection unit ^130 outputs the detection result detectjresult by logic. "〇" changes to logic 1", so that the internal counter of the optimization unit 534 counts once, and at the same time, the most 20 TW 24449twf.doc/n 200939183 the internal register of the optimization unit 534 records the control data DC_c〇n at this time. The value of [n:l] is 4. Next, when the control data DC_con[n:1] = 8, 16, the detection result detect_result is logical "1". When the control data DC_C〇n[n:l] = 32, the detection result detect - this is logical "0". This indicates that the control data DC_con[iKl] = 4, 8, 16 and the like can cause the phase adjuster 532 to output an appropriate phase relationship, so that the value recorded by the internal counter of the optimization unit 534 is 3 at this time. The rotation temporary storage unit 535 cyclically changes the value of the control data Dc_c〇n[n:1], and when the control data DC_con[n:l] is changed again to 4 (same as the internalization of the optimization unit 534) The value recorded by the device), so the optimization unit 534 counts the control data DC_con[n:l]=4 from the control data DC_c〇n[n:1] and then changes "3/2" times (equivalent The value of the internal counter of the optimization unit 534 is shifted to the right by 1 bit, so 3/2=1) 'that is, when the control data Dc_c〇n(4) is changed to 8 again, the optimization unit 534 is used. The Optimal-signal control rotation register unit 535 keeps the output control data DC_con[n:l] at 8 without recurring changes. Figure 12 is a diagram showing an example of the implementation of the sample generator ιιι in Figure u in accordance with the present invention. The sample generator 1110 includes an oscillator 121, a delay 1220, a second delay 1230, and a switch 124. The oscillator 12 is supplied with a clock sample rs_clk. The first delay 122 〇 and the second delay 123 各自 each receive and delay the clock sample rs_clk. The switch 124 selects the output of one of the first delay 122 〇 and the second delay 1230 as a data sample according to the control of the sample setting signal setup_result. 21 200939183 TW 24449twf.doc/n Considering the system signal The signal conversion circuit can also be configured in the sample generator 1110. For example, Figure 13 illustrates another embodiment of a sample processor 1110 of Figure u in accordance with the present invention. The sample generator ηι〇 includes an oscillator 1210, a first retarder 122A, a second retarder 123A, a switch 124A, and a differential interface unit 1310. The oscillator 121 provides the original clock p_dk. The first delay 1220 and the second delay 123 〇 each receive and delay the original clock p_dk. The switch 1240 selects the output of one of the first delay 1220 and the second delay 1230 as the original data p_data according to the control of the sample setting signal ❹ setuP-result. The differential interface unit 1310 can convert the original clock p_clk and the original data p_data into the clock sample rS-Clk and the data sample rs_data of the differential mode, respectively. The clock sample rs_clk and the data sample rs_data may be signals conforming to reduced swing differential signaling (RSDS) or other signal transmission interfaces. The circuit shown in Fig. 8 can also be used as an example of the implementation of the differential interface unit 1310. Figure 14 is a diagram showing an example of the implementation of the detecting unit 113 in Figure η in accordance with the present invention. In the present embodiment, the detecting unit 1130 includes a flip-flop 1410 and a comparator 1420. The flip-flop 1410 latches the second data data_delay according to the second clock cik_delay. The comparator 1420 checks whether the data latched by the flip-flop 1410 is correct to output the detection result detect_result and the sample setting signal setup_result. According to the phase relationship between the clock sample rs_clk and the data sample rS-data generated by the sample generator 1110, the comparator 1420 can compare whether the second data data-delay latched by the flip-flop 141 is "1". . Therefore, the detecting unit U30 can be based on 22 rw 24449twf.doc/n ❹
200939183 閂鎖之第二資料data_delay來判斷相位調整器532之調整 結果是否適當’並依據上述判斷輸出檢測結果detect_result 以及樣本設定彳s號setupjesult。 比較器1420包括及閘1421、或閘1422以及第二正反 器H23。及閘1421之第一輸入端耦接至正反器141〇之輸 出端，及閘1421之第二輸入端接收一邏輯值（在此為邏輯 「1」）’而其輸出端輸出檢測結果detect—result。或閘1422 之第一輸入端接收第二時脈clk_delay (圖14要修改）。 第二正反器1423之觸發端耦接至或閘1422之輸出端。第 二正反器1423之輸入端耦接至及閘1421之輸出端。第二 正反器1423之輸出端耦接至或閘1422之第二輸入端。其 中，第二正反器1423之輸出端輸出樣本設定信號 setup_result給樣本產生器，使得樣本產生器mo更 依據樣本較錢setup—麵lt碰㈣#本 '齡及/或 時脈樣本rs_clk之相位。 綜上所述，上述實施例中相位校正電路利用檢測單元 =測目標電路之輪出，並依據制結果動態選擇所需要延 1 ^此’上述實施例可以動態修正因延遲偏移所造 成的δ又足蚪間與保持時間問題。 限定ΪΪί發明已哺佳實闕揭露如上，然其並非用以 脫離太旅Β任何所屬技術領域中具有通常知識者，在不 因此本二!1神和範圍内，當可作些許之更動與潤飾， 為準。X保蠖範圍當視後附之申請專利範圍所界定者 23 TW 24449twf.doc/n 200939183 【圖式簡單說明】 圖1A是說明數位信號的信號路徑。 圖1B是說明圖ία中信號時序關係。 圖2A是說明傳統技術利用一組固定延遲緩衝器來修 正數位信號偏移之方塊圖。 圖2B是說明圖2A中信號時序關係。200939183 The second data data_delay of the latch is used to judge whether the adjustment result of the phase adjuster 532 is appropriate' and the detection result detect_result and the sample setting 彳s number setupjesult are output according to the above judgment. The comparator 1420 includes a AND gate 1421, or a gate 1422, and a second flip-flop H23. The first input end of the gate 1421 is coupled to the output end of the flip-flop 141, and the second input of the gate 1421 receives a logic value (here, logic "1") and its output outputs a detection result detect —result. The first input of the OR gate 1422 receives the second clock clk_delay (Fig. 14 is to be modified). The trigger end of the second flip-flop 1423 is coupled to the output of the OR gate 1422. The input end of the second flip-flop 1423 is coupled to the output of the AND gate 1421. The output of the second flip-flop 1423 is coupled to the second input of the OR gate 1422. Wherein, the output of the second flip-flop 1423 outputs the sample setting signal setup_result to the sample generator, so that the sample generator mo is more in accordance with the sample setup-surface touch (four) #本's age and/or the phase of the clock sample rs_clk . In summary, the phase correction circuit in the above embodiment uses the detection unit = the rotation of the target circuit, and dynamically selects the required delay according to the result of the system. The above embodiment can dynamically correct the delta caused by the delay offset. There is also an issue between time and time. ΪΪ 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明 发明, whichever is the case. The scope of the X warranty is defined by the scope of the patent application. TW 24449twf.doc/n 200939183 [Simplified Schematic] FIG. 1A is a diagram illustrating the signal path of a digital signal. Fig. 1B is a diagram showing the relationship of signal timing in Fig. Figure 2A is a block diagram illustrating conventional techniques for correcting digital signal offsets using a fixed set of delay buffers. Figure 2B is a diagram showing the timing relationship of the signals in Figure 2A.
❹ 圖3是依照本發明實施例說明一種内喪有相位校正電 路之積體電路方塊圖。 圖4是依照本發明另一實施例說明内嵌有相位校正電 路之積體電路方塊圖。 圖5是依照本發明說明一種相位校正電路之實施範 例。 圖6疋依照本發明實施例說明圖5相位校正電路之信 號時序圖。 圖7A是依照本發明說明圖5中樣本產生器之實施範 例。 圖7B是依照本發明說明圖5中樣本產生器之另一實 施範例。 圖8是依照本發明說明圖5中差動介面單元之實施範 例。 圖9是依照本發明說明圖5中相位調整器之實施範例。 圖1〇是依照本發縣_ 5巾檢測單元之實施範例。 圖η是依據本發明說明另一種相位校正電路之實施 24 TW 24449twf.doc/n 200939183 对圖12是依據本發明說明圖樣本產生器之實施範 圖13是依據本發明說明目^中樣本產生器 範例。 貫 圖14是依照本發明制圖u巾檢解元之實施範例。 【主要元件符號說明】 110、310、410 :發送器 ❹ ❹ 120 :信號路徑 130、320、336、420 :接收器 240 :延遲緩衝器 300、400 :顯示驅動器 330、 430 :相位校正電路 331、 431、5M、1110 :樣本產生器 332、 337、432、532 :相位調整器 333、 433、533、1130 :檢測單元 334、 434、534:最佳化單元 335、 435、535 :旋轉暫存單元 436:選擇器 520 :目標電路 710、1210 :振盪器 720 :樣本單元 72卜 722、1220、1230 :延遲器 730、1310 :差動介面單元 810、820 :反相器 25 TW 24449twf.doc/n 200939183 811-816、821-826 :電阻 900 :延遲選擇器 911-916 :延遲單元 921-926 :開關 1010、1410、1423 :正反器 1020、1420 :比較器 1240 :切換器 1421 :及閘 1422 :或閘3 is a block diagram showing an integrated circuit with a phase correction circuit in accordance with an embodiment of the present invention. Fig. 4 is a block diagram showing an integrated circuit in which a phase correcting circuit is embedded in accordance with another embodiment of the present invention. Figure 5 is a diagram showing an embodiment of a phase correction circuit in accordance with the present invention. Figure 6 is a timing diagram showing the signal of the phase correction circuit of Figure 5 in accordance with an embodiment of the present invention. Figure 7A is a diagram showing an embodiment of the sample generator of Figure 5 in accordance with the present invention. Figure 7B is a diagram showing another embodiment of the sample generator of Figure 5 in accordance with the present invention. Figure 8 is a block diagram showing an embodiment of the differential interface unit of Figure 5 in accordance with the present invention. Figure 9 is a block diagram showing an embodiment of the phase adjuster of Figure 5 in accordance with the present invention. Fig. 1 is an example of implementation according to the present invention. Figure η illustrates an implementation of another phase correction circuit in accordance with the present invention. 24 TW 24449 twf.doc/n 200939183 FIG. 12 is an illustration of a sample generator in accordance with the present invention. FIG. 13 is a sample generator in accordance with the present invention. example. Figure 14 is an illustration of an embodiment of a U-shaped inspection element in accordance with the present invention. [Main component symbol description] 110, 310, 410: Transmitter ❹ 120: Signal path 130, 320, 336, 420: Receiver 240: Delay buffer 300, 400: Display driver 330, 430: Phase correction circuit 331, 431, 5M, 1110: sample generators 332, 337, 432, 532: phase adjusters 333, 433, 533, 1130: detection units 334, 434, 534: optimization units 335, 435, 535: rotation temporary storage unit 436: selector 520: target circuit 710, 1210: oscillator 720: sample unit 72 722, 1220, 1230: delay 730, 1310: differential interface unit 810, 820: inverter 25 TW 24449twf.doc / n 200939183 811-816, 821-826: Resistor 900: delay selector 911-916: delay unit 921-926: switch 1010, 1410, 1423: flip-flop 1020, 1420: comparator 1240: switch 1421: and gate 1422 : or brake
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