200937668 九、發明說明： 【發明所屬之技術領域】 、 *㈣極體晶片封褒結構及其封 裝方法，尤指一種具有不同排列間距（different a麵gement spacing)之發光二極體晶片封裝結構及其封裝方法。 【先前技術】 凊參閱第一圖所示，其係為習知發光二極體之封裝方 法之流程圖。由流私圖中可知，習知發光二極體之封裝方 法，其步驟包括：首先，提供複數個封裝完成之發光二極 體（packaged LED) (S100);接著，提供一條狀基板本體 (stripped substrate body )’其上具有一正極導電軌跡 (positive electrode trace )與一負極導電執跡（ electrode trace) (S102);最後，依序將每一個封裝完成之 發光=極體（packaged LED)設置在該條狀基板本體上， 並將每一個封裝完成之發光二極體（packagedLED)之正、 ©負極端分別電性連接於該條狀基板本體之正、負極導 跡（S104)〇 然而丄關於上述習知發光二極體之封裝方法，由於每 一顆封裝元成之發光二極體（packaged LED)必須先從— 整塊發光广極體封裝切割下來，然後再以表面黏著技術 (SMT^製程，將每—顆封裝完成之發光二極體（ρ_㈣ LE=)设置於該條狀基板本體上，因此無法有效縮短其製 ㈣夺間。再者’由於習知發光二極體之封裝結構無任何的 保4裝置’因此常造成供電或其它不穩定的情形發生。 200937668 是以，由上可知，目前習知之發光二極體的封裝方法 - 及其封裴結構，顯然具有不便與缺失存在，而待加以改善 . 者。 緣是，本發明人有感上述缺失之可改善，且依據多年 來從事此方面之相關經驗，悉心觀察且研究之，並配合學 理之運用，而提出一種設計合理且有效改善上述缺失之本 發明。 ❹ 【發明内容】 本發明所要解決的技術問題，在於提供一種具有不同 排列間距（different arrangement spacing )之發光二極體晶 片封裝結構及其封裝方法。本發明之發光二極體晶片封襄 結構係具有複數個發光二極體晶片，並且該等發光二極體 晶片彼此之間係具有完全不同或部分不同之間距，以符合 不同使用者之需求。 再者，本發明係透過晶片直接封裝（Chip On Board， © COB)製程並利用壓模（die mold)的方式，以使得本發明 可有效地縮短其製程時間，而能進行大量生產。此外，本 發明之結構設計更適用於各種光源，諸如背光模組、裝飾 燈條、照明用燈、或是掃描器光源等應用，皆為本發明所 應用之範圍與產品。 為了解決上述技術問題，根據本發明之其中一種方 案’長:供一種具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝結構，其包括：一基板單 元（substrate unit)、—發光單元（light emitting uni〇、及 200937668 一封裝膠體單元（package colloid unit)。 • 再者，該發光單元係具有複數個電性地設置於該基板 • 單元上之發光二極體晶片（LEDchip)，並且該等發光二極 體晶片彼此之間係具有完全不同或部分不同之間距。該封 裝膠體單元係覆蓋於該等發光二極體晶片上。 再者’上述發光二極體晶片封裝結構更進一步包括下 列七種實施態樣： ^ 第一種實施態樣：該封裝膠體單元係為一相對應該等 發光二極體晶片之條狀螢光膠體（stripped fluorescent colloid) ° 第二種實施態樣：該封裝膠體單元係為一相對應該等 發光二極體晶片之條狀螢光膠體（stripped fluorescent colloid)，並且該條狀螢光膠體之上表面及前表面係分別具 有一膠體弓瓜面（colloid cambered surface)及一勝體出光面 (colloid light-exiting surface)。此外，該發光二極體晶片 封裝結構更進一步包括：一框架單元（frame unit )，其用於 © 包覆該條狀螢光膠體而只露出該條狀螢光膠體之側表面。 第三種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之螢光膠體（fluorescent colloid )。 第四種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之螢光膠體（fluorescent colloid )。 此外’該發光二極體晶片封裝結構更進一步包括：一框架 單元（frame unit)，其具有複數個框架層，並且每一個框架 層係用於圍繞該相對應之螢光膠體而只露出該相對應螢光 膠體之上表面。 200937668 第五種實施態樣：該封裝膠體單元係具有複數個相對 , 應該等發光二極體晶片之螢光膠體（fluorescent colloid)。 • 此外，該發光二極體晶片封裝結構更進一步包括：一框架 單元（frame unit) ’其用於圍繞該等螢光膠體而只露出該等 螢光膠體之上表面，其中該框架單元係為一不透光框架層 (opaque frame layer) ° 第六種實施態樣：該封裝膠體單元係具有複數個相對 ❹ 應該等發光二極體晶片之螢光膠體（fluorescent colloid)， 並且每一個螢光膠體之上表面及前表面係分別具有一膠體 弧面（colloid cambered surface)及一膠體出光面（c〇ll〇id light-exiting surface)。此外，該發光二極體晶片封裝結構 更進一步包括：一框架單元（frame unit )，其具有複數個框 架層’並且每一個框架層係用於包覆該相對應之螢光膠體 而只露出該相對應螢光膠體之側表面。 第七種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之螢光膠體（fluorescent colloid )， G 並且每一個螢光膠體之上表面及前表面係分別具有一膠體 弧面（colloid cambered surface)及一膠體出光面（colloid light-exiting surface)。此外，該發光二極體晶片封裝結構 更進一步包括：一框架單元（frame unit )，其用於包覆該等 螢光膠體而只露出該等螢光膠體之側表面。 為了解決上述技術問題，根據本發明之其中一種方 案’提供一種具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝方法，其包括下列步驟： 首先，提供一基板單元（substrate unit);接著，電性地言史 200937668 置一發光單元（light-emitting unit)於該基板單元上，其中 • 該發光單元係具有複數個發光二極體晶片（LED chip)，並 • 且該等發光二極體晶片彼此之間係具有完全不同或部分不 同之間距；然後，覆蓋一封裝膠體單元（package colloid unit) 於該等發光二極體晶片上。 另外，該發光二極體晶片封裝方法更進一步包括下例 七種實施態樣： ❹ 第一種實施態樣：該封裝膠體單元係為一相對應該等 發光一極體晶片之條狀螢光膠_體（stripped fluorescent colloid) ° 第二種實施態樣：該封裝膠體單元係為一相對應該尊 發光·一極體晶片之條狀螢光膠體（stripped fluorescent colloid)，並且該條狀螢光膠體之上表面及前表面係分別具 有一膠體弧面（colloid cambered surface )及一膠體出光面 (colloid light-exiting surface)。此外，上述覆蓋該封裝滕 體單元於該等發光二極體晶片上之步驟後，更進一步包 ❹ 括：透過一框架單元（frame unit )，以包覆該條狀螢光膠體 而只露出該條狀螢光膠體之側表面。 第三種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之螢光膠體（fluorescent colloid)。 第四種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之榮光膠體（fluorescent colloid )。 此外，上述覆蓋該封裝膠體單元於該等發光二極體晶片上 之步驟後，更進一步包括：提供一具有複數個框架層之框 架單元（frame unit )，並且每一個框架層係甩於圍繞該相對 200937668 應之螢光膠體而只露出該相對應螢光膠體之上表面。 第五種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之螢光膠體（fluorescent colloid)。 此外，上述覆蓋該封裝膠體單元於該等發光二極體晶片上 之步驟後’更進一步包括：透過一框架單元（frame unit)， 以圍繞該等螢光膠體而只露出該等螢光膠體之上表面。 第六種實施態樣：該封裝膠體單元係具有複數個相對 應該等發光二極體晶片之螢光膠體（fluorescent colloid)， 並且每一個螢光膠體之上表面及前表面係分別具有一膠體 弧面（colloid cambered surface)及一膠體出光面（colloid light-exiting surface )。此外，上述覆蓋該封裝膠體單元於 該等發光二極體晶片上之步驟後，更進一步包括：提供一 具有複數個框架層之框架單元（frame unit )，並且每一個框 架層係用於包覆該相對應之螢光膠體而只露出該相對應螢 光膠體之側表面。 第七種實施態樣：該封裝膠體單元係具有複數個相對 〇 應該等發光二極體晶片之螢光膠體（fluorescent colloid)， 並且每一個螢光膠體之上表面及前表面係分別具有一膠體 弧面（colloid cambered surface)及一膠體出光面（colloid light-exiting surface)。此外，上述覆蓋該封裝膠體單元於 該等發光二極體晶片上之步驟後，更進一步包括：透過一 框架單元（frame unit )，以包覆該等螢光膠體而只露出該等 螢光膠體之侧表面。 因此，該等發光二極體晶片彼此之間係具有完全不同 或部分不同之間距，例如下列六種實施方式： 200937668 第-種實施方式.該等發光-一極體晶片彼此之間的間 距係由疏（rarefaction )到密（condensation )。 . 第二種實施方式：該等發光二極體晶片彼此之間的間 距係由密（condensation )到疏（rarefaction )。 第三種實施方式：該等發光二極體晶片彼此之間的間 距係由中間疏（rarefaction )到外圍密（condensation )。 第四種實施方式：該等發光二極體晶片彼此之間的間 q 距係由中間密（condensation )到外圍疏（rarefaction )。 第五種實施方式：該等發光二極體晶片彼此之間的間 距係為疏密（rarefaction and condensation)相間。 第六種實施方式：該等發光二極體晶片彼此之間的間 距係為密疏（condensation and rarefaction)相間。 再者’本發明係透過晶片直接封裝（Chip On Board， C〇B)製程並利用壓模（die mold)的方式，以使得本發明 可有效地縮短其製程時間，而能進行大量生產。 為了能更進一步暸解本發明為達成預定目的所採取之 技術、手段及功效，請參閱以下有關本發明之詳細說明與 附圖，相信本發明之目的、特徵與特點，當可由此得一深 入且具體之瞭解，然而所附圖式僅提供參考與說明用，並 非用來對本發明加以限制者。 【實施方式】 其分別為本發明發 種、第四種、第五 “請參閱第二A圖至第二F圖所示， 光二極體晶片之第一種、第二種、第三 種、第六種排列方式之示意圖。 200937668 由第二A圖可知，該等發光二極體晶片L 1彼此之間 的間距（al、a2、a3、a4、a5、a6、a7、a8 )係由疏（rarefaction ) 到密（condensation )。因此，該等發光二極體晶片L 1彼 此之間的間距係由大排到小（al > a2> a3 > a4 > a5> a6> a7 > a8 )。 由第二B圖可知’該等發光二極體晶片L 2彼此之間 的間距（b 1、b2、b3、b4、b5、b6、b7、b8 )係由密（condensation ) ❿ 到疏（rarefaction)。因此，該等發光二極體晶片l 2彼此 之間的間距係由大排到小（bl < b2< b3 < b4< b5 <b6<b7 <b8) 〇 由第二C圖可知，該等發光二極體晶片l 3彼此之間 的間距（cl、c2、c3、c4、c5、c6、c7、c8 )係由中間疏 (rarefaction )到外圍密（condensation )。因此，該等發光 二極體晶片L 3彼此之間的間距係由中間大排到外圍小 (c4 = c5 > c3 = c6 > c2 = c7 > cl=c8 ) 0 由第二D圖可知，該等發光二極體晶片l 4彼此之間 G 的間距（dl、d2、d3、d4、d5、d6、d7、d8 )係由中間密 (condensation )到外圍疏（rarefacti〇n )。因此，該等發光 二極體晶片L 4彼此之間的間距係由中間小排到外圍大 (d4 = d5 < d3 = d6 < d2 = d7 < d 1 =d8 )。 由第二E圖可知’該等發光二極體晶片L 5彼此之間 的 f日1 距（el、e2、e3、e4、e5、e6、e7、e8 )係為疏密（rarefacti〇n and condensation)相間。因此，該等發光二極體晶片L 5 彼此之間的間距係為大間距與小間距彼此相間（e 1 = = e5 = e7 > e2 = e4 = e6 = e8 )。 12 200937668 由第二F圖可知，該等發光二極體晶片L 6彼此之間 的間距（fl、f2、f3、f4、f5、f6、f7、f8 )係為密疏（condensation and rarefaction)相間。因此，該等發光二極體晶片L 6彼 此之間的間距係為小距離與大距離彼此相間（fl = f3 = f5 =f7 < f2 = f4 = f6 = f8 ) 〇 雖然上述係以透過晶月直接封裝（Chip On Board， COB)製程來進行該等發光二極體晶片的排列，但此描述 係非用以限定本發明，舉凡任何有關多個發光元件的排列 方式，例如使用表面黏著型（Surface Mounted Device，SMD ) 發光二極體，皆為本發明所保護之範疇。 以下共有七個實施例，此七個實施例之發光二極體晶 片的排例方式係以上述第二A圖之第一種排列方式為例來 進行說明。 請參閱第三圖、第三A圖至第三C圓、及第三D圖所 示’其中第三圖係為本發明具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝方法之第一實 Ο 施例之流程圖；第三A圖至第三C圖係分別為本發明具有 不同排列間距（different arrangement spacing )之發光二極 體晶片封裝方法之第一實施例之封裝流程示意圖；第三D 圖係為第三C圖之3 — 3剖面圖。 凊配合第三圖及第三A圖所示，本發明之第一實施例 係提供一種具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝方法，其包括下列步驟： 首先’ k供一基板單元（substrate unit) 1，其中該基板單 元係具有一基板本體（substrate body) 1 〇、及分別形成 13 200937668 於该基板本體1 〇上之一正極導電執跡（p〇sitiveelectr〇de trace) 1 1 與一負極導電執跡 “egative dectr〇de trace；) 1 2 (S200)〇 再者，依據設計者的需要，該基板單元i係可為一印 刷電路板（PCB)、一 軟基板（flexible substrate)、一 I呂基 板（aluminum substrate )、一陶瓷基板（⑽犯此）、 或一銅基板（copper substrate)。此外，該基板本體i 〇係 ❹包括一金屬層（metallayer) 1 〇 Α及—成形在該金屬層工 ◦=上之電木層（bakelitelayer) 〇 Β，並且該正、負極 導％軌跡（1 1、1 2 )係可為紹線路（aiuminumcircuit) 或銀線路（silver circuit)。 明配合第二圖及第三b圖所示，本發明之第一實施例 更進步包括：電性地設置一發光單元（丨ight_emitting unit) 2於該基板本體1 〇上，其中該發光單元2係具有複數個 ，光二極體晶片（LED chip) 2 0，並且該等發光二極體 B曰片2 〇彼此之間的間距係由疏（rarefacti〇n )到密 ❹（⑶ndensati〇n) (S202)，其中每一個發光二極體晶片2 0係具有分別電性連接於該基板單元i的正、負極導電軌 跡（.1 1 1 2 )之一正極端（positive electrode.side) 2 〇 1 與一負極端（negative electrode side) 2 0 2。 請配合第三圖、第三C圖及第三d圖所示，本發明之 第一實施例更進一步包括：覆蓋一封裝膠體單元（package colloidumt> 4 a於該等發光二極體晶片2 〇上（S206)。 再者’該封裝膠體單元4 a係為一相對應該等發光二極體 日日片 2 0 之條狀榮光膠體（str]jpped fj[u〇rescent c〇H〇id)， 200937668 並且該條狀螢光膠體係可「由一矽膠（silicon)與一螢光粉 (fluorescent powder )混合而成」或「由一環氧樹脂（epoxy ) 與一螢光粉（fluorescent powder )混合而成」。 請參閱第四圖、第四A圖至第四B圖、及第四C圖所 示’其中第四圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之第二實 施例之流程圖；第四A圖至第四B圖係分別為本發明具有 ❹ 不同排列間距（different arrangement spacing )之發光二極 體晶片封裝方法之第二實施例之部分封裝流程示意圖；第 四C圖係為第四B圖之4 — 4剖面圖。 由第四圖之流程圖中可知，第二實施例之步驟S300至 S304係分別與第一實施例之步驟S200至S204相同。亦即， 步驟S300係等同於第一實施例之第二A圖之示意圖說 明；步驟S302及S304係等同於第一實施例之第二B圖之 示意圖說明。 請參閱第四圖及第四A圖所示，本發明第二實施例之 ❹ 步驟S304之後，更進一步包括：覆蓋一封裝膠體單元 (package colloid unit) 4 b於該等發光二極體晶片2 0 上，並且該封裝膠體單元4 b之上表面及前表面係分別具 有一膠體弧面（colloid cambered surface) 4 0 b 及一膠體 出光面（colloid light-exiting surface) 4 1 b (S306)。再 者，該封裝膠體單元4 b係可為一相對應該等發光二極體 晶片 2 0 之條狀榮光膠體（stripped fluorescent colloid)， 因此該條狀螢光膠體之上表面及前表面係分別為該膠體弧 面（colloid cambered surface ) 4 Ό b 及該膠體出光面 15 200937668 (colloid light-exiting surface) 4 1 b ° . 請參閱第四圖、第四B圖及第四C圖所示，本發明第 二實施例更進一步包括：透過一框架單元（frame unit) 5 b，以包覆該封裝膠體單元4 b而只露出該封裝膠體單元 4 b之側表面（即為該膠體出光面4 1 b ) (S308 )，並且 該框架單元5 b係為一不透光框架層（opaque frame layer) ° ©請參閱第五圖、第五A圖及第五B圖所示，其中第五 圖係為本發明具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝方法之第三實施例之流程 圖；第五A圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之第三實 施例之部分封'裝流程示意圖；第五B圖係為第五A圖之5 一 5剖面圖。 由第五圖之流程圖中可知，第三實施例之步驟S400至 S404係分別與第一實施例之步驟S200至S204相同。亦即， Ο 步驟S400係等同於第一實施例之第二A圖之示意圖說 明；步驟S402及S404係等同於第一實施例之第二B圖之 示意圖說明。再者，配合第五A圖及第五B圖所示，本發 明第三實施例之步驟S404之後，更進一步包括：分別覆蓋 複數個榮光膠體（fluorescent colloid) 4 0 C於該等發光二 極體晶片2 0上（S406)，其中該等螢光膠體4 0 c係組成 一封裝膠體單元4 c。 請參閱第六圖、第六A圖至第六B圖、及第六C圖所 示，其中第六圖係為本發明具有不同排列間距（different 16 200937668 arrangement spacing )之發光二極體晶片封裝方法之第四實 施例之流程圖；第六A圖至第六B圖係分別為本發明具有 不同排列間距（different arrangement spacing )之發光二極 體晶片封裝方法之第四實施例之部分封裝流程示意圖；第 六C圖係為第六B圖之6—6剖面圖。 由第六圖之流程圖中可知，第四實施例之步驟S500至 S504係分別與第一實施例之步驟S200至S204相同。亦即， 步驟S500係等同於第一實施例之第二A圖之示意圖說 ® 明；步驟S502及S504係等同於第一實施例之第二B圖之 示意圖說明。 請參閱第六圖及第六A圖所示，本發明第四實施例之 步驟S504之後，更進一步包括：分別覆蓋複數個螢光膠體 (fluorescent colloid) 4 0 d於該等發光二極體晶片2 〇上 (S506)’其中該等螢光膠體4 0 d係組成一封裝膠體單元 4 d ;然後，提供一具有複數個框架層5 0 d之框架單元 (frame unit) 5 d，並且每一個框架層5 0 d係用於圍繞 〇 該相對應之螢光膠體4 0 d而只露出該相對應螢光膠體4 0 d之上表面（S508)’其中該等框架層5 0 d係為複數個 不透光框架層（opaque frame layer )。 請參閱第七圖、第七A圖至第七B圖、及第七C圖所 示，其中第七圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之第五實 施例之流程圖；第七A圖至第七B圖係分別為本發明具有 不同排列間距（different arrangement spacing)之發光二極 體晶片封裝方法之第五實施例之部分封裝流程示意圖；第 17 200937668 七C圖係為第七B圖之7—7剖面圖。 由第七圖之流程圖中可知，第五實施例之步驟S6〇〇至 S604係分別與第一實施例之步驟S2〇〇至S204相同。亦即， 步驟S600係等同於第一實施例之第二A圖之示意圖說 明；步驟S602及S604係等同於第一實施例之第二b圖之 不意圖說明。 請參閱第七圖及第七A圖所示，本發明第五實施例之 ❹ 步驟S604之後，更進一步包括：分別覆蓋複數個螢光膠體 (fluorescent colloid)4 0 e於該等發光二極體晶片2 〇上 (S606 ) ’其中該等螢光耀體4 〇 e係組成一封裝膠體單元 4 e，然後’透過一框架單元（frame unit) 5 e，以圍繞 該等螢光膠體4 0 e而只露出該等螢光膠體4 〇 e之上表 面（S608 )，其中該框架單元5 e係為一不透光框架層 (opaque frame layer) 〇 請參閲第八圖、第八A圖至第八B圖、及第八c圖所 示，其中第八圖係為本發明具有不同排列間距（different © arrangement spacing )之發光二極體晶片封裝方法之第六實 施例之流程圖；第八A圖至第八B圖係分別為本發明具有 不同排列間距（different arrangement spacing)之發光二極 體晶片封裝方法之第六實施例之部分封裝流程示意圖；第 八C圖係為第八B圖之8 — 8剖面圖。 由第八圖之流程圖.中可知，苐六貫施例之步驟S7〇〇至 S704係分別與第一實施例之步驟S200至S2〇4相同。亦即， 步驟S700係等同於第一實施例之第二A圖之示意圖說 明；步驟S702及S704係等同於第一實施例之第二B圖之 18 200937668 示意圖說明。 請參閱第八圖及第八A圖所示，本發明第六實施例之 步驟S704之後，更進一步包括：分別覆蓋複數個螢光膠體 (fluorescent colloid) 4 0 f於該等發光二極體晶片2 0 上，並且每一個螢光膠體4 0 f之上表面及前表面係分別 具有一膠體弧面（colloid cambered surface) 4 0 0 f 及一 膠體出光面（colloid light-exiting surface ) 4 0 1 f i (S706)。再者，該等螢光膠體4 0 f係組合成一封裝膠體 〇 單元（package colloid unit) 4 f。 請參閱第八圖、第八B圖及第八C圖所示，本發明第 六實施例更進一步包括：提供一具有複數個框架層5 0 f 之框架單元（frame unit) ，並且每一個框架層5 Of 係用於包覆該相對應之螢光膠體4 0 f而只露出該相對應 螢光膠體4 0 f之側表面（S708 )，其中該等框架層5 0 f 係為複數個不透光框架層（opaque frame layer )。 請參閱第九圖、第九A圖至第九B圖、及第九C圖所 © 示，其中第九圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之第七實 施例之流程圖；第九A圖至第九B圖係分別為本發明具有 不同排列間距（different arrangement spacing )之發光二極 體晶片封裝方法之第七實施例之部分封裝流程示意圖；第 九C圖係為第九3圖之9 — 9剖面圖。 由第九圖之流程圖中可知，第七實施例之步驟S800至 S804係分別與第一實施例之步驟S200至S204相同。亦即， 步驟S800係等同於第一實施例之第二A圖之示意圖說 19 200937668 明；步驟S802及S804係等同於第一實施例之第二B圖之 不意圖說明。 請參閱第九圖及第九A圖所示，本發明第七實施例之 步驟S804之後，更進一步包括：分別覆蓋複數個螢光膠體 (fluorescent colloid) 4 0 g於該等發光二極體晶片2 0 上，並且每一個螢光膠體40 g之上表面及前表面係分別 具有一膠體弧面（colloidcamberedsurface) 4 0 0 g及一 膠體出光面（colloid light-exiting surface ) 4 0 1 g ® (S806)。再者，該等螢光膠體4 0 g係組合成一封裝膠體 單元（package colloid unit) 4 g。 請參閱第九圖、第九B圖及第九C圖所示，本發明第 七貫施例更進一步包括：透過一框架單元（frame unit) 5 g，以包覆該等螢光膠體4 0 g而只露出該等螢光膠體4 0 g之側表面（S808 )，其中該框架單元5 g係為一不透光 框架層（opaque frame layer)。 综上所述，本發明之發光二極體晶片封裝結構係具有. ❹ 複數個發光二極體晶片，並且該等發光二極體晶片彼此之 間係具有完全不同或部分不同之間距，以符合不同使用者 之需求。 再者，本發明係透過晶片直接封裝（Chip 0n B〇ard， COB)製程ϋ利用壓模（die mold)的方式，以使得本發明 可有效地縮短其製程時間’而能進行大量生產。此外，本 發明之結構設計更適用於各種光源，諸如背光模組、裝飾 燈條、照明用燈、或是掃描器光源等應用，皆為本發明所 應用之範圍與產品。 ❹ Ο 200937668 淮以上所述，僅為本發明芒彳土夕一沾曰μ — 詳細說明與圖式，惟本發 二：施例之 以限制本發明，本發明 2並不偈限於此，並非用 圍為準，凡合於本發_ ^^應以下述之_請專利範 之實施例，皆應包含於本;;與其類似變化 藝者在本發明之領域内， ^ ’任何熟悉該項技 蓋在以下本案之專利範圍<變化或修飾皆可涵 【圖式簡單說明】 ，-圖係為習知發光二極體封裝方法之流程圖； 本發明發光二極體晶片之第-種排列方式之 第二1 =本發明發光二極體晶片之第二種排列方式之 第二c圖係為本發明發光二極體晶片 示意圖； /之弟二種排列方式之 第二D圖係為本發明發光二極體晶片 示意圖； 之弟四種排列方式之 第二E圖係為本發明發光二極體晶片 示意圖； 第五種排列方式之 第一 F圖係為本發明發光二極體晶片之笛上#上 示：S®; 種排列方式 第三圖係為本發明具f不同排列間距（撕咖 a腿ge_tsp謂g)之發光二極體晶片封装 第一實施例之流程圖； 一 21 200937668 第三A圖至第三C圖係分別為本發明具有不同排列間距 (different arrangement spacing )之發光二極體晶片 封裝方法之第一實施例之封裝流程示意圖； 第三D圖係為第三C圖之3 — 3剖面圖； 第四圖係為本發明具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝方法之 第二實施例之流程圖； 第四A圖至第四B圖係分別為本發明具有不同排列間距 ❹ （different arrangement spacing)之發光二極體晶片 封裝方法之第二實施例之部分封裝流程示意圖； 弟四C圖係為弟四B圖之4 一 4剖面圖； 第五圖係為本發明具有不同排列間距（different arrangement spacing)之發光二極體晶片封裝方法之 第三實施例之流程圖； 第五A圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之 ❹第三實施例之部分封裝流程示意圖； 第五B圖係為第五A圖之5 — 5剖面圖； 第六圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之 第四實施例之流程圖； 第六A圖至第六B圖係分別為本發明具有不同排列間距 (different arrangement spacing )之發光二極體晶片 封裝方法之第四實施例之部分封裝流程示意圖； 第六C圖係為第六B圖之6 ~ 6剖面圖； 22 200937668 第七圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之 . 第五實施例之流程圖； 第七A圖至第七B圖係分別為本發明具有不同排列間距 (different arrangement spacing )之發光二極體晶片 封裝方法之第五實施例之部分封裝流程示意圖； 第七C圖係為第七B圖之7. — 7剖面圖； - 第八圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方.法之 第六實施例之流程圖； 第八A圖至第八B圖係分別為本發明具有不同排列間距 (different arrangement spacing )之發光二極體晶片 封裝方法之第六實施例之部分封裝流程示意圖； 第八C圖係為第八B圖之8 — 8剖面圖； 第九圖係為本發明具有不同排列間距（different arrangement spacing )之發光二極體晶片封裝方法之 ❹ 第七實施例之流程圖； 第九A圖至第九B圖係分別為本發明具有不同排列間距 (different arrangement spacing )之發光二極體晶片 封裝方法之第七實施例之部分封裝流程示意圖；以 及 第九C圖係為第九B圖之9—9剖面圖。 【主要元件符號說明】 基板單元 1 基板本體 1〇 23 200937668 金屬層 電木層 正極導電軌跡200937668 IX. Description of the invention: [Technical field of the invention], (4) a polar body chip sealing structure and a packaging method thereof, in particular, a light emitting diode package structure having different spacing spacings and Its packaging method. [Prior Art] Referring to the first figure, it is a flow chart of a conventional LED package method. As can be seen from the flow private diagram, the conventional LED package method includes the steps of: firstly providing a plurality of packaged LEDs (S100); and then providing a strip substrate body (striped) The substrate body has a positive electrode trace and an anode electrode trace (S102); finally, each packaged light-emitting component is disposed in sequence. On the strip substrate body, the positive and negative terminals of each packaged LED are respectively electrically connected to the positive and negative guides of the strip substrate (S104). The above-mentioned conventional method for packaging a light-emitting diode, since each packaged LED is required to be cut from the entire package of the light-emitting wide-body package, and then the surface adhesion technology (SMT^) In the process, each of the packaged light-emitting diodes (ρ_(four) LE=) is disposed on the strip substrate body, so that the system cannot be effectively shortened (four). In addition, due to the conventional light-emitting diode The package structure does not have any protection devices. Therefore, it often causes power supply or other unstable conditions. 200937668 Therefore, it can be seen from the above that the conventional LED package method and its sealing structure are obviously inconvenient. The reason is that the inventor feels that the above-mentioned deficiency can be improved, and based on years of relevant experience in this field, carefully observed and studied, and with the use of academic theory, The present invention is designed to improve the above-mentioned deficiencies. ❹ SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a light-emitting diode package structure having different arrangement spacings and a packaging method thereof. The LED package structure of the present invention has a plurality of LED chips, and the LED chips have completely different or partially different distances from each other to meet the needs of different users. Furthermore, the present invention is through a Chip On Board (© COB) process and The die mold is used to enable the invention to effectively shorten the process time, and mass production can be performed. In addition, the structural design of the present invention is more suitable for various light sources, such as a backlight module, a decorative light bar, Applications such as illumination lamps or scanner light sources are the scope and products of the present invention. In order to solve the above technical problems, one of the solutions according to the present invention is long: for a different arrangement spacing The light emitting diode chip package structure comprises: a substrate unit, a light emitting unit (light emitting unit, and a 200937668 package colloid unit). In addition, the light emitting unit has a plurality of LED chips electrically disposed on the substrate, and the LED chips are completely different or partially different from each other. spacing. The packaged colloid unit is overlaid on the light emitting diode wafers. Furthermore, the above-mentioned light-emitting diode package structure further includes the following seven embodiments: ^ First embodiment: the package colloid unit is a strip-like phosphor colloid corresponding to a light-emitting diode chip. (stripped fluorescent colloid) ° The second embodiment: the encapsulating colloid unit is a stripped fluoro colloid corresponding to the illuminating diode wafer, and the upper surface of the strip of fluorescent colloid And the front surface system has a colloid cambered surface and a colloid light-exiting surface, respectively. In addition, the LED package structure further includes: a frame unit for covering the strip of phosphor to expose only the side surface of the strip of phosphor. In a third embodiment, the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the illuminating diode chips. A fourth embodiment: the encapsulant unit has a plurality of fluorescent colloids corresponding to the illuminating diode chips. In addition, the LED package structure further includes: a frame unit having a plurality of frame layers, and each of the frame layers is configured to expose the phase around the corresponding phosphor colloid Corresponds to the upper surface of the phosphor colloid. 200937668 A fifth embodiment: the encapsulating colloid unit has a plurality of opposing fluorescent colloids that should be aligned with the LED wafer. In addition, the LED package structure further includes: a frame unit that surrounds the phosphor colloids and exposes only the upper surface of the phosphor colloids, wherein the frame unit is An opaque frame layer ° The sixth embodiment: the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the illuminating diode chip, and each of the phosphors The upper surface and the front surface of the colloid have a colloid cambered surface and a colloidal light-exiting surface, respectively. In addition, the LED package structure further includes: a frame unit having a plurality of frame layers ′ and each of the frame layers for covering the corresponding phosphor colloid to expose only the frame Corresponding to the side surface of the phosphor colloid. According to a seventh embodiment, the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the same LED, and each of the upper surface and the front surface of the phosphor colloid has a colloid. A colloid cambered surface and a colloid light-exiting surface. In addition, the LED package structure further includes: a frame unit for coating the phosphor colloids to expose only side surfaces of the phosphor colloids. In order to solve the above technical problem, according to one aspect of the present invention, a method for packaging a light emitting diode having different arrangement spacings is provided, which comprises the following steps: First, a substrate unit is provided; Next, the electrical history 200937668 is provided with a light-emitting unit on the substrate unit, wherein the light-emitting unit has a plurality of LED chips, and the light-emitting diodes The polar body wafers are completely different or partially different from each other; and then a package colloid unit is coated on the light emitting diode wafers. In addition, the LED package method further includes the following seven embodiments: ❹ The first embodiment: the package colloid unit is a strip of phosphor corresponding to the corresponding one-pole wafer Stripped luminescent colloid ° The second embodiment: the encapsulating colloid unit is a stripped fluorescent colloid corresponding to the illuminating one-pole wafer, and the strip-like fluorescent colloid The upper surface and the front surface have a colloid cambered surface and a colloid light-exiting surface, respectively. In addition, after the step of covering the package body unit on the light-emitting diode wafers, the method further includes: passing a frame unit to cover the strip-shaped phosphor colloid to expose only the frame unit The side surface of the strip of fluorescent colloid. A third embodiment: the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the illuminating diode chips. A fourth embodiment: the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the illuminating diode chips. In addition, after the step of covering the package colloid unit on the LED chips, the method further includes: providing a frame unit having a plurality of frame layers, and each frame layer is surrounding the frame unit. Relative to the phosphorescent colloid of 200937668, only the upper surface of the corresponding phosphor colloid is exposed. A fifth embodiment: the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the illuminating diode chips. In addition, after the step of covering the encapsulating colloid unit on the LED wafers, the method further includes: transmitting a frame unit to surround the phosphor colloids and exposing only the phosphor colloids. Upper surface. A sixth embodiment: the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the equal-emitting diode chips, and each of the upper surface and the front surface of the phosphor colloid has a colloidal arc Colloid cambered surface and colloid light-exiting surface. In addition, after the step of covering the package colloid unit on the LED chips, the method further includes: providing a frame unit having a plurality of frame layers, and each frame layer is used for cladding The corresponding phosphor colloid only exposes the side surface of the corresponding phosphor colloid. A seventh embodiment: the encapsulating colloid unit has a plurality of fluorescent colloids corresponding to the illuminating diode chips, and each of the upper surface and the front surface of the phosphor colloid has a colloid A colloid cambered surface and a colloid light-exiting surface. In addition, after the step of covering the packaged colloidal unit on the light-emitting diode wafers, the method further includes: passing a frame unit to cover the phosphor colloids to expose only the phosphor colloids Side surface. Therefore, the light-emitting diode wafers have completely different or partially different distances from each other, for example, the following six embodiments: 200937668 The first embodiment: the spacing of the light-emitting diode wafers with each other From rarefaction to condensation. The second embodiment: the distance between the LED chips is from condensing to rarefaction. A third embodiment: the distance between the light-emitting diode wafers is from a rarerefration to a peripheral condensation. A fourth embodiment: the distance between the light-emitting diode wafers is from a condensation to a rarefaction. A fifth embodiment: the distance between the light-emitting diode chips is rarefaction and condensation. A sixth embodiment: the distance between the LED chips is condensed and rare. Further, the present invention is a chip on board (C〇B) process and utilizes a die mold so that the present invention can effectively shorten the process time thereof and can be mass-produced. In order to further understand the technology, the means and the effect of the present invention in order to achieve the intended purpose, refer to the following detailed description of the invention and the accompanying drawings. The detailed description is to be understood as illustrative and not restrictive. [Embodiment] They are respectively the seed, the fourth, and the fifth of the present invention. Please refer to the second, second, and third embodiments of the photodiode wafer. A schematic diagram of the sixth arrangement. 200937668 As can be seen from the second diagram A, the spacing (al, a2, a3, a4, a5, a6, a7, a8) of the LEDs L1 is separated from each other. The ratio of the light-emitting diode chips L 1 to each other is from large to small (al > a2 > a3 > a4 > a5 > a6 > a7 > A8) It can be seen from the second B diagram that the spacing (b1, b2, b3, b4, b5, b6, b7, b8) between the LEDs L2 is condensed to Therefore, the distance between the light-emitting diode wafers 12 is from large to small (bl < b2 < b3 < b4 < b5 < b6 < b7 < b8 ) As can be seen from the second C-picture, the spacing (cl, c2, c3, c4, c5, c6, c7, c8) between the LED chips 13 is from the rare to the periphery. Therefore, the distance between the light-emitting diode chips L 3 is small from the middle to the periphery (c4 = c5 > c3 = c6 > c2 = c7 > cl = c8 ) 0 2D, it can be seen that the spacing (d, d2, d3, d4, d5, d6, d7, d8) of G between the LEDs 14 is from the middle to the periphery (rarefacti). Therefore, the distance between the light-emitting diode wafers L 4 is large from the middle small row to the periphery (d4 = d5 < d3 = d6 < d2 = d7 < d 1 = d8 ). It can be seen from the second E diagram that the distances (el, e2, e3, e4, e5, e6, e7, e8) of the light-emitting diode wafers L 5 are sparse (rarefacti〇n and Therefore, the distance between the light-emitting diode wafers L 5 is such that a large pitch and a small pitch are mutually spaced (e 1 == e5 = e7 > e2 = e4 = e6 = e8 ). 12 200937668 As can be seen from the second F diagram, the pitch (fl, f2, f3, f4, f5, f6, f7, f8) between the LED chips L6 is between the condensation and rarefaction phases. Therefore, the distance between the LED chips L 6 is a small distance and a large distance from each other (fl = f3 = f5 = f7 < f2 = f4 = f6 = f8) 〇 although the above is a transmission crystal The Moon On Board (COB) process is used to perform the arrangement of the light emitting diode chips, but the description is not intended to limit the present invention, and any arrangement of the plurality of light emitting elements may be used, for example, using a surface mount type. (Surface Mounted Device, SMD) Light-emitting diodes are all protected by the present invention. There are seven embodiments in the following. The arrangement of the LED arrays of the seven embodiments is described by taking the first arrangement of the second A diagram as an example. Please refer to the third figure, the third A to the third C circle, and the third D picture. The third picture is the LED package method with different arrangement spacing of the present invention. The flow chart of the first embodiment is a schematic diagram of the package flow of the first embodiment of the method for packaging a light-emitting diode chip having different arrangement spacings according to the present invention. The third D picture is a 3 - 3 sectional view of the third C picture. As shown in FIG. 3 and FIG. 3A, the first embodiment of the present invention provides a method for packaging a light emitting diode having different arrangement spacings, which includes the following steps: First, a substrate unit 1, wherein the substrate unit has a substrate body 1 〇, and respectively forms 13 200937668 on the substrate body 1 正极 a positive conductive trace (p〇sitiveelectr〇de trace 1 1 and a negative electrode conductive trace "egative dectr〇de trace;) 1 2 (S200) 〇 Furthermore, according to the designer's needs, the substrate unit i can be a printed circuit board (PCB), a soft substrate (flexible substrate), an aluminum substrate, a ceramic substrate ((10), or a copper substrate. In addition, the substrate body i includes a metal layer 1 〇 Α和—formed in the metal layer work = bakelite layer 〇Β, and the positive and negative conductance % track (1 1 , 1 2 ) can be a The first embodiment of the present invention further includes: electrically arranging a illuminating unit 2 on the substrate body 1 Wherein the light-emitting unit 2 has a plurality of LED chips 20, and the distance between the LEDs 2 and the light-emitting diodes 2 is from sparse to n. ((3)ndensati〇n) (S202), wherein each of the light-emitting diode chips 20 has one of positive and negative conductive tracks (.1 1 1 2 ) electrically connected to the substrate unit i (positive electrode) 2 〇 1 and a negative electrode side 2 0 2 . Please cooperate with the third, third C and third d, the first embodiment of the present invention further includes: covering one A package colloidum unit is applied to the light-emitting diode chips 2 (S206). Further, the package colloid unit 4a is a corresponding one of the light-emitting diodes. Glorious colloid (str]jpped fj[u〇rescent c〇H〇id), 20 0937668 and the strip of fluorescent glue system can be "mixed with a layer of silicone and a fluorescent powder" or "mixed with an epoxy resin and a fluorescent powder" Made out." Please refer to the fourth figure, the fourth A picture to the fourth B picture, and the fourth C picture. The fourth picture is the LED package method with different arrangement spacing of the present invention. The flow chart of the second embodiment; the fourth A to the fourth B are respectively a partial package flow diagram of the second embodiment of the LED package method with different arrangement spacings of the present invention. The fourth C picture is a 4 - 4 sectional view of the fourth B picture. As can be seen from the flowchart of the fourth figure, steps S300 to S304 of the second embodiment are the same as steps S200 to S204 of the first embodiment, respectively. That is, step S300 is equivalent to the schematic diagram of the second A diagram of the first embodiment; steps S302 and S304 are equivalent to the schematic diagram of the second diagram of the first embodiment. Referring to FIG. 4 and FIG. 4A, after the step S304 of the second embodiment of the present invention, the method further includes: covering a package colloid unit 4 b to the light emitting diode chips 2 0, and the upper surface and the front surface of the encapsulating colloid unit 4 b respectively have a colloid cambered surface 4 0 b and a colloid light-exiting surface 4 1 b (S306). Furthermore, the encapsulating colloid unit 4 b can be a stripped luminescent colloid corresponding to the illuminating diode chip 20 , so that the upper surface and the front surface of the strip fluorochrome are respectively The colloid cambered surface 4 Ό b and the colloidal light emitting surface 15 200937668 (colloid light-exiting surface) 4 1 b ° . Please refer to the fourth figure, the fourth B picture and the fourth C picture, The second embodiment of the invention further includes: a frame unit 5 b is coated to cover the encapsulant unit 4 b to expose only the side surface of the encapsulant unit 4 b (ie, the colloidal surface 4 1 ) b) (S308), and the frame unit 5b is an opaque frame layer ° © Please refer to the fifth figure, the fifth A picture and the fifth B picture, wherein the fifth picture system A flow chart of a third embodiment of a method for packaging a light-emitting diode chip having different arrangement spacings according to the present invention; and a fifth embodiment of the present invention is a light-emitting diode having different arrangement spacings of the present invention. body Third embodiment the sealing portion of the sheet packaging method of Example 'means a schematic flow; a fifth line B in FIG. 5 is a cross-sectional view of a fifth 5 A of FIG. As can be seen from the flowchart of the fifth figure, steps S400 to S404 of the third embodiment are respectively the same as steps S200 to S204 of the first embodiment. That is, Ο step S400 is equivalent to the schematic diagram of the second A diagram of the first embodiment; steps S402 and S404 are equivalent to the schematic diagram of the second diagram of the first embodiment. In addition, as shown in FIG. 5A and FIG. 5B, after step S404 of the third embodiment of the present invention, the method further includes: covering a plurality of fluorescent colloids 40 C in the respective light emitting diodes. The bulk wafer 20 is on (S406), wherein the phosphor colloids 40c constitute an encapsulant unit 4c. Please refer to FIG. 6 , FIG. 6A to FIG. 6B , and FIG. 6C , where the sixth figure is a light emitting diode package with different arrangement spacing (different 16 200937668 arrangement spacing). A flow chart of a fourth embodiment of the method; and a sixth part of the sixth embodiment to a sixth embodiment of the present invention are respectively a part of the packaging process of the fourth embodiment of the method for packaging a light emitting diode having different arrangement spacings Schematic; the sixth C diagram is a 6-6 sectional view of the sixth B diagram. As can be seen from the flowchart of the sixth figure, steps S500 to S504 of the fourth embodiment are the same as steps S200 to S204 of the first embodiment, respectively. That is, step S500 is equivalent to the schematic diagram of the second diagram of the first embodiment; steps S502 and S504 are equivalent to the schematic diagram of the second diagram of the first embodiment. Referring to FIG. 6 and FIG. 6A, after step S504 of the fourth embodiment of the present invention, the method further includes: covering a plurality of fluorescent colloids for each of the light emitting diode chips. 2 〇上(S506)' wherein the phosphor colloids 40 d form an encapsulating colloid unit 4 d; then, a frame unit having a plurality of frame layers 50 d is provided for 5 d, and each The frame layer 50 d is used to surround the corresponding phosphor colloid 40 d and expose only the upper surface of the corresponding phosphor colloid 40 d (S508), wherein the frame layers 5 0 d are plural An opaque frame layer. Referring to FIG. 7 , FIG. 7A to FIG. 7B , and FIG. 7C , the seventh figure is a method for packaging a light emitting diode chip having different arrangement spacing according to the present invention. A flow chart of a fifth embodiment of the present invention; a seventh embodiment of the present invention is a schematic diagram of a part of a packaging process of a fifth embodiment of a method for packaging a light emitting diode having different arrangement spacings; The 17th 200937668 seventh C diagram is a sectional view of 7-7 of the seventh B diagram. As can be seen from the flowchart of the seventh embodiment, steps S6 to S604 of the fifth embodiment are respectively the same as steps S2 to S204 of the first embodiment. That is, step S600 is equivalent to the schematic diagram of the second A diagram of the first embodiment; steps S602 and S604 are equivalent to the second diagram of the first embodiment. Referring to FIG. 7 and FIG. 7A, after the step S604 of the fifth embodiment of the present invention, the method further includes: covering a plurality of fluorescent colloids 40 in the respective light emitting diodes. Wafer 2 〇 (S606) 'where the phosphor radiances 4 〇 e form an encapsulant unit 4 e, and then 'through a frame unit 5 e to surround the phosphor colloids 40 e Only the upper surface of the phosphor colloid 4 〇e is exposed (S608), wherein the frame unit 5 e is an opaque frame layer. Please refer to the eighth figure, the eighth figure A to the first 8B and FIG. 8C, wherein the eighth diagram is a flowchart of a sixth embodiment of a method for packaging a light emitting diode chip having different arrangement spacings according to the present invention; FIG. 8B is a partial schematic diagram of a package process of a sixth embodiment of a method for packaging a light-emitting diode package having different arrangement spacings according to the present invention; and FIG. 8C is a diagram of FIG. 8 - 8 section view. As can be seen from the flowchart of the eighth embodiment, the steps S7 to S704 of the sixth embodiment are the same as the steps S200 to S2〇4 of the first embodiment, respectively. That is, step S700 is equivalent to the schematic diagram of the second A diagram of the first embodiment; steps S702 and S704 are equivalent to the schematic diagram of 18 200937668 of the second B diagram of the first embodiment. Referring to FIG. 8 and FIG. 8A, after step S704 of the sixth embodiment of the present invention, the method further includes: covering a plurality of fluorescent colloids 40 f in the respective light emitting diode chips. 2 0, and each of the upper surface and the front surface of the phosphor colloid 40 f has a colloid cambered surface 4 0 0 f and a colloid light-exiting surface 4 0 1 Fi (S706). Furthermore, the phosphor colloids 40 f are combined into a package colloid unit 4 f. Referring to the eighth, eighth, and eighth C, the sixth embodiment of the present invention further includes: providing a frame unit having a plurality of frame layers 5 0 f , and each frame The layer 5 Of is used to coat the corresponding phosphor colloid 40f and expose only the side surface of the corresponding phosphor colloid 40f (S708), wherein the frame layer 5 0 f is a plurality of An opaque frame layer. Please refer to the ninth, ninth to ninth, and ninth, and the ninth, and the ninth, the ninth, and the second embodiment of the present invention. A flowchart of a seventh embodiment of the present invention; and a ninth embodiment to a ninth embodiment of the present invention are a schematic diagram of a partial packaging process of a seventh embodiment of a method for packaging a light-emitting diode package having different arrangement spacings. The ninth C diagram is a sectional view of 9:9, 9-9. As can be seen from the flowchart of the ninth embodiment, steps S800 to S804 of the seventh embodiment are the same as steps S200 to S204 of the first embodiment, respectively. That is, the step S800 is equivalent to the schematic diagram of the second A diagram of the first embodiment, and the steps S802 and S804 are equivalent to the second diagram of the first embodiment. Referring to FIG. 9 and FIG. 9A, after step S804 of the seventh embodiment of the present invention, the method further includes: covering a plurality of fluorescent colloids 40 g on the light emitting diode chips respectively. 20 0, and each of the upper surface and the front surface of the phosphor colloid 40 g has a colloidcambered surface 400 g and a colloid light-exiting surface 4 0 1 g ® ( S806). Furthermore, the phosphor colloids 40 g are combined into a package colloid unit 4 g. Referring to the ninth, ninth, and ninth Cth, the seventh embodiment of the present invention further includes: a frame unit 5g to cover the phosphor colloids 40. g, only the side surface of the phosphor colloid 40 g (S808) is exposed, wherein the frame unit 5 g is an opaque frame layer. In summary, the light emitting diode package structure of the present invention has a plurality of light emitting diode chips, and the light emitting diode chips have completely different or partially different distances from each other to meet The needs of different users. Furthermore, the present invention is capable of mass production by means of a chip direct package (COB) process using a die mold so that the present invention can effectively shorten the process time'. In addition, the structural design of the present invention is more suitable for various light sources, such as backlight modules, decorative light strips, illumination lamps, or scanner light sources, and is applicable to the scope and products of the present invention. ❹ Ο 200937668 The above description is only for the purpose of the present invention, but the present invention is not limited thereto, and is not limited thereto. The use of the enclosure shall prevail in the present invention. The embodiments of the patent specification shall be included in the following; and similarly different artists in the field of the invention, ^ 'any familiarity with the technique Covering the following patent scope of the present invention <variation or modification can be succinct [simplified description], the diagram is a flow chart of a conventional LED package method; the first arrangement of the LED array of the present invention The second embodiment of the second embodiment of the second embodiment of the present invention is a schematic diagram of the light-emitting diode chip of the present invention; The invention is a schematic diagram of a light-emitting diode chip; the second E-picture of the four arrangements is a schematic diagram of the light-emitting diode chip of the present invention; the first F-picture of the fifth arrangement is the light-emitting diode chip of the present invention.笛上#上上:S®; The third arrangement of the arrangement A flow chart of a first embodiment of a light-emitting diode package having different arrangement pitches of the present invention (a tear-off leg ge_tsp-g); a 21 200937668 A third to third C-pictures respectively having the present invention A schematic diagram of a package flow of a first embodiment of a method for packaging a light-emitting diode package with different arrangement spacing; a third D-picture is a 3 - 3 cross-sectional view of the third C-picture; A flow chart of a second embodiment of a light emitting diode package method having different arrangement spacing; the fourth to fourth panels are respectively different arrangement spacings of the present invention. A schematic diagram of a part of the packaging process of the second embodiment of the method for packaging a light-emitting diode chip; a fourth embodiment of the fourth embodiment of the invention is a four-fourth cross-sectional view of the fourth embodiment; the fifth figure is a different arrangement of the present invention. A flowchart of a third embodiment of a method for packaging a light-emitting diode chip; a fifth embodiment of the present invention has different arrangement spacing (different arrangement spacing) A schematic diagram of a part of the packaging process of the third embodiment of the LED package method; the fifth diagram is a 5-5 cross-sectional view of the fifth A diagram; and the sixth diagram is a different arrangement pitch of the present invention ( A flow chart of a fourth embodiment of a method for packaging a light-emitting diode package; a sixth embodiment to a sixth embodiment of the present invention are light-emitting diode chips having different arrangement spacings, respectively. A schematic diagram of a part of the packaging process of the fourth embodiment of the packaging method; the sixth C is a 6-6 cross-sectional view of the sixth B; 22 200937668 The seventh figure is the illuminating of the invention with different arrangement spacing The second embodiment of the present invention is a flowchart of the fifth embodiment. The seventh embodiment to the seventh embodiment are the fifth embodiment of the method for packaging a light-emitting diode chip having different arrangement spacings. A schematic diagram of a part of the packaging process of the embodiment; a seventh C diagram is a sectional view of the seventh diagram of the seventh diagram; - the eighth diagram is a different arrangement spacing of the invention (differ Entity arrangement of the light-emitting diode package method. The eighth embodiment to the eighth embodiment are the light-emitting diodes of the present invention having different arrangement spacings. A schematic diagram of a part of the packaging process of the sixth embodiment of the bulk wafer packaging method; the eighth C is a sectional view of the eighth embodiment of FIG. 8; and the ninth is a luminous arrangement with different arrangement spacing of the present invention. The second embodiment is a flowchart of the seventh embodiment; the ninth to the ninth bbth diagrams are respectively the seventh method of the LED package method having different arrangement spacings of the present invention. A schematic diagram of a part of the packaging process of the embodiment; and a ninth C diagram is a sectional view of 9-9 of the ninth B diagram. [Description of main component symbols] Substrate unit 1 Substrate body 1〇 23 200937668 Metal layer Electric wood layer Positive conductive track
1 0 A 1 0 B ❹ 負極導電軌跡 12 發光單元 2 發光二極體晶片 2 0 正極端 2 0 1 負極端 2 0 2 封裝膠體單元 4 a 封裝膠體單元 4 b 膠體弧面 4 0b 膠體出光面 4 1b 封裝膠體單元 4 c 螢光膠體 4 0c 封裝膠體單元 4 d 螢光膠體 4 0 d 封裝膠體單元 4 e 螢光膠體 4 0 e 封裝膠體單元 4 f 螢光膠體 4 0 f 膠體弧面 40 0 f 膠體出光面 40 1 f 封裝膠體單元 4 g 螢光膠體 4 0 g 膠體弧面 4 0 0 g 膠體出光面 4 0 1 g 框架單元 5 b 框架單元 5 d 框架層 5 0 d 框架單元 5 e 框架單元 5 f 框架層 5 0 f 框架單元 發光二極體晶片 5 g L 1 24 200937668 間距 al、a2、a3、a4、a5、a6、a7、a8 . 發光二極體晶片 L 2 間距 bl、b2、b3、b4、b5、b6 ' b7、b8 發光二極體晶片 L 3 間距 cl、c2、c3、c4、c5、c6、c7、c8 發光二極體晶片 L 4 間距 dl、d2、d3、d4、d5、d6、d7、d8 發光二極體晶片 ❹間距 L 5 el、e2、e3、e4、e5、e6、e7、e8 發光二極體晶片 L 6 間距 fl、f2、f3、f4、f5、f6、f7、f8 〇 251 0 A 1 0 B ❹ Negative Conductor Track 12 Illumination Unit 2 LED Diode Wafer 2 0 Positive Extreme 2 0 1 Negative Terminal 2 0 2 Encapsulant Unit 4 a Encapsulant Unit 4 b Colloidal Surface 4 0b Colloidal Surface 4 1b encapsulant unit 4 c fluorescent colloid 4 0c encapsulant unit 4 d fluorescent colloid 4 0 d encapsulant unit 4 e fluorescent colloid 4 0 e encapsulant unit 4 f fluorescent colloid 4 0 f colloidal arc surface 40 0 f Colloidal glazing surface 40 1 f Encapsulant colloid unit 4 g Fluorescent colloid 4 0 g Colloidal curved surface 4 0 0 g Colloidal illuminating surface 4 0 1 g Frame unit 5 b Frame unit 5 d Frame layer 5 0 d Frame unit 5 e Frame unit 5 f frame layer 5 0 f frame unit light-emitting diode wafer 5 g L 1 24 200937668 spacing a1, a2, a3, a4, a5, a6, a7, a8. light-emitting diode wafer L 2 spacing bl, b2, b3 , b4, b5, b6 ' b7, b8 light-emitting diode wafer L 3 pitch cl, c2, c3, c4, c5, c6, c7, c8 light-emitting diode wafer L 4 spacing dl, d2, d3, d4, d5 , d6, d7, d8 light-emitting diode wafer spacing L 5 el, e2 e3, e4, e5, e6, e7, e8 emitting diode chip spacing L 6 fl, f2, f3, f4, f5, f6, f7, f8 square 25