200935585 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有 — 窗口型半導體封裝構造及其堆疊結構。 …種可堆# 【先前技術】 面積當二路載板越來越小時’其表面可供安裝元件的 目前有人提出可以將多個窗口型半導體封 裝構故相互縱向堆疊，以節省佔據在印刷 接.坎怂—《 电塔板上的面 積，其係在多個習知窗口型半導體封裝構造之間以複數 個銲球縱向電性連接該些窗口型半導體封裝冑造。而採 用銲球除了會有斷裂問題外，銲球必須變大才可提供足 夠堆疊間隔，除了會有掉球之問題，並且該窗口型半導 體封裝構造並無法達到高密度端子數之要求。此外，在 迴銲銲球（Solder Reflow)以進行時封裝堆疊時，易有封 裝位移偏斜的問題。 明參閲第1圖所示，一種習知窗口型半導體封裝構 造100係包含一基板110、一晶片12〇、複數個電性連 接元件130、一模封膠體14〇以及複數個銲球15〇。該 基板no係具有一上表面ln、一下表面112以及一槽 孔113。該晶片120係設置於該基板11〇之該上表面 並具有複數個銲墊123。藉由該些電性連接元件13〇通 過該槽孔113以電性連接該些銲墊123至該基板11〇之 該下表面112。該模封膠體14〇係局部覆蓋該基板uo 之該上表面111以密封該晶片12〇,並且該模封膠體！4〇 200935585 更填入該槽孔113並突出於該基板11()之該下表面ι12 以密封該些電性連接元件13〇。該些銲球15〇係設置於 該基板110之該下表面112，以供該窗口型半導體封裝 構造100可接合至一電路载板（圖未繪出）或是堆疊接合 至另一窗口型半導體封裝構造1〇〇之基板11〇之上表面 111(如第2圖所示）。 請參閱第2圖所示’多個習知窗口型半導體封裝構 造100係相互堆疊並藉由該些銲球15〇電性連接位於較 © 下方之窗口型半導體封裝構造100。在進行封裝堆疊 時，該些ip球150需經過一道迴銲（Refi〇w)步驟才可銲 接至另一窗口型半導體封裝構造1〇〇。然而，在迴銲過 程中，該些銲球15〇會熔融，而造成位於上方之窗口型 半導體封裝構造100產生位移或是歪斜之情況，當位移 或傾斜之角度過大時，會導致部分銲球被拉長變形而無 法確實連接位於下方之窗口型半導體封裝構造100，甚 Φ 至會造成位於上方之窗口型半導體封裝構造1〇〇發生 掉球之情況，而導致電性連接不良或斷路等問題，進而 降低產品之可靠性。 【發明内容】 本發明之主要目的係在於提供一種可堆疊窗口型半導體 封裝構造及其堆疊結構’達到貫穿在模封膠體之上下電性導 通’符合高密度端子數與穩固的封裝堆疊。並能取代習知窗 口型半導體封裝構造之銲球進行封裝堆疊而不會有掉球與 歪斜的問題。 200935585 本發明之次-目的係在於提供—種可堆疊窗口型半導體 封裝構造及其堆#結構，可符合高密度端子數封裝堆疊之需 求並且不需要增加元件以達到水平穩固，以控制在—較 確之封裝堆疊厚度。 ‘ 本發明的目的及解決其技術問題是採用以下技術方案來 實現的。依據本發明之-種可堆疊窗口型半導體封裝構造， 主要包含-基板、一晶片、複數個電性連接元件、一模封膠 〇體以及複數個導體柱。該基板係具有一上表面、一下表面： 一槽孔以及複數個周邊外接墊。該晶片係設置於該基板之該 上表面並具有複數個料。該些t性連接元件係通過該槽孔 以使該晶片t該些銲墊電性連接至該基板之該些周邊外接 墊。、該模封膠體係主要形成於該基板之該上表面，並具有突 出於該下表面之一中央封膠條以及複數個側封膠體，其中該 中央封穋條係覆蓋該槽孔並密封該些電性連接元件，該些侧 封膠體係覆蓋該些周邊外接堅。該些導體柱係對準於該些周 ® 邊外接墊並貫穿該模封膠體在該基板之該上表面上的部 位、該基板以及該些側封膠體。 在前述之可堆疊窗口型半導體封裝構造中，該些侧封膠 體係可具有與該令央封膠條大致為共平面之疊置表面。 在前述之可堆疊窗口型半導體封裝構造中，該些侧封膠 體係可包含複數個絕緣凸塊。 在前述之可堆疊窗口型半導體封裝構造中，該些側封膠 係可為條狀並與該中央封膠條大致平行配置。 在前述之可堆疊窗口型半導體封裝構造中，該些電性連 200935585 接元件係可包令％ 復數個銲線，其中該些録線之弧高係不 超過該中央封膠條。 在前述之可始 堆且窗口型半導體封裝構造中，該模封膠體 係可完全密封該晶片。 在前述之可土合基办 *營由口型半導體封裝構造中，該晶片係可 具有顯露於該模封膠體之一背面。 【實施方式】 I本發明之第一具體實施例，配合參閱第315圖揭示 «可堆疊窗口型半導體封裝構造。請參閱第3圖所示，一 種可堆疊® α型半導體封裝構造，主要包含—基板m 曰曰片220、複數個電性連接元件230、一模封膠體240以 及複數個導體柱250。該基板210係具有一上表面211、一 下表面212、一槽孔213以及複數個周邊外接墊214。該基 板210係可適用於「晶片在基板上」之窗口型封裝型態，藉 由該貫穿該上表面211與該下表面212之槽孔213,以供如 φ 打線連接等方式達到該晶片22〇與該基板21〇之電性連接。 該些周邊外接墊214係位於該基板210之該下表面212之周 邊’可位於兩相對側邊或四周側邊。 請參閱第3圖所示，該晶片220係設置於該基板21〇之 該上表面211。該晶片220係可為高頻記憶體晶片或其他積 體電路晶片。該晶片220係具有一主動面221與一相對之背 面222並具有複數個銲墊223，該些銲墊223係位於該主動 面221之中央區域並可為雙排銲墊，但亦可為單排排列。通 常係以一黏晶層260’例如雙面黏著膠帶或B階膠體，將該 200935585 晶片220之該主動面221黏貼至該基板21〇之該上表面 211，並使該些銲墊223係對準於該槽孔213内，以供後續 電性連接。 該些電性連接元件230係通過該槽孔213以使該晶片22〇 之該些銲墊223電性連接至該基板21〇之該些周邊外接墊 214。具體而言，該些銲墊223係藉由該些電性連接元件 連接至該基板210之該下表面212之接指（圖未繪出），再經 由該基板210本身之内線路層將電訊傳導至該些周邊外接墊 © 214，達到該晶片220與該基板210之電性互連。 請參閱帛3圖所*，純封膠體24〇係主要形成於該基 板210之該上表面211，並具有突出於該下表面212之一中 央封膠條241以及複數個侧封膠體242，其中該中央封膠條 241係覆蓋該槽孔213並密封該些電性連接元件23〇，該些 側封膠體242係覆蓋該些周邊外接墊214。#由該些側封勝 體242使該模封膠體240係完全覆蓋該基板21〇之該下表面 ❹212之侧邊，以提供封裝堆疊之兩侧支撑，以在封裝堆疊時 維持較佳的水平面’此外亦有助於兩側模流平衡，避免在填 充該槽孔213以形成該中央封膠條241時產生中央模流速度 過快而導致溢膠。在本實施例中，該模封膠體謂係可完全 密封該晶片220。再如第3圃私― _ , 弟3圖所不’該些電性連接元件23〇 係可包含複數個銲線’其中該些銲線之弧高係不超過該中央 封膠條24Ρ以避免該些銲線外露造成電性短路。較佳地， 該些側封膠體242係、可具有與該中央封勝條241大致為共平 面之整置表面(如第3圖之水平虛線所示），以避免因堆叠歪 10 200935585 斜所導致電性連接不完整之問題。請參閱第4圖所示，該此 侧封膠體242係可包含複數個絕緣凸塊，該些侧封膠體242 係不遮蓋該些導體柱250,故可藉由該些導體柱25〇在該可 堆疊窗口型半導體封裝構造200與堆疊於另一可堆疊窗口型 半導體封裝構造200之間提供縱向的電性連接（如第5圖所 請再參閲第3圖所示 ❹ 邊外接墊214並貫穿該模封膠體24〇在該基板21〇之該上^ 面211上的部位、該基板21〇以及該些側封膠體242，達至 貫穿在該模封膠體240之上下電性導通。該些導體柱25〇 ^ 材質係可為具有良好導電性與導熱性較佳的金屬，例如鋼 因此，該些導體柱250不僅能達到貫穿在該模封膠體2仂之 上下電性導通以符合高密度端子數之封裝堆疊之需求，配会 該些側封膠體242能取代習知窗口型半導體封裝構造之銲球 進行封裝堆疊而不會有掉球與歪斜的問題。由於本發明之該 可堆疊窗口型半導體封裝構造2〇〇不需使用習知鲜球之迴鲜 步驟以達到電性連接之目的，於封裝堆疊時將具有較佳的水 平面與穩1U性（如第5圖所示），更可控制在_較為準確之封 裝堆曼厚度。此外，如第4圖所示，在該基板21〇之該下表 面212無需設置球墊，故即使該模封谬體24 會影響電性連接之品質。 屋生溢膠也不 本發明進-步揭示—種前述之可堆#窗口 構造細之堆疊結構導體封裝 包含複數個如前所述之圖所不，該堆叠結構主要 所述之可堆疊窗口型半導體封裝構造200、 200935585BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a window type semiconductor package structure and a stacked structure thereof. ... Kind of stacking # [Prior Art] Area when the two-way carrier board is getting smaller and smaller 'The surface is available for mounting components. It has been proposed that multiple window-type semiconductor package structures can be stacked vertically with each other to save occupation in the printed interface.怂 怂 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 《 。 。 In addition to the problem of cracking in the use of solder balls, the solder balls must be enlarged to provide sufficient stacking spacing, in addition to the problem of falling balls, and the window-type semiconductor package structure cannot meet the requirements for high-density terminals. In addition, when the solder ball (Solder Reflow) is packaged for stacking, there is a problem that the package displacement is skewed. Referring to FIG. 1 , a conventional window-type semiconductor package structure 100 includes a substrate 110 , a wafer 12 , a plurality of electrical connection elements 130 , a molding compound 14 , and a plurality of solder balls 15 . . The substrate no has an upper surface ln, a lower surface 112, and a slot 113. The wafer 120 is disposed on the upper surface of the substrate 11 and has a plurality of pads 123. The pads 123 are electrically connected to the lower surface 112 of the substrate 11 through the slots 113. The molding compound 14 is partially covering the upper surface 111 of the substrate uo to seal the wafer 12, and the molding compound! 4〇 200935585 is further filled into the slot 113 and protrudes from the lower surface ι12 of the substrate 11 () to seal the electrical connecting elements 13A. The solder balls 15 are disposed on the lower surface 112 of the substrate 110 for the window type semiconductor package structure 100 to be bonded to a circuit carrier (not shown) or stacked to another window type semiconductor. The upper surface 111 of the substrate 11 of the package structure 1 (as shown in Fig. 2). Referring to Fig. 2, a plurality of conventional window-type semiconductor package structures 100 are stacked on each other and electrically connected to the window-type semiconductor package structure 100 located below the solder balls 15 . During the package stacking, the ip balls 150 are subjected to a reflow process to be soldered to another window type semiconductor package structure. However, during the reflow process, the solder balls 15 熔融 melt, causing displacement or skew of the window-type semiconductor package structure 100 located above, and when the angle of displacement or tilt is too large, a partial solder ball is caused. The window-type semiconductor package structure 100, which is stretched and deformed, cannot be reliably connected to the window-type semiconductor package structure 100, so that the window-type semiconductor package structure located above will be dropped, resulting in poor electrical connection or open circuit. , thereby reducing the reliability of the product. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a stackable window-type semiconductor package structure and a stacked structure thereof that achieve electrical conduction through a high-density terminal and a stable package stack. It can replace the solder ball of the conventional window type semiconductor package structure for package stacking without the problem of ball drop and skew. 200935585 The second and second object of the present invention is to provide a stackable window type semiconductor package structure and a stack structure thereof, which can meet the requirements of high-density terminal number package stacking and does not need to add components to achieve water-stable solidity to control Make sure the package thickness is packaged. The purpose of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a stackable window type semiconductor package structure mainly comprises a substrate, a wafer, a plurality of electrical connection elements, a mold encapsulation body, and a plurality of conductor columns. The substrate has an upper surface and a lower surface: a slot and a plurality of peripheral lands. The wafer is disposed on the upper surface of the substrate and has a plurality of materials. The t-connecting elements pass through the slots to electrically connect the pads to the peripheral lands of the substrate. The molding compound system is mainly formed on the upper surface of the substrate, and has a central sealing strip protruding from the lower surface and a plurality of side sealing bodies, wherein the central sealing strip covers the slot and seals the hole Electrically connecting components, the side sealant systems covering the peripheral outer joints. The conductor posts are aligned with the peripheral rim pads and extend through the portion of the molding compound on the upper surface of the substrate, the substrate, and the side seals. In the foregoing stackable window type semiconductor package construction, the side sealant systems may have an overlay surface that is substantially coplanar with the center sealant strip. In the foregoing stackable window type semiconductor package construction, the side sealant systems may comprise a plurality of insulating bumps. In the foregoing stackable window type semiconductor package construction, the side sealants may be strip-shaped and disposed substantially parallel to the central sealant strip. In the foregoing stackable window type semiconductor package structure, the electrical connections 200935585 can be used to enclose a plurality of bonding wires, wherein the arc lines of the recording lines do not exceed the central sealing strip. In the foregoing stackable and window type semiconductor package construction, the mold sealant can completely seal the wafer. In the above-described organic semiconductor package structure, the wafer system may have a back surface exposed on one of the mold sealing bodies. [Embodiment] A first embodiment of the present invention, together with reference to FIG. 315, discloses a "stackable window type semiconductor package structure. Referring to FIG. 3, a stackable® α-type semiconductor package structure mainly includes a substrate m cymbal 220, a plurality of electrical connection elements 230, a molding compound 240, and a plurality of conductor posts 250. The substrate 210 has an upper surface 211, a lower surface 212, a slot 213, and a plurality of peripheral ferrules 214. The substrate 210 is applicable to a window-type package type of "wafer on the substrate", and the wafer 22 is penetrated by the upper surface 211 and the lower surface 212 of the lower surface 212 for connection to the wafer 22 by φ wire bonding or the like. 〇 is electrically connected to the substrate 21〇. The peripheral ferrules 214 are located on the periphery of the lower surface 212 of the substrate 210 and may be located on opposite sides or sides. Referring to Fig. 3, the wafer 220 is disposed on the upper surface 211 of the substrate 21A. The wafer 220 can be a high frequency memory chip or other integrated circuit chip. The wafer 220 has an active surface 221 and an opposite back surface 222 and has a plurality of pads 223. The pads 223 are located in a central region of the active surface 221 and may be double-row pads, but may also be single. Arranged in rows. Generally, the active surface 221 of the 200935585 wafer 220 is adhered to the upper surface 211 of the substrate 21 by a bonding layer 260' such as a double-sided adhesive tape or a B-stage colloid, and the pads 223 are paired. It is within the slot 213 for subsequent electrical connection. The electrical connection elements 230 pass through the slots 213 to electrically connect the pads 223 of the wafer 22 to the peripheral lands 214 of the substrate 21 . Specifically, the pads 223 are connected to the contacts (not shown) of the lower surface 212 of the substrate 210 by the electrical connection elements, and the telecommunication is provided through the circuit layer inside the substrate 210 itself. Conducted to the peripheral ferrules 214 to electrically interconnect the wafer 220 with the substrate 210. Referring to FIG. 3, the pure encapsulant 24 is mainly formed on the upper surface 211 of the substrate 210, and has a central sealing strip 241 protruding from the lower surface 212 and a plurality of side sealing bodies 242, wherein The central sealing strip 241 covers the slot 213 and seals the electrical connecting elements 23 , and the side sealing bodies 242 cover the peripheral outer pads 214 . The side seals 242 are completely covered by the side seals 242 to completely cover the sides of the lower surface 212 of the substrate 21 to provide support on both sides of the package stack to maintain a better horizontal level during package stacking. 'In addition, it also contributes to the balance of the flow of the two sides, avoiding the excessive flow rate of the central mold flow when filling the slot 213 to form the central sealing strip 241, resulting in overflow. In the present embodiment, the molding compound is said to completely seal the wafer 220. Another example is that the third electrical connector _, the younger brother does not include the plurality of bonding wires, wherein the arc height of the bonding wires does not exceed the central sealing strip 24 to avoid These wire bonds are exposed to cause an electrical short circuit. Preferably, the side seal bodies 242 can have an entire surface that is substantially coplanar with the central seal strip 241 (as indicated by the horizontal dashed line in FIG. 3) to avoid skewing due to stacking 200910 200935585 The problem of incomplete electrical connection. As shown in FIG. 4 , the side sealant 242 can include a plurality of insulating bumps, and the side seals 242 do not cover the conductor posts 250 , so that the conductor posts 25 can be The stackable window type semiconductor package structure 200 and the stacked stackable window type semiconductor package structure 200 provide a longitudinal electrical connection (as shown in FIG. 5, please refer to the edge outer pad 214 shown in FIG. The portion of the mold encapsulant 24 on the upper surface 211 of the substrate 21, the substrate 21 and the side seal 242 are electrically connected to the mold encapsulation 240. The conductor posts 25 〇 ^ material can be a metal having good conductivity and thermal conductivity, such as steel. Therefore, the conductor posts 250 can not only achieve electrical conduction through the molding compound 2 以 to meet the high The requirement of the package stack of the number of the density terminals is such that the side sealant 242 can replace the solder balls of the conventional window type semiconductor package structure for package stacking without the problem of ball drop and skew. Since the present invention can be stacked Window type semiconductor package structure 2 〇〇You don't need to use the freshening step of the fresh ball to achieve the purpose of electrical connection. It will have a better horizontal plane and stable 1U when packaged and stacked (as shown in Figure 5), and can be controlled at _ The package thickness is accurately packaged. Further, as shown in Fig. 4, the lower surface 212 of the substrate 21 is not required to be provided with a ball pad, so that the molded body 24 may affect the quality of the electrical connection. The glue is also not disclosed in the present invention. The above-mentioned stackable structure has a fine structure. The stacked structure conductor package comprises a plurality of the above-mentioned figures. The stacked structure mainly has the stackable window type semiconductor package structure. 200, 200935585
一電路載板10以及複數個外接端子2〇〇該電路載板1〇係具 有一頂面11以及一相對之底面12,該頂面n係形成有複數 個接墊13，該些接墊13係位於該電路載板1〇之兩相對側。 請參閱第5圖所示，該些可堆疊窗口型半導體封裝構造2〇〇 係疊設於該電路載板1〇之該頂面u並藉由該些導體柱25〇 電性導通至該電路載板丨〇之該些接墊13，以達到該些可堆 疊窗口型半導體封裝構造200與該電路載板1〇之電性互 連。該些可堆疊窗口型半導體封裝構造2〇〇係為縱向堆疊， 位於較下方之可堆疊窗口型半導體封裝構造2〇〇係藉由該些 導體柱250與位於較上方之可堆疊窗口型半導體封裝構造 200之該些導體柱25〇電性連接，亦可與位於下方之可堆疊 窗口型半導體封裝構造200之該些導體柱25〇電性連接或與 該電路載板10之該些接墊13連接。具體而論，每一可堆疊 窗口型半導體封裝構造綱可另包含有點著材们其係形 成於該中央封膠條241與該些側封膠體242之間，以黏接下 方的另一可堆叠窗口型半導體封裝構造2〇〇或該電路載板 10。該些外接端子20係設置於該電路載板1〇之該底面12。 、由上述可知，該些可堆疊窗口型半導體封裝構造200在 封裝堆疊過程中’藉由該些導體柱25〇與被貫穿之側封膠體 242取代習知銲球。位於較上方之可堆叠窗口型半導體封裝 冓迨200之該些導體柱25〇係直接連接位於較下方之可堆疊 ^口型半導體封裝構造·，符合高密度端子數與穩固的封 :堆疊°因此’能取代習知窗口型半導體封裝構造之鲜球進 仃封裝堆4^會有掉球與歪斜的_，亦可縮短該些可堆 12 200935585 疊窗口型半導體封裝構造200之間電氣連接的長度，以降低 該些可堆疊窗口型半導體封裝構造2〇〇之間因訊號傳遞路徑 太長而導致延遲的現象。 在本發明之第二具體實施例中，請參閱第6圖所示，揭 示另一種可堆疊窗口型半導體封裝構造300主要包含一基板 31〇、一晶片320、複數個電性連接元件330、一模封膠體340 以及複數個導體柱3 50。該基板310係具有一上表面311、 一下表面312、一槽孔313以及複數個周邊外接墊314。該 © 晶片320係設置於該基板310之該上表面311並具有複數個 鲜塾323。該些銲墊323係形成於該晶片32〇之一主動面 321 ’且對準於該基板31〇之該槽孔313内，而例如銲線之 該些電性連接元件330係通過該槽孔3 13以使該晶片32〇之 該些銲墊323電性連接至該基板31〇，並經由該基板31〇之 線路電性連接至該些周邊外接墊314。在本實施例中，該晶 片320係可具有顯露於該模封膠體34〇之一背面π],故該 ❹模封膠體340係不完全密該晶片32〇，以增加散熱。該模封 膠體340係主要形成於該基板31〇之該上表面，並具有 突出於該下表面312之一中央封膠條341以及複數個側封膠 體342 ’其中該中央封膝條341係覆蓋該槽孔313並密封該 些電性連接件330，該些側封膠體342係覆蓋該些周邊外 接塾314。請參閱第7圖所示，在本實施例中，該些側封膠 體342係可為條狀並與該中央封膠條341大致平行配置，以 增進模流填充。該些側封膠體342之寬度係可小於該中央封 膠條341之寬度。 13 200935585 ❹A circuit carrier board 10 and a plurality of external terminals 2, the circuit carrier board 1 has a top surface 11 and an opposite bottom surface 12, the top surface n is formed with a plurality of pads 13, and the pads 13 It is located on the opposite side of the circuit carrier 1〇. Referring to FIG. 5, the stackable window type semiconductor package structure 2 is stacked on the top surface u of the circuit carrier 1 and electrically connected to the circuit by the conductor posts 25 The pads 13 are mounted on the carrier to electrically interconnect the stackable window-type semiconductor package structure 200 with the circuit carrier 1 . The stackable window type semiconductor package structure 2 is a vertical stack, and the lower stackable window type semiconductor package structure 2 is formed by the conductor posts 250 and the upper stackable window type semiconductor package The conductor posts 25 of the structure 200 are electrically connected to each other, or may be electrically connected to the conductor posts 25 of the stackable window type semiconductor package structure 200 located below or to the pads 13 of the circuit carrier board 10. connection. In particular, each of the stackable window-type semiconductor package structures may further comprise a plurality of materials formed between the central sealant strip 241 and the side sealants 242 to adhere to another stackable underneath. A window type semiconductor package structure 2 or the circuit carrier board 10. The external terminals 20 are disposed on the bottom surface 12 of the circuit carrier 1 . As can be seen from the above, the stackable window type semiconductor package structures 200 replace the conventional solder balls by the conductor posts 25 and the through side sealants 242 during the package stacking process. The conductor posts 25 located on the upper stackable window type semiconductor package 200 are directly connected to the lower stackable semiconductor package structure, conforming to the high-density terminal number and the stable package: stacking 'Can replace the conventional window-type semiconductor package structure of the fresh ball into the package stack 4 ^ will drop the ball and skew _, can also shorten the length of the electrical connection between the stackable 12 200935585 stacked window-type semiconductor package structure 200 In order to reduce the delay caused by the signal transmission path being too long between the stackable window type semiconductor package structures 2〇〇. In the second embodiment of the present invention, as shown in FIG. 6, another stackable window type semiconductor package structure 300 is disclosed. The main structure includes a substrate 31, a wafer 320, and a plurality of electrical connecting elements 330. The molding compound 340 and the plurality of conductor posts 3 50. The substrate 310 has an upper surface 311, a lower surface 312, a slot 313, and a plurality of peripheral ferrules 314. The © chip 320 is disposed on the upper surface 311 of the substrate 310 and has a plurality of fresh dies 323. The pads 323 are formed on one of the active faces 321' of the wafer 32 and aligned in the slots 313 of the substrate 31, and the electrical connecting elements 330 such as bonding wires pass through the slots. The pads 323 of the wafer 32 are electrically connected to the substrate 31 , and are electrically connected to the peripheral pads 314 via the wires of the substrate 31 . In this embodiment, the wafer 320 may have a back surface π] exposed on the one of the mold seals 34, so that the mold seal 340 is not completely dense with the wafer 32 to increase heat dissipation. The molding compound 340 is mainly formed on the upper surface of the substrate 31, and has a central sealing strip 341 protruding from the lower surface 312 and a plurality of side sealing bodies 342', wherein the central sealing strip 341 is covered The slot 313 seals the electrical connectors 330, and the side seals 342 cover the peripheral rims 314. Referring to Figure 7, in the present embodiment, the side seals 342 may be strip-shaped and disposed substantially parallel to the central seal strip 341 to enhance mold flow filling. The width of the side sealant 342 can be less than the width of the central seal strip 341. 13 200935585 ❹
請參閱第6圖所示，該可堆疊窗口型半導體封裝構造3〇〇 更具有複數個貫通孔370，其係對準於該些周邊外接墊314 並貫穿該於該模封膠體340在該基板31〇之該上表面311的 部位、該基板310以及該些側封膠體342。該些貫通孔37〇 之形成方式係可選用雷射鑽孔或是反應性離子蝕刻 (Reactive I〇n Etching，RIE)。請參閲第7圖所示較佳地， 該些貫通孔370係可為交錯排列，以符合高密度端子之周邊 排列。請參閱第8圖所示，該些導體柱35〇係穿設於該些貫 通孔370内，更詳細地說’該些導體柱35〇係對準於該些周 邊外接墊314並貫穿該模封膠體34〇在該基板31〇之該上表 面311上的部位、該基板31〇以及該些側封膠體Μ]。因此， 該可堆疊窗π型半導體封裝構造3⑽能達到貫穿在該模封膠 體340之上下電性導通並取代習知窗口型半導體封裝構造之 銲球進行封裝堆疊而不會有掉球與歪斜的問題，藉以控制在 厚度較薄、較準確與更為水平的封裝堆疊。 該可堆疊窗口型半導體封裝構造3〇〇能作為多個可堆疊 窗口型半導體封裝構造堆疊時之縱向堆疊之要求。請參閱^ 8圖所示，該些可堆#窗σ型半導體封裝構造则係疊設於 -電路載板4〇之頂面41，每—可堆疊窗口型半導體封裝構 造300係可另包含有黏著材料5()，其係形成於該中央封谬條 341與該些侧封膠體342之間，以黏接下方的另一可堆疊窗 口型半導體封裝構造300或該電路載板4〇。其中，該電路載 板40係具有複數個結合？L43，可為貫穿或半貫冑，以μ 些導體柱350之插接。而該些結合孔43之位置係對準於每 14 200935585 -可堆#窗π型封裝構造之該些貫通孔37G。該些可堆叠窗 口型半導體封裝構造300係藉由該些導體纟35()電性導通至 該電路载板40,以使該些可堆叠窗口型半導體封裝構造3〇〇 與該電路載板40能相互電性連接。在本實施例中，該些可 堆疊窗口型半導體封裝構造扇中垂直對應之該些導體柱 350係可為—體連接。在封裝疊堆疊時可以先行定位與黏著 複數個可堆疊窗口型半導體封裝構造_，再以該些導體柱 350同時穿設於每_可堆疊窗口型半導體封裝構造卿之該 些貫通孔370至該電路載板4()之該些結合孔43。該些導體 柱350係可突出於該電路載板4〇之該底面42，以供對外接 合。 以上所述，僅是本發明的較佳實施例而已，並非對本發 月作任何形式上的限制，本發明技術方案範圍當依所附申請 專利範圍為準。任何熟悉本專業的技術人員可利用上述揭示 、技術内>作出些^更動或修飾為等同變化的等效實施 鲁例，但凡是未脫離本發明技術方案㈣容，依據本發明的技 術實質對以上實施例所作的任何簡單修改、等同變化與修 飾，均仍屬於本發明技術方案的範圍内。 【圖式簡單說明】 第1圖：一種習知可堆疊窗口型半導體封裝構造之截面 示意圖。 第2圖：複數個習知可堆疊窗口型半導體封裝構造縱向 堆疊之截面示意圖。 第3圓：依據本發明之第一具體實施例，一種可堆疊窗口 15Referring to FIG. 6 , the stackable window type semiconductor package structure 3 further includes a plurality of through holes 370 aligned with the peripheral external pads 314 and penetrating the mold sealing body 340 on the substrate. 31. The portion of the upper surface 311, the substrate 310, and the side seals 342. The through holes 37 are formed by laser drilling or reactive ion etching (RIE). Preferably, as shown in Fig. 7, the through holes 370 may be staggered to conform to the peripheral arrangement of the high density terminals. Referring to FIG. 8 , the conductor posts 35 are threaded through the through holes 370 . In more detail, the conductor posts 35 are aligned with the peripheral outer pads 314 and penetrate the mold. The sealing body 34 is located on the upper surface 311 of the substrate 31, the substrate 31〇, and the side seals. Therefore, the stackable window π-type semiconductor package structure 3 (10) can be electrically connected to the die-bonding body 340 and replace the solder ball of the conventional window-type semiconductor package structure for package stacking without dropping or skewing. The problem is to control the stacking of packages that are thinner, more accurate, and more horizontal. The stackable window type semiconductor package structure 3 can be required as a vertical stack when stacking a plurality of stackable window type semiconductor package structures. Referring to FIG. 8, the stackable window sigma type semiconductor package structure is stacked on the top surface 41 of the circuit carrier board 4, and each of the stackable window type semiconductor package structures 300 may further include An adhesive material 5 () is formed between the central sealing strip 341 and the side sealing bodies 342 to adhere to another stackable window-type semiconductor package structure 300 or the circuit carrier 4 below. Wherein, the circuit carrier 40 has a plurality of combinations? L43, which may be a through or a semi-transparent 胄, with a plug of some conductor posts 350. The positions of the bonding holes 43 are aligned with the through holes 37G per 14 200935585 - stackable window π-type package structure. The stackable window type semiconductor package structure 300 is electrically connected to the circuit carrier 40 by the conductors 35 ( ) such that the stackable window type semiconductor package structures 3 and the circuit carrier 40 Can be electrically connected to each other. In this embodiment, the plurality of conductor posts 350 vertically corresponding to the stackable window type semiconductor package construction fan may be a body connection. In the package stacking, the plurality of stackable window type semiconductor package structures can be positioned and adhered first, and the conductive pillars 350 are simultaneously disposed in the through holes 370 of each of the stackable window type semiconductor package structures. The bonding holes 43 of the circuit carrier 4 (). The conductor posts 350 are protruded from the bottom surface 42 of the circuit carrier 4 for external engagement. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is subject to the scope of the appended claims. Any person skilled in the art can make use of the above disclosure, the technology, and the equivalent implementation of the equivalent embodiment, but without departing from the technical solution of the present invention, the technical essence according to the present invention is Any simple modifications, equivalent changes and modifications made by the above embodiments are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional stackable window type semiconductor package structure. Figure 2 is a cross-sectional view of a plurality of conventional stackable window type semiconductor package structures in a longitudinal stack. Third Circle: According to a first embodiment of the present invention, a stackable window 15
200935585 型半導體封裝構造之戴面示意圖。 第4圖：依據本發明之第-具體實施例，該可堆疊窗口 半導體封裝構造之基板下表面示意圖。 第5圖.依據本發明之第—具體實施例，複數個可堆疊 口型半導體封裝構造縱向堆疊並接合至一電 載板之截面示意圖。 第6圖··依據本發明之第二具體實施例，另〆種可堆叠 ^ 口型半導體封裝構造之截面示意圖。 第7圖依據本發明之第二具體實施例，該可堆疊窗口 半導體封裝構造之基板下表面示意圖。 第圖依據本發明之第二具體實施例，多個可堆疊窗 型半導體封裝構造縱向堆疊並接合至一電路 板之截面示意圖。 【主要元件符號說明】 型 窗 路 窗 型 P 載 10 電路載板 11 頂面 12 底面 13 接墊 20 外接端子 30 黏著材料 40 電路載板 41 頂面 42 底面 43 結合孔 50 黏著材料 100 窗口型半導體封裝構造 110 基板 111 上表面 112 下表面 113 槽孔 120 晶片 123 銲墊 130 電性連接元件 140 模封膠體 150 銲球 200 可堆疊窗口型半導體封裝構造 210 基板 211 上表面 212 下表面 16 200935585 213 槽孔 214 周邊外接墊 220 晶片 221 主動面 222 背面 223 銲墊 230 電性連接元件 240 模封膠體 241 中央封膠條 242 側封膠體 250 導體柱 260 黏晶層 300 可堆疊窗口型半導體封裝構造 310 基板 311 上表面 312 下表面 313 槽孔 314 周邊外接墊 〇 320 晶片 321 主動面 322 背面 323 銲墊 330 電性連接元件 340 模封膠體 341 中央封膠條 342 側封膠體 350 導體柱 370 貫通孔Schematic diagram of the wearing surface of the 200935585 type semiconductor package structure. Figure 4 is a schematic view of the lower surface of the substrate of the stackable window semiconductor package structure in accordance with a first embodiment of the present invention. Figure 5 is a cross-sectional view of a plurality of stackable die-type semiconductor package structures stacked longitudinally and bonded to a carrier board in accordance with a first embodiment of the present invention. Fig. 6 is a cross-sectional view showing another stackable semiconductor package structure according to a second embodiment of the present invention. Figure 7 is a schematic view of the lower surface of the substrate of the stackable window semiconductor package structure in accordance with a second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS In accordance with a second embodiment of the present invention, a plurality of stackable window-type semiconductor package structures are stacked longitudinally and joined to a schematic cross-sectional view of a circuit board. [Main component symbol description] Type window window type P Load 10 Circuit carrier board 11 Top surface 12 Bottom surface 13 Pad 20 External terminal 30 Adhesive material 40 Circuit carrier board 41 Top surface 42 Bottom surface 43 Bonding hole 50 Adhesive material 100 Window type semiconductor Package structure 110 substrate 111 upper surface 112 lower surface 113 slot 120 wafer 123 pad 130 electrical connection element 140 molding compound 150 solder ball 200 stackable window type semiconductor package structure 210 substrate 211 upper surface 212 lower surface 16 200935585 213 slot Hole 214 Peripheral external pad 220 Wafer 221 Active surface 222 Back surface 223 Pad 230 Electrical connection element 240 Molding paste 241 Central sealing strip 242 Side sealant 250 Conductor post 260 Bonding layer 300 Stackable window type semiconductor package structure 310 Substrate 311 Upper surface 312 Lower surface 313 Slot 314 Peripheral external pad 320 Wafer 321 Active surface 322 Back 323 Pad 330 Electrical connection element 340 Molding paste 341 Central sealing strip 342 Side sealant 350 Conductor post 370 Through hole
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