200935576 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝結構及其封裝方法，且特別 是有關於一種抗電磁干擾封裝結構及其封裝方法。 【先前技術】 一般來說，半導體元件封裝是將電路設置在電路基 板上，例如印刷電路板或陶瓷基板上。其電路的效能可能 ❿ 會因電磁干擾（EMI)而受到不利的影響。電磁干擾（EMI) 是由於電磁場能量放射而產生之信號干擾或雜訊。由於系 統内電子元件擺放的密度越來越高，相關的操作頻率亦往 更高的頻段發展，於是不必要的輻射雜訊更趨明顯，進而 導致更嚴重的電磁干擾。因此，多種利用導電材料形成屏 蔽結構之防止電磁干擾的封裝結構已經被開發出來。 現有的一種抗電磁干擾封裝結構，是在元件進行封 膠體製程後，切割封膠體後再形成導電膜於封膠體上。然 φ 後，再將基板切割形成獨立之封裝元件。請參照第1A圖 及第1B圖，其分別繪示傳統一種抗電磁干擾封裝結構的 第一道切割製程及第二道切割製程之示意圖。如第1A圖 所示，晶片12係以金線13與基板17電性連接，導電凸 塊16與基板17之接地元件15電性連接。本步驟中係以 切割刀10a將封膠體14切割分離，但不切割基板17。然 後，如第1B圖所示，形成導電膜18。導電膜18係塗佈 於封膠體14上，其中導電凸塊16係與導電膜18耦接。 本步驟中，以厚度較薄之切割刀10b切割基板17，以形 6 200935576 成獨立之封裝元件10，如2圖所示。由於此種封裝結構 在封裝過程中必須經過兩次切割，除了容易因切割失敗導 致良率降低外，由於兩道切割製程會浪費較多的基板材 料，因此基板的利用率也相對較低。 現有的另一種抗電磁干擾封裝結構，是將導電殼體 例如一金屬蓋以黏膠設置在完成封裝的元件上。如第3圖 所示，其繪示傳統另一種抗電磁干擾封裝結構的示意圖。 封裝元件20包括基板21、晶片22、封膠體25、導電殼 φ 體26及多個表面連接技術（SMT)元件28。晶片22係以金 線23電性連接基板21。導電殼體26係以黏膠27設置在 封膠體25上。表面連接技術元件28係配置於基板21上。 但是此種作法係以黏膠固定導電殼體，除了增加製程的複 雜度及時間外，容易因為溫度、濕度導致黏膠性質改變而 導致導電殼體脫落的問題。此外，導電殼體與封裝件的尺 寸必須配合，不同尺寸的封裝件必須製作不同的殼體，增 加導電殼體製造的困難度。 ^ 因此，如何克服傳統封裝結構的缺點，以產生高良 率，低成本之具有抗電磁干擾之封裝元件，乃業界所致力 的課題之一。 【發明内容】 本發明係有關於一種封裝結構及其封裝方法，在封裝 過程中直接形成導電膜，可以達到簡化封裝流程、節省封 裝時間以降低成本、並提高製程良率之優點。本發明更可 適用於各種尺寸之封裝件，同時亦可節省基板材料，提高 7 200935576 封裝件密度以提高基板使用率。 根據本發明，提出一種封裝結構，包括一基板、一半 導體元件、一封膠體以及一導電膜。基板具有一第一表 面、一第二表面、一第一侧面及一接地元件，第一側面連 接第一表面及第二表面。半導體元件設置於第一表面上並 與基板電性連接。接地元件設置於基板内部並外露於第一 側面，且具有一平面。封膠體覆蓋於半導體元件上，封膠 體之一第二側面係與接地元件之平面實質上切齊。導電膜 ❹ 直接形成於封膠體之一外表面、接地元件外露之平面及基 板之側面上，導電膜與接地元件電性連接。 根據本發明，提出一種封裝方法，包括下列步驟。首 先，提供一基板，至少具有相鄰之一第一基板單元及一第 二基板單元，一第一半導體元件及一第二半導體元件係配 置於第一基板單元及第二基板單元上，基板具有一第一表 面、一第二表面及一接地元件。第一表面與第二表面相 對，接地元件位於第一表面及第二表面之間。第一半導體 ❹ 元件及第二半導體元件設置於第一表面上並與基板電性 連接，接地元件位於第一半導體元件及第二半導體元件之 間。一膠帶係貼附於第二表面上。接著，形成一封膠體， 封膠體覆蓋第一半導體元件、第二半導體元件及第一表 面。然後，形成一切割狹縫，切割狹縫分割封膠體、基板、 接地元件及部分之膠帶，以形成貼附於膠帶上之一第一半 導體裝置及一第二半導體裝置。切割狹縫於膠帶中之一切 割深度係小於膠帶之厚度，接地元件之一平面係外露於封 8 200935576 膠體。接著，直接形成一導電膜於封膠體及切割狹缝上， 以使導電膜覆蓋第一半導體裝置及第二半導體裝置之封 膠體之外表面、接地元件外露之平面及基板之側面。 為讓本發明之上述内容能更明顯易懂，下文特舉較佳 實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本發明提出一種封裝結構，包括一基板、一半導體元 ❹ 件、一封膠體以及一導電膜。基板具有一第一表面、一第 二表面、一第一側面及一接地元件，第一側面連接第一表 面及第二表面。半導體元件設置於第一表面上並與基板電 性連接。接地元件設置於基板内部並外露於第一側面，且 具有一平面。封膠體覆蓋於半導體元件上，封膠體之一第 二側面係與接地元件之平面實質上切齊。導電膜直接形成 於封膠體之一外表面、接地元件外露之平面及基板之侧面 上，導電膜與接地元件電性連接。茲舉實施例說明如下。 ❿ 請參照第4圖，其繪示依照本發明一較佳實施例的一 種抗電磁干擾封裝結構之示意圖。如第4圖所示，半導體 裝置100c之封裝結構包括基板110a、半導體元件120a、 封膠體140a，以及導電膜160a。基板110a具有表面112、 表面114、側面116及118及接地元件151a及152a，側面 116、118分別連接表面112及表面114。接地元件151a 及152a設置於基板110a内部且分別具有一平面SI、S2， 平面SI、S2並分別外露於側面116及118。較佳地，接地 9 200935576 元件151a、152a係為接地貫孔，接地元件151a、152a之 高度實質上等於基板110a之厚度，且係由表面112延伸至 表面114。 半導體元件120a設置於表面U2上並與基板11〇&電 性連接。較佳地，半導體元件12〇a係以至少一金線13〇 與基板U〇a打線連接。封膠體140a覆蓋於半導體元件 12〇&上，封膠體140a之側面142及144係分別與平面S1 及S2實質上切齊。 _ 導電膜160a直接形成於封膠體14〇&之外表面、接地 兀件151a、152a外露之平面S1及S2及基板11〇a之側面 116及118上，導電膜16〇a與接地元件151a及152a電性 連接。較佳地，導電膜160a的組成材料係由鋁、銅、鉻、 錫、金、銀及鎳所構成的群組中選出。因此，基板内部u〇a 之接地元件151a及152a與導電膜i6〇a接觸，半導體裝置 100c即可完成接地。200935576 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure and a package method thereof, and more particularly to an EMI-resistant package structure and a package method therefor. [Prior Art] In general, a semiconductor component package is provided with a circuit on a circuit board such as a printed circuit board or a ceramic substrate. The performance of its circuit may be adversely affected by electromagnetic interference (EMI). Electromagnetic interference (EMI) is signal interference or noise generated by the emission of electromagnetic fields. Due to the increasing density of electronic components placed in the system, the associated operating frequencies are also developed in higher frequency bands, so unnecessary radiated noise is more pronounced, leading to more severe electromagnetic interference. Therefore, a variety of package structures for preventing electromagnetic interference using a conductive material to form a shield structure have been developed. An existing anti-electromagnetic interference package structure is formed by cutting a sealant after the component is subjected to a sealing process to form a conductive film on the sealant. After φ, the substrate is then cut to form a separate package component. Please refer to FIG. 1A and FIG. 1B respectively, which respectively illustrate schematic diagrams of a first cutting process and a second cutting process of a conventional anti-electromagnetic interference package structure. As shown in Fig. 1A, the wafer 12 is electrically connected to the substrate 17 by a gold wire 13, and the conductive bump 16 is electrically connected to the grounding member 15 of the substrate 17. In this step, the sealant 14 is cut and separated by the cutter 10a, but the substrate 17 is not cut. Then, as shown in Fig. 1B, a conductive film 18 is formed. The conductive film 18 is coated on the encapsulant 14, wherein the conductive bumps 16 are coupled to the conductive film 18. In this step, the substrate 17 is cut by a thin cutting blade 10b to form a separate package component 10 in the form of 200935576, as shown in FIG. Since the package structure must be cut twice during the packaging process, in addition to the easy yield reduction due to the cutting failure, since the two cutting processes waste more base material, the substrate utilization rate is relatively low. Another existing EMI-resistant package structure is to place a conductive housing such as a metal cover with an adhesive on the finished package. As shown in Fig. 3, it shows a schematic diagram of another conventional anti-electromagnetic interference package structure. The package component 20 includes a substrate 21, a wafer 22, a sealant 25, a conductive shell φ body 26, and a plurality of surface mount technology (SMT) elements 28. The wafer 22 is electrically connected to the substrate 21 by a gold wire 23. The conductive housing 26 is disposed on the sealant 25 with an adhesive 27. The surface connection technology element 28 is disposed on the substrate 21. However, this method is to fix the conductive shell with adhesive. In addition to increasing the complexity and time of the process, it is easy to cause the peeling of the conductive shell due to the change of the adhesive properties caused by temperature and humidity. In addition, the size of the conductive housing and the package must be matched. Different sizes of the package must be made of different housings, which increases the difficulty in manufacturing the conductive housing. ^ Therefore, how to overcome the shortcomings of the traditional package structure to produce high-yield, low-cost package components with electromagnetic interference resistance is one of the topics of the industry. SUMMARY OF THE INVENTION The present invention relates to a package structure and a package method thereof, which directly form a conductive film during a package process, which can achieve the advantages of simplifying the packaging process, saving the packaging time, reducing the cost, and improving the process yield. The invention is more applicable to packages of various sizes, and can also save substrate material and increase the density of the package of 200935576 to increase the substrate utilization rate. According to the present invention, a package structure is proposed comprising a substrate, a half conductor element, a gel and a conductive film. The substrate has a first surface, a second surface, a first side and a grounding member, the first side connecting the first surface and the second surface. The semiconductor component is disposed on the first surface and electrically connected to the substrate. The grounding element is disposed inside the substrate and exposed to the first side and has a flat surface. The encapsulant is overlaid on the semiconductor component, and the second side of the encapsulant is substantially aligned with the plane of the ground component. The conductive film ❹ is directly formed on the outer surface of one of the sealing body, the exposed surface of the grounding member, and the side of the substrate, and the conductive film is electrically connected to the grounding member. According to the present invention, a packaging method is proposed comprising the following steps. First, a substrate is provided, which has at least one adjacent first substrate unit and a second substrate unit. A first semiconductor component and a second semiconductor component are disposed on the first substrate unit and the second substrate unit, and the substrate has a first surface, a second surface, and a grounding element. The first surface is opposite the second surface and the grounding element is between the first surface and the second surface. The first semiconductor 元件 element and the second semiconductor element are disposed on the first surface and electrically connected to the substrate, and the ground element is located between the first semiconductor element and the second semiconductor element. A tape is attached to the second surface. Next, a gel is formed, and the sealant covers the first semiconductor element, the second semiconductor element, and the first surface. Then, a slit slit is formed, and the slit is divided into a seal body, a substrate, a grounding member, and a portion of the tape to form a first semiconductor device and a second semiconductor device attached to the tape. Everything that cuts the slit into the tape is less than the thickness of the tape, and one of the grounding elements is exposed to the seal of 200935576. Then, a conductive film is directly formed on the encapsulant and the dicing slit so that the conductive film covers the outer surface of the sealing body of the first semiconductor device and the second semiconductor device, the exposed surface of the grounding member, and the side surface of the substrate. In order to make the above description of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. The present invention provides a package structure including a substrate and a semiconductor. A piece of plastic, a gel and a conductive film. The substrate has a first surface, a second surface, a first side and a grounding member, the first side connecting the first surface and the second surface. The semiconductor component is disposed on the first surface and electrically connected to the substrate. The grounding element is disposed inside the substrate and exposed on the first side and has a flat surface. The encapsulant is overlaid on the semiconductor component, and the second side of the encapsulant is substantially aligned with the plane of the ground component. The conductive film is directly formed on the outer surface of one of the sealing body, the exposed surface of the grounding member, and the side of the substrate, and the conductive film is electrically connected to the grounding member. The embodiments are described below. ❿ Referring to FIG. 4, a schematic diagram of an anti-electromagnetic interference package structure in accordance with a preferred embodiment of the present invention is shown. As shown in Fig. 4, the package structure of the semiconductor device 100c includes a substrate 110a, a semiconductor element 120a, a sealant 140a, and a conductive film 160a. The substrate 110a has a surface 112, a surface 114, sides 116 and 118, and grounding members 151a and 152a. The sides 116, 118 are coupled to the surface 112 and the surface 114, respectively. The grounding elements 151a and 152a are disposed inside the substrate 110a and have a plane SI, S2, planes SI, S2, and are exposed to the side surfaces 116 and 118, respectively. Preferably, ground 9 200935576 elements 151a, 152a are ground vias, and ground elements 151a, 152a have a height substantially equal to the thickness of substrate 110a and extend from surface 112 to surface 114. The semiconductor element 120a is disposed on the surface U2 and electrically connected to the substrate 11A & Preferably, the semiconductor element 12A is wire-bonded to the substrate U〇a by at least one gold wire 13〇. The encapsulant 140a covers the semiconductor device 12A & the side faces 142 and 144 of the encapsulant 140a are substantially aligned with the planes S1 and S2, respectively. _ The conductive film 160a is directly formed on the outer surface of the sealing body 14 amp & the exposed surfaces S1 and S2 of the grounding 兀 151a, 152a and the sides 116 and 118 of the substrate 11 〇 a, the conductive film 16 〇 a and the grounding member 151a And 152a electrical connection. Preferably, the constituent material of the conductive film 160a is selected from the group consisting of aluminum, copper, chromium, tin, gold, silver, and nickel. Therefore, the ground elements 151a and 152a of the substrate internal u〇a are in contact with the conductive film i6〇a, and the semiconductor device 100c can be grounded.
❹ 至於本發明之封裝結構之封裝方法，請參照第5A-5E 圖’其繪示依照本發明一較佳實施例的一種抗電磁干擾封 裝結構之封裝流程圖。 首先’如第5A圖所示，提供一基板110，基板U0 具有相鄰之基板單元Sbl及Sb2，基板11〇上配置有多個 半導體元件，例如是半導體元件12〇a及12〇b，分別配置 於基板單元Sbl及Sb2上。基板11〇具有表面112及表面 114 ’且表面112與表面U4相對。表面112及表面114 之間包括至少一接地元件，例如包括接地元件151、152 200935576 及153。其中，接地元件152係位於半導體元件12〇a及 120b之間。本實施例中，接地元件151、152及153之高 度實質上等於基板ll〇a之厚度。較佳地，接地元件15ι、 152及153係為接地貫孔，且由表面112延伸至表面114。 半導體元件120a及半導體元件12〇b設置於表面U2 上並與基板110電性連接。半導體元件120a及半導體元 件120b例如係以金線130與基板11〇電性連接。膠帶ι〇1 係貼附於表面114上，以避免基板11〇在切割後散落。 接著’如第5B圖所示’形成封膠體14〇。封膠體ι4〇 覆盍半導體元件120a、半導體元件pob及表面112。 然後，如第5C圖所示，形成至少一切割狹縫，例如 是切割狹縫141、143及145。切割狹缝HI、143及145 分割封膠體140、接地元件ι51、152及153、基板11()及 部分之膠帶101 ’以形成貼附於膠帶1〇1上之半導體裝置 100a及半導體裝置l〇〇b。於形成至少一切割狹縫之後， 每個接地元件係被切割成兩個接地元件，例如接地元件 ❹152係被切割成接地元件i52a及152b，而接地元件151 及153亦被切割形成接地元件i5丨a及丨53b。封膠體J40 亦被切割成多個封膠體，例如是封膠體丨4〇a及140b，而 基板110亦被分割成多個基板，例如是基板11〇&及HOb。 半導體裝置100a包括半導體元件12〇a、基板u〇a、接地 元件151a及152a，以及封膠體MOa ;半導體裝置l〇ob 包括半導體元件120b、基板ii〇b、接地元件152b及153b， 以及封膠體140b。切割狹縫141、143及145於膠帶 200935576 中之切割深度D1係小於膠帶101之厚度D2。 於此步驟中，於形成至少一切割狹縫之後，位於基板 中之接地元件將外露出來。例如，接地元件151a及152a 之平面S1及S2係外露。此外，藉由切割狹缝之形成，封 膠體140之表面142、接地元件15la之平面S1及基板110a 之側面116係實質上切齊；同樣的，封膠體140之表面 144、接地元件152a之平面S2及基板110a之表面118亦 實質上切齊。 • 接著，如第5D圖所示，直接形成導電膜160於封膠 體140a及140b及切割狹缝141、143及145上，以形成 半導體裝置100c及半導體裝置100d。較佳地，導電膜160 的形成方式例如由化學氣相沈積、無電電鐘、電解電鍍、 喷塗、印刷及濺鍍所構成的群組中選出，而導電膜160的 組成材料係由銘、銅、絡、錫、金、銀及錄所構成的群組 中選出。導電膜160覆蓋半導體裝置100c及封膠體140a 之外表面、外露之接地元件151a及152a之平面S1及S2, ❹ 及基板110a之全部側面116及118。同樣的，導電膜160 亦以相同之方式覆蓋半導體裝置100d。 然後，如第5E圖所示，除去膠帶101以分離半導體 裝置100c及半導體裝置100d，如此，即可得到第4圖所 示之結構之半導體裝置。 請參照第6圖，其繪示依照本發明另一較佳實施例的 一種抗電磁干擾封裝結構之示意圖。半導體裝置200之封 裝結構與第4圖之半導體裝置100c之封裝結構的差別在 12 200935576 於’半導體元件220係以覆晶方式與基板210電性連接。 雖然本發明之半導體元件係以打線連接或覆晶方式與基 板連接為例做說明’然本發明並不限於此，其他的電性連 接方式亦可適用於本發明。 而本發明之基板11〇，也可以是一陣列式基板或長條 式基板’具有以一陣列形式或條列形式排列之複數個基板 單元。請參照第7A及第7B圖，其分別繪示陣列式基板及 長條式基板之示意圖。如第7A圖所示，陣列式基板2具 ® 有多個基板單元2a ’相鄰之兩個基板單元2a係以切割道 2b隔開。半導體元件i2〇a及半導體元件i2〇b可以分別設 置於相鄰之兩個基板單元2a上進行封裝，而相鄰兩個基 板單元2a之切割道2b則通過接地元件上方，例如通過接 地元件152上方。當封膠體製程完成後，可以沿切割道2b 切割後，再形成導電膜。 如第7B圖所不’長條式基板4具有多個基板單元 4a，每一基板單元4a係以切割道4b隔開。同樣的，半導 W 體元件120a及半導體元件120b可以分別設置於相鄰之兩 個基板單元4a上進行封裝，而相鄰兩個基板單元4a之切 割道4b則通過接地元件上方，例如通過接地元件152上 方。當封膠體製程完成後，可以沿切割道4b切割後，再 形成導電膜。 本發明上述實施例所揭露之封裝結構及其封裝方 法，係將膠帶貼在具有複數個半導體裝置之基板背面，基 板内部具有接地貫孔或其他接地元件。並在封膠體完成 13 200935576 後，對準接地貫孔或其他接地元件所在之位置進行切割， 再直接形成導電膜於封膠體上，最後再將各半導體裝置分 離。藉由使用膠帶，進行切割後的多個半導體裝置不會散 落，切割後之所有的半導體裝置係仍然黏著於膠帶上。如 此，可以讓所有的半導體裝置之導電膜可以同時形成，以 節省製程時間。而且，不需二次切割，只需一次切割即可 同時分離封膠體及基板。此外，由於僅需進行一次切割， 更可以降低切割失敗的機率，以提高產品良率。同時也因 _ 切割次數減少，可以提高基板上元件的配置密度，而增加 基板的利用率。 另外，以直接形成於封膠體上之方式產生的導電膜， 可以適應各種元件尺寸，同時也可以抵抗溫、濕度的變 化，提升元件可靠度。此外，利用基板内原有的接地貫孔 即可與導電膜接地，不需另外設置接地元件，可以節省物 料成本及製程步驟。 綜上所述，雖然本發明已以較佳實施例揭露如上，然 ❹ 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者，在不脫離本發明之精神和範圍内，當可作各種之 更動與潤飾。因此，本發明之保護範圍當視後附之申請專 利範圍所界定者為準。 200935576 【圖式簡單說明】 第1A圖繪示傳統一種抗電磁干擾封裝結構的第一道 切割製程之示意圖； 第1B圖繪示傳統一種抗電磁干擾封裝結構的第二道 切割製程之示意圖； 第2圖繪示使用第1A及1B圖之製程後所得到之傳統 抗電磁干擾封裝結構的示意圖； 第3圖繪示傳統另一種抗電磁干擾封裝結構的示意 圖， 第4圖繪示依照本發明一較佳實施例的一種抗電磁 干擾封裝結構之示意圖； 第5A-5E圖繪示依照本發明一較佳實施例的一種抗 電磁干擾封裝結構之封裝流程圖； 第6圖繪示依照本發明另一較佳實施例的一種抗電 磁干擾封裝結構之示意圖； 第7A圖繪示陣列式基板之示意圖；以及 ❹ 第7B圖繪示長條式基板之示意圖。 【主要元件符號說明】 2:陣列式基板 2a、4a :基板單元 2b、4b :切割道 4 :長條式基板 10、20 :封裝元件 15 200935576 10a、10b :切割刀 12、 22 :晶片 13、 23 ' 130 :金線 14、 25、140、140a、140b :封膠體 15、 151、151a、152、152a、152b、153、153b :接地 元件 17、 21、110、110a、110b、210 :基板 18、 160、160a、160b :導電膜 〇 26 :導電殼體 27 :黏膠 100a、100b、100c、100d、200 :半導體裝置 101 :膠帶 112、114 :表面 116、118、142、144 :側面 120a、120b、220 :半導體元件 141、143、145 :切割狹縫 ❿ SI、S2 :平面❹ As for the encapsulation method of the package structure of the present invention, please refer to FIG. 5A-5E, which illustrates a package flow chart of an anti-electromagnetic interference package structure according to a preferred embodiment of the present invention. First, as shown in FIG. 5A, a substrate 110 is provided. The substrate U0 has adjacent substrate units Sb1 and Sb2. The substrate 11 is provided with a plurality of semiconductor elements, for example, semiconductor elements 12a and 12b, respectively. It is disposed on the substrate units Sb1 and Sb2. The substrate 11 has a surface 112 and a surface 114' and the surface 112 is opposite the surface U4. At least one grounding element is included between surface 112 and surface 114, including, for example, grounding elements 151, 152 200935576 and 153. The grounding element 152 is located between the semiconductor elements 12a and 120b. In this embodiment, the heights of the grounding members 151, 152, and 153 are substantially equal to the thickness of the substrate 11a. Preferably, grounding members 15i, 152, and 153 are grounded through holes and extend from surface 112 to surface 114. The semiconductor element 120a and the semiconductor element 12A are disposed on the surface U2 and electrically connected to the substrate 110. The semiconductor element 120a and the semiconductor element 120b are electrically connected to the substrate 11 by, for example, a gold wire 130. A tape ι〇1 is attached to the surface 114 to prevent the substrate 11 from being scattered after cutting. Next, the encapsulant 14 is formed as shown in Fig. 5B. The encapsulant ι4 盍 covers the semiconductor device 120a, the semiconductor device pob, and the surface 112. Then, as shown in Fig. 5C, at least one slit is formed, for example, slits 141, 143, and 145. The slits HI, 143, and 145 are divided into a sealing body 140, grounding members ι 51, 152, and 153, a substrate 11 (), and a portion of the tape 101' to form a semiconductor device 100a and a semiconductor device attached to the tape 101. 〇b. After forming at least one cutting slit, each grounding element is cut into two grounding elements, for example, grounding element 152 is cut into grounding elements i52a and 152b, and grounding elements 151 and 153 are also cut to form grounding element i5丨a and 丨53b. The encapsulant J40 is also cut into a plurality of encapsulants, such as sealants 〇4〇a and 140b, and the substrate 110 is also divided into a plurality of substrates, such as substrates 11 amp & and HOb. The semiconductor device 100a includes a semiconductor element 12a, a substrate u〇a, grounding elements 151a and 152a, and a sealant MOa; the semiconductor device 10b includes a semiconductor element 120b, a substrate ii〇b, grounding elements 152b and 153b, and a sealant 140b. The cutting depths D1 of the slits 141, 143, and 145 in the tape 200935576 are smaller than the thickness D2 of the tape 101. In this step, after the at least one slit is formed, the grounding member located in the substrate will be exposed. For example, the planes S1 and S2 of the grounding elements 151a and 152a are exposed. In addition, by the formation of the slit, the surface 142 of the encapsulant 140, the plane S1 of the grounding element 151a, and the side 116 of the substrate 110a are substantially aligned; likewise, the surface 144 of the encapsulant 140, the plane of the grounding element 152a The surface 118 of S2 and substrate 110a is also substantially aligned. Then, as shown in Fig. 5D, the conductive film 160 is directly formed on the sealants 140a and 140b and the dicing slits 141, 143, and 145 to form the semiconductor device 100c and the semiconductor device 100d. Preferably, the formation of the conductive film 160 is selected, for example, by a group consisting of chemical vapor deposition, electroless clock, electrolytic plating, spray coating, printing, and sputtering, and the constituent material of the conductive film 160 is Selected from the group consisting of copper, collateral, tin, gold, silver and recorded. The conductive film 160 covers the outer surfaces of the semiconductor device 100c and the encapsulant 140a, the planes S1 and S2 of the exposed ground members 151a and 152a, and the entire sides 116 and 118 of the substrate 110a. Similarly, the conductive film 160 also covers the semiconductor device 100d in the same manner. Then, as shown in Fig. 5E, the tape 101 is removed to separate the semiconductor device 100c and the semiconductor device 100d, and thus, the semiconductor device having the structure shown in Fig. 4 can be obtained. Please refer to FIG. 6, which is a schematic diagram of an anti-electromagnetic interference package structure according to another preferred embodiment of the present invention. The difference between the package structure of the semiconductor device 200 and the package structure of the semiconductor device 100c of Fig. 4 is that the semiconductor element 220 is electrically connected to the substrate 210 in a flip chip manner at 12, 2009, 576. Although the semiconductor device of the present invention is connected to the substrate by wire bonding or flip chip as an example, the present invention is not limited thereto, and other electrical connection methods are also applicable to the present invention. The substrate 11 of the present invention may also be an array substrate or a long substrate having a plurality of substrate units arranged in an array or in a strip. Please refer to FIGS. 7A and 7B for a schematic view of the array substrate and the elongated substrate, respectively. As shown in Fig. 7A, the array substrate 2 has two substrate units 2a adjacent to each other, and the two substrate units 2a adjacent to each other are separated by a dicing street 2b. The semiconductor element i2〇a and the semiconductor element i2〇b may be respectively disposed on the adjacent two substrate units 2a for packaging, and the dicing streets 2b of the adjacent two substrate units 2a pass through the grounding element, for example, through the grounding element 152. Above. After the sealing process is completed, the conductive film can be formed after cutting along the cutting path 2b. The elongated substrate 4 has a plurality of substrate units 4a as shown in Fig. 7B, and each of the substrate units 4a is separated by a dicing street 4b. Similarly, the semi-conductive W body element 120a and the semiconductor element 120b may be respectively disposed on the adjacent two substrate units 4a for packaging, and the dicing streets 4b of the adjacent two substrate units 4a pass through the grounding element, for example, through grounding. Above element 152. After the sealing process is completed, it can be cut along the cutting path 4b to form a conductive film. The package structure and the packaging method thereof disclosed in the above embodiments of the present invention are characterized in that a tape is attached to the back surface of a substrate having a plurality of semiconductor devices, and a ground through hole or other grounding member is provided inside the substrate. After the sealing body is completed 13 200935576, it is cut at the position where the grounding through hole or other grounding member is located, and then the conductive film is directly formed on the sealing body, and finally the semiconductor devices are separated. By using the tape, the plurality of semiconductor devices after the dicing is not scattered, and all the semiconductor devices after the dicing are still adhered to the tape. Thus, the conductive films of all the semiconductor devices can be simultaneously formed to save process time. Moreover, without the need for secondary cutting, the sealant and the substrate can be separated simultaneously with one cut. In addition, since only one cut is required, the probability of cutting failure can be reduced to improve product yield. At the same time, due to the reduced number of _cuts, the density of components on the substrate can be increased, and the utilization of the substrate can be increased. In addition, the conductive film produced in a manner directly formed on the encapsulant can be adapted to various component sizes, and can also resist changes in temperature and humidity, thereby improving component reliability. In addition, the original grounding through hole in the substrate can be grounded to the conductive film, and no additional grounding components are required, which can save material cost and process steps. In view of the above, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 200935576 [Simple description of the drawing] FIG. 1A is a schematic view showing a first cutting process of a conventional anti-electromagnetic interference package structure; FIG. 1B is a schematic view showing a second cutting process of a conventional anti-electromagnetic interference package structure; 2 is a schematic view showing a conventional anti-electromagnetic interference package structure obtained by using the processes of FIGS. 1A and 1B; FIG. 3 is a schematic view showing another conventional anti-electromagnetic interference package structure, and FIG. 4 is a view showing a structure according to the present invention. A schematic diagram of an anti-electromagnetic interference package structure according to a preferred embodiment; 5A-5E is a package flow chart of an anti-electromagnetic interference package structure according to a preferred embodiment of the present invention; and FIG. 6 is a cross-sectional view of another embodiment of the present invention. A schematic diagram of an anti-electromagnetic interference package structure of a preferred embodiment; FIG. 7A is a schematic view of the array substrate; and FIG. 7B is a schematic view of the elongated substrate. [Main component symbol description] 2: Array substrate 2a, 4a: substrate unit 2b, 4b: dicing street 4: elongated substrate 10, 20: package component 15 200935576 10a, 10b: dicing blade 12, 22: wafer 13, 23 '130: gold wire 14, 25, 140, 140a, 140b: sealant 15, 151, 151a, 152, 152a, 152b, 153, 153b: grounding member 17, 21, 110, 110a, 110b, 210: substrate 18 , 160, 160a, 160b: conductive film 〇 26: conductive case 27: adhesive 100a, 100b, 100c, 100d, 200: semiconductor device 101: tape 112, 114: surface 116, 118, 142, 144: side 120a, 120b, 220: semiconductor elements 141, 143, 145: slit slits ❿ SI, S2: plane
Sbl、Sb2 :基板單元 16Sb1, Sb2: substrate unit 16