200934334 九:、發明說明： 〜’【發明所屬之技術領域】 ‘- 本發明係有關於一種半導體製程技術’尤指一種電路 板製法。 【先前技術】 隨著電子產業的蓬勃發展’電子產品亦逐漸邁入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration)以及微型化（Miniaturizati〇n)的封裝 ©需求，承載半導體晶片之封裝基板，逐漸由單層板演變成 多層板（Multi-layer Board)，俾於有限的空間下，藉 由層間連接技術（lnteriayer connection)以擴大封裝 基板上可利用的線路面積，以因應高電子密度之積體電路 (Integrated Circuit)的使用需求；為此，遂發展出一 種增層技術（bui ld-up)，亦即在一核心電路板（c〇re circuit board)表面利用線路增層技術交互堆疊多層介 ❹電層及線路層，並於該介電層中開設導電盲孔 (conductive Via)以供上、下層線路之間電性連接。 為因應微處理器、晶片組、繪圖晶片與特殊應用積體 電路（ASIC)等高效能晶片之運算需要，佈有線路之半導體 封裝基板亦需提昇其傳遞晶片訊號、改善頻寬、控制阻抗 等功旎，以因應高I / 〇數封裝件的發展；且為符合半導體 封裝件輕薄短小、多功能、高速度、高線路密度及高頻化 的開發方向，封裝基板已朝向細線路及小孔徑發展；現有 半導體封裝基板製程從傳統100微米之線路尺寸，已縮減 ]10595 5 200934334 、至現在的30微米以下其中，包括導線寬度 width)、線路間距（space)及深寬比（⑽的^ 等持 續朝向更小的線路精度進行研發。 '叫參閱第1A至1F圖所示，係顯示習知封裝基板之製 法，如第1A圖所示，提供一核心板1〇，該核心板1〇具 有相對之第一表面1〇a及第二表面議，且於該第一表面 l〇a及第二表面1〇b分別形成有第一線路層u，並於該核 :反1G中形成有電料通孔m，以電性連接該核心板 之第一及第二表面10a，10b之第一線路層u，其中， °亥電鍛導通孔1G1中並填人有填充材料12;如第1B圖所 厂於該核心板10之第一表面1〇a及其上之第一線路層 1上、以及於該第二表面⑽及其上之第—線路屬Uji 为別形成一介電層13;如第1C圖所示，該介電層Μ中200934334 Nine: Invention Description: ~' [Technical field to which the invention pertains] ‘- The present invention relates to a semiconductor process technology, particularly a circuit board manufacturing method. [Prior Art] With the booming of the electronics industry, electronic products are gradually entering the direction of multi-functional and high-performance research and development. In order to meet the requirements of high integration and miniaturization of semiconductor packages, package substrates carrying semiconductor wafers have gradually evolved from single-layer boards to multi-layer boards. In a limited space, the interlayer area connection technology is used to expand the available circuit area on the package substrate to meet the demand for the use of a high electron density integrated circuit; for this reason, an increase has been developed. Bui ld-up, that is, on the surface of a core circuit board (c〇re circuit board), a plurality of dielectric layers and circuit layers are alternately stacked by a line build-up technology, and a conductive blind is opened in the dielectric layer. A conductive Via is used to electrically connect the upper and lower lines. In order to meet the computational needs of high-performance chips such as microprocessors, chipsets, graphics chips, and special application integrated circuits (ASICs), semiconductor package substrates with lines need to be upgraded to transmit chip signals, improve bandwidth, control impedance, etc. In order to meet the development trend of high I / 封装 packages, and in line with the development direction of thin, versatile, high speed, high line density and high frequency of semiconductor packages, the package substrate has been oriented toward fine lines and small apertures. Development; existing semiconductor package substrate process has been reduced from the traditional 100 micron line size] 10595 5 200934334, up to now 30 microns, including wire width), line spacing (space) and aspect ratio ((10) ^ etc. Continuous research and development towards smaller line accuracy. 'Refer to Figures 1A to 1F, showing the method of manufacturing a conventional package substrate, as shown in Fig. 1A, providing a core board 1〇 having The first surface layer 〇a and the second surface are opposite to each other, and the first circuit layer 〇a and the second surface 〇b are respectively formed with a first circuit layer u, and the core layer: the reverse 1G shape The electric material through hole m is electrically connected to the first circuit layer u of the first and second surfaces 10a, 10b of the core board, wherein the electric through-hole 1G1 is filled with a filling material 12; The first surface 1〇a of the core board 10 and the first circuit layer 1 thereon, and the second surface (10) and the first line Uji of the core board 10 are formed into a dielectric. Layer 13; as shown in FIG. 1C, the dielectric layer is in the middle
$成有開孔130 ’以顯露部分之第-線路層11;如第1D !所示’於該介電層13上及其開孔13〇表面上形成一導 〇=14’、且於該導電層14上形成有阻層15,並使該阻層 形成有開口 150以露出該導電们4之部份表面；如 圖斤示於該阻層15之開口 150中的導電層14上 電=第二線路層16，且於該介電層13之開孔13。中 =成導電盲孔16卜以電性連接該第一線路層ιι;如第 圖所不’移除該阻層15及其所覆蓋之 出該第二線路層16。 以露 之導中，於利用_方式移除該阻層15所覆蓋 時，因侧蝕問題將使得位於介電層13表面之 110595 6 200934334 、第丄線路層16之線寬縮減，即該第二 广預定線寬;因此，無法二:冗低 -製…質不穩定可能會造成其中層之:: 路的情形，但倘若增加原本第二線路層而發f斷 則有礙於細線路製程能力之提升。 叹计線見， 另請配合參閱第2圖，係為第1F圖 圖，該限層15之開口⑽必須大於該圏介=的;;視 130,使該第二線路層16利於對應；曰孔 ©於該導電盲孔161上來# ,, Ιβ, 1β1 盲孔16卜因此 第一錄政恳c ’且該孔環MU與 第-線路層16電性連接，而該導電盲孔16 部分佈線面積，同樣礙於細線路製程能力之^ f+J:現有第二線路層16位於介電層13表面之結構 對於k升細線路製程能力，仍存在其技術瓶頸。 【發明内容】 ◎ β鑑於以上所述習知技術之缺點，本發明之主要目的係 提供-種電路板製法，藉以形成細線路之電路板，俾 電路板之電性功能。 ^為達上述及其他目的，本發明揭露一種電路板製法， 係包括·提供一核心板，其表面係具有核心線路層，且該 $心線路層具有複數接觸墊；力該核心板上形成第 私層，以短波雷射於該第一介電層中形成複數深開口，並 對應露出該接觸塾；以長波雷射於該第-介電層中形成 複數淺開口，且部份淺開口連通該深開口，並對應露出該 ]10595 7 200934334 接觸塾；於該第—介電層上、深開口中、淺開口中及接觸 墊上形成有導電層；於該導電層表面形成有金屬層，且於 該冰開口中形成第一導電盲孔，於該淺開口中形成第一線 路層；以及移除未形成於該深開口及淺開口中之導電層 及金屬層，且使該第一線路層及第一導電盲孔上表面與^ 一介電層齊平。 本發明復提供另一種電路板製法，係包括：提供一核 心板’其表㈣具有核心祕層，且該核义線路層具有複 €)數接觸塾；於該核心板上形成第一介電層；以短波雷射 於該第-介電層中形成複數深開口，並對應露出該接觸 塾’以長波雷射於該第一介電層中形成複數淺開口，且部 份淺開口連通該深開口，並對應露出該接觸塾；於該深開 口中以化學沉積形成有第一導電盲孔以電性連接該接觸 塾；於該第一介電層上、淺開口中及第-導電盲孔上形成 有導電層；於該導電層表面形成有金屬層，且㈣淺開口 〇中形成第-線路層^及移除未形成於該深心及淺開 口中之V電層及金屬層，且使該第一線路層及第一導電盲 孔上表面與第一介電層齊平。 、本發明又提供另一種電路板製法，係包括：提供一核 〜板’其表面係具有核心線路層，且該核心線路層具有複 數接觸墊，於e亥核心板上形成第一介電層；以長波雷射 於該第—介電層中形成複數淺開Π;於該第—介電層上 及該淺開口中形成光罩金屬層；該光罩金屬層進行圖案 化衣耘形成複數光罩開口，以露出該第一介電層之部份表 8 110595 200934334 、冰開^並對應露出該接㈣，且部份淺開口連通該深開 口，和除该光罩金屬層；於該第—介 淺開口中及接觸墊上形成有導電層，·於^導電 面中矿 二有：屬層，且於該深開口中形成第—導電盲孔，料淺 :二成f'線路層；以及移除未形成於該深開口及 反開口中之導電層及金屬層，且使該第一線路層及第—導 電盲孔上表面與第一介電層齊平。 〇 本發明再提供另-種電路板製法，係包括：提供—核 心板，其表面係具有心線路層，且該核轉路層= 數接觸墊；於該核心板上形成第—介電層；以長波 於該第-介電層中形成複數淺開σ;於該第—介電2 及該淺開口中形成光罩金屬層；該光罩金屬層進行 化製程形成複數光罩開口，以露出該第一介電層之部份表 =以長f雷身？該光罩開口中之第—介電層形成複數 ❹冰幵口並對應路出該接觸墊，且部份淺開口連通該深 口；移除該光罩金屬層；於該深開口中以化學沉積形^ 有第一導電盲孔以電性連接該接觸墊；於該第一介電屉 上、淺開口中及第一導電盲孔上形成有導電層；於該導; 層表面形成有金屬層；以及移除未形成於該深開D及淺 開口中之導電層及金屬層，以於該淺開口中形成第一線路 層，並於該深開口中形成第一導電盲孔，且使該第一線路 層及第一導電盲孔上表面與第一介電層齊平。 依上述之各製法，該核心板係為絕緣板或具有核心線 110595 9 200934334 路層之線路板；該短波雷射係為紫外線雷射、敛鏡銘石權 石（Nd-YAG)雷射或準分子（Excimer)雷射；該長波雷射係 '為二氧化碳雷射。 又依上述之製法，復包括於該第一介電層及第一線路 層表面形成有線路增層結構，該線路增層結構係包括有至 少-具有複數淺開口及深開口之第二介電層、形成於該第 叫I電層之w開π中之第二線路層、以及形成於該第二介 電層之深開口中並電性連接該第二線路層之第二導電盲 〇孔，其中’該第二線路層及第二導電盲孔上表面盥第二介 電層齊平，且於該線路增層結構表面形成複數電性連接該 第二線路層之電性連接墊，又於該線路增層結構上形成絕 緣保護層，該絕緣保護層形成有複數個開孔以對 電性連接墊。 ★因此，本發明之電路板製法，該第一、第二線路層及 第一、第二導電盲孔之上表面係與該第一、第二介電層之 ❹上表面齊平，故能有效控制線路之形狀，以避免該第L、 第二線路層之線寬過寬而影響細線路之提昇；且該第 -、第二導電盲孔上表面無須形成孔環，而可免除佔用佈 線空間，以提高佈線密度。 【實施方式】 、以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 [第一實施例] 110595 10 200934334 '請參閱第3A至3H圖，係顯示本發明之電路板製法第 '一實施例之剖面示意圖。 ‘·· 如第3A圖所示，首先提供一核心板2〇，其表面2〇a 係具有核心線路層201，且該核心線路層201具有複數接 觸墊201a。 如第3B圖所示，接著於該核心板2〇之表面20a上以 熱壓（hot press)、滾壓（rolier coating)、印刷 (printing)、^tS(spin coating)、浸泡（dipping)或真 ❹空壓合（vaccum lamination)形成第一介電層21a。 如第3C圖所示，以係為紫外線雷射、鉉镱鋁石榴石 (Nd-YAG)雷射或準分子（Excimer)雷射之短波雷射於該第 一介電層21a中形成複數深開口 211，並對應露出該接觸 墊 201a 。 如第3D圖所示，以係為二氧化碳雷射長波雷射於該 第一介電層21a中形成複數淺開口 212,且部份淺開口 212 #通：深開口 211’並對應露出該接觸墊2〇la; 之後並進 行去膠淺（desmer)及粗化處理。 如第3E圖所示’於該第一介電層21a上、深開口 211 中、淺開口 212中及接觸塾201a上形成有導電層23。 如第3F圖所示，於該導電層23表面形成有金屬層 24，且於該深開口 211中形成第一導電盲孔24〇，於該淺 開口 212中形成第一線路層241。 如第3G圖所示，移除未形成於該深開口 21丨及淺開 口 212中之導電層23及金屬層24’且使該第一線路層241 110595 11 200934334 及第一導電盲孔240上表面與第一介電層2ia齊平。 另請配合參閱第3G’圖，係為第3G圖之局部β的上 圖，其中，該第一導電盲孔24〇之上表面無須形成孔 環，而可免除佔用佈線空間，以提高佈線密度。 如第3Η圖所示，於該第一介電層21a及第一線路層 241表面形成有線路增層結構25，該線路增層結構25係 包括有至少一具有複數淺開口 212及深開口 211之第二介 電層21b、形成於§亥第二介電層2ib之淺開口 212之第二 ©線路層242、以及形成於該第二介電層21b之深開口 211 中並電性連接該第二線路層242之第二導電盲孔250，其 中，該第二線路層242及第二導電盲孔25〇上表面與第二 介電層21b齊平，且於該線路增層結構25表面形成複數 電性連接該第二線路層242之電性連接墊251，於該線路 增層結構25上形成絕緣保護層26，該絕緣保護層26形 成有複數個開孔260以對應露出該電性連接塾251。 [第二實施例] 請參閱第4A至4D圖’係顯示本發明之電路板製法第 二實施例之剖面示意圖。 如第4A圖所示，提供一係如第3£)圖所示之結構，並 於該核心板20之深開口 211中以化學沉積形成有第一導 電盲孔240以電性連接該接觸墊2〇la。 如第4B圖所示，之後，於該第一介電層21a上、淺 開口 212中及第一導電盲孔240上形成有導電層23。 如第4C圖所示，於該導電層23表面形成有金屬層 12 110595 200934334 24:’且於該淺開口 212中形成第—線路層241。 如第4D圖所示，最後，移除未形成於該深開口 2ΐι ' -及淺開口 212中之導電層23及金屬層24’且使該第—線 路層241及第一導電盲孔240上表面與第一介電層21& 齊平。 [第三實施例] 请參閱第5A至5H圖，係顯示本發明之電路板製法第 三實施例之剖面示意圖。 ° 如第5A圖所示，提供一係如第3B圖所示之結構，於 "亥核〜板20之表面20a的第一介電層2ia上以長波雷射 形成有複數淺開口 212。 如第5B圖所示，於該第一介電層21&及淺開口 212 上形成以化學沉積或濺鍍（sputting)形成厚度為〇 〇3至 之間的光罩金屬層22，該光罩金屬層22係為鋼 (Cu)、鋁（A1)、鎳（Ni)、鉻（Cr)、鈦（Ti)、鈦/銅（Ti/Cu)、 ❽銀（Ag)、金（Au)、或鈀（pd)所組成群組之其中一者。 如第5C圖所示，該光罩金屬層22進行圖案化製程形 成複數光罩開口 220,以露出該第一介電層21&之部份表 面、及露出該淺開口 212。 如第5D圖所示，於該光罩開口 22〇中之第一介電層 21a以長波雷射形成深開口 21丨，並對應露出該接觸墊 201a，且部份深開口 211連通該淺開口 212。 如第5E圖所示’移除該光罩金屬層22以露出該第一 介電層21a、深開口 211及淺開口 212。 13 110595 200934334 如第5F圖所示，於該第一介電層21 a上、深開口 211 中、淺開口 212中及接觸墊2〇la上形成有導電層23。 、 如第5G圖所示’於該導電層23表面形成有金屬層 24，且於該深開口 211中形成第一導電盲孔24〇，於該淺 開口 212中形成第一線路層241。 如第5H圖所不，移除未形成於該深開口 21丨及淺開 口 212中之導電層23及金屬層24，且使該第一線路層241 及第一導電盲孔240上表面與第一介電@21a齊平；其 〇中，該第-導電盲孔240之上表面無須形成孔環，而可免 除佔用佈線空間，以提高佈線密度。 [第四實施例] 明參閱第6A至6H圖’係顯示本發明之電路板製法第 四實施例之剖面示意圖。 如第6A圖所示’提供一係如第5A圖所示之結構，並 於該核心板20之表面20a上的第一 ❾ 口 m中形成光罩金屬層22。第”電層…上及淺開 a 如第6B圖所示’對該光罩金屬層22進行圖案化製 私，以形成複數光罩開口 22〇’以露出該第一介電層Η 之部份表面、並露出該淺開口 212。 曰 如圖所示，於該光罩開口 22〇中之第 U以長波雷射形成深開口 211，並對應露出該接= 〇la，且部份淺開口 212連通該深開口 。 如第6D圖所示，移除該光罩金屬層Μ 介電層na、深開口 211及淺開口犯。 出”亥苐- 310595 14 200934334 :如第6E圖所示’於該核心板2〇 .•與、-接# 古馇 播 又/木開口 211中以化 U電彳生連接該接觸墊 子/儿積形成有第一導電盲孔240 、201a。 如第6F圖所示，之後，於該第 開口 212中及第一導電盲孔24。 層 上、淺 ,^ ar 上形成有導電層23。 如第6G圖所不，於該導電層 24。 增以表面形成有金屬層 如第6H圖所示’最後，移除， 。丄 秒除未形成於該深開口 211 ❹及淺開口 212中之導電層23及金 212 M ^ a 、屬層24,以於該淺開口 中形成第一線路層241，並於兮您„ 01，丄 一道#亡 Λ /木開口 2ll中形成第 導電盲孔2 4 0，且使★ 玄望一 rtJb m 94ημ主a 更以、線路層241及第一導電盲孔 240上表面與第一介電層21a齊平。 因此’本發明之電路板製法 篦- He 取衣忐该第-、第二線路層及 一導電盲孔之上表面係與該第一、第二介電層之 上表面齊平，故能有效控制線路之形狀，以避免該第一、 線路層之線寬過寬而影響細線路之提昇；且該第 a第一導電盲孔上表面無須形成孔環，而可免除佔用佈 線二間，以提高佈線密度。 上述實施例係用以例示性說明本發明之原理及其功 效’而非用於限制本發明。任何熟習此項技藝之人士均可 在=違背本發明之精神及範疇下，對上述實施例進行修 因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單說明】 110595 15 200934334 '苐1A至1F圖係為習知於』士 勺* $於封裝基板表面接置半導體晶 片之示意圖； .第2圖係為第1F圖之局部Α的立體圖. 第3Α至则係為本發明電路板製法第；_實施例剖視 圖； 第3G’圖係為第3G圖之局部Β的立體圖； 第4Α至4D ®係為本發明電路板製法第二實施例剖視 圖； ❾第5Α·^ 5Η圖係為本發明ΐ：路板製法第三實施例剖視 圖；以及 第6Α至6Η圖係為本發明電路板製法第四實施例剖視 圖。 【主要元件符號說明】 10、 20 核心板 101 電鍍導通孔 10a 第一表面 10b 第二表面 η、 241 第一線路層 12 填充材料 13 介電層 130 ' 260 開孔 14、 23 導電層 15 阻層 150 開口 16 110595 200934334 16 ; 242 '161 161a 201 201a 20a 211 212 O^la 21b 22 220 24 240 25 250 26 第二線路層 導電盲孔 孔環 核心線路層 接觸墊 表面 深開口 淺開口 第一介電層 第二介電層 光罩金屬層 光罩開口 金屬層 第一導電盲孔 線路增層結構 第二導電盲孔 電性連接墊 絕緣保護層 17 110595$ has an opening 130' to expose a portion of the first-line layer 11; as shown in FIG. 1D!, a guide 〇=14' is formed on the surface of the dielectric layer 13 and the opening 13 thereof, and A resist layer 15 is formed on the conductive layer 14, and the resist layer is formed with an opening 150 to expose a portion of the surface of the conductive layer 4; the conductive layer 14 in the opening 150 of the resist layer 15 is electrically charged. The second circuit layer 16 is in the opening 13 of the dielectric layer 13. The middle = conductive via 16 is electrically connected to the first wiring layer; the resist layer 15 and the second wiring layer 16 are removed as shown in the figure. In the lead guide, when the resist layer 15 is removed by the method, the side etching problem will reduce the line width of the 110595 6 200934334 and the second circuit layer 16 on the surface of the dielectric layer 13, that is, the first Erguang has a predetermined line width; therefore, it cannot be two: redundancy - system... quality instability may cause the middle layer:: road situation, but if the original second circuit layer is added, f is broken, which hinders the fine line process. The improvement of ability. See the sigh line, please refer to Figure 2, which is the 1F map. The opening (10) of the layer 15 must be larger than the = =;; 130, so that the second circuit layer 16 is favorable; The hole © is on the conductive blind hole 161, #,, Ιβ, 1β1, the blind hole 16 is thus first recorded, and the hole ring MU is electrically connected to the first circuit layer 16, and the conductive blind hole 16 is partially wired. The area is also hindered by the fine line process capability. ^f+J: The structure of the existing second circuit layer 16 on the surface of the dielectric layer 13 still has its technical bottleneck for the k-liter fine line process capability. SUMMARY OF THE INVENTION In view of the above-mentioned disadvantages of the prior art, the main object of the present invention is to provide a circuit board manufacturing method for forming a circuit board of a fine circuit and an electrical function of the circuit board. For the above and other purposes, the present invention discloses a circuit board manufacturing method comprising: providing a core board having a core circuit layer on its surface, and the $ core circuit layer has a plurality of contact pads; a private layer, a short-wave laser is formed in the first dielectric layer to form a plurality of deep openings, and the contact opening is correspondingly exposed; a long-wave laser is formed in the first-dielectric layer to form a plurality of shallow openings, and a part of the shallow opening is connected The deep opening, corresponding to the exposed 10595 7 200934334 contact 塾; a conductive layer is formed on the first dielectric layer, in the deep opening, in the shallow opening, and on the contact pad; a metal layer is formed on the surface of the conductive layer, and Forming a first conductive via hole in the ice opening, forming a first circuit layer in the shallow opening; and removing a conductive layer and a metal layer not formed in the deep opening and the shallow opening, and removing the first circuit layer And the upper surface of the first conductive blind via is flush with the dielectric layer. The present invention provides another method for manufacturing a circuit board, comprising: providing a core board having a core layer, wherein the core circuit layer has a plurality of contacts; and forming a first dielectric on the core board Forming a plurality of deep openings in the first dielectric layer by short-wave lasers, and correspondingly exposing the contact 塾' to form a plurality of shallow openings in the first dielectric layer by long-wave lasers, and a portion of the shallow openings are connected to the layer a deep opening, and correspondingly exposing the contact 塾; a first conductive blind via is formed by chemical deposition in the deep opening to electrically connect the contact 塾; on the first dielectric layer, in the shallow opening, and the first-conductive blind a conductive layer is formed on the hole; a metal layer is formed on the surface of the conductive layer; and (4) a first circuit layer is formed in the shallow opening, and the V electrical layer and the metal layer not formed in the deep and shallow openings are removed, And the upper surface of the first circuit layer and the first conductive via is flush with the first dielectric layer. The invention further provides another circuit board manufacturing method, comprising: providing a core-board having a core circuit layer on its surface, and the core circuit layer has a plurality of contact pads, and forming a first dielectric layer on the e-core core plate Forming a plurality of shallow openings in the first dielectric layer by using a long-wave laser; forming a photomask metal layer on the first dielectric layer and the shallow opening; and forming a plurality of patterned metal layers on the photomask metal layer The reticle is opened to expose a portion of the first dielectric layer, Table 8 110595 200934334, and the ice is opened and correspondingly exposed (4), and a portion of the shallow opening communicates with the deep opening, and the reticle metal layer is removed; a conductive layer is formed in the first-different opening and the contact pad, and the mineral layer has a genus layer in the conductive surface, and a first conductive bland is formed in the deep opening, and the material is shallow: 20% f' circuit layer; And removing the conductive layer and the metal layer not formed in the deep opening and the reverse opening, and the upper surface of the first circuit layer and the first conductive via hole are flush with the first dielectric layer. The present invention further provides another method of manufacturing a circuit board, comprising: providing a core board having a core circuit layer on its surface, and the core turn layer = a number of contact pads; forming a first dielectric layer on the core board Forming a plurality of shallow opening σ in the first dielectric layer; forming a photomask metal layer in the first dielectric layer 2 and the shallow opening; and forming the photomask metal layer into a plurality of photomask openings to form a plurality of photomask openings Exposed part of the first dielectric layer table = long f mine? a first dielectric layer in the reticle opening forms a plurality of ice mash openings corresponding to the contact pads, and a portion of the shallow opening communicates with the deep opening; removing the reticle metal layer; chemistry in the deep opening Depositing a first conductive via to electrically connect the contact pad; forming a conductive layer on the first dielectric tray, in the shallow opening, and on the first conductive via; on the surface of the layer; a layer; and removing a conductive layer and a metal layer not formed in the deep opening D and the shallow opening to form a first wiring layer in the shallow opening, and forming a first conductive blind hole in the deep opening, and The first circuit layer and the upper surface of the first conductive via are flush with the first dielectric layer. According to the above various methods, the core board is an insulating board or a circuit board having a core line 110595 9 200934334; the short-wave laser system is an ultraviolet laser, a mirrored stone (Nd-YAG) laser or Excimer laser; the long-wave laser system is a carbon dioxide laser. According to the above manufacturing method, a line build-up structure is formed on the surface of the first dielectric layer and the first circuit layer, and the line build-up structure includes at least a second dielectric having a plurality of shallow openings and deep openings. a second circuit layer formed in the first opening of the first electrical layer, and a second conductive blind via formed in the deep opening of the second dielectric layer and electrically connected to the second wiring layer Wherein the second circuit layer and the second conductive via hole upper surface and the second dielectric layer are flush, and a plurality of electrical connection pads electrically connected to the second circuit layer are formed on the surface of the line build-up structure, An insulating protective layer is formed on the line build-up structure, and the insulating protective layer is formed with a plurality of openings to electrically connect the pads. Therefore, in the circuit board manufacturing method of the present invention, the upper surface of the first and second circuit layers and the first and second conductive blind holes are flush with the upper surface of the first and second dielectric layers, so Effectively controlling the shape of the line to avoid that the line width of the Lth and second circuit layers is too wide to affect the improvement of the thin line; and the upper surface of the first and second conductive blind holes does not need to form a hole ring, and the wiring is eliminated. Space to increase wiring density. [Embodiment] The embodiments of the present invention will be described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. [First Embodiment] 110595 10 200934334 'Please refer to Figs. 3A to 3H, which are schematic cross-sectional views showing a first embodiment of the circuit board manufacturing method of the present invention. ‘·· As shown in Fig. 3A, a core board 2 is first provided, the surface 2A of which has a core circuit layer 201, and the core circuit layer 201 has a plurality of contact pads 201a. As shown in FIG. 3B, hot pressing, rolier coating, printing, spin coating, dipping, or the like on the surface 20a of the core plate 2A. The first dielectric layer 21a is formed by vaccum lamination. As shown in FIG. 3C, a short-wave laser which is an ultraviolet laser, a yttrium aluminum garnet (Nd-YAG) laser or an excimer laser is formed in the first dielectric layer 21a to form a complex deep. The opening 211 is corresponding to the contact pad 201a. As shown in FIG. 3D, a plurality of shallow openings 212 are formed in the first dielectric layer 21a by a long-wavelength laser beam, and a portion of the shallow opening 212 is: a deep opening 211' and correspondingly exposing the contact pad. 2〇la; followed by despel and roughening. As shown in Fig. 3E, a conductive layer 23 is formed on the first dielectric layer 21a, in the deep opening 211, in the shallow opening 212, and on the contact pad 201a. As shown in FIG. 3F, a metal layer 24 is formed on the surface of the conductive layer 23, and a first conductive via hole 24 is formed in the deep opening 211, and a first wiring layer 241 is formed in the shallow opening 212. As shown in FIG. 3G, the conductive layer 23 and the metal layer 24' not formed in the deep opening 21丨 and the shallow opening 212 are removed and the first circuit layer 241 110595 11 200934334 and the first conductive blind via 240 are removed. The surface is flush with the first dielectric layer 2ia. Please also refer to the 3G' diagram, which is the upper part of the part β of the 3G figure, wherein the upper surface of the first conductive blind hole 24〇 does not need to form a hole ring, and the occupied wiring space can be eliminated to improve the wiring density. . As shown in FIG. 3, a line build-up structure 25 is formed on the surface of the first dielectric layer 21a and the first circuit layer 241. The line build-up structure 25 includes at least one of a plurality of shallow openings 212 and deep openings 211. a second dielectric layer 21b, a second circuit layer 242 formed in the shallow opening 212 of the second dielectric layer 2ib, and a deep opening 211 formed in the second dielectric layer 21b and electrically connected to the second dielectric layer 21b. a second conductive via hole 250 of the second circuit layer 242, wherein the upper surface of the second circuit layer 242 and the second conductive blind via 25 are flush with the second dielectric layer 21b, and are on the surface of the circuit buildup structure 25 An electrical connection pad 251 electrically connected to the second circuit layer 242 is formed, and an insulating protection layer 26 is formed on the circuit build-up structure 25, and the insulating protection layer 26 is formed with a plurality of openings 260 to correspondingly expose the electrical property. Connect 塾251. [Second Embodiment] Referring to Figures 4A to 4D, there is shown a schematic cross-sectional view showing a second embodiment of the circuit board manufacturing method of the present invention. As shown in FIG. 4A, a structure as shown in FIG. 3A is provided, and a first conductive blind via 240 is chemically deposited in the deep opening 211 of the core board 20 to electrically connect the contact pad. 2〇la. As shown in Fig. 4B, a conductive layer 23 is formed on the first dielectric layer 21a, in the shallow opening 212, and on the first conductive via 240. As shown in Fig. 4C, a metal layer 12 110595 200934334 24:' is formed on the surface of the conductive layer 23, and a first wiring layer 241 is formed in the shallow opening 212. As shown in FIG. 4D, finally, the conductive layer 23 and the metal layer 24' not formed in the deep opening 2ΐι'-and the shallow opening 212 are removed and the first wiring layer 241 and the first conductive blind via 240 are disposed. The surface is flush with the first dielectric layer 21& [THIRD EMBODIMENT] Please refer to Figs. 5A to 5H, which are schematic cross-sectional views showing a third embodiment of the circuit board manufacturing method of the present invention. ° As shown in Fig. 5A, a structure as shown in Fig. 3B is provided, and a plurality of shallow openings 212 are formed by long-wave laser light on the first dielectric layer 2ia of the surface 20a of the "Hui core~ board 20. As shown in FIG. 5B, a photomask metal layer 22 having a thickness of 〇〇3 to between the first dielectric layer 21& and the shallow opening 212 is formed by chemical deposition or sputtering. The metal layer 22 is made of steel (Cu), aluminum (A1), nickel (Ni), chromium (Cr), titanium (Ti), titanium/copper (Ti/Cu), yttrium silver (Ag), gold (Au), Or one of the groups consisting of palladium (pd). As shown in FIG. 5C, the mask metal layer 22 is patterned to form a plurality of mask openings 220 to expose portions of the first dielectric layer 21& and expose the shallow openings 212. As shown in FIG. 5D, the first dielectric layer 21a in the mask opening 22A forms a deep opening 21丨 with a long-wave laser, and correspondingly exposes the contact pad 201a, and a part of the deep opening 211 communicates with the shallow opening. 212. The mask metal layer 22 is removed as shown in Fig. 5E to expose the first dielectric layer 21a, the deep opening 211, and the shallow opening 212. 13 110595 200934334 As shown in FIG. 5F, a conductive layer 23 is formed on the first dielectric layer 21a, in the deep opening 211, in the shallow opening 212, and on the contact pad 2A1a. A metal layer 24 is formed on the surface of the conductive layer 23 as shown in FIG. 5G, and a first conductive via hole 24 is formed in the deep opening 211, and a first wiring layer 241 is formed in the shallow opening 212. As shown in FIG. 5H, the conductive layer 23 and the metal layer 24 not formed in the deep opening 21 and the shallow opening 212 are removed, and the upper surface of the first wiring layer 241 and the first conductive blind via 240 are A dielectric @21a is flush; in the crucible, the upper surface of the first conductive via 240 does not need to form a hole ring, and the wiring space can be eliminated to increase the wiring density. [Fourth Embodiment] Referring to Figures 6A to 6H, there is shown a cross-sectional view showing a fourth embodiment of the circuit board manufacturing method of the present invention. As shown in Fig. 6A, a structure as shown in Fig. 5A is provided, and a mask metal layer 22 is formed in the first opening m on the surface 20a of the core board 20. "Electrical layer...upper and shallower opening a as shown in FIG. 6B' patterning the reticle metal layer 22 to form a plurality of reticle openings 22" to expose the portion of the first dielectric layer The surface is exposed, and the shallow opening 212 is exposed. As shown in the figure, the U in the reticle opening 22 is formed by a long-wave laser to form a deep opening 211, and correspondingly exposes the connection = 〇la, and a portion of the shallow opening 212 is connected to the deep opening. As shown in Fig. 6D, the reticle metal layer 介 dielectric layer na, deep opening 211, and shallow opening are removed. "海苐- 310595 14 200934334: as shown in Fig. 6E" The first conductive blind holes 240, 201a are formed in the core board 2 〇.•和, 接 #古馇播/木开口211 in the connection of the contact pads/children. As shown in FIG. 6F, the first conductive via 24 is then formed in the first opening 212. A conductive layer 23 is formed on the layer, shallow, and ar. The conductive layer 24 is as shown in Fig. 6G. The surface is formed with a metal layer as shown in Fig. 6H. Finally, removed. The second layer includes a conductive layer 23 not formed in the deep opening 211 ❹ and the shallow opening 212, and a gold 212 M ^ a, a genus layer 24 to form a first wiring layer 241 in the shallow opening, and , a Λ Λ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / The electric layer 21a is flush. Therefore, the circuit board of the present invention has a surface on the upper surface of the first and second circuit layers and a conductive via hole and a surface on the upper surface of the first and second dielectric layers. Flush, so that the shape of the line can be effectively controlled to avoid the line width of the first and the circuit layer being too wide to affect the improvement of the thin line; and the upper surface of the first first conductive blind hole does not need to form a hole ring, and can be exempted The wiring is used to increase the wiring density. The above embodiments are used to exemplify the principles of the present invention and its functions, and are not intended to limit the present invention. Anyone skilled in the art can In the spirit and scope, the above embodiments are modified so that the rights of the present invention are protected. The scope shall be as listed in the scope of application of the patents described later. [Simple description of the drawings] 110595 15 200934334 '苐1A to 1F is a schematic diagram of a conventional semiconductor wafer mounted on the surface of a package substrate; 2 is a perspective view of a partial Α of the 1Fth diagram. The third embodiment is the circuit board manufacturing method of the present invention; the cross-sectional view of the embodiment; the 3G' image is a partial view of the partial 第 of the 3G image; 4th to 4D ® is a cross-sectional view of a second embodiment of the circuit board manufacturing method of the present invention; ❾5❾·5 5Η is a cross-sectional view of the third embodiment of the road plate manufacturing method; and the sixth drawing to the sixth drawing is the circuit board manufacturing method of the present invention. Cross-sectional view of four embodiments. [Description of main components] 10, 20 core board 101 plating via 10a first surface 10b second surface η, 241 first wiring layer 12 filling material 13 dielectric layer 130 ' 260 opening 14, 23 Conductive layer 15 resist layer 150 opening 16 110595 200934334 16 ; 242 '161 161a 201 201a 20a 211 212 O^la 21b 22 220 24 240 25 250 26 second circuit layer conductive blind via ring core circuit layer contact pad surface Deep opening shallow opening first dielectric layer second dielectric layer photomask metal layer photomask opening metal layer first conductive blind hole line build-up structure second conductive blind via electrical connection pad insulating protective layer 17 110595