200934160 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於多輸入多輸出正交分頻多工系統 之決策回饋式通道估測器。 【先前技術】 對於習知多輸入多輸出正交分頻多工系統而言，接收端 欲進行決策回饋式通道估測時，會將其他天線所造成的干 擾估測出來並扣除，參考先前技術文獻[丨卜卩]。 在決策回饋通道估測中，接收訊號*㈨和Λμ+1]可表示 印]=好。[々]./。[々]+/^+1】.尤卜+1】+昨] λ[α：+1]=一丑。[灸+κ μ+!]+仏⑷尤:⑷+時+^200934160 IX. Description of the Invention: [Technical Field] The present invention relates to a decision feedback type channel estimator for a multiple input multiple output orthogonal frequency division multiplexing system. [Prior Art] For the conventional multi-input multi-output orthogonal frequency division multiplexing system, when the receiving end wants to perform the decision feedback channel estimation, the interference caused by other antennas is estimated and deducted, refer to the prior art literature. [丨卜卩]. In the decision feedback channel estimation, the received signals *(9) and Λμ+1] can indicate the print]=good. [々]./. [々]+/^+1].Yub +1]+ yesterday] λ[α:+1]= ugly. [Moxibustion + κ μ+!] + 仏 (4) Especially: (4) + hour + ^
習知決策回饋式通道估測法如下式表示： 2,5W _2·作+ 1] IW 外+1】+υμ·[々+1] 2 部+ 1] -2-5*W ⑴ (2) 其中片Mls，〇M為利用改良型最小平方（Modified Least Square，MLS)估測器所求得之初始通道，左㈨與巧纣丨]為利 用初始通道所解調出之訊號，而[為多重路徑數和^洲為訊 號雜訊比。 麥考圏1A及1B ’其顯示習知通道估測器之電路示意 圖。習知通道估測器100包括：一第五乘法器丨丨j、一第六 125058.doc 200934160 乘法器112、一第二減法器113、一第三減法器114、一第 三除法器115、一第四除法器116、一第四減法器117、一 第七乘法器121、一第八乘法器122、一第五減法器123、 一第六減法器124、一第五除法器125、一第六除法器126 及一第七減法器127。因此，利用圖1A及1B之電路可以實 現上述式（1)及（2)之計算。然而，習知通道估測器之電路 過於複雜’降低習知決策回饋式通道估測器之估測效能。The conventional decision-making feedback channel estimation method is expressed as follows: 2,5W _2·+1] IW outer +1]+υμ·[々+1] 2 parts + 1] -2-5*W (1) (2) The slice Mls, 〇M is the initial channel obtained by the Modified Least Square (MLS) estimator, and the left (nine) and the sinus 纣丨 are the signals demodulated by the initial channel, and [for The number of multiple paths and the number of channels are signal noise ratios. McCaw 圏 1A and 1B' show circuit diagrams of conventional channel estimators. The conventional channel estimator 100 includes: a fifth multiplier 丨丨j, a sixth 125058.doc 200934160 multiplier 112, a second subtractor 113, a third subtractor 114, a third divider 115, a fourth divider 116, a fourth subtractor 117, a seventh multiplier 121, an eighth multiplier 122, a fifth subtractor 123, a sixth subtractor 124, a fifth divider 125, and a The sixth divider 126 and a seventh subtractor 127. Therefore, the calculation of the above equations (1) and (2) can be realized by the circuits of Figs. 1A and 1B. However, the circuit of the conventional channel estimator is too complex to reduce the estimated performance of the conventional decision feedback channel estimator.
另外，假設資料完全解調正確的情況下，習知決策回饋 式通道估測器之均方誤差可表為下式（3) E{丨卜w-lwll:} 1 ll 2·^] ~~」’ (3) . 2¾ 2—部+ 1]~~ Γ L 1 (Λ 2ΐλIn addition, assuming that the data is completely demodulated correctly, the mean square error of the conventional decision-feedback channel estimator can be expressed as the following equation (3) E{丨卜w-lwll:} 1 ll 2·^] ~~ "' (3) . 23⁄4 2 - part + 1]~~ Γ L 1 (Λ 2ΐλ
N SNR、 NJ 其中#]=//#]-々_[々];紐+1]=琴μ+1卜U+1]。藉由上 述之數學分析’可以發現習知方式會受到初始通道估測錯 誤的影響’因而降低決策回饋通道估測的準確度。 因此，有必要提供一種創新且具進步性的用於多輸入多 輸出正交分頻多工系統之決策回饋式通道估測器，以解決 上述問題。 先前技術文獻： [1] S.Bowei ,Z. Wenjun ,and G.Lin, "Iterative joint channel estimation and signal detection in ΜΙΜΟ OFDM systems," 125058.doc 200934160 in Proc. Wireless comm. Con/., vol.,Sep. 2005, pp. 23-23. . [2] C.Jiming and L.Shaoqian,"Iterative channel estimation for ΜΙΜΟ OFDM systems," in Proc. Circuit and System Conf., vol.27-30,May 2005, pp. 180-184.N SNR, NJ where #]=//#]-々_[々]; New+1]=琴 μ+1 Bu U+1]. Through the above mathematical analysis, it can be found that the conventional method is affected by the initial channel estimation error, thus reducing the accuracy of the decision feedback channel estimation. Therefore, it is necessary to provide an innovative and progressive decision feedback feedback channel estimator for a multiple input multiple output quadrature frequency division multiplexing system to solve the above problem. Previous Technical Literature: [1] S.Bowei, Z. Wenjun, and G.Lin, "Iterative joint channel estimation and signal detection in ΜΙΜΟ OFDM systems," 125058.doc 200934160 in Proc. Wireless comm. Con/., Vol., Sep. 2005, pp. 23-23. . [2] C.Jiming and L. Shaoqian, "Iterative channel estimation for ΜΙΜΟ OFDM systems," in Proc. Circuit and System Conf., vol.27- 30, May 2005, pp. 180-184.
[3] E.Karami and M.Shiva, "A new joint channel estimation and detection algorithm for ΜΙΜΟ channels," in APCC Con/., vol.21-24,Sep. 2003, pp. 283-286. 【發明内容】 本發明提供一種用於多輸入多輸出正交分頻多工系統之 決策回饋式通道估測器，包括：一第一乘法器、一第二乘 法器、一第一減法器、一第一除法器、一第三乘法器、一. 第四乘法器、一第一加法器及一第二除法器。該第一乘法 器用以將一第一接收訊號與一第一初始通道解調訊號之共 軛訊號相乘，以計算得一第一乘法結果。該第二乘法器用 以將一第二接收訊號與一第二初始通道解調訊號相乘，以 ❹ 計算得一第二乘法結果。該第一減法器用以將該第一乘法 結果減該第二乘法結果，以計算得一第一減法結果。該第 一除法器用以將該第一減法結果除一第一設定值，以計算 得一第一通道估測。該第三乘法器用以將該第一接收訊號 與一第二初始通道解調訊號之共軛訊號相乘，以計算得一 第三乘法結果。該第四乘法器用以將該第二接收訊號與一 第一初始通道解調訊號相乘，以計算得一第四乘法結果。 該第一加法器用以將該第三乘法結果加該第四乘法結果， 以計算得一第一加法結果。該第二除法器用以將該第一加 125058.doc 200934160 法結果除該第一設定值’以計算得一第二通道估測。 * 本發明用於多輪入多輸出正交分頻多工系統之決策回饋 式通道估測器。利用空頻區塊碼或空時區塊碼進行決策回 饋通道估測’可降低硬體電路之複雜度，且可改善決策回 饋式通道估測的效能。 【實施方式】 參考圓2,其顯示本發明多輸入多輸出正交分頻多工系 0 統之示意圖。本發明多輸入多輸出正交分頻多工系統2〇包 括：一調變器21、一空頻區塊碼編碼器22、一第一反快速 傅立葉轉換器及循環字首插入器23、一第二反快速傅立葉 轉換器及循環字首插入器24、一第一發射器25、一第二發 射器26、一接收器31、一快速傅立葉轉換器及循環字首移 除器32、一空頻區塊碼解碼器33、一決策回饋式通道估測 器34及一解調變器35 » 在本發明之實施例中係以空頻區塊碼（Space_Frequency ❹ Block Codes，SFBC)進行通道估測，因此利用空頻區塊碼 編碼器22及空頻區塊碼解碼器33進行編碼及解瑪β但本發 明不限於利用空頻區塊碼進行通道估測，亦可利用空時區 塊碼（Space-Time Block Codes, STBC)進行通道估測 β 在本發明之實施例中將兩根天線經過的通道分別表示為 通道//利與，並假設札闪=/^+1]與Ηι[十接收 訊號和Λ[λ：+1]可表示為： μ]=//〇 Μ. χ0 [ λ]+巧 μ+1].不 μ+1]+r [*] 125058.doc 200934160 Λ[λ+1] 一付。[灸+ 1】〇 + 1】+丑掛不•卜]十昨+幻 * 如上所述習知決策回饋通道估測法如下式表示： ' 片c.〇m=^L^s.,w.+i],々[“ι]-υ+ιμ·⑷ 2S[k] ^25*μ + ΐ] ⑴ 都].卟+ι]+υΗ·ί 纣 11 2 部+1】 T¥[k] (2) 本發明用於多輸入多輸出正交分頻多工系統之決策回饋 ❹ 式通道估測器之實施例中則利用空頻區塊碼進行通道估 測’如下式表示 瓦小卜少KW-啡+1]部+1】 1 綱 f+M2 (4) 瓦.μ卜％]仰+11+哗+1]部] (5) 參考囷3A及3B，其顯示本發明用於多輸入多輸出正交 分頻多工系統之決策回饋式通道估測器之電路示意囷。本 © 發明用於多輸入多輸出正交分頻多工系統之決策回館式通 道估測器34包括：一第一乘法器41、一第二乘法器42、一 第一減法器43、一第一除法器44、一第三乘法器5 1、一第 四乘法器52、一第一加法器53及一第二除法器54。 該第一乘法器41用以將一第一接收訊號/?[々】與一第一初 始通道解調訊號之共軛訊號士[幻相乘，以計算得一第一乘 法結果Λ⑷χίγ/Γ]。該第二乘法器42用以將一第二接收訊號 叫灸叫與一第二初始通道解調訊號/ [hi]相乘，以計算得一 第二乘法結果Λ[々 + 1]χί R + 1]。該第一減法器43用以將該第 125058.doc -10- 200934160 一乘法結果減該第二乘法結果，以計算得一第一減法結 果。該第一除法器44用以將該第一減法結果除一第一設定 值，以計算得一第一通道估測。闪。該笫一設定值為第 一初始通道解調訊號大小之平方加上第二初始通道解調訊 號大小之平方 S[k] 故可利用圖3 A電路實現式（4) 之計算。 ❹ 該第三乘法器51用以將該第一接收訊號與一第二初 始通道解調訊號之共軛訊號ί·ρ+1]相乘，以計算得一第三 乘法結果[幻[Λ + 1] »該第四乘法器52用以將該第二接收 訊號哗+1]與一第一初始通道解調訊號《[幻相乘，以計算得 一第四乘法結果Λ[* + 1]χί [々]。該第一加法器53用以將該第 三乘法結果加該第四乘法結果，以計算得一第一加法結 果。該第二除法器54用以將該第一加法結果除該第一設定 值，以計算得一第二通道估測[幻。故可利用圖3Β電路 實現式（5)之計算。 而利用式（4)和式（5)兩式進行的通道估測，在假設資料 完全解調正確的情況下，其均方誤差可表為 Ε (6) 比較習知式（3)之均方誤差和式（6)之均方誤差，可以明 顯發現，本發明利用空頻區塊碼進行決策回饋通道估測的 均方誤差值明顯小於一般直接使用干擾消除的方式β習知 消除千擾的泱策回餚適道估測之均方誤差比利用空頻區塊 瑪特性作決策回饋通道估測多出了通道估測錯誤量因此 125058.doc -Π · 200934160 會得到較差的效能。 . 參考圖4 ’其顯示習知系統與本發明系統之模擬比較示 • 意圖。利用Matlab模擬進行驗證，可以發現在高訊雜比的 條件下，理論值和模擬值的結果相當接近。這是由於理論 值的推導做了當資料解調完全正確的假設。更進一步，可 以發現利用空頻區塊碼進行之決策回饋式通道估測器，其 效能始終比習知直接干擾消除的方式佳。 @ 分析比較習知電路與本發明電路之複雜度，由式（1)和 式（2)及圖1A及1B可知，習知決策回饋通道估測電路需要 四個乘法器’四個除法器，六個加減法器；由式（4)和式 (5)及圖3A及3B可知，本發明利用空頻區塊碼作通道估測 需要四個乘法器’二個除法器，二個加減法器。因此，本 發明利用空頻區塊碼之決策回饋式通道估測器，只需要較 低的複雜度便可達成。 雖然上述實施例係以2x1的空頻區塊碼正交分頻多工系 ❿ 統（SFBC-〇FDM)下進行探討，不過本發明可以拓展到 的空頻區塊碼正交分頻多工系統（sfbc_〇Fdm)或是空時區 塊碼正交分頻多工系統（STBC-OFDM)中。 惟上述實施例僅為說明本發明之原理及其功效，而非限 制本發明。因此’習於此技術之人士對上述實施例進行修 改及變化仍不脫本發明之精神。本發明之權利範圍應如後 述之申請專利範圍所列。 【圖式簡單說明】 圖1A及1B係顯示習知通道估測器之電路示意圖； 125058.doc 12 200934160 圖2係顯示本發明多輸入多輸出正交分頻多工系統之示 意圖； 圖3 A及3B係顯示本發明用於多輸入多輸出正交分頻多 工系統之決策回饋式通道估測器之電路示意圖；及 圖4係顯示習知系統與本發明系統之模擬比較示意圖。 【主要元件符號說明】 20 本發明多輸入多輸出正交分頻多工系統[3] E.Karami and M. Shiva, "A new joint channel estimation and detection algorithm for ΜΙΜΟ channels," in APCC Con/., vol.21-24, Sep. 2003, pp. 283-286. SUMMARY OF THE INVENTION The present invention provides a decision feedback loop estimator for a multiple input multiple output orthogonal frequency division multiplexing system, including: a first multiplier, a second multiplier, a first subtractor, and a first multiplier a first divider, a third multiplier, a fourth multiplier, a first adder, and a second divider. The first multiplier is configured to multiply a first received signal by a conjugate signal of a first initial channel demodulation signal to calculate a first multiplication result. The second multiplier is configured to multiply a second received signal by a second initial channel demodulation signal to calculate a second multiplication result. The first subtractor is configured to subtract the first multiplication result from the second multiplication result to calculate a first subtraction result. The first divider is configured to divide the first subtraction result by a first set value to calculate a first channel estimate. The third multiplier is configured to multiply the first received signal by a conjugate signal of a second initial channel demodulation signal to calculate a third multiplication result. The fourth multiplier is configured to multiply the second received signal by a first initial channel demodulation signal to calculate a fourth multiplication result. The first adder is configured to add the third multiplication result to the fourth multiplication result to calculate a first addition result. The second divider is configured to divide the first plus 125058.doc 200934160 method result by the first set value ' to calculate a second channel estimate. * The present invention is a decision feedback type channel estimator for a multi-wheeled multi-output quadrature frequency division multiplexing system. The use of space-frequency block codes or space-time block codes for decision feedback channel estimation can reduce the complexity of the hardware circuit and improve the performance of the decision feedback channel estimation. [Embodiment] Referring to Circle 2, there is shown a schematic diagram of a multiple input multiple output orthogonal frequency division multiplexing system of the present invention. The multi-input multi-output orthogonal frequency division multiplexing system 2 of the present invention comprises: a modulator 21, a space-frequency block code encoder 22, a first inverse fast Fourier converter, and a cyclic prefix inserter 23, a first a two-inverse fast Fourier converter and a cyclic prefix inserter 24, a first transmitter 25, a second transmitter 26, a receiver 31, a fast Fourier transformer and a cyclic prefix remover 32, a space frequency region The block code decoder 33, a decision feedback channel estimator 34, and a demodulation transformer 35 are used in the embodiment of the present invention to perform channel estimation by using Space_Frequency ❹ Block Codes (SFBC). Therefore, the space frequency block code encoder 22 and the space frequency block code decoder 33 are used for encoding and decoding. However, the present invention is not limited to channel estimation using a space frequency block code, and may also utilize a space time block code (Space). -Time Block Codes, STBC) Perform Channel Estimation β In the embodiment of the present invention, the channels through which the two antennas pass are respectively represented as channels ///, and assumes that the flash is =/^+1] and Ηι [ten reception The signal and Λ[λ:+1] can be expressed as: μ]=//〇Μ. χ0 [ λ]+巧μ+1]. Not μ+1]+r [*] 125058.doc 200934160 Λ[λ+1] One payment. [Moxibustion + 1] 〇 + 1] + ugly hang not • Bu] Ten Yesterday + Magic * As mentioned above, the decision-making feedback channel estimation method is expressed as follows: 'C. 〇m=^L^s.,w .+i],々[“ι]-υ+ιμ·(4) 2S[k] ^25*μ + ΐ] (1) Both].卟+ι]+υΗ·ί 纣11 2 Part +1] T¥[k (2) The present invention is used for the decision feedback of the multi-input multi-output orthogonal frequency division multiplexing system. In the embodiment of the channel estimation device, the channel estimation is performed by using the space-frequency block code, which is represented by the following formula: Less KW-Pan +1] +1] 1 class f+M2 (4) watt.μb%] ++11+哗+1]] (5) Reference 囷3A and 3B, which show the invention is used for Circuit diagram of a decision feedback loop estimator for a multi-input multi-output quadrature frequency division multiplexing system. The present invention is a decision-making back-channel channel estimator for a multiple input multiple output quadrature frequency division multiplexing system. The method includes a first multiplier 41, a second multiplier 42, a first subtractor 43, a first divider 44, a third multiplier 51, a fourth multiplier 52, and a first adder. 53 and a second divider 54. The first multiplier 41 is configured to use a first received signal /?[々] with a first beginning The conjugate signal of the channel demodulation signal is [phantom multiplication to calculate a first multiplication result Λ(4) χίγ/Γ]. The second multiplier 42 is used to call a second reception signal a moxibustion and a second initial channel. The demodulation signal /[hi] is multiplied to calculate a second multiplication result Λ[々+ 1]χί R + 1]. The first subtractor 43 is used to multiply the 125058.doc -10- 200934160 As a result, the second multiplication result is subtracted to calculate a first subtraction result. The first divider 44 is configured to divide the first subtraction result by a first set value to calculate a first channel estimate. The first set value is the square of the first initial channel demodulation signal plus the square of the second initial channel demodulation signal size S[k], so the calculation of equation (4) can be implemented by using the circuit of Fig. 3A. The third multiplier 51 is configured to multiply the first received signal by a conjugate signal ί·ρ+1] of a second initial channel demodulation signal to calculate a third multiplication result [illusion [Λ + 1] » The fourth multiplier 52 is configured to demodulate the second received signal 哗+1] with a first initial channel demodulation signal [[phantom multiplication to calculate a fourth multiplication result Λ[* + 1] χί [々]. The first adder 53 is configured to add the third multiplication result to the fourth multiplication result to calculate a first addition result. The second division method The device 54 is configured to divide the first addition result by the first set value to calculate a second channel estimation [magic. Therefore, the calculation of the equation (5) can be implemented by using the circuit of FIG. 3, and the equation (4) is utilized. The channel estimation by equation (5) can be expressed as Ε (6) comparing the mean square error of the conventional equation (3) and the equation (6) under the assumption that the data is completely demodulated correctly. The mean square error can be clearly found that the mean square error value of the decision-making feedback channel estimation using the space-frequency block code is obviously smaller than that of the general direct use interference cancellation method. Estimated mean square error is more than the use of the space frequency block feature for decision feedback channel estimation. The channel estimation error is therefore 125058.doc -Π · 200934160 will get poor performance. Referring to Figure 4', a comparison of the conventional system and the system of the present invention is shown. Using Matlab simulation to verify, it can be found that under the condition of high signal-to-noise ratio, the theoretical and analog values are quite close. This is due to the assumption that the derivation of the theoretical value is completely correct when the data is demodulated. Further, it can be found that the decision feedback feedback channel estimator using the space frequency block code is always better than the conventional direct interference cancellation method. @ Analyze the complexity of the conventional circuit and the circuit of the present invention. From equations (1) and (2) and FIGS. 1A and 1B, the conventional decision feedback channel estimation circuit requires four multipliers 'four dividers, Six adder-subtracters; from equations (4) and (5) and Figures 3A and 3B, the present invention utilizes a space-frequency block code for channel estimation requiring four multipliers 'two dividers, two addition and subtraction methods Device. Therefore, the present invention utilizes a decision-back feedback channel estimator of a space-frequency block code, which can be achieved with only a low complexity. Although the above embodiment is discussed under the 2x1 space-frequency block code orthogonal frequency division multiplexing system (SFBC-〇FDM), the space frequency block code orthogonal frequency division multiplexing can be extended by the present invention. The system (sfbc_〇Fdm) or the space-time block code orthogonal frequency division multiplexing system (STBC-OFDM). However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1B are schematic diagrams showing a conventional channel estimator; 125058.doc 12 200934160 FIG. 2 is a schematic diagram showing a multiple input multiple output orthogonal frequency division multiplexing system according to the present invention; And 3B show a circuit diagram of a decision feedback type channel estimator of the present invention for a multiple input multiple output orthogonal frequency division multiplexing system; and FIG. 4 is a schematic diagram showing a simulation comparison between a conventional system and the system of the present invention. [Main component symbol description] 20 Multi-input multi-output orthogonal frequency division multiplexing system of the present invention
21 調變器 22 23 24 25 26 31 41 42 43 44 51 52 空頻區塊碼編瑪器 第一反快速傅立葉轉換器及循環字首插入器 第二反快速傅立葉轉換器及循環字首插入器 第一發射器 第二發射器 接收器 &速傅A葉轉換器及循環字首移除器 空頻區塊碼解碼器 決策回饋式通道估測器 解調變器 第一乘法器 第二乘法器 第一減法器 第一除法器 第三乘法器 第四乘法器 125058.doc -13 - 20093416021 Modulator 22 23 24 25 26 31 41 42 43 44 51 52 Space-frequency block code coder first inverse fast Fourier converter and cyclic prefix inserter Second inverse fast Fourier converter and cyclic prefix inserter First Transmitter Second Transmitter Receiver & Fast Four Leaf Transformer and Cyclic Header Remover Space Frequency Block Code Decoder Decision Feedback Channel Estimator Demodulation Transmuter First Multiplier Second Multiplication First subtractor first divider third multiplier fourth multiplier 125058.doc -13 - 200934160
53 第一加法器 54 第二除法器 100 習知通道估測器 111 第五乘法器 112 第六乘法器 113 第二減法器 114 第三減法器 115 第三除法器 116 第四除法器 117 第四減法器 121 第七乘法器 122 第八乘法器 123 第五減法器 124 第六減法器 125 第五除法器 126 第六除法器 127 第七減法器 125058.doc _ 14·53 first adder 54 second divider 100 conventional channel estimator 111 fifth multiplier 112 sixth multiplier 113 second subtractor 114 third subtractor 115 third divider 116 fourth divider 117 fourth Subtractor 121 seventh multiplier 122 eighth multiplier 123 fifth subtractor 124 sixth subtractor 125 fifth divider 126 sixth divider 127 seventh subtractor 125058.doc _ 14·