200921863 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體封裝構造，特別係有關於一 免黏晶溢膠之半導體封裝構造。 【先前技術】 當先進的半導體封裝技術朝向高頻記憶體及高 晶片之封裝，除了使用高密度佈線之基板或印刷電 作為晶片載體’晶片則希望藉由低成本的黏晶層以 在基板上。在黏晶的昇溫與施壓過程中，黏晶層將 机動性而發生溢膠。又當晶片之銲塾與打線通孔越 時’則黏晶層之溢膠情形會導致封裝_不良率提高。 凊參閱第1圖所示’一種習知半導體封裝構造 主要包含一基板11 0、一晶片1 2 0、複數個電性連 件1 40以及一封膠體1 5 0。該基板1 1 〇係具有一打 孔1 1 3與11 4以及複數個形成於該基板1丨〇下方之 塾1 1 5。請參閱第2圖所示，部分之打線通孔i i 3 於該基板1 1 0周邊，其中一打線通孔1 1 4係位於該 1 1 〇中央。該晶片1 2 0係具有複數個銲墊1 2 3，其 成於該晶片1 20之周邊與中央區域，以在黏晶後分 露於打線通孔1 1 3與1 1 4。請參閱第2圖所示，一 層1 3 0係塗佈於該基板11 〇之上方且不覆蓋該打線 U 3與1 1 4。該黏晶層1 3 0係黏貼該晶片1 2 0之主 至該基板11 0之上表面（如第1圖所示）。該些電性 元件1 4 0係可通過該打線通孔1 1 3與1 1 4並電性連 種避 效能 路板 貼設 具有 接近 100 接元 線通 外接 係位 基板 係形 別顯 黏晶 通孔 動面 連接 接該 200921863 些銲墊1 2 3至該基板1 1 〇。該封膠體1 5 0係以壓模方式 形成於該基板11 〇之上方以及該些打線通孔11 3與11 4 内，以密封該晶片1 2 0與該些電性連接元件1 4 0。複數 個例如銲球之外接端子1 6 0係設置於該基板1 1 0之該些 外接墊1 1 5。 在黏晶過程中，將該晶片1 2 0熱壓合至該基板1 1 〇 之上方，使該黏晶層1 3 0黏接該晶片1 20與該基板1 1 0。 然而’在受到高溫與壓力下該黏晶層1 3 0會具有流動200921863 Nineth, the invention is related to the invention. [Prior Art] When advanced semiconductor packaging technology is oriented toward high-frequency memory and high-wafer packaging, in addition to using high-density wiring substrate or printed electricity as a wafer carrier, the wafer is desired to be on the substrate by a low-cost adhesive layer. . During the temperature rise and pressure application of the viscous crystal, the viscous layer will be maneuverable and overflow. In addition, when the solder bumps of the wafer and the through-holes of the wires are turned over, the overflow of the adhesive layer may cause an increase in the package ratio. Referring to Fig. 1, a conventional semiconductor package structure mainly comprises a substrate 110, a wafer 120, a plurality of electrical connectors 144, and a colloid 150. The substrate 1 1 has a perforation 1 1 3 and 11 4 and a plurality of crucibles 1 15 formed under the substrate 1 . Referring to FIG. 2, a portion of the wire through hole i i 3 is around the substrate 1 10 , and a wire through hole 1 14 is located at the center of the 1 1 。. The wafer 120 has a plurality of pads 1 2 3 formed in the periphery and the central region of the wafer 1 20 to be exposed to the wire vias 1 1 3 and 1 1 4 after being bonded. Referring to Fig. 2, a layer of 130 is applied over the substrate 11 and does not cover the wires U 3 and 1 14 . The adhesive layer 130 is adhered to the upper surface of the wafer 110 to the upper surface of the substrate 110 (as shown in Fig. 1). The electrical components 140 can pass through the wire through holes 1 1 3 and 1 1 4 and electrically connect to the circuit board to have a close-to-100 connection line to the external system. The through-hole moving surface is connected to the 200921863 pads 1 2 3 to the substrate 1 1 〇. The encapsulant 150 is formed over the substrate 11 〇 and the wire vias 11 3 and 11 4 by a stamper to seal the wafer 120 and the electrical connection elements 140. A plurality of, for example, solder ball external terminals 160 are disposed on the external pads 1 15 of the substrate 110. During the die bonding process, the wafer 120 is thermocompression bonded to the substrate 1 1 ,, and the die layer 110 is bonded to the wafer 110 and the substrate 110. However, the viscous layer 1 300 will have a flow under high temperature and pressure.
性’該黏晶層1 3 0會往打線通孔1 1 3與11 4之方向流動 而產生溢膠1 3 1進而污染至該晶片1 20之該些銲墊 123(如第1圖之放大圖所示），甚至導致該些電性連接 元件1 4 0之一端沾不黏於該些銲墊1 2 3，也使得該半導 體封裝構造1 〇〇之可靠度降低。 【發明内容】 本發明之主要目的係在於提供一種避免黏晶溢膠之半導 體封裝構造，基板之上表面設有低成本之擋膠機構，具有良 好固著丨生以及與打線通孔微間隔之準確性，以控制基板 上的黏晶層的溢膠流動。 依據本發明之一種避免黏晶溢膠之半導體封裝構造係包 含一基板、一晶片、複數個電性連接元件以及一封膠體。該 土板係八彳上表面、__下表面以及至少—打線通孔，該基 二us有至少一導電金屬擋膠條與一防銲層該導電金屬 擋膠條係設於職板之該上表面且鄰近於該 銲層係形成於續其板之#卜# J ^ 、以基板之疏上表面並覆蓋該導電金屬擋膠 200921863 條。該晶片係設置於該基板之該上表面並局部覆蓋該打線通 孔與該導電金屬稽祕。該些電性連接元件係透過該打線通 孔電性連接該晶片與該基板。該封膠體係形成於該基板之上 表面及該打線通孔，以密封該晶片之至少一部位以及該些電 性連接元件。 本發月的目的及解決其技術問題還可採用以下技術措施 進一步實現。 在前述之半導體封裝構造t，該導電金屬擋膠條係可具 有至少一超出該晶片之延伸端。 在前述之半導體封裝構造中，該導電金屬擋膠條之該延 伸端係可連通至該基板之側邊。 在則述之半導體封裝構造中，該導電金屬擋膠條係可為 直線狀。 在前述之半導體封裝構造中，該導電金屬擋膠條係可為 u形。 ， 〔 在前述之半導體封裝構造中，該導電金屬擋膠條係可為 一印刷電路板之表面線路。 在前述之半導體封裝構造中，該導電金屬擋膠條係可為 接地或電源線。 — 在前述之半導體封裝構造中，該導電金屬擋膠條係可為 電鍍線。 η 在前述之半導體封裝構造中，該打線通孔係可為中央槽 孔。 、曰 在前述之半導體封裝構造中，該打線通孔係可為周邊小 7 200921863 窗孔。 在别述之半導體封裝構造中，該導電金屑擋膠條在該些 ^伸端之間係形成有_非封閉導膠口。 【實施方式】 依本發明之第—具體實施例，如第3圖所示，一種避免 黏曰曰溢膠之半導體封裝構造2GG係包含-基板21G、-晶片 220複數個電性連接元件240以及一封膠體250。該基板 ,210係具有_上表面2n、—下表面212以及至少—打線通 -與2 1 4 ’ β亥打線通孔2 1 3與2 1 4係由該上表面2 11貫 穿下表面2 1 2，以供該些電性連接元件24〇之通過。請 參閱第4圖所示，該打線通孔214係可為中央槽孔。該打線 通孔214《形狀係為狹長形槽孔彡長度可小於或大於該基 板2 1 〇之對應側邊之長度。在本實施例巾，該打線通孔2 1 3 係可為周邊小窗孔。 凊參閱第4及5圖所示，該基板21〇係包含有至少一導 ί電金屬擋膠條216與一防銲層217,該導電金屬擋膠條216 系：°亥基板2 1 〇之該上表面2 1 1且鄰近於該打線通孔2 ^ 3 與214，該防銲層217係形成於該基板21〇之該上表面2Η 並覆蓋該導電金屬擋膠條216。該防銲層217係作為一電性 絕緣之保護層而令該導電金屬擋膠條2 1 6輿外界隔離，避免 與該晶片220電性短路或是壓傷該晶片22〇之主動面221， 又可增進該導電金屬擋膠條2丨6之固著性。一般而言，該基 板2 1 0係作為晶片載體並具有單層或多層線路結構，例如單 層或多層印刷電路板。該導電金屬擋膠條216係可為一印刷 8 200921863 電路板之表面線路，也就是說該導電金屬擋膠條21 6係由該 基板210原有的表面線路形成，而不會增加元件與成本。在 本實施例中，該導電金屬擋膠條216係可為接地或電源線。 在不同實施例中，該導電金屬擋膠條2 1 6係可為電鍍線。請 參閱第4圖所示，該導電金屬檔膠條216係可為U形。 具體而言，該基板210係具有複數個形成於該下表面212 之外接墊2 1 5，例如圓形之接球墊，該些外接墊2 1 5係可呈 多排排列或是格狀陣列型態。請參閱第4圖所示，一黏晶層 230係形成於該基板2 1 0之該上表面2 11，以黏接該晶片 220，該黏晶層230之塗佈範圍係小於且鄰臨該導電金屬擋 膠條2 16所圍之範圍，故該導電金屬擋膠條2 1 6可以即時限 制該黏晶層230之擴散流動’避免該黏晶層230不當溢流。 請參閱第3及6圖所示’該晶片220係設置於該基板2 1 〇 之5亥上表面211 ’該晶片220係具有一主動面221以及一相 對之背面222 ’該主動面221係形成有複數個銲墊223。該 些銲墊223係排列於該主動面22 1之中央區域以及該主動面 22 1之兩側邊之部分區域，並作為該晶片220之對外電極， 其中該些位於該主動面221之中央區域之銲墊223係可為單 排或雙排之排列方式。利用上述之該黏晶層230黏接該晶片 220之該主動面221至該基板210，並使該些銲整223分別 對準在該打線通孔213與214内（如第3圖所示）。該晶片22〇 係設置於該基板2 1 0之該上表面2 11之方式將會局部覆蓋該 打線通孔213與214與該導電金屬擋膠條216。 請參閱第4及6圖所示’在設置該晶片22〇時，由於該 200921863 導電金屬擋膠條2 1 6係鄰近於該打線通孔2丨3與2 14，故該 導電金屬播膠條2 1 6係具有限制該黏晶層23〇往該打線通孔 2 1 3與2 1 4溢膠流動之功能，故該黏晶層23〇能適當地被控 制不會溢流而污染該晶片22〇之該些銲墊223(如第3圖所 不），以確保該半導體封裝構造2〇〇之品質。請再參閱第6 圖所示，較佳地，該導電金屬擋膠條216係可具有至少一超 出該晶片220之延伸端216A，當在該基板21〇上塗佈該黏 晶層230並將該晶片22〇熱壓合至該基板21〇上時，該導電 金屬擋膠條216係控制並導引該黏晶層23〇往該延伸端 2 1 6A流動，使該黏晶層23〇不會產生溢膠，即使塗佈過多 的該黏晶層230，亦能有效控制該黏晶層23〇在該基板21〇 之該導電金屬擋膠條216所圍之範圍内流動，因此在黏晶過 程中’該黏晶層23G不會產生溢膠至該打線通孔213。該導 電金屬擔膠條216之該延伸端216A係可連通至該基板21〇 之側邊。在本實施例中，言玄導電金屬㈣條216在該些延伸 端216A之間係形成有一非封閉導膠口 2i6B，提供了不會影 響半導體封裴品質之溢膠區域（如第6圖所示）。 請參閱第3圖所示，該些電性連接元件24〇係分別透過 該打線通孔2丨3與214電性連接該晶片22〇與該基板21〇。 其中A些電性連接兀件24G係可為打線形成之銲線，該些焊 線之一端係連接該晶片220之該些銲墊223，而另一端係連 ，至該基板210在該下表面212之接指(圖未繪出），達到該 晶片220與該基板2 i 〇之電性互連。 25〇係形成於該基板210 凊再參閱第3圖所示，該封膠體 200921863 之面211及該打線通孔213與214，以密封該晶片22〇 之至少一部位以及該些電性連接元件240,而令該晶片22〇 =該些電性連接元# 24Q與外界隔離，而不致受污染物侵 °具體而5，再如第3圖所示，該半導體封裝構造200係 可另包含有複數個外接端子26G，其係設置於該些外接些 215 ’以供作為輸入端及/或輸出端以使該半導體封裝構造 200與外界裝置形成電性連接關係，故該半導體封裝構造· 係可藉由該些外接端子2 6 0接合至一外部印刷電路板。該些 外接端子260係可包含金屬球、錫f、接觸墊或接觸針。 因此’利用上述被包覆導電金屬擋膠條2丨6之導引 與阻擋效果，該黏晶層23〇不會擴散至該打線通孔213 與214即疋3亥黏晶層230之溢膠不會污染至該晶片220 之該些銲墊223。使在後續的電性連接製程中，該些電 性連接元件240之一端可穩固結合至該些銲墊223。此 外’該導電金屬擋膠條2 1 6係由該基板21〇原有的表面線 路形成，故不會增加元件與成本。此外，本發明利用以被包 覆導電金屬擋膠條216除了具有黏晶膠擋膠效果之 外’並具有良好固著性以及與打線通孔微間隔之準確 性。 本發明之第二具體貫施例揭示另一種避免黏晶溢膠之半 導體封裝構造。請參閱第7圖所示，該半導體封裝構造3〇〇 係包含一基板3 1 0、一晶片320、複數個電性連接元件340 以及一封膠體350。該基板310係具有一上表面311、一下 表面3 1 2以及至少一打線通孔3 1 4，該下表面3 1 2係形成有 200921863 複數個外接塾3 1 5。在本實施例中，該打線通孔3丨4係可為 中央槽孔。請參閱第8及9圖所示，該基板31〇係包含有至 少一導電金屬擋膠條316與—防銲層317，該導電金屬擋膠 條316係設於該基板31〇之該上表面3ιι且鄰近於該打線通 孔314 ’該防銲$ 317係形成於該基板31〇之該上表面3ιι 並覆蓋4導電金屬擒膠條3 i 6。在本實施例中，該導電金屬 播膠條316係可為直線狀。請參閱第7及8圖所示，在該基 6 板310之該上表自311係塗佈有一黏晶層33〇，以黏貼該晶 片 3 20。 該晶片320係具有_主動面32卜一相對之背面322以及 複數個形成於該主動面321之銲墊323，該些銲墊323係可 為單排或雙排排列於該主動面321之中央區域。請參閱第7 及1 〇圖所示，利用該黏晶層33〇之黏接使該晶片設置 於忒基板3 1 0之該上表面3〖i並局部覆蓋該打線通孔3 14與 忒導電金屬擋膠條316，並使該些銲墊323位於該打線通孔 4 314内。請參閱第1〇圖所示，該導電金屬擋膠條3丨6係可具 有至少-超出該晶片320之延伸端316A，以發揮較佳地播 導膠之功效。因此，在黏晶過程甲，可藉由該導電金屬 擋膠條316以有效限制該黏晶層咖之流動散佈區域，使該 黏晶層330不致溢流至該晶片32〇之該些銲墊323上而產生 不當溢膠之問題。該導電金屬擋膠條316係可為一印刷電路 板之表面線路，與該防銲4 317皆為印刷電路板之基礎構 件具有低製造成纟、高固著性以及極度鄰近對應打 314之功效。 ’ 12 200921863 请參閱第7圖所示，該些電性連接元件34〇係透過該打 線L孔3 14電性連接該晶片3 2 〇之該些銲墊3 2 3與該基板 3 。該封膠體350係形成於該基板31〇之上表面311及該 打線通孔3 1 4，以畨封該晶片3 2 〇之至少一部位以及該些電 性連接元件34G。另外，複數個外接端子36()係可設置於該 基板310之該些外接墊315上。 、 所it 僅疋本發明的較佳實施例而已，並非對本發 Γ 明作任何形式上的限制，本發明技術方案範圍當依所附申請 、la圍為準任何熟悉本專業的技術人員可利用上述揭示 的技術内容作出些許更動或修飾為等同變化的等效實施 例，但凡是未脫離本發明技術方案的内容，依據本發明的技 術實質對以上實施例所作的任何簡單修改、等同變化與修 飾，均仍屬於本發明技術方案的範圍内。 【圖式簡單說明】 圖 種驾知半導體封裝構造橫切中央打線通孔以及周 ' 邊打線通孔之截面示意圖與局部放大之截面示意 圖。 第2圖.習知半導體封裝構造中一基板之上表面示意圖。 圖依據本發明之第一具體實施例，一種半導體封裝構 k橫切令央打線通孔以及周邊打線通孔之截面示 意圖與局部放大之截面示意圖。 第4圖’依據本發明之第—具體實施例，該半導體封裝構造 中一基板之上表面示意圖。 又據本發明之第一具體實施例，該半導體封裝構造 13 200921863 中該基板在第4圖5-5線之截面示意圖。 第6圖：依據本發明之第一具體實施例’該半導體封裝構造 之基板在黏晶後之上表面示意圖。 第7圖：依據本發明之第二具體實施例’一種半導體封裝構 造橫切打線通孔之截面示意圊 第8圖：依據本發明之第二具體實施例，該半導體封裝構造 中一基板之上表面示意圖。 第9圖：依據本發明之第二具體實施例，該半導體封裝構造 中該基板在第7圖8-8線之截面示意圖。 第1 0圖：依據本發明之第二具體實施例，該半導體封裝構 4之基板在黏晶後之上表面示意圖。 【主要元件符號說明】 100半導體封裝構造 11〇基板 111上表面 112下表面 113打線通孔 114打線通孔 120晶片 121主動面 11 5外接墊 122背面 123銲墊 1 3 0黏晶層 阳層 1 3 1溢膠 160外接端子 140電性連接元件15〇封膠體 200半導體封裝構造 2 1 〇基板 211上表面 2 1 2下表面 2 1 5外接塾 216A延伸端 217防銲層 213打線通孔 214打線通孔 216導電金屬擋膠條 216B非封閉導膠口 14 200921863 220 晶片 221 主 動 面 222 背面 223 銲墊 230 黏 晶 層 240 電性連接 元 件 250 封 膠 體 260 外接端子 300 半導體封裝構造 310 基板 311 上 表 面 312 下表面 314 打線通孔 315 外接墊 316 導電金屬 擋 膠. 條 3 1 6 A延伸端 317 防銲層 320 晶片 321 主 動 面 322 背面 323 銲塾 330 黏 晶 層 340 電性連接 元 件 350 封 膠 體 360 外接端子 15The viscous layer 130 will flow in the direction of the through-holes 1 1 3 and 11 4 to generate an overflow 133 and then contaminate the pads 123 of the wafer 1 20 (as shown in FIG. 1 As shown in the figure, even the one end of the electrical connecting elements 1 40 is not adhered to the pads 1 2 3, which also reduces the reliability of the semiconductor package structure 1 . SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package structure that avoids the adhesion of glue, and a low-cost rubber stopper mechanism is provided on the upper surface of the substrate, which has good fixation and micro-interval with the wire through hole. Accuracy to control the flow of glue in the die layer on the substrate. A semiconductor package structure for preventing adhesion of a glue according to the present invention comprises a substrate, a wafer, a plurality of electrical connection elements, and a gel. The soil plate is a top surface of the gossip, a lower surface, and at least a wire through hole, the base 2 has at least one conductive metal strip and a solder resist layer. The conductive metal strip is disposed on the plate. The upper surface and adjacent to the solder layer are formed on the slab of the slab, and the upper surface of the substrate is covered with the conductive metal stopper 200921863. The wafer is disposed on the upper surface of the substrate and partially covers the wire through hole and the conductive metal. The electrical connection elements are electrically connected to the substrate and the substrate through the wire through holes. The encapsulation system is formed on the upper surface of the substrate and the wire through hole to seal at least a portion of the wafer and the electrical connection elements. The purpose of this month and the resolution of its technical problems can be further realized by the following technical measures. In the foregoing semiconductor package construction t, the conductive metal barrier strip can have at least one extended end beyond the wafer. In the foregoing semiconductor package construction, the extended end of the conductive metal strip can be connected to the side of the substrate. In the semiconductor package structure described above, the conductive metal barrier strip may be linear. In the foregoing semiconductor package construction, the conductive metal barrier strip may be u-shaped. [In the foregoing semiconductor package construction, the conductive metal barrier strip can be a surface line of a printed circuit board. In the foregoing semiconductor package construction, the conductive metal barrier strip can be a ground or power line. - In the aforementioned semiconductor package construction, the conductive metal barrier strip can be an electroplated wire. η In the aforementioned semiconductor package construction, the wire via can be a central slot.曰 In the foregoing semiconductor package structure, the wire through hole may be a small window of the perimeter of 200921863. In the semiconductor package construction described above, the conductive gold chip strip is formed with a non-closed glue guide between the extension ends. [Embodiment] According to a third embodiment of the present invention, as shown in FIG. 3, a semiconductor package structure 2GG for preventing adhesion of glue is included - a substrate 21G, a plurality of electrical connection elements 240 of the wafer 220, and A gel 250. The substrate 210 has an upper surface 2n, a lower surface 212, and at least a wire-passing and a 2 1 4 '-thick wire through hole 2 1 3 and 2 1 4 through the lower surface 2 11 through the lower surface 2 1 2, for the passage of the electrical connecting elements 24. Referring to Figure 4, the wire through hole 214 can be a central slot. The wire through hole 214 is shaped such that the length of the slotted slot 可 can be less than or greater than the length of the corresponding side of the base plate 2 1 〇. In the towel of the embodiment, the wire through hole 2 1 3 may be a peripheral small window hole. Referring to Figures 4 and 5, the substrate 21 includes at least one conductive metal strip 216 and a solder resist layer 217. The conductive metal strip 216 is: The upper surface 2 1 1 is adjacent to the wire through holes 2 ^ 3 and 214 , and the solder resist layer 217 is formed on the upper surface 2 of the substrate 21 , and covers the conductive metal strip 216 . The solder resist layer 217 is used as a protective layer of electrical insulation to isolate the conductive metal strip 2 16 6 from the outside, avoiding electrical short circuit with the wafer 220 or crushing the active surface 221 of the wafer 22 . Moreover, the adhesion of the conductive metal strip 2丨6 can be improved. In general, the substrate 210 is used as a wafer carrier and has a single layer or multilayer wiring structure such as a single layer or multilayer printed circuit board. The conductive metal strip 216 can be a surface line of a printed circuit board of 200921863, that is, the conductive metal strip 21 6 is formed by the original surface line of the substrate 210 without increasing components and costs. . In this embodiment, the conductive metal strip 216 can be a ground or power line. In various embodiments, the conductive metal strip 2 16 can be an electroplated wire. Referring to Figure 4, the conductive metal strip 216 can be U-shaped. Specifically, the substrate 210 has a plurality of pads 2 15 formed on the lower surface 212, such as a circular ball pad. The external pads 2 15 may be arranged in multiple rows or in a grid array. Type. Referring to FIG. 4, a bonding layer 230 is formed on the upper surface 211 of the substrate 210 to bond the wafer 220. The coating range of the bonding layer 230 is smaller than and adjacent to the substrate. The conductive metal strip 2 16 can limit the diffusion flow of the bonding layer 230 in time to avoid improper overflow of the bonding layer 230. Referring to Figures 3 and 6, the wafer 220 is disposed on the upper surface 211 of the substrate 2 1 . The wafer 220 has an active surface 221 and an opposite back surface 222 . There are a plurality of pads 223. The pads 223 are arranged in a central region of the active surface 22 1 and a partial region of the two sides of the active surface 22 1 and serve as external electrodes of the wafer 220 , wherein the central regions of the active surface 221 are located The pads 223 can be arranged in a single row or in a double row. The active surface 221 of the wafer 220 is bonded to the substrate 210 by using the above-mentioned bonding layer 230, and the soldering 223 is respectively aligned in the wiring through holes 213 and 214 (as shown in FIG. 3). . The wafer 22 is disposed on the upper surface 2 11 of the substrate 210 to partially cover the wire vias 213 and 214 and the conductive metal strip 216. Please refer to Figures 4 and 6 'When the wafer 22 is set, since the 200921863 conductive metal strip 2 16 is adjacent to the wire through holes 2丨3 and 2, the conductive metal tape The 2 1 6 system has a function of restricting the flow of the adhesive layer 23 to the through-holes 2 1 3 and 2 1 4, so that the adhesive layer 23 can be appropriately controlled without overflowing to contaminate the wafer. 22 of these pads 223 (as shown in FIG. 3) to ensure the quality of the semiconductor package structure. Referring to FIG. 6 again, preferably, the conductive metal strip 216 can have at least one extended end 216A beyond the wafer 220, and the adhesive layer 230 is coated on the substrate 21〇 and When the wafer 22 is thermally bonded to the substrate 21, the conductive metal strip 216 controls and guides the layer 23 to flow toward the extended end 2 1 6A, so that the layer 23 is not If the adhesive layer 230 is coated too much, the adhesive layer 23 can be effectively controlled to flow in the range surrounded by the conductive metal strip 216 of the substrate 21, thus During the process, the adhesive layer 23G does not generate an overflow to the wire through hole 213. The extended end 216A of the conductive metal strip 216 is connectable to the side of the substrate 21A. In this embodiment, the conductive metal (four) strip 216 is formed with a non-closed glue guide 2i6B between the extended ends 216A, providing an overflow area that does not affect the quality of the semiconductor package (as shown in FIG. 6). Show). Referring to FIG. 3, the electrical connecting elements 24 are electrically connected to the substrate 22 and the substrate 21 through the wire through holes 2丨3 and 214, respectively. A plurality of electrical connecting members 24G may be wire bonding wires formed by wire bonding, one of the bonding wires is connected to the pads 223 of the wafer 220, and the other end is connected to the substrate 210 at the lower surface. The finger of 212 (not shown) reaches the electrical interconnection of the wafer 220 and the substrate 2 i. 25〇 is formed on the substrate 210. Referring to FIG. 3, the surface 211 of the sealant 200921863 and the wire through holes 213 and 214 are used to seal at least a portion of the wafer 22 and the electrical connecting elements. 240, so that the wafer 22 〇 = the electrical connection element # 24Q is isolated from the outside, without being contaminated by the specific 5, and as shown in Figure 3, the semiconductor package structure 200 may additionally include A plurality of external terminals 26G are disposed on the external 215's for inputting and/or outputting to electrically connect the semiconductor package structure 200 to an external device. Therefore, the semiconductor package structure can be The external terminals 220 are bonded to an external printed circuit board. The external terminals 260 may comprise metal balls, tin f, contact pads or contact pins. Therefore, by using the guiding and blocking effect of the coated conductive metal strip 2丨6, the bonding layer 23〇 does not diffuse to the bonding vias 213 and 214, that is, the 亥3 黏 黏 layer 230 The pads 223 of the wafer 220 are not contaminated. One of the electrical connection members 240 can be firmly coupled to the pads 223 in a subsequent electrical connection process. In addition, the conductive metal strip 2 16 is formed by the original surface line of the substrate 21, so that the components and cost are not increased. In addition, the present invention utilizes the ability to be coated with a conductive metal strip 216 in addition to having a viscous gel blocking effect and having good adhesion and micro-interval with the wire through-hole. A second embodiment of the present invention discloses another semiconductor package construction that avoids viscous spills. Referring to FIG. 7, the semiconductor package structure 3 includes a substrate 310, a wafer 320, a plurality of electrical connection elements 340, and a gel 350. The substrate 310 has an upper surface 311, a lower surface 3 1 2 and at least one wire through hole 3 1 4 , and the lower surface 3 1 2 is formed with a plurality of external 塾 3 1 5 of 200921863. In this embodiment, the wire through hole 3丨4 may be a central slot. Referring to FIGS. 8 and 9, the substrate 31 includes at least one conductive metal strip 316 and a solder resist layer 317 disposed on the upper surface of the substrate 31. 3 ι and adjacent to the wire through hole 314 ′′ the solder resist $ 317 is formed on the upper surface 3 ι of the substrate 31 并 and covers the 4 conductive metal enamel strip 3 i 6 . In this embodiment, the conductive metal strip 316 may be linear. Referring to Figures 7 and 8, a layer of adhesive layer 33 is applied from the 311 series on the upper surface of the base plate 310 to adhere the wafer 3 20. The wafer 320 has a _ active surface 32, an opposite back surface 322, and a plurality of solder pads 323 formed on the active surface 321 . The solder pads 323 may be arranged in a single row or in a double row at the center of the active surface 321 . region. Referring to FIG. 7 and FIG. 1 , the wafer is disposed on the upper surface 3 of the germanium substrate 3 1 0 by using the bonding layer 33 and is partially covered with the wire through hole 3 14 and conductive. The metal strip 316 is disposed, and the pads 323 are located in the wire through holes 4 314. Referring to Figure 1, the conductive metal strip 3丨6 can have at least - beyond the extended end 316A of the wafer 320 to provide better performance of the broadcast adhesive. Therefore, in the adhesion process A, the conductive metal strip 316 can be used to effectively limit the flow dispersion area of the adhesion layer, so that the adhesion layer 330 does not overflow to the pads of the wafer 32. 323 on the issue of improper spillage. The conductive metal strip 316 can be a surface circuit of a printed circuit board, and the solder resist 4 317 is a basic component of the printed circuit board, which has low manufacturing efficiency, high fixation, and extreme proximity. . As shown in FIG. 7, the electrical connecting elements 34 are electrically connected to the pads 3 2 3 of the wafer 3 through the wires L 14 and the substrate 3 . The encapsulant 350 is formed on the upper surface 311 of the substrate 31 and the wire through hole 3 1 4 to seal at least a portion of the wafer 3 2 and the electrical connection elements 34G. In addition, a plurality of external terminals 36() may be disposed on the external pads 315 of the substrate 310. The present invention is not limited to the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The technical scope of the present invention is subject to the application of the present application, and is applicable to those skilled in the art. The above-disclosed technical content makes a few modifications or modifications to equivalent embodiments, but any simple modifications, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention without departing from the technical scope of the present invention. All still fall within the scope of the technical solution of the present invention. [Simple description of the drawing] Fig. Schematic diagram showing a cross-sectional view of a semiconductor package structure transverse to a central wire through hole and a circumferential 'side wire through hole, and a partially enlarged cross-sectional schematic view. Fig. 2 is a schematic view showing the upper surface of a substrate in a conventional semiconductor package structure. BRIEF DESCRIPTION OF THE DRAWINGS In accordance with a first embodiment of the present invention, a cross-sectional view of a semiconductor package structure and a cross-sectional view of a peripheral wire through hole and a peripheral wire through hole are schematically schematic and partially enlarged. Fig. 4 is a schematic view showing the upper surface of a substrate in the semiconductor package structure according to the first embodiment of the present invention. According to a first embodiment of the present invention, the semiconductor package structure 13 200921863 is a schematic cross-sectional view of the substrate in FIG. 4-5-5. Figure 6 is a schematic view showing the upper surface of the substrate of the semiconductor package structure after the die bonding according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a cross section of a semiconductor package structure according to a second embodiment of the present invention. FIG. 8 is a view showing a second embodiment of the present invention. Surface schematic. Figure 9 is a cross-sectional view of the substrate in the semiconductor package structure taken along line 8-8 of Figure 7 in accordance with a second embodiment of the present invention. FIG. 10 is a schematic view showing the upper surface of the substrate of the semiconductor package 4 after the die bonding according to the second embodiment of the present invention. [Main component symbol description] 100 semiconductor package structure 11 〇 substrate 111 upper surface 112 lower surface 113 wire through hole 114 wire through hole 120 wafer 121 active surface 11 5 external pad 122 back 123 pad 1 3 0 viscous layer positive layer 1 3 1 overflow glue 160 external terminal 140 electrical connection component 15 〇 sealant 200 semiconductor package structure 2 1 〇 substrate 211 upper surface 2 1 2 lower surface 2 1 5 external 塾 216A extended end 217 solder mask 213 wire through hole 214 wire Through hole 216 conductive metal stopper strip 216B non-closed rubber guide port 14 200921863 220 wafer 221 active surface 222 back surface 223 solder pad 230 adhesive layer 240 electrical connection element 250 sealant 260 external terminal 300 semiconductor package structure 310 substrate 311 upper surface 312 Lower surface 314 Wire through hole 315 External pad 316 Conductive metal stopper. Strip 3 1 6 A Extension end 317 Solder mask 320 Chip 321 Active surface 322 Back 323 Soldering 330 Bonding layer 340 Electrical connection component 350 Sealing body 360 External terminal 15