TW200921679A - Non-volatile memory and method for improved sensing having bit-line lockout control - Google Patents

Abstract

In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

Description

200921679 IX. Description of the Invention: [Technical Field] The present invention relates to non-volatile semiconductor memory (for example, electrically erasable programmable read only memory (EEPROM) and flash EEPROM), and Specifically, s is a sensing operation and memory in which control is applied to the locking of the 7L line associated with a relatively high conduction current memory cell. [Prior Art]

Close to, solid-state memory with charge non-volatile storage capacity. The solid-state memory in the form of EEPR〇M and flash EEpR〇M packaged into a shape factor card has become a variety of mobile and handheld devices. The preferred storage in appliances and consumer electronics. Unlike RAM (random access memory), which is also a solid-state memory, flash memory is non-volatile and retains its stored data even after the power is turned off. Despite the higher cost, flash memory is increasingly being used in high-volume storage applications. Conventional large-capacity storage based on rotating magnetic media (4)

For example, hard drives and floppy disks are not suitable for mobile and handheld environments. This is due to the fact that disk drives tend to be bulky and subject to mechanical failures with high latency and high power requirements. These undesired attributes make disk-based storage unsuitable for most mobile and portable applications. The other flash memory (whether in the form of a detachable or a removable card) is suitable for mobile and handheld environments due to its small size, low power consumption, south speed and reliability. feature. EEPR〇M and electrically programmable read-only memory (epr〇m) and new (4)^ or “stylized” into its memory unit = 131985.doc 200921679 Volatile memory. Both are 扃, θ ^ ^ (the unconnected transistor structure utilizes a floating ^ channel [ a pole, the floating trousers are located - the semiconductor substrate Yin: upper = between the source and the drain region. Then in the The floating room, = two (four) gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge left on the (4) of the closed electrode. That is, the corresponding ty applied to the control electrode before the floating body is turned on" The conduction between the dipole regions of the electro-crystals is limited to permit the source and the (4) closed-cell _charge (four), and the heart can be programmed to - the threshold electric window (also known as "" In the conduction window") - the threshold voltage level. The threshold voltage window is delimited by the minimum and maximum threshold levels of the device, and the minimum and maximum threshold levels of the device correspond to the range of charge that can be programmed onto the floating gate. The threshold window generally depends on the characteristics, operating conditions and history of the memory device. In principle, each of the different analyzable threshold voltages in the window (4) can be used to identify the material element. In the case where the threshold voltage is divided into two different districts, the temple will be able to store data for each bit. Similarly, when the Linyang electric window is divided into more than two different areas, each memory unit 2 can store more than one bit of data for the month b. At least one current breakpoint level is established in a typical two-state EEPROM cell to divide the conductive window into two regions. When a predetermined, fixed voltage read-cell is applied, its source " and the pole current are resolved into a memory state by comparison with the breakpoint level (or reference current IREF). If the current being read is higher than the current at the breakpoint level, then the cell is determined to be in the state of 1985. doc 200921679 (for example, a "0" state). On the other hand, if the current is less than the current at the breakpoint level, then the cell is determined to be in another logic state (e.g., state 1). Therefore, the two state units store a digital bit 7L. A reference current source that can be externally programmed is often provided as a source of a memory system to produce a ±-breakpoint level current. In order to increase the memory capacity, as the state of semiconductor technology advances, flash EEPROM devices are being fabricated at increasingly higher densities. Another way to increase the storage of the valley 1 is to store more than two states per memory unit. For a multi-state or multi-bit quasi-EEPROM memory cell, the conduction window is divided into more than two regions by more than one breakpoint, so that each cell can store data for one bit at a time. Therefore, the information that can be stored by an established eeprom array increases with the number of states that each unit can store. An EEPROM or flash EEPROM having a multi-state or multi-bit memory cell has been described in U.S. Patent No. 5,172,338. Although the transistor of the memory cell is usually programmed into one by one of two mechanisms, it has been programmed to state. In "hot electron injection", a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time, a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric to the f-movement pole. In the "follow-through", the voltage is applied to the control closed-cell relative to the substrate in such a manner that electrons are pulled from the substrate to the intervening floating gate. ^ The memory device can be erased by a number of mechanisms. 'You can use a light bulb from the floating gate (four) to remove a large amount of rubbing. For EEPR0M, a high voltage can be applied to the substrate relative to the control electrode 131985.doc 200921679 to cause electrons in the floating gate to tunnel through a thin oxide to reach the substrate channel region (ie, Fule-Nuo Dehan Tunneling) Incoming Call Erase - Memory Unit. Usually, 'eepr〇m can be erased one by one: For (iv) EEPRQM, all blocks or one or more blocks can be erased immediately, one block can be 512 or more memory bits. The tuple is composed.

Memory devices typically include one or more memory chips that can be mounted on a card. Each memory chip includes an array of memory cells supported by peripheral circuitry (e.g., decoders and erase, write, and read circuitry). More complex memory devices operate with an external memory controller that controls the implementation of intelligent and higher level memory operations and interfaces. Today, many commercially successful non-volatile solid state memory devices are being used. These memory devices can be flash EEPR 〇 M or other types of non-volatile memory cells can be used. Examples of flash memory and methods of making the same are described in U.S. Patent Nos. 5, 5, 095, 344, 5, 315, 541, 5, 343, 063 and 5, 661, 053, 5, 313, 421 and 6, 222, 762. A flash memory device having a NAND string structure is also described in the 'U.S. Patent Nos. 5,570, 3, 5, 903, 495, 6, 046, 935, which are also non-volatile from a memory cell having a dielectric layer for storing charge. Memory device. A dielectric layer is used in place of the previously described conductive floating gate elements. By Eitan et al. "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," (IEEE Electron

A memory device that can utilize a dielectric storage element is described in Device Letters, Vol. 21, No. 11, November 2000, 543- 131985.doc 200921679, page 545). A dielectric layer extends across the channel between the source diffusion region and the drain diffusion region. The charge of one data bit is concentrated in the dielectric layer adjacent to the drain, and the charge of the other negative bit is concentrated in the dielectric layer adjacent to the source. For example, a non-volatile memory cell having a trapping dielectric layer sandwiched between two dioxide layers is disclosed in U.S. Patent Nos. 5,768,192 and 6, the disclosure of which is incorporated herein by reference. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric layer. To improve read and program efficiency &, read or program multiple charge storage elements or memory transistors in an array in parallel. Therefore, together read or stylize - store component logic, oh,. In existing memory architectures, a column typically contains a number of interleaved pages or it can constitute a page. All memory elements of a page will be read or programmed together. Styling a memory unit page typically involves a series of alternating stylization/verification cycles. Each stylized loop causes the memory unit page (4) to have one or more programmed voltage pulses. The stylized loop is followed by a validation loop in which each-single S is read back to determine if it has properly programmed the unit. The stylization/verification loop continues with the increased stylized voltage level until all units in the page have been programmatically verified. Both the read and verify operations are performed by performing a plurality of sensing cycles in which the conduction of each memory cell relative to the page, the value of the knife 1 is equalized, or the threshold is applied. In general, if the memory is divided into = cancer, then at least... the sensory ring will be present to resolve the state of the body. In many embodiments, each of the brothers can also be involved in 131985.doc 200921679 two or more passes. For example, the interaction between adjacent charge storage elements becomes significant when the memory cells are tightly packaged and some sensing techniques involve sensing memory cells on adjacent word lines to compensate for such interactions. error. Therefore, since more memory cells are being highly integrated into a single chip and more and more states are being packaged into each memory cell to increase capacity, the read and verify performance is due to the most demanding The number is greatly affected.

Therefore, high capacity and high performance non-volatile memory are generally required. In particular, it is desirable to have a south volume non-volatile memory having improved sensing performance in which the above disadvantages are minimized. SUMMARY OF THE INVENTION According to one aspect of the present invention, a case where a bit line is locked in a parallel sense (a bit line is grounded: a memory cell exceeding a predetermined current level is In this way, it is allowed to achieve the current consumption - the established budget::: the additional sensing sub-clock for identifying and turning off the high current unit, and with a selectable number of sensing control (four) pole voltage sensing will result in the corresponding Turning on the unit's position and turning off the line and using other control gates will not cause any = (4) closed operation. By applying this technology, the performance of the sensing operation is in place: the number of cycles Improvements in reducing noise due to bit line lines when bit lines are turned off. In this context, =: bits - electricity present between adjacent global bit lines in a preferred embodiment The bit line locking is implemented by a pull-down circuit capable of pulling the bit line 131985.doc •10-200921679 to the ground. The pull-down circuit includes two pass gates connected in series between the line 70 and ground. From the gate – the gate, one of which passes The pole is controlled by a pull enable or disable control signal and the other pass gate is controlled by whether the cell in question has a current above or below a reference current. When the pull down circuit is deactivated, As a result of the unsatisfactory sensing, the bit line will not be grounded. When the pull-down circuit is enabled, the bit line will be pulled to ground when the sensed result is from a high current memory unit. An embodiment of a multi-state memory that involves performing multiple sensing passes on a memory cell page relative to each of a plurality of states. 'Performing only by predetermined sensing by locking and identifying higher than a predetermined current The step of registering the bit line associated with the body unit. In this way, the bit line locking benefit of reducing the total current and source bias error is harvested, while reducing it due to more sub-cycles Longer sensing times and negative effects of longer latency for decay of generated noise. To ensure uniform distribution of high current conditions in a page, the page is preferably coded to make the data relatively consistent The cloth is stored in all possible memory states. In a preferred embodiment, the encoded data appears to be pseudo-random. According to another aspect of the invention, the bit line lock is reduced by no more than a predetermined amount. The maximum current flowing in the memory cell page of the maximum current is equivalent. In this way, the bit line lock is minimized but the total current (which is dependent on the data) will exceed a predetermined current level reference. In an embodiment of sensing a multi-state memory (which involves implementing 131985.doc 200921679 multiple sensing passes with respect to each of a plurality of states), only in the memory cell The step in which the total current flowing in the page will exceed the pre-maximum current by a predetermined sense by performing a lock on the bit line associated with the memory cell identified as being above a predetermined current level. In one embodiment, a current monitor is provided to monitor the total current flowing in the memory cell page. In another embodiment, the number of bit lines corresponding to the highly conductive cells is accumulated and this information is used to estimate the total current flowing in the memory cell page. Additional features and advantages will be understood from the following description of the preferred embodiments of the invention. [Embodiment] Memory System Figs. 1 through 9 illustrate the exemplification of an exemplary memory system in which various aspects of the present invention can be implemented. Figures 10 through 21 illustrate various aspects and embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of functional blocks in which a non-volatile memory wafer of the present invention may be implemented. The memory chip 1A includes a two-dimensional memory cell array 200, a control circuit 210, and peripheral circuits such as a decoder, a read/write circuit, and a multiplexer. The 5 memory array 200 can be via a column decoder via a word line (divided into 23 0A, 230B) and via a bit line via a row decoder 26 (divided into 26 A, 260B) (see also Figures 4 and 5). Addressing. The read/write circuit 27 (divided into 270A, 270B) allows a memory cell page to be read or programmed in parallel. A data I/O bus 231 is coupled to the read/write circuit 27A. 131985.doc -12· 200921679 #在-: In the preferred embodiment, the page is composed of one column sharing the same word line adjacent to each other: a single 7L. In another embodiment, in the case where the 'in-array memory cell' is smashed into a page, the block multiplexer 250 is provided (divided into 250A and discussed) to multiplex the read/write circuit 27 to individual page. For example, the singular and even row memory cells are respectively formed into the read/write circuits.

1 illustrates a preferred arrangement in which a plurality of peripheral electrical material rows are accessed on opposite sides of the memory array 200 in a symmetrical manner to halve the density of the access lines and circuits of each side. . Because &, the column decoder is divided into column decoders 2 and 2, and the row decoder is divided into row decoders 260A and thin. In the actual case where the column memory cell is divided into multiple pages'! The rural worker 250 is divided into page multiplexers 25, 8 and 2 times. Similarly, the read/write circuit 270 is divided into a read/write circuit 270A connected from the bottom to the bit line and a read/write circuit 270B connected from the top to the bit line. In this manner, the density of the read/write modules, and thus the density of the sense module 380, is substantially halved. Control circuit 110 is an on-wafer controller that cooperates with read/write circuit 270 to perform memory operations on memory array 200. Control circuit 110 typically includes a state machine 112 and other circuitry (e.g., an on-wafer address decoder and a power control module (not explicitly shown)). The state machine ιΐ2 provides wafer level control for memory operations. The control circuit communicates with a host via an external memory controller. Memory array 200 is typically organized as a two-dimensional array of memory cells arranged in columns and rows and addressable by word lines and bit lines. The array can be formed according to a 131985.doc 13 200921679 nor type or a NANr^M type architecture. Figure 2 is an illustration of a non-volatile memory unit. The memory cell 10 can be constructed from a field effect transistor having a charge storage unit 2 (e.g., a floating gate or a dielectric layer). The memory unit 1A also includes a source 14, a pole 16 and a control gate 3〇. Many commercially available non-volatile solid state memory devices are being used today. The memory devices can employ different types of memory cells, each having one or more charge storage elements. Typical non-volatile memory cells include eepr〇m and flash EEPR0M. An example of an EEpR〇M unit and a method of manufacturing the same are given in U.S. Patent No. 5,595,924. Examples of flash EEPROM cells, their use in memory systems, and methods of making the same are given in U.S. Patent Nos. 5, 〇 7,32, 5,95,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421, and 6,222,762. . In particular, examples of memory devices having a unit structure are described in U.S. Patent Nos. 5,57,315, 5,903,495 and 6,046,935. Similarly, Eitan et al. have been "NR〇M: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell, " (IEEE Electron Device Letters, Vol. 21, No. U, (9) (Eight) Year ^ Month, No. 543-S45 An example of a memory device utilizing a dielectric storage element is described in U.S. Patent No. 5,768,192 and U.S. Patent No. 6,725. In practice, the memory state of the cell is typically read by sensing the conduction current across a single 7L source and drain electrode when a reference voltage is applied to the control gate. Therefore, for each of the predetermined charges on the floating gate of a cell, a corresponding voltage can be detected relative to a fixed reference control. The voltage is 131985.doc •14· 200921679 = current. Similarly, the range of charge that can be programmed to the floating idler corresponds to the S-limit voltage window or a corresponding conduction current window. Another-selection, no--detects the conducted electricity in the divided current window, but can set the threshold current for a given memory state at the control closed-end: and detect whether the conduction current is lower or higher A limit current. In one embodiment, the conduction current is detected relative to the - threshold current by checking the rate at which the conduction current is discharged through the capacitance of the bit line. Ο u Figure Addition The four different outputs Q1-Q4 that can be selectively stored at any time for the floating gate illustrate the relationship between source _ immersion current 1 〇 and control idle voltage vCG. These four solid lDfiVeG curves represent four possible charge levels that can be programmed into one of the memory cells, which correspond to the four possible memory states, respectively. As one of the H-unit groups, the electricity house window can be ... to 3.5 V. The seven possible memory states of an erased state and seven stylized states can be respectively demarcated by dividing the threshold window into eight regions at intervals of about 〇·4 V. , 2", "3,,,,,4","5",%", and 7,7, for example, if the use of one is 〇.〇5uA reference current bribe, as shown The unit stylized in Q1 is considered to be in the memory state "1" because its curve intersects IREF in the threshold window of the boundary between VCG=0.43 ¥ and 〇88 v. Similarly, Q4 is in a memory state "5" As can be seen from the above description, the more states a memory cell is stored, the finer the limit value (4) is. For example, the memory device It can be: a memory unit with a threshold window in the range -1·5 V to 5 V. This provides a maximum width of 6.5 V. If the memory unit will store 16 shapes, 13I985.doc 15 In the 200921679 state, each state can occupy from 35〇...to mV in the threshold window. This will require higher stylization and read operation accuracy to achieve the required resolution. An example of an array of NOR memory cells is illustrated. In the memory array 200, 'per-column memory cells are connected by their sources} 4 and no poles! 6 is connected in a daisy-chain manner. This design is called a The virtual grounding design. The single 7L 10 in one column has its control gate 3〇 connected to a word line (for example, word line 42). The cell in one row connects its source and drain to the selected positioning element (eg , bit lines 34 and 3 6). Figure 5A schematically illustrates a string of memory organized into a NAND string The unit NAND string 50 is composed of a series of memory transistors M1, M2, ... Μη (for example, n = 4, 8, 16 or higher) which are daisy-chained by their sources and spurs. A pair of selective transistors SI S2 controls the connection of the memory transistor chain to the outside via the source terminal 54 and the NMOS terminal 56 of the NAND string. In a memory array, the source terminal is coupled when the source selective transistor S1 is turned on. To a source line (see Figure 5B). Similarly, when the drain select transistor S2 is turned on, the 汲 terminal of the NAND string is coupled to one of the bit lines of the memory array. Each of the transistors 10 functions as a memory cell. It has a charge storage element 20 for storing a predetermined amount of charge to represent a desired memory state. Each memory transistor - control gate 3 is allowed to be white The read and write operations are controlled. As will be seen in Figure 5B, the control gates 3 of the corresponding memory transistors of a column of NAND strings are all connected to the same word line. Similarly 'select transistor S1, One of each of S2 controls gate 32 via its source terminal 54 and its drain Terminal % Control 131985.doc 16 200921679 The access to the NAND string is made. Similarly, the control gates 32 of the corresponding select transistors of a column of NAND strings are all connected to the same select line. Or verifying that the addressed δ 忆 体 电 电 , , , , , , , , , , , , , , , , 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证 验证The remaining unaddressed memory transistors in the NAND string 50. In this manner, a conductive path is effectively created from the source of the individual memory transistors to the source terminals 54 of the nand string, and likewise from individual memories The drain of the bulk transistor creates a conductive path to the germanium terminal 56 of the cell. A memory device having such a NAND string structure is described in U.S. Patent Nos. 5,570,315, 5,903,495 and 6,046,935. Figure 5B illustrates an example of a NAND memory cell array 2 (9) constructed of, for example, the nand string 5 图 shown in Figure 5a. Along the per-banking string, a bit line (e.g., bit line 36) is coupled to the 汲 terminal 56 of each NAND string. /0 Each row of NAND strings, a source line (e.g., source line μ) is coupled to source terminal 54 of each NAND string. Similarly, the control gates of the column memory cells along a row of strings are connected to a word line (e.g., word line 42). The control idlers of the selected transistor along one of the row-row NAND strings are all connected to a select line (e.g., select line 44). An entire column of memory cells in a row of nand strings can be addressed by the word lines of the row of NAND strings and the appropriate voltage on the select lines. While a memory transistor in the -nand string is being read, the remaining memory transistors in the string are strongly "on" via their associated word lines such that the current flowing through the string is substantially dependent on the stored The level of charge in the cell being read. 131985.doc , 17- 200921679 Stylization and Verification Figure 6 illustrates a typical technique for stylizing a single-page of a hidden body into a target memory state by means of a series of alternating stylization/verification cycles. A stylized voltage vPGM is applied to the control gate of the memory cell via a pre-coupled σ. The VPGM is a series of stylized voltage pulses in the form of a staircase waveform starting from an initial voltage level. The stylized early is subject to this series of stylized voltage pulses, while each attempting to add a charge to the floating m. Between the stylized pulses, the cell is read back or verified to determine its source-drain current relative to a breakpoint level. The readback process can involve one or more sensing operations. Stylized stop when the unit has been verified to have reached the goal. The stylized pulse sequence used can have an increasing period or amplitude to counteract the accumulated electrons that are programmed into the charge storage unit of the memory unit. In general, the stylized circuit applies a series of stylized pulses to a selected word line. In this way, the memory cells can be programmed together to control one of the memory cells. As long as the U (four) page - memory unit is programmed to its target state, its program is disabled. Other singles 70 continue to undergo normalization. JL has verified that all units of the page have been programmed. An example of memory state partitioning is illustrated in Figure 7(1)—with the _erased state as the grounded state Gr and progressively more stylized memory states, A",,,B" and "C" The threshold voltage distribution of the 4 state memory array. During the reading, four states are delimited by three boundary breakpoints 0. θ (2) illustrates a preferred, 2-bit speaker code to represent the memory states of the four At which are shown in Figure 13(1), 131985.doc -18·200921679. Use a pair of "upper, partial code bits (ie, "1 1 " " π 1 " 11 , 01 , , '〇〇" and "10") to represent the memory ( That is, "Γ ”

Each of Gf, "Α", "Β" and "c") - US Patent No. 6,657 891 % 士#, 91 揭示 reveals "LM" code, and it avoids the need for large charge changes The 4&^ operation facilitates reducing the field effect of the adjacent floating gates. It will be shortened ztzhou. The 忒 code is counted as separable and can be read separately: position 兀 (below. |5 & upper bit). When stylized part of the element,

The threshold level of the unit is maintained in the "erased" area or moved to one of the threshold windows "lower and middle areas. In the stylized upper part, one of the two areas The threshold level is further increased to a slightly higher level in one of the "lower middle" regions of the threshold window. Figure 8 (1) illustrates the threshold voltage distribution of the exemplary 8-state memory array. The possible threshold voltage spans a threshold divided into eight zones to demarcate eight possible memory states "Ο〆,, "Α" ' "Β" ' π ' "D" ' "E" 'nF" and "G"."&" is a grounded state, which is an erased state in a tightly distributed state, and "eight"-"... is seven progressively Stylized state. During reading, the eight states are delimited by seven boundary breakpoints DA-DG. Figure 8 (2) illustrates - preferred, 3-bit encoding to represent the eight possible memory states shown in Figure 8 (丨). Use a three-tuple "upper, middle, lower" (ie, "m","011", "_,,,, "", "_··, 'real' and &quot ;m") to represent each of the memory states of the person. w hai code is designed to be separate and read 3 code bits "lower,", "middle" and "upper" bits . Therefore, in the first round, if the 131.3.doc •19- 200921679 part element is “1”, then T plus π h ρ page stylizes to maintain a unit, erased " or ^, accounted for 'or The lower part is "quote", which is stylized to the middle and lower part. The ",", "Gr" or "grounded" state is studded to a narrow threshold. M, Ke &; 乍 _ , , ,, ice-erased state with a close-distributed system erase state. "The lower middle Λ 呈 ^ is the ancient σ 卩 state can have a wide threshold voltage distribution across the state of the memory. During stylization, it can be verified against a coarse breakpoint threshold level (for example, db), the lower middle " state. When the intermediate bit is privately categorized, the threshold of one unit begins with one of the two regions resulting from the lower page programming and moves to one of the four possible regions. When stylizing the upper part, a unit's threshold level starts with the four possible areas of the free intermediate page stylization and moves to eight possible memory states. SENSE CIRCUIT AND TECHNIQUE Figure 9 illustrates the read/write circuits 270 and 27B of a memory cell array having a row of p sensing modules as shown in the Figure. The entire row of p sensing modules 480 operating in parallel allows parallel reading or programming of blocks (pages) of P cells 10 along a row. In essence, the sensing module 丨 will sense one of the currents I in the unit ,, the sensing module 2 will sense one of the currents 12 in the sensing unit 2, ..., the sensing module P will sense the unit p One of the currents Ip and so on. The total cell current flowing from the source line 34 of the page to a gathering node CLSRC and from there to ground will be the sum of all of the currents in the p cells. In a driving S-memory architecture, a column of memory cells having a common word line forms two or more pages' in which the δ-resonant cells in a page are read and programmed in parallel. In the case of a page with two pages, one page is accessed by the even bit 131985.doc -20-200921679 line, and the other pages are accessed by the odd bit line. A sense circuit page is coupled to an even bit line or an odd bit line at any one time. In the currently produced 56 nm technology based wafer p > 64000 and in the 43 nm 32 Gbit x 4 wafer p > 150000. In the preferred embodiment, the block is a series of aligned memory cells. This is a so-called "all bit line" architecture in which the page consists of a column of adjacent memory cells respectively coupled to adjacent bit lines. In another embodiment, the block is a subset of the cells in the column. For example, the unit sub-group can be half of the entire column or a quarter of the entire column. The unit sub-group may be a series of adjacent units or one string every other unit, or one string each of a predetermined number of units. Each sensing module is coupled to a memory cell via a bit line and includes a sense amplifier for sensing the conduction current of a memory cell. In general, if the read/write circuits are distributed on opposite sides of the memory array, the rows of p sense modules will be distributed between the two sets of read/write circuits 270A and 270B. A preferred sensing module is disclosed in U.S. Patent Publication No. 2005-0169082-A1, the entire disclosure of which is incorporated herein by reference. The entire disclosure of U.S. Patent Publication No. 2005-01 69082-A1 is incorporated herein by reference in its entirety herein in its entirety in in in in in in in in in in in The sensing module 480 senses a conduction current of a memory cell in a NAND chain 50 via a consuming bit line 36. It has a sense of being selectively coupled to a bit line Measure node 48 1 , a sense 131985.doc -21 - 200921679 amp 600 and a read bus 499. Initially, an isolation transistor 482 "connects" the bit line to the sense when enabled by a signal 8^ Node 481. The sense amplifier 600 senses the sense node 481. The sense amplifier includes a precharge/clamp circuit 64A, a cell current discriminator 65A, and a latch 660. Sensing module 480 enables sensing of the conduction current of selected memory cells in the NAND chain. In a preferred embodiment, a pull-down circuit 55 is provided to selectively pull the bit line 36 to ground. The pull-down circuit 55 is activated when both the signal INv and the other signal GRS are high. The b-number GRS controlled by the state machine (see Fig. 供应) is supplied as part of the control and timing signals from the page controller 498. As will be described in more detail later, the 'signal GRS can be enabled by the state machine as a control b number to enable (GRS = high) or disable (GRS = low) pull down circuit 550 to enable or disable the locking of the high current bit line, respectively. When the sense indicates a high current state, 'INV will be high, and if the pull-down circuit is enabled, it will pull down the bit line. Prior to sensing, the voltage to the gate of the selected memory cell must be set via the appropriate word line and bit line in one or more pre-charge operations. For example, as shown in FIG. 10, a memory cell page along a word line WL1 intersecting the NAND chain 50 can be selected for sensing. The precharge operation begins with the unselected word lines WL0, WL2_WL3 1 being positively charged to a voltage Vread and being selected for a predetermined memory state to be charged to a predetermined threshold voltage VT(i). Next, the bit line precharge circuit 640 causes the bit line 36 to reach a predetermined non-polarity suitable for sensing. This will cause a source-drain conduction current to flow in the selected memory of the NAND chain 50, the source-drain conduction current being passed through a coupled bit line 36. The channel of the NAND chain is detected. The conduction current is programmed as a function of the charge in the selected memory cell and the applied VT(i) when there is a nominal voltage difference between the source and drain of the memory cell. Figure 11A illustrates the precharge/clamp circuit shown in Figure 1A in more detail. The circuit has a voltage clamp 620' component and a precharge circuit 640, component. The voltage clamp 620' is constructed from an analog signal 612 [χ controlled by a transistor 612 at its gate. BLX ensures sufficient voltage on node SEN2 481 (see Figure 1A) to clamp the bit line voltage to 6 丨〇 to operate properly. When the VT(i) voltage is stable, the conduction current or the programmed threshold voltage of the selected memory cell can be sensed via the coupled bit line 36 via the transistor 63 闸 gated by a b-th XXL. The cell current discriminator 65A acts as a current discriminator or comparator. It is coupled to the sensing node to sense the conduction current in the memory unit. Figure 11B illustrates the cell current discriminator circuit shown in Figure 1A in more detail. The single 70 current discriminator 65A includes a capacitor 652 and a p-channel transistor 656. The cell current discriminator measures the conduction current of a memory memory cell substantially at a rate at which it causes the capacitor 652 to charge or discharge. This is done by sensing the signal SEN at node 631. Signal SEN controls the gate of p-electrode 656. Prior to sensing, SEN is precharged to vdd (high) by means of precharge circuit 6. Referring also to Figure 10, pre-charging is enabled by turning on the coupled transistor 632 to cause the node SEN 651 to couple to the pre-charge circuit signal HHL at node 647. This will initially set the voltage across capacitor 652 to zero. The sensing is then measured by measuring the conduction current of the capacitor according to the rate at which the capacitor is discharged according to the unit 131985.doc • 23 - 200921679. The conduction current of the memory cells in the bit line during sensing will cause capacitor 652 to discharge. The electric dust of the node SE will then decrease from vdd at a rate dependent on the conduction current. After a pre-top 疋 discharge period (which corresponds to a reference current), SEN will decrease to a value that can be turned on or off • the value of transistor 656. If it is reduced enough to turn on P transistor 656, this would mean that the conduction current is higher than the reference current. This will also cause (10) to pull high when the signal STB is asserted. Another aspect: if the transistor 656 is not turned on during the sensing period; the conduction current is lower than the reference current and the signal is

It is low. Referring also to Figure 10, the end of the sensing period is marked by de-energizing the bit line from the SEN node by disengaging the XXL of the coupling transistor 63A. The sensed result is then latched into the latch by means of a strobe signal STB. The cell current discriminator 650 effectively determines whether the conduction current of the cell is above or below a predetermined demarcation current value. The predetermined demarcation current value corresponds to a pre-emission discharge time. If the current sensed by the right is higher than the value of the demarcation current, the latch "60 is set to a predetermined state" and its ten signal chest = 1 (high). This is also intended to be in the control. The gate has a threshold less than the applied VT(i). In general, there will be a page of memory cells being processed by the sensing module 480 by a corresponding number. % supplying control and timing signals to each of the sensing modules. The page controller 498 cycles each of the multiple pass sensing sets 480 - a predetermined number of passes 〇 = 1 to N) and A predetermined demarcation current value is also supplied for each pass (1). As is well known in the art, the demarcation current value can also be implemented as a demarcation limit of 131985.doc -24-200921679 voltage or for sensing Time period. After the last pass, page controller 498 enables a transmit gate 488 by means of a signal NCO to read the state of sense node 481 as sensed data to read bus 499. In short, 'will All multi-pass module 48〇 reads a sensing data page. The problem of the high current memory unit is as described above, in order to increase the read performance, a memory single page is sensed in parallel, and the page is more powerful. However, as is apparent from Fig. 9, a large number of operations are performed in parallel. The unit will also consume a large amount of current. Many problems are caused by operation with a large amount of current. In general, it is always desirable to have a device that consumes less power. In particular, components that must accommodate higher currents will likely be more cumbersome and occupy Valuable wafer space. Often, suffix devices are designed for worse currents, and most of the time is operating with less current. This is because the current system is dependent on the data programmed into the cells. A less-programmed unit has a higher conduction current. Another problem involves introducing one of the finite resistances between the source line and the ground pad of the wafer. One potential problem of the sense memory cell is crossed. The source line bias caused by the source load of the effective resistor. When a large number of § memory cells are sensed in parallel, the combined current can have a finite resistance A significant voltage drop is caused in the ground loop. This results in a source line bias that causes an error in a read operation with threshold voltage sensing. Figure 12A illustrates the presence of a limited-to-ground The source voltage error caused by the current in the source line of the resistor. The read/write circuit and the 2 memory simultaneously process a memory cell page. 131985, doc -25 in the read/write circuit - 200921679

Each sensing module 480 is coupled to a corresponding unit via a bit line 36. For example, a sensing module 480 senses the conduction current source-drain current of a memory cell. The conduction current flows from the sensing module through the bit ^36 into the memory unit 1G, and flows out of the source 14 through the source line ^J to the ground. In an integrated circuit chip, the secrets of the cells in a cell array are all connected as a branch of the source line 34, and the source line 34 is connected to an external ground of the memory chip. Solder pads (eg, Vss pads). Even when a metal strip is used to reduce the resistance of the source line, a finite resistance R is maintained between the source electrode of a memory cell and the ground pad. Usually, the ground loop resistance is about 5 〇 〇hm. For the entire memory page being sensed in parallel, the total current flowing through the source line is the sum of all conducted currents, that is, ^ corp..., lp-like, σ, mother-s-resonant unit Each has a conduction current that is dependent on the amount of charge programmed into its charge storage element. For a given control gate voltage of one of the memory cells, a small amount of charge will produce a relatively high conduction current (see Figure 3). When there is a finite resistance between the source electrode of a memory cell and the ground pad, the voltage drop across the resistor is given by Vcirop^Z'rorR. For example, if the 24,000 bit lines each having a current of 0.25 μA are simultaneously discharged, the source line voltage drop will be equal to 24 turns χ〇 25 μΑ / each χ 50 ohms to 0.3 volts. When sensing the threshold voltage of the memory cell, this source line bias will result in a sensing error of 0.45 volts, assuming that the body effect causes the source voltage to rise by 0, 3 V causing the threshold voltage to rise 〇 45 v. Figure 12B illustrates the error in the threshold voltage level of the memory cell 131985.doc -26- 200921679 caused by a source line voltage drop. The threshold voltage VT supplied to the control gate 30 of the memory cell 1 is relative to GND. However, the effective voltage vT of the memory cell is controlled by the voltage difference between the gate 30 and the source 14. There is a difference between the supplied ντ and the effective % - about i 5xvdrcp (ignoring the effect of a smaller voltage drop from the source 14 to the source line). When 纟 senses the threshold voltage of these memories, the ν" or source line bias will cause a sensing error of (for example, 0.45 volts). This bias cannot be easily removed because of The data (4) 'is dependent on the memory state of the memory cells of the page. The source load and the power saving technique using the bit line lock have been applied by U et al. on March 16, 2005. A power saving technique is disclosed in U.S. Patent Application Serial No. 1 1/083, No. 5, the entire disclosure of which is hereby incorporated by reference. The manner is incorporated herein. In particular, a read or program verify operation includes one or more sensing cycles corresponding to one or more demarcation threshold voltages to determine which of a plurality of possible memory states per memory cell Among them. Each sensing cycle is used to sense with respect to a threshold threshold voltage and process a memory cell page in parallel. A sensing loop typically contains more than P passes or sub-cycles to resolve the memory state of all cells in the page. In one aspect, a first pass or sub-cycle senses and identifies as many memory cells as possible with the highest conduction current in the page. This will minimize the presence of the high current cells during a subsequent sub-cycle. And caused the error of 131985.doc -27- 200921679 7 sensing. Since the cells have been read, their conduction current is turned off to save power. The cells are disconnected by grounding their associated bit lines such that there is substantially no potential difference across the source and drain of each cell. In a subsequent pass or sub-cycle, the remaining memory cells of the page will be sensed again in parallel with reduced interference from the higher current cells. Thus, at least two sense passes 35 are implemented by distinguishing between two adjacent memory states with respect to each threshold threshold voltage. The first pass or sub-cycle identifies a high current unit having a threshold voltage below the demarcation level. The second pass or sub-cycle is repeated after the bit line of the high current cell is locked to a ground potential to turn it off. Figure 10 also shows that one of the bit lines 36 pull-down circuit 55 〇 ' pull-down circuit 55 启动 is activated when both the signal INV and the other signal GRS are high. The pull-down circuit 55 is preferably formed by a first NMOS transistor 55 串联 in series with a second n transistor 552. Signals INV and GRS will turn on transistors 55A and 552, respectively, when both are high. This will pull the sense node 48 1 and also the connected bit line 36 down to the ground voltage. Regardless of the control gate voltage, this will suppress the flow of conduction current in the memory cell 1' because there will be no voltage difference between its source and drain. The effective 'signal GRS can be considered by the state machine as a control signal to enable (GRS = high) or disable (GRS = low) bit line lock. Fig. 13(Α)·13(1) is a timing diagram of the sensing through the bit line lock 2 . It should be understood that there will generally be a sensing cycle % for determining whether each cell in the page has a threshold voltage below - above or above the threshold level, the threshold threshold is used to distinguish Two memory states. For each-sensing cycle, there will be 2 sensing passes relative to the mother of the reference threshold voltage supported by the memory 131985.doc •28· 200921679. The specific map i3(A)-13(J) is a timing diagram for controlling the signals of the sensing module shown in Fig. 1A. The overall scheme senses the memory cell pages in parallel with respect to the established reference threshold or reference conduction current. As described above, by determining a conduction current of a memory cell with respect to a reference current, the threshold (4) in the cell is sensed relative to a threshold threshold level - having - lower than the boundary The limit current limit unit will cause its conduction current to be higher than the reference current. Therefore, if the sensing cycle performs the next threshold threshold in a step-up sequence, each sensing cycle will distinguish between cells having conduction currents lower than the reference conduction current. U.S. Patent No. 7,196,931 discloses a method of reducing the source bias error by sensing a loop by _2. The 2 pass sensing cycle has a first pass identifying the cells having conduction currents that are substantially higher than the reference current. The relative reference current measurements are performed in the second pass after the cells are identified and disconnected in the absence of high current cell interference. Each of the sensing relative to a reference threshold voltage thus includes at least two sub-cycles of phase (1)-(4) and phase (5)-(9), respectively, wherein each sub-cycle is When the memory cell page is sensed in parallel, it passes through. Each of the sense sub-cycles requires a setting to set the word line and bit line to the appropriate voltage before sensing can occur. This is done by a precharge operation. The pre-charge operation of the first sub-cycle is between phase (丨)_(2) and the pre-charge operation of the second cycle is between phases. Figure 13 (A) shows the timing of precharging of the selected word line. If the sensing system is at the threshold voltage level of vT1, the word line begins to be precharged to this voltage level. Looking at the word line relative to the bit line <RC delay rc delay, the pre-charge of the sub-line can begin earlier than the pre-charging of the bit line. Precharging of the bit lines can occur with or without the memory cells coupled to the bit lines. As previously described, in one embodiment, the cells are initially decoupled from the bit line such that their drain current does not prevent the bit line from being pulled up. This is done by connecting the precharge circuit to the bit line via the isolation transistor 482 with the signal BLS high (Fig. 3(E)) and at S(}S low (Fig. 3(f)). This is done by cutting off the NAND chain that reaches the source. By turning the signal HHL high (Figure 13(B)), it is coupled into the precharge/clamp circuit as shown in Figure 10). In this way, the pull-up bit line (eg, Figures 13 (H1) and 13 (Π)) will begin to be pulled up. The bit line precharge phase (2) will begin when the bit line has been charged close to its target value. In phase (2), precharge continues, but the cell is coupled to the bit line to allow the bit line voltage to be stable under sensing conditions. The total precharge period during the first sub-cycle pass is represented by a precharge period. This embodiment in which the bit line is initially self-decoupled by the cell is only awkward after allowing the coupling to not cause a long wait period for the bit line voltage to stabilize. In other words, this embodiment is preferred if the wait period is shorter than the settling time in the case where the bit line is coupled to the cell at the beginning of the bit line precharge operation. Otherwise, it would be preferable to have another embodiment in which the phase (") is not implemented and the bit line precharge is only started with the phase (2) in which the bit line is precharged with respect to the conduction current of the cell. Sensing occurs in phase (3). As previously described, in the first sensor, 133985.doc •30- 200921679

High current unit identified in the ring. Thus, the sensing system is relative to a reference threshold that can be used at the margin of the sub-sensing sub-cycle. In other words, the first-sub-judging can use - a dividing current that is higher than the margin of the current of the next sub-cycle. In one embodiment, this is accomplished by shortening the discharge time of capacitor II 652 in the cell current discriminator 65Q (see Figure iib) of the sensing module (see Figure 1G). The signal master control combines or decouples the pre-charging circuit to the transistor 632 of the SEN node (see Figure 1A) and thus the current discriminator 650. On the other hand, the signal XXL controls the transistor 63 耦合 that couples or decouples the bit line from the SEN node. At the beginning of phase (3), signal HHL goes low (Fig. 13(B)), thereby terminating precharge and the conduction current of the cell will discharge capacitor 652. The end of the discharge period is controlled by xxl which is low at the end of phase (3), thereby cutting off the current by decoupling the bit line from the SEN node. As can be seen from the cell current discriminator 65 5 shown in Figure b, a demarcation current level according to its demarcation is related to the discharge time, and a longer discharge time produces a smaller demarcation current level. The voltage in the discharged capacitor is then compared in phase (4) with respect to the threshold voltage of p transistor 656 (see Fig. 11B), and the result is latched by strobe signal STB. This increase margin is then accomplished by shortening the sensing period in phase (3). In this manner, only the highest current will be able to discharge the capacitor to break the P transistor 656 during the shortened period. After the high current unit has been identified in the first sub-cycle, it is then latched and turned off before the next sensing. This is done by means of a high current unit having a result of sensing the INV = high. For example, in Figure 13, the cell coupled to bit line BL1 has a conduction current of approximately 120 nA below the threshold of 131985.doc • 31 - 200921679 (see Figure 13 (H1)). . This relatively small current will be sufficient to discharge capacitor 652 to reduce the charge at SEN (see Figure ΠΒ) to turn on p-transistor 656 so that when asserting the strobed stb signal, signal INV (Figure 13 (H2) ) A shows up as a swim!) Do not pull up to 胄. Therefore, a cell with a relatively small current will have INV = low.

In the aspect, a cell having a relatively large current (e.g., greater than 3 〇〇 nA or see Fig. 13 (11)) will have a signal latched at a high level (shown as INV2 in (7)). & is used to start the pull-down circuit 55〇 shown in FIG. When the pull-down circuit is enabled by the GRS signal high (Fig. 13(J)), then the pull-down circuit 550 is about to pull the bit line to ground via the enabled isolation transistor 482 (see figure just). Therefore, the sense lines of the cells with relatively large currents will be grounded to turn off their cells. In the first: sense pass or down __ sense sub-cycle represented by phase (5) (9), the process is similar to the first sub-cycle. The precharge cycle 702 occurs in phase (5)_(4). The sensed voltage in phase (7) has occurred after the displacement current has been stabilized by attenuating to a certain - unimportant value. Gating and Locking Any other high power that occurs at ::::(8) and is missing in the first pass == as shown in Figure 13 (10) in the previous phase (4) (4) = Reverse: Ground. In phase (9), the result of sensing the SEN form in a substantially signal stream will be assisted by reading the sink or the like: the meta-line is locked to ground to turn off the current sense independent of the current sense. Reduce the culvert, ώ · . a ^. First of all, this will, 2A). This has two benefits, power. Second, when Vdrop decreases with "or 131985.doc -32- 200921679 this will reduce the source (CLSRC) ground loop bias error. Therefore, existing sensing techniques have implemented this two-pass sensing with respect to each memory state. Figure 14 is an unintentional illustration of an example of applying an existing two pass sensing scheme to the eight state memory shown in Figure 8. The 8-state memory system has at least 7 boundary threshold voltage levels (i.e., Da, Db, dc, Dd, De,

Dd Dg) Demarcation. Thus there will be at least as many sensing cycles, each associated with one of the boundary threshold voltage levels. For example, DA is demarcated between the memory states "Gr" and "a", and % is demarcated between the memory state "A" and B, and so on. During each sensing cycle, a threshold threshold voltage level is applied to the selected word line. Each sensing cycle will have two more passes. The first is a "pre-sensing" that is locked by one of the 鬲 current bit lines detected by the follower. The pre-sensing will sense and identify a threshold that is lower than the applied threshold voltage level. Two current states of voltage. The bit line associated with the identified high current unit will be locked by latching to ground. In the case of removing the high current state, the second pass will be more accurate Similarly, any high current state that is not identified in the first pass will be properly identified and locked in such a way that the cells will be accurately sensed so that the data is below or above the finest boundary In order to distinguish all possible memory states, the memory cell pages are sequentially sensed relative to each threshold threshold. One of the threshold windows of the boundaries is bounded by the boundary threshold. When a high value is moved, more of the cells in the page will most likely be identified as having a higher current (with a threshold charge below the threshold threshold voltage level) and thus will lock more bit lines of the page. 131985.doc •33- 200921679 as previously The bit line lock is completed by the _ 不 不 pulldown circuit 550. In the existing two pass sensing scheme, the ^ Τ pull-down circuit 5 〇〇 is always prepared as long as the latched signal INV is high It is about to be pulled down. In the pull-down circuit 550 shown in Figure ι, the circuit is enabled by having the signal GRS always high so that the η transistor 552 always provides a connection to ground. This is caused by the bit line lock. Performance and Power Issues U.S. Patent No. 7,196,93 1 has indicated that by means of bit line locking, % has been sensed or no longer relevant in current sensing, the two pass sensing schemes help limit the involved The maximum current also provides a more accurate sensing in the second pass due to the reduced ground loop bias error of the source. However, any advantage is due to the diversity of sensing passes and the bit line locking operation The performance reduction caused by the generated noise is offset. The grounded selective bit lines in the bit lines in the memory array have interactions due to the capacitance between the bit lines. Capacitance The density of integrated circuits is becoming more and more important and becoming more and more important. For the memory of the so-called "all-line"("ABL") architecture mentioned in the previous), the bit line to the bit The line capacitance can be even higher. A page in all bit line architectures is formed by adjacent column memory cells along a column. If the memory plane is longer along the bit line direction, the ABL bit line to the bit The line capacitance can be higher. In the ABL and the conventional architecture, the distance from the bit line to the adjacent bit line is the same. In the conventional case, half of the bit line is precharged and its nearest neighbor remains grounded. The worst case scenario in which all bit-to-bit line crosstalk capacitors are facing. In ABL, all bit lines are charged together' but then discharged at different times. 131985.doc • 34- 200921679 Since the 7G line (and word line) acts as a capacitive load, there are two associated with the bit line locking scheme when one bit line is being precharged or discharged. The effect of expectations. First, many of the bit lines will be locked to ground potential, while the # bit line is pulled to a higher potential during pre-charging. Since bit-to-bit line capacitance 'is generally more difficult and would have to consume more than pulling all the bit lines in the page without facing some bit lines to be grounded The power is to precharge the bit line in the background of the bit line of the anchored ground. Second, an alternating current ("AC") displacement current will initially flow and eventually decay to zero as the bit line becomes charged to the applied power. Decay time line: A function of the RC constant of the line, where c is the effective capacitance. Since sensing a unit is essential to determine its DC (, DC) conduction current, accurate sensing in the bit line can only begin after the AC displacement current has decayed. The substantial part of the AC displacement current flowing in the line can be regarded as the capacitance from the charging bit line to the nearest bit line line, because the total capacitance of most per-bit lines is from each bit line to the resident The capacitance of its two neighbors on the side. The capacitance of each bit line or each electrode is equal to the sum of the capacitances of the electrodes to all its neighbors. If you subtract all the capacitances of all neighbors, there is nothing left. About 9〇% of the total capacitance of each bit line is tied to its first, second, and third nearest neighbors. This leaves a slightly more than 10% bit line capacitance for the upper or lower screen. When the 70 lines are simultaneously charged and discharged at the same time, the effective capacitance of each bit line is only about 1 G% of the total capacitance of each bit line. If it is: both are charged simultaneously but during various sensing operations Every time dropped to 131985.doc •35· 200921679

Ground, the effective bit line capacitance of the foil 杵AS and ^ is very high and can be viewed whether the bit line is locked at the same time or at different times with respect to the neighbors. Each bit line has: moxibustion due to bit There are many different opportunities for meta-line locking, so the chances of locking the bit line at the same time as the neighbors can be quite low. When all the bit lines are charged at the same time 2, the energy consumed is Cxy2, wherein CxV is stored as an electric field in the dielectric between the capacitor electrodes, and X Cxv is converted into heat of internal resistance combustion across the power source that delivers the energy. energy. This second term does not depend on the 4 resistance values within the voltage/power source. As long as all of the bit lines are uniformly charged, C in all of these expressions is valid c, which is only about 1% of the 'electrocardiogram' for each bit line as previously explained. However, when the bit line is locked at a different time than its neighbor (which occurs quite often), the power supply no longer has to deliver any energy to the bit line that is pulled down to ground. It only has to supply energy to adjacent bit lines that will sustain the bit line voltage but are capacitively pulled down by the neighbors that are forced to ground. For a bit line that will remain at its bit line voltage and its neighbor is pulled down to ground, the entire bit line to bit line capacitance is occupied. The bit line being grounded converts the electric field stored in the dielectric around it into thermal energy that is dissipated along the resistive path to ground. Figure 15 illustrates three adjacent bit lines and their capacitive coupling effects. A memory bank 7C 10-0 has two adjacent memory cells (7) - 丨 and (7) - 2. Similarly, three adjacent bit lines 36_〇, "一一刊" are respectively coupled to the three memory cells. The sum of the capacitances of each bit line's own capacitance from all other electrodes (eg, its pair of first nearest neighbors, its pair of second nearest neighbors, its pair of third nearest neighbors, etc.) Group I31985.doc -36 - 200921679, except that it reaches the capacitance of the electrode above or below it. Figure i5 does not depict all of the above capacitors, but rather depicts the largest capacitance of greatest importance. It can then be seen that various current branches may exist due to various capacitances. In particular, the current due to the capacitance of each bit line is formed: IBLO - C8L0, d/dt (VBL0 - VBLI) + Cbl〇2 d/dt (VBL〇- VBL2) Ignore the second and third And the effect of other neighbors and the effect of the electrodes in the layer above or below the bit line of interest. If all of the bit lines are charged together, the above expression is zero, and the displacement current will be such that the capacitance between the electrodes corresponding to the bit line of interest and the layer above or below it reaches The voltage is not caused by an ignoring of the degree of movement of the voltage of the bit line of interest. The cell current given above is an approximation because it only contains the effects from the adjacent bit 兀 line. In general, for the bit line BL0, there will also be a capacitance Cbl〇3 due to the non-adjacent bit line on the left side and a capacitance CBL〇4 due to the right side (the non-adjacent bit line on the J side). Similarly, there will be a common charge Cbli2 between non-adjacent bits 7L lines BL1 and BL2. These capacitances cause displacement currents that are dependent on varying voltages across each capacitor. The total bit line current is then displaced by current and conduction. The sum of the currents. The sense amp must provide a positive conduction current that enters the bit line and passes through the cell and then into ground. Similarly, the sense amp must provide additional positive current on the bit line whose neighbor is being pulled down to ground. The displacement current caused by the impact. The bit line pulled down to ground is only grounded and does not require power from sensing amps I31985.doc -37- 200921679 or any other supply to bring an electrode to ground. In other words, the displacement current will depend on the rate of change of the voltage difference between the bit lines. The rate of change of the voltage difference can come from different charging and discharging between the bit line and its neighbors. During pre-charging, as previously described, bit lines coupled to more conductive cells will require more net current for voltage charging and may thus be charged compared to a neighbor with one less conductive cell. Thus, when a bit line and its neighbors have similar memory states and thus similar conduction currents, they will all charge at a similar rate and have similar voltages at any given time. In this case, crossover The voltage difference of the coupling capacitor will be relatively small and the associated displacement current will be the same. By reducing the bit line voltage, not only does it require less energy to charge the capacitor involved, but also linearly reduces the maximum conduction. Current. The desired effect is that a sense amplifier with a fixed strength can easily maintain the charge boost rate of all bit lines, despite the fact that some bit lines are connected to non-conducting cells and other bit lines are connected to conductive cells. In the embodiment of the vehicle, the voltage of the bit line of the plurality of bit lines that are consumed to the plurality of memory cells is controlled so that each of the four adjacent bit lines is between The difference is substantially independent of the time at which the conduction current is being sensed. When this condition is applied, 'all currents due to various bit line capacitances are omitted because they are all dependent on a time-varying voltage difference. Therefore, according to the above formula & (10)% (10) Qiu (10) Bu 0, the current sensed from the bit line and the current of the unit (4), for example - the maximum displacement current will be in the line with the positive sense The associated unit and its 131985.doc -38- 200921679 neighbors have different memory states; see. For example, positive sensing: 立元线: when its neighbors are lightly coupled to a highly conductive unit To a non-conducting hidden body unit. In general, the displacement current will be stored in the extremely attenuated life time range. This means that the 'precharge recovery operation occurs during a pre-second period'. Exceeding the worst case recovery times " The bit line will be considered stable and accurate to be sensed before the displacement current must have decayed to a predetermined level. In the 2 sense pass, the tea right locks some adjacent 7L lines at the end of the first pass, and the second pass precharge period is further increased. In the bit line locking scheme, the identified high current cell latches its bit line to ground just before the second pass precharge. In some cases where the bit line is quickly pulled from the previous pre-charge level to the ground potential and the other bits = approximately maintained at the pre-charge potential, the power difference is extreme. This will result in a current in the bit line in the event that the next-sensing will occur. The precharge period must be long enough for all of the displacement locks to be subtracted. By this bit line lock scheme, after the parent lock operation, a more twist line voltage must be provided to stabilize before sensing can occur. Referring again to Figure 14, this delay between each test occurs in two _ persons with respect to the armor of the shield. For multi-level memory: - Steps are compounded at the per-demarcation threshold. For example, there will be ten (2 purchase periods for the seven read levels that will distinguish 8 states) due to the bit line locking effect = causing severe performance degradation. 13 13 131985.doc •39· 200921679 by means of opt-in enabling bit line lock for sensing according to the invention - when - bit ~ ..., in parallel sensing a memory cell page ^ a line grounded ( It is a memory line that is grounded by a bit line to close the current level of μ~~ predetermined current level: way, the neighboring 蛊, soil, and beer are minimized. This turns off the high power production list: (4) current consumption One of the established budgets skips the identification and sensing =; additional sensing sub-cycles, and sensing with a selectable number of = will cause the detection to correspond to the connected unit

Simultaneous sensing with other control poles will not result in any line closing operation. By reducing the efficiency of the sensing subsense... sensing operation: the number of clothing and the reduction of the noise generated by the bit line '70 line coupling when the bit line is turned off is improved. In this context, 'bit-to-bit line coupling refers to neighboring global bits.

Capacitive coupling. + βI In the preferred embodiment, the bit line is implemented by pulling the bit line to the ground pull-down circuit. The pull-down circuit includes two pass gates connected in series between the bit line and ground. The two pass gates are from a gate, one of which is controlled by a pull-up enable or disable control signal and the other pass-through is sensed by whether the cell in question has a higher or lower than one The current of the reference current is controlled. When the pull-down circuit is disabled, the bit line will not be grounded regardless of the result of the sensing. When the pull-down circuit is enabled, the bit line will be pulled to ground when the sensed result is from the high current memory unit. 16(A)-16(J) are timing diagrams for controlling signals incorporating the operation of a selective bit line locked sensing module. In essence, the sensing module 131985.doc • 40, 200921679 4 8 0 shown in FIG. 10 has a bit line locking special signal enabled or disabled by the control signal GRS. The state machine is called as shown in the figure (10). The pull-down circuit 55G is enabled when the signal (10) is two (see Fig. 1G). Conversely, when the grs is low, the pull-down circuit 55 is used. In the aspect, the figure is not in the figure (α)·ι3(7). The timing diagram refers earlier to the case where the signal GRS is always high (the bit line lock is enabled under the graph. On the other hand, the graph / Λ = timing diagram refers to the signal (10) is low (Figure 16 (J)) In the case of the choice, the bit line lock is disabled. In some embodiments, when the bit (4) lock is enabled, it precedes a sense T to determine the locked high current unit. On the other hand, when selectively using the bit line lock; t, the first sensing sub-cycle for determining the high current unit will also be skipped. Figure 16 (Α)_16σ) illustrates the selective stop The timing of the two sensing cycles with the bit line locking period/knife relative to the two consecutive demarcation threshold levels: therefore, unlike the enabling bit line In the case of locking, each 1 is sensed. = Relative to Klit over sensing, the selected word line is precharged to, before or at the same time as the pre-charging of the bit line. In particular, '2-wire pre-charging (4) Occurs in phase (1.5)_(16). Phase: Sensing occurs in the bit line. The voltage has been attenuated to a certain - unimportant =:: Displacement current is stable after 1 pass and latch occurs in phase lock The "high" current unit with a threshold voltage lower than VT1 has a latched tiger 1Nv' and has a lower limit of VT1. The unit has a low mv. In phase (1.9), The result of the sensing of the signal SEN in the inverse of the signal (10) J31985.doc 41 200921679 will be transmitted via the readout bus. As can be seen from Figure 16(J), the signal GRS is applied to two sensing cycles. In terms of low, the deactivation circuit 55〇 (Fig. 1〇) of each bit line is deactivated regardless of the sensed INV value. This means that even if there is less than Vti (see Figure ΐ6(ιι) and 16( For the high current unit of 12)), the bit line will be locked by grounding without being locked.

To limit page current and source bias errors, a bit line locking scheme is used to turn off the high current cells by locking their bit lines to ground so that they are no longer relevant for the implementation-sensing pass. Therefore, existing sensing techniques have implemented two pass sensing with respect to each memory state by means of bit line lock. It has also been explained that the shortcomings of the two-pass sensing are that they can greatly affect the sensing performance. Implementing two pass sensing will double the number of sense passes, thereby extending the sensing operation by a factor of two relative to single pass sensing. In fact, this delay = very long due to the need to manage the instantaneous noise generated by latching the bit line to ground. As previously described, a significant amount of displacement current is induced as noise in a bit line that enters a positive sense current. The displacement current is caused by a change in the voltage between adjacent bit lines due to the mutual capacitance of the bit lines. Because of this, the bit line precharge period of the sensing cycle is sufficiently extended to wait until the displacement current is attenuated. During this period of delay, the memory binary fits into the bit line and thus draws additional power in the case where the bit line is pulled over the precharge circuit (4) the conduction current of the cell prevents it. By not implementing the bit line lock of the detected high current cell, only m is over-sensed and the bit line is not pulled to ground. The noise will be minimized and not 131985.doc •42- 200921679 Need to extend the bit line precharge cycle. This is schematically illustrated by the shortened precharge period 702 of the phase (2.5) in the Vt2 sensing cycle shown in FIG. In fact, it has been estimated that all of the unit's turn-on periods are shortened, resulting in power savings. In the event that the number of bit line locks is reduced in accordance with the present invention to improve sensing performance, more high current cells will remain in an on state to cause source bias errors as previously described in connection with Figures 12A and 12B. Regardless of the high level of "(10)R, a solution to minimize the error is to reference all the voltages reaching the control gates and drains of the individual memory cells with a node as close as possible to the source of the memory cell as a reference. For example, as shown in Figures 12A and i2B, the reference point can be selected at source line 32 instead of ground to minimize ground loop resistance. U.S. Patent Nos. 7,17,784 and 7,173,854 and Sekar et al., April 24, 2007, entitled "c〇mpensating SOURCE VOLTAGE DROP in NON-VOLATILE STORAGE" Techniques for minimizing source bias errors are disclosed in U.S. Patent Application Serial No. 7, the entire disclosure of each of which is incorporated herein by reference. The pre-equivalent potential is in the implementation of a sensing multi-state memory ("there is a relatively small sensing pass on the memory unit page relative to each other") By implementing a step of locking and identifying a bit line associated with a memory cell that is above a predetermined current level, bit line locking is used to reduce the benefits of total current and source bias errors and more The negative effect caused by the longer sensing time caused by the sub-cycle and the longer waiting time of the noise generated by the sub-circulation is balanced. By selecting 13I985.doc -43« 200921679 to reduce the number of locks, the reduction is reduced. Such negative effects of lower sensing performance and higher power consumption.Figure 17A illustrates an exemplary schedule for selectively enabling bit line locking in multiple passes of a multi-state sensing operation. Associated with the 8-state memory shown in Figure 8. To resolve all possible eight states, the memory cell pages will have to be sensed in at least 7 sensing cycles, each with a different demarcation threshold. Standard, such as Da*D b, ..., etc. Two pass sensing is implemented in each sensing cycle. However, the difference from the existing two pass sensing (see Figure 14) will disable the bit line locking operation during the second pass. In other words, every other sensing will be performed by skipping the bit line locking operation. In particular, the bit line locking operation will be skipped after sensing in the second pass. The number of passes and the existing two pass sensing At the same time, the bit line locking operation is reduced by 50%. In this case, less noise will be generated after the second pass and the first pass in the next cycle will be passed through with a shortened bit line. Charging cycle. If the word line settling time has the same magnitude as the bit line to bit 70 line crosstalk recovery number, then this embodiment does not significantly increase the performance, because the bit line lock and recovery from it can be compared with the next sensing bit. The steady word line voltages occur simultaneously. Figure 1 7B illustrates another exemplary schedule for selectively enabling bit line locks in multiple passes of a multi-state sensing operation. This example is also shown in Figure 8. 8 state memory is not relevant and similar The example shown in Figure 1 A 'except that two pass sensing will be performed in every other sensing sub-ring. In the cycle of solid pass, only the sensing operation will be performed and the pre-sensing will be skipped and Bit line locking operation. In this case, the number of passes is reduced by 131985.doc -44 - 200921679 5 0 and the number of bit line locking operations is reduced by 75. Figure 1 7C illustrates a store Pseudo-randomization of the second, page. In order to ensure a high current state in a page, the 己 八 布料 布料 布料 布料 布料 以 以 以 以 以 以 以 以 以 以 以 以 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越 跨越In the body state, in the preferred embodiment 4: all possible records appear to be pseudo-randomly distributed in the possible memorization coding in the state, so as to be based on the skipped bit line locking operation. In the form of 10,000, the amount of current in the system is called _ # 忆. Estimated. t 〇己

- According to another aspect of the invention, the reduction in bit line lock is equivalent to the total current of the predetermined maximum current of the memory single page t flow. Conversely, the bit line locking operation is referenced when the total current (which is dependent on the data) appears to exceed a predetermined current level. In this case, the bit line locking operation is minimized in the case where the system does not exceed a peak current. The predetermined current level is in an embodiment of sensing a multi-state memory that involves performing multiple sensing passes on the memory cell page relative to each of the plurality of states, only in the memory cell The step in which the current flowing in the page will exceed a predetermined maximum current by predetermined sensing by performing a locking and associated bit line associated with a memory cell that is above a predetermined current level. In one embodiment, a current monitor is provided to monitor the total current flowing in the memory cell page. Figure 18 illustrates a bit line locking operation in response to a monitored current of one of the memory systems. Figure 18 illustrates a current flowing in a memory cell page that is being sensed by a corresponding sensing module in a read/write circuit 270A as shown in Figure 9. A current monitor 71 0 is positioned at a path that sums the sum of the currents of the individual memory cells from page 131985.doc •45-200921679. For example, it is placed in the conduction path between the source line 34 and the system ground. In a practical example, the 4 current monitor is constructed as a voltage monitor across a resistor such that the monitored current is divided by a voltage drop similar to the resistance shown in the figure. The current monitor 71A preferably includes logic to provide a signal BLNqL〇c to the state machine i i2 (see FIG. As long as the monitor current ^ is lower than the -predefined level, BLNqLC)c is the output high. In response to BLNoLOCW, the state machine will cause the sensing to be performed while the bit line is locked, while the control signal GRS goes low (see Figure 1). Otherwise, at Zro:r>iA^z畤, BLN〇LOC will output low and this will signal the state machine to operate sensing to disable the current of some memory cells in the case of enabling bit line lock. Figure 19 illustrates another embodiment in which the total current flowing in the page of the cryptographic unit is estimated based on the number of bit lines that have been locked. Figure 19 illustrates the current flowing in the memory cell page being sensed by a corresponding sensing module similar to the one in the read/write circuit 27A shown in Figure 9. - The number of bit lines that the accumulator count has latched to ground. Next, the total current ^ can be estimated as the number of ungrounded bit lines in the (4) page of the average current per unit. Accumulator 720 preferably includes logic to provide a signal BLNoLOC to state machine 112. As long as the estimated total current (10) is bubbled at a level of 芥~μ' BLNoLOC, the output is high. In response to BLN〇L〇c being high, the state machine will cause sensing to be performed with the bit line locked, while the control signal GRS goes low (see Figure 1〇). Otherwise, the heart BLNoLOC will output low and its signal state machine will operate to sense the current in some memory cells in the clear mode of the enable bit line lock 131985.doc -46 - 200921679. The eve diagram 20 illustrates an example result for selectively enabling bit line lock in response to an over-current system current limit in the multi-passion of the multi-cell cancer cancellation J operation. In contrast to the examples shown in Figures 17A and i7B, the bit line locking operation is based on the level of the total current (which is dependent). Therefore, for the second time, in the case of the shape m, two pass sensing is cited to get rid of the most current state. Then for the state "B" in a pass sensing situation

The lower V uses the 7L line lock $. If, after that, it is determined that ^^ exceeds ^, then the person activates the TL line lock to implement two-pass sensing for the state "c". Class (4) 'If the S-line lock causes "reduction" during the sizing period, the bit line lock will be enabled again. This is maintained during sensing at the states "D" and "Έ" and allows the soap to pass through the sense until sense Test "E" ends. At some point, it exceeds or will exceed ". Therefore, a cycle under the sensing state is implemented in (4), etc. ^ Figure 2 1 - illustrates the position during sensing according to a preferred embodiment of the present invention Flow chart of the line lock control. Step 810 · Access to the individual memory cells of the group by means of the associated bit line and the shared word line. ^ Group step 82G: Select _ will be sensed relative to it The boundary threshold voltage level is one of a plurality of threshold voltage levels. Step 83G: Precharge the common word line to the selected threshold threshold voltage level. Step 832: The pre-charged bit lines are pre-charged to a predetermined voltage level of 131985.doc -47- 200921679. Step 840: Enable bit line lock? If enabled, proceed to step 842' Otherwise, Go to step 85. Step 842: Sensing the memory cell group in parallel with respect to the selected threshold threshold voltage level. ~ Step 844: The identification sense has a threshold voltage less than the selected threshold. Any of the memory cells of the threshold voltage level.

Step 846: Lock the associated bit line by setting the associated bit 70 line of any identified memory cell to a ground potential for voltage bits less than the threshold voltage level from the set All of the iterations are selectively implemented for this lock. , 骒850: Relative to the selected boundary, the memory unit group ★ step 860. Is the voltage determined by the voltage equal to the last voltage level in the group? If it is equal to ', proceed to step 870, otherwise return to step 82. Step 870. Complete the sensing of the group. The figure illustrates an embodiment in which one of the pre-sensing lock current units is performed by one of the sense sensors without any pre-sensing lock current units. The current load level or the response to the predetermined schedule implementation bit line lock ' The first and the rising read period and the recovery period from it can be simultaneously caused by the conduction current continuous = two. In this mode, if this mode is valid, it needs t: it can increase the conduction current. ^ The constant between the word lines should be reduced as much as possible, and the voltage level of each sub-line to the next word line voltage level is 131985.doc -48- 200921679 line sensing. For example, this line is completed. You can use the line... or more conductive words to make all the bit lines and discharge the bit lines in the last word line to minimize each bit to quickly sense all the strong I , , n, energy. ~,, 'Reduce the period of current consumption to minimize the transmission of the second instance - memory with 16 states. - One embodiment makes the material 2 after the third state (4)—3 sense operation, and pass, of which the third sense is sent 4/16 of these units = 1/4 turn-on. Based on the result of this third sensing operation, all cells that have been found to have been turned on during the second sensing operation will be immediately locked. In addition, bit line crosstalk recovery The number of times will occur simultaneously with the word line rising from the third sensing level to the fourth sensing level, and the lower-bit 'line locking operation occurs at the seventh sensing level. Between a strobe sensing at the level of measurement. The lower-locking operation occurs between the (4) and ^ sensing levels. As explained, there will then be only 3 敎(4), and the domain should be H(4) for each of the recovery times - The second time will occur simultaneously with the word line rising to the next __ level, and the entire sequence of events allows the unit to conduct DC current if and before it is turned on and before it reaches the next operation. Figure 23 is based on Figure 22. An alternate embodiment of the illustration illustrates a flow chart of bit line lock control during sensing. Step 910: access to individual memory cells of the group by means of associated hatred lines and a common word line. 920: Selection—the threshold voltage level at which the sensing will be performed relative to the sensing. The threshold threshold voltage level is a set of multiple threshold voltage levels - 131985.doc -49- 200921679. Step 930: Precharge the common word line to the selected threshold threshold voltage level. : Precharging the common word line to a selected threshold threshold voltage level. Step 940: Sensing the memory cell group in parallel with respect to the selected threshold threshold voltage level.

Step 950: Enable bit line lock? If enabled, proceed to step 952, otherwise proceed to step 960. Step 952: Identifying any memory unit that senses a threshold voltage level that is less than the selected threshold threshold voltage level. Step 954: Locking the associated less than the threshold from the set by setting the associated bit line of any identified memory unit to all of the iterative selected bit lines to a ground potential The voltage level of the voltage level is selectively implemented to perform the locking. Step 960: Is the selected voltage equal to the last voltage level in the group? If it is equal to ', proceed to step 970, otherwise return to step 92. Step 970: Complete sensing of the group. Figure 24 illustrates yet another embodiment in which actual sensing is performed without locking one of the pass-through sensing. Avoid any - locking \" 彳糸 a predetermined scheduling result or can respond to the current load level of the system. In this mode, the increased conduction current can be offset by the decrease in the bit line voltage previously described and also the amount of conduction current duration that is reduced. As previously described, the two features help to reduce the number of passes through the implementation of 131985.doc -50- 200921679, even to the extent that no two-pass sensing is required. - The reduction of the line voltage of one line and the randomization or scrambling of another line of data. A very efficient case is to reduce the bit line voltage during read and verify operations to minimize conduction energy and capacitive charging energy. The reduced cell current will also reduce the CLSRC load and allow for less locking operation. The sense current—which must also be reduced to achieve a good transconductance at the (VT, Iref) point, is reduced by the 70-line voltage and the resulting turn-on current is reduced. However, in the case of a sensing scheme in a conventional memory architecture, the reduction in bit line voltage is limited. This is because the conventional sensing scheme uses bit line capacitance to measure the conduction current of the cell. The unit line is charged to an initial voltage and then allowed to discharge by the unit current. One of the current rate cell current measurements. The bit line voltage is limited because the initial voltage cannot be so low that it discharges to an undetectable value relative to the R C time constant of the bit line. In addition, the reference sense current is fixed to the RC constant of the bit line and cannot be easily adjusted. On the other hand, in the sensing scheme first introduced into the ABL memory architecture, the sensing does not depend on the time constant of the bit line because the discharge rate is relative to the dedicated capacitor of the sense amplifier. Such sensing schemes have been disclosed in U.S. Patent No. 1,93. The RC constant of the dedicated capacitor can be adjusted to optimize sensing. In this case, the bit line house can be further reduced. The result will be that the sensing will have to be performed at a lower reference current, which is easily accomplished by a suitable choice of the value of the capacitor n. In the case of data scrambling/randomization, there is a roughly equal number of single πs in each state. Means that the unit of ln6 is in each of these states. 131985.doc •51 - 200921679

Among them. In the case of scrambled data, since only 1/16 of the cells are turned on at each higher control gate voltage, it is better to use single pass (one gate) for sensing, and at the beginning of the connection In the meantime, if the state to state is separated by only 400 mV, it is not fully conductive. Even in the case of the previously described 2 pass scheme, a significant number of cells will be locked after the first gating to escape the lock due to the high cell source load present during the first gating. The evacuees will then conduct more current orders of magnitude during the bit-to-bit line crosstalk recovery period because the non-escaper has been turned off and the CLSRC load has been reduced. Therefore, the escaper who flees the first gate due to its current of, for example, nA, will conduct 700 nA as long as the non-escaper is locked and the CLSRC voltage is reduced. The first gating or second gating integration time is 〇 4. However, the number of crosstalk recovery from the bit line to the bit line is 4 4 "Μ. Under these conditions, the 2 pass scheme (ie, the two gates) produces the exact opposite in terms of efficiency and energy consumption. As a result, this does not randomize the data 'that is, or the bit line voltage cannot be kept low, and the state to state separation is substantial (this is not the state of 8 states, or the state of 16 states, memory). Even if it has In the state memory with a large state to a state separated, # is only reduced by the bit line so that the on-current of the averaging cell is ~〇3 UA, so that the page is more than - the half cell is completely conducted and still used. All patents, specialties, papers, books, brochures, other publications, documents, and articles mentioned in this article are for all purposes: for all purposes: Definition or use of terms between any of the publications, documents or things in the person and the text of this document 13I985.doc -52- 200921679 The definition or use of terms in this document will have any Contradictory or conflicting party While the various aspects of the invention have been described in terms of certain embodiments, the invention is intended to be protected within the scope of the appended claims. FIG. The functional map illustrates the functional blocks of the non-volatile simon memory wafer in which the present invention can be implemented. Figure 2 schematically illustrates a non-volatile memory cell. Figure 3 is selective for floating gates at any time. The four different charges Q1-Q4 stored in the ground illustrate the relationship between the source _ drain current 1 〇 and the control gate voltage VCG. Figure 4 illustrates an example of an N 〇 R memory cell array. The unintentional map illustrates the organization of a string of memory strings into a nand string - early. Figure 5B illustrates an example of a NAND memory cell array constructed of, for example, the string shown in Figure 5A. A typical technique for programming a memory cell page to a target memory state by means of a series of alternating stylization/verification cycles. Figure 7(1) illustrates an erased state as a ground state &q Uot; Gr" and progressively more routineized memory states "A", "B" and "c" an exemplary 4-state memory array threshold voltage distribution. Figure 7(2) illustrates a preferred, 2-bit LM code to represent the four possible memory states shown in Figure 7(1). 131985.doc -53· 200921679 Figure 8 (1) illustrates the threshold voltage distribution of an exemplary 8-state memory array. Figure 8(2) illustrates a preferred '3-bit encoding to represent the eight possible memory states shown in Figure 8(1). Figure 9 illustrates the read/write circuit of Figure 1 including a row of sensing modules across a memory cell array. Figure 1 is a schematic illustration of the sensing module shown in Figure 9 suitable for practicing the present invention in more detail.

Figure 11A illustrates in more detail the precharge/clamp circuit shown in Figure 。. Figure 11B illustrates in more detail the cell current discriminator circuit shown in Figure 。. Figure 12A illustrates the source voltage error problem due to current in the source line with a limited pair of ground resistance. Figure 12B illustrates the error in the memory cell threshold voltage level caused by a source line voltage drop. Fig. 13(A)-13(J) is a timing chart of 2 pass sensing by means of the position 亓 & ~~ )W symbol 1 70 green lock. 8 of the state memory should be schematically illustrated in Fig. 8 as an example of the existing two pass sensing scheme shown in Fig. 8. The picture should be. 1 5 illustrates the capacitive coupling effect of three B adjacent bit lines and between them. Figures 16(A)-16(J) are timing diagrams for controlling the signals incorporating the operation of the selective bits. The sensing mode set of the meta-line lock 131985.doc 200921679 The majority of the selection by the middle selection Figure 17A illustrates an exemplary scheduling for selectively enabling bit line locking in the multi-state sensing operation. Figure 17B illustrates another exemplary schedule for selectively enabling bit line locking in a multi-state sensing operation. Figure 17C illustrates the page. Memory Unit for Storing Pseudo IW Machined Data Figure 18 illustrates the response to the 恃 恃 糸 。. The bit line locking operation of one of the monitored currents of the corpus system. Figure 19 illustrates another embodiment in which the total current flowing in the page of the memory unit is estimated by the number of bit lines that have been locked by the initial error G. Figure 20 illustrates one exemplary result for selectively enabling bit line lock in response to a multi-state sensing operation in response to a system current limit being exceeded. Figure 21 is a flow chart illustrating bit line lock control during sensing in accordance with a preferred embodiment of the present invention. Figure 22 illustrates an alternate embodiment in which one of the single sensing passes is performed without any pre-sensing locked high current cells. Figure 23 is a flow diagram illustrating bit line lock control during sensing in accordance with an alternate embodiment shown in Figure 22. Figure 24 illustrates yet another embodiment in which actual sensing is performed without locking one of the high current cells. [Main component symbol description] 10 Memory unit 10-0 Memory unit 131985.doc -55- 200921679 10-1 Memory unit 10-2 Memory unit 14 Source 16 Deuterium 20 Charge storage unit 30 Control gate 32 Control gate 34 bit line 36 bit line 36-0 bit line 36-1 bit line 36-2 bit line 42 word line 44 select line 50 NAND string 54 source terminal 56 汲 terminal 100 memory chip 110 Control Circuit 112 State Machine 200 Two-Dimensional Memory Cell Array 230A Column Decoder 230B Column Decoder 231 Data I/O Bus 131985.doc -56- 200921679 250A Page Multiplexer 250B Page Multiplexer 260A Row Decoder 260B Row Decoder 270A Read/Write Circuit 270B Read/Write Circuit 480 Sensing Module 481 Sensing Node 482 Isolation Transistor 488 Transmission Gate 498 Page Controller 499 Read Bus 550 Pull Down Circuit / First η Transistor 552 second η transistor 600 sense amplifier 610 \ bit line voltage clamp J 612 transistor 620 丨 voltage clamp 630 transistor 631 node 632 coupling transistor 640 precharge / clamp Circuit 640 'node precharge circuit 647 131985.doc -57- 200921679 650 651 652 656 660 710 720 Π cell current discriminator capacitor node SEN P-channel latch transistor current monitor accumulator

U 131985.doc -58-

Claims (1)

200921679 X. Patent Application Range: 1. A non-volatile memory comprising: a memory cell array accessible by bit lines and word lines; a sensing circuit group for parallel sense Detecting a conduction current in a group of corresponding memory cells, wherein individual memory cells of the group are accessible by associated bit lines and a common word line; a word line voltage supply for relative implementation The sensed voltage level pre-charges the common word line to a selected threshold threshold voltage level, the threshold threshold voltage level being one of a plurality of threshold voltage levels; a bit line voltage supply for substantially precharging the associated bit line to a predetermined voltage level; a set of control signals for controlling the sense circuit group relative to the selected threshold threshold voltage, Sensing the memory cell group in parallel; and a bit line grounding circuit for causing each sensing circuit to respond to one of the sensing circuits and enabling bits in each sensing circuit during sensing Line lock one of the control signals The bit line associated with the ground. 2. The non-volatile memory of claim 1, wherein: the sensing result is when the sensed memory cell has a conduction current higher than a reference sense current; and the control signal is in a bit One of the line locks is asserted when the condition is enabled. 3. The non-volatile memory of claim 2, wherein: the bit line lock enable condition comprises one of the memory cell groups. 131985.doc 200921679 When the current reaches a predetermined current level. 4. The non-volatile memory of claim 2, wherein: the bit line lock enable condition includes when the identified memory reaches a predetermined number. A few sighs 5 · The non-volatile memory of claim 2, where: the bit line voltage supply is supplied during sensing - the predetermined minimum bit 6. The non-volatile memory of claim 2, wherein: the bit line lock enable condition includes when the selected demarcation threshold voltage level is consistent with one of the plurality of threshold voltage levels of the group, τ - Pre-position 7. The non-volatile memory of claim 6, wherein: § hai sub-group is formed by selecting a spaced-off threshold threshold voltage level among the plurality of threshold voltage levels of the set. [Approximately: 8. The non-volatile memory of claim 7, wherein: the memory cell group is stored in a pseudo-random pattern. 9. The non-volatile memory of the request item, wherein: the sub- The group is an ordered group of multiple threshold voltages. The boundary is limited to the difficulty. $ —, s , and η are divided into the selection of the drought, and the η is an integer greater than 1. 10. The non-volatile memory of claim 1, wherein: the s-component threshold voltage comprises at least three voltage levels. 11. The non-volatile memory of claim 1, wherein: the component threshold voltage Containing at least seven voltage levels 12 • Non-volatile memory as claimed in claim 1, wherein: 131985.doc 200921679 The component threshold voltage contains at least fifteen voltage levels. 13. The non-volatile memory of claim 1, wherein the sensing circuit group operates in a read operation to read a memory state stylized into the memory cell group. 14. a non-volatile memory as in the case of a kiss, wherein the sensing circuit group operates in a portion of the operation to verify whether the threshold voltage has been programmed relative to the threshold Any of the memory units. 15. The non-volatile memory of claim 1 wherein the non-volatile memory cell group is part of a flash EEPROM. ~% like the non-volatile memory of the requester, which is the fast (four) coffee NAND type. The non-volatile memory of the group, wherein the non-volatile memory of the group has at least one charge storage element. 18_ The non-volatile memory of claim 17, wherein the charge storage element is a floating gate, wherein the charge storage element is the non-volatile portion of the group. Volatile memory - a dielectric layer. 20. The non-volatile memory memory unit of the present invention stores at least two bits of information in the length of 1 to 2G of the non-volatile memory of the request item, wherein the non-volatile memory The memory unit is embodied in a memory card. 22. A non-volatile memory comprising: a memory cell array accessible by bit lines and word lines; 13I985.doc 200921679 A sensing circuit group for parallel sensing a corresponding current in the group of memory cells, wherein the individual memory cells of the group are accessible by associated bit lines and a common word line; a sub-wire voltage supply for the common word line Precharging to a selected threshold voltage level relative to which the sensing is to be performed, the threshold threshold voltage level being one of a plurality of threshold voltage levels; a 7L line voltage supply Used to substantially precharge the associated bit line to a predetermined voltage level; a control component for controlling the sensing circuit group 'with respect to the selected threshold threshold voltage to sense the memory in parallel a unit cell group; and a one-element grounding circuit for controlling each sensing power in response to the sensing result of the per-sensing circuit and enabling one of the bit line locks during sensing Both of the signals ground the associated bit line. 23. The non-volatile memory of claim 22, wherein the non-volatile memory cells are embodied in a memory card. 24. A method of sensing in parallel—a group of non-volatile memory cells, including: 〃 (a) the associated payment + r u. ro ., the outer 1 bit 70 line and a common word a line that provides access to individual memory cells of the group; (b) selects a boundary that will be relative to the device, <, B|, T7, with the threshold voltage threshold for performing the sensing The threshold electric 懕彳 M zy electric vertical level is a set of multiple threshold voltage levels _ _ m. · 9 (C) pre-charging the common word line 1 兮揖 # 人 人 人 人 人 人 人 人 人 人The threshold of the threshold of the main election is 131985.doc 200921679 (d) The pre-charged bit lines are substantially precharged to a predetermined voltage level; (e) relative to the selected threshold threshold voltage level Sensing the memory cell group in parallel; (0) when a bit line lock enable condition is satisfied by grounding the bit line, that is, (8) to (4) are performed before continuing to (8), otherwise skipping To (h): (gl) identifying any memory unit that is sensed to have a threshold voltage level that is less than the selected threshold threshold voltage level; (g2) by leaving any identified signature card _ > ϋ, η. Meng (1) 屺 hidden body early 兀 this associated bit line is set to a ground potential to pin Ma Ruguan, not 颂疋 β associated bit line, whenever a line lock enable condition is met The voltage level of the threshold voltage level is applied to the lock; and that is, for all generations less than the plurality of iterations from the group, selectively (h) Repeat (b) to (h) for each of the voltage levels from the set of multiple thresholds, repeating (b) to (h) until it has been repeated and from each voltage level of the group. 25. The method of claim 24, wherein: the implementations (gl) through (g2) further comprise: (g3) thresholding the group of memory cells relative to the selected boundary. Voltage level, sensing in parallel 26. The method of claim 24, wherein: the bit line lock enable condition includes when the current of the memory early group reaches a predetermined current level. 27. The method of claim 24, wherein: the bit line lock enable condition includes when the identified memory element reaches a predetermined number. 28. The method of claim 24, further comprising: operating the line at a predetermined minimum bit line voltage during the sensing period. The method of claim 24, wherein: the bit line lock enable condition includes when the selected demarcation threshold dust level is in a subset of the plurality of threshold voltage levels of the group - a predetermined level Consistent. The method of claim 29, wherein: the subgroup is formed by selecting a substantially equidistantly spaced boundary threshold voltage level among the plurality of threshold voltage levels. 31. The method of claim 30, wherein: the group of memory cells stores data encoded by the pseudo-Ik machine pattern of the power station. 32. The method of claim 29, wherein: the subgroup is shaped by selecting every n boundary thresholds in a viscous day 4 and at a threshold voltage level ~ Attack and η is an integer greater than one. 33. The method of claim 24, wherein: the component boundary threshold voltage is included? , 丨, the main J two voltage levels. 34. The method of claim 24, wherein: the component threshold voltage comprises a right 5, 丨,, 3 has at least seven voltage levels. 35. The method of claim 24, wherein: the component threshold voltage comprises, 啕 to fifteen voltage levels. The method of claim 24, wherein the sensing is a portion of a read operation to read a memory state stylized into the group of memory cells. The method of claim 24, wherein the sensing is part of a stylized operation to verify whether any of the memory cells have been programmed relative to the selected/demarcation threshold voltage. 38. The method of claim 24, wherein the non-volatile memory cell group is part of a flash EEPROM. 39. The method of claim 24, wherein the flash EEPR〇M is of a type. The method of claim 24, wherein the non-volatile memory cells of the group each have at least one charge storage element. The method of claim 40, wherein the charge storage element is a floating gate 0. 42. The method of claim 39, wherein the charge storage element is a dielectric layer. 43. The method of claim 24 wherein the non-volatile memory cells of the group store at least two bits of data. The method of any one of claims 24 to 43 wherein the non-volatile memory unit is embodied in a memory card. 131985.doc