TW200921322A - Clock synchronization device, clock synchronization method and clock generation device using the same - Google Patents

Abstract

A clock synchronization device is used for synchronizing a first clock signal and a second clock signal produced respectively by a first clock generator and a second clock generator. The clock synchronization device comprises a delay-locked loop circuit and a phase-locked loop circuit. The delay-locked loop circuit receives the first clock signal and the second clock signal and produces a first signal according to the phase relation between both of them. The phase-locked loop circuit is coupled to the delay-locked loop circuit and is used for receiving the first reference signal to produce a second reference signal to the second clock generator, wherein the second reference signal conforms to an input requirement of the second clock generator.

Description

200921322

OybUlbi 74jyutwf.doc/p Nine, invention description: [Technical field of the invention] The present invention relates to a clock synchronization device, and the clock signal generated by different clock generators is selected, Technology] Eight devices. The traditional clock generates the f) o provided by the quartz oscillator as an input source, and generates the clock signals of different frequencies through the internal phase-locked loop electrical frequency t for the system to operate. Missing 3 = computer system, whether the pulse signal is synchronized 'is very important ^ Phase-locked loop (Phase-i〇cked 1〇 PLL) 匕, synchronization circuit. Fig. 1 shows a schematic diagram of a clock generator. Please include the phase-locked loop 120 and the divide-by-unit unit no. The logic control unit 150 is controlled by the lock to control the fall of the phase locked loop 丨20. The phase-locked loop (10) is generated by the raw-phase inverter and the frequency divider and the stone receiving crystal coiler 140 respectively. 4 4 ‘Asian and according to the signal, it usually requires a different frequency of the clock processing star. A variety of different types of devices can function normally. For example, Zhongben f. Therefore, in the general clock output, the signal generated by the phase-locked loop (10) is divided by frequency to generate the clock signal of the desired frequency, for example, 200921322 0960163 24390twf.doc/pr:=&quot;2' The clock position, "the frequency can be limited. When the system requires the clock; === = =, ' can be reconfigured by the coupling method to raise =.: mention = f see. That is to say ' The time delay generated by the clock generator (10) is different from that of the clock provided by the other clock generator, which can cause the electronic system to malfunction. The word red 5 tiger is not synchronized. Thus, the content of the invention is The antimony ore m generation device can easily synchronize the clock signals of the plurality of independent operation &gt; clock generators to each other. The operation of the present invention provides a clock synchronization 褒 二 二 时 产生 所 所The pulse generation device is generated. The clock synchronization device includes a 'sigma first time=the fixed circuit receives the first time===== fixed:, with the _- reference letter one clock generator, wherein the The requirements of the wheel of the device. Η - reference (4) the second clock generation 200921322 0960163 24390twf.doc/p In addition, the clock signal generated by the clock is proposed. The clock generation includes the first-day synchronous pulse generator and the clock-synchronized farmer. The first and second clock signals generate the first clock. The second pulse generation state is based on the reference time test signal 'generating the second one. According to the first-parameter generator and the second whistle generator, the light-connected first-clock signal' is based on the phase signal between the two and the first The second clock generates a first reference signal. ', phase and frequency lock, and from another point of view, the present invention is further connected to 屮 ± first, first, receive the first-time gland signal and the first synch. The phase difference of the clock two-clock signal: production;; the clock signal and the second clock signal are synchronized. The mouth says that the brother and the other half use the pulse of the output of the one-time generator, and the main phase is a == system, and the phase-locked loop is phase-locked. In addition, [when: m signal] bridges the two clock generation states of the clock synchronization device, so that the two outputs synchronous clock signals. The above and other objects, features, and advantages of the present invention will become apparent from the <RTIgt; Port diagram, [Embodiment] Ο ο 200921322 0960163 243y〇twf.doc/p Figure. The schematic of the clock generating device of an embodiment of the present invention 囷 卞 产生 产生 产生 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 。 。 。 。 。 。 。 The clock generator 21G ^ raw / water 210, 2 ί, and generates the clock signal CLK1, and the clock production &gt; test field f2 and produces the pulse signal CLK2 ^ oscillator (not provided by the channel supply %· pulse signal, so it is not limited to this. The generator ί 23_ clock generator 2 timely pulse production - according to the pulse signal CLK1 timely pulse processing, and generate the reference signal heart: 22 〇: _ pulse generator According to the clock signal CLK2, it is known that the clock signal CLK2 is fed back to the clock to form a closed loop circuit with the clock generator 22 and the clock generator 22, which can provide a closed loop circuit. System-loop response. _, 218 shows the clock generators 21〇, 22〇 in Fig. 2A of the embodiment of the present invention. Please see Fig. 2B, where the circuit of the clock generator 2 〇 is operated, For example, the clock generator U includes a phase locked loop 2 ι and a frequency dividing unit 212, and the phase locked loop 211 includes frequency dividing units 213 and 214, a phase frequency gamma unit 215, and a low pass filtering unit (L〇w

Pass Filter, PF) 217, and voltage controlled vibration recovery unit 216. The input terminal of the frequency dividing unit 213 receives the reference clock signal fREF ', and its output terminal subtracts the phase frequency detecting unit 2 i 5 from the input terminal. The other input of the phase frequency price measuring unit 215 is deducted from the output of the frequency unit 214, and the output end thereof is coupled to the input end of the low pass filtering unit 217. The input end and the output end of the voltage control oscillating unit 216 are respectively coupled to 200921322

Uy〇Ult&gt;3 243 yutwf. doc/p The output of the low pass filtering unit 217 and the input of the dividing unit 214. 〇

The U phase frequency detection unit τ 215 compares the phase relationship between the input signal &amp; and the feedback signal fFB, and outputs the comparison result to the low pass filtering unit 217 ′ such that the low pass filtering unit 217 generates a proportional phase difference. The DC control voltage vcom is output to the voltage-controlled oscillating unit 216, wherein the input signal center is generated by the frequency dividing unit 213 as the reference clock signal fREB, and the feedback signal fFB is generated by the frequency dividing unit 214 for the output signal fout ( Details later). The voltage-controlled oscillating unit 216 is coupled to the phase frequency detecting unit S215 via the low-pass filtering unit 217, and generates or adjusts the frequency of the output signal ^ according to the DC control voltage V_ outputted by the low-pass filter and wave unit 217. In this embodiment, the frequency dividing factor of the frequency dividing unit 213 is, for example, M1, and the power dividing factor of the frequency dividing unit 214 is, for example, N1, wherein the dividing frequency unit 214 is received by the factor m, N1, and the reference clock signal is respectively received.佗唬fDut, the two are subjected to frequency division processing to generate an input signal heart and a feedback signal fFB. When the system is in a steady state, the frequency of the phase frequency detecting unit 215 is the same, that is, WMi=f(10)/ni. Because 'only need to pass the system management bus (_ 咖 面 (6), face) frequency unit 213, 214 division factor Ni Ni, you can determine the output frequency, that is, the output signal KNl / Ml) fREF. Single_• can be processed according to its needs, materialized processing or non-materialized processing to generate the clock signal CLK1 of the same rate, wherein the factor P1 is a positive integer. Secondly, the pulse generator 220 can also be used for circuit operation. Therefore, in the clock generator 21, the phase frequency detecting unit 215, 200921322 υνουιο^ ^yutwf.doc/ρ low-pass filter unit 217, voltage control (four) unit 214, and fresh element 2ΐ4 are formed. -_路电路. When the secret is difficult, this output signal. Same as the wheel signal fin Step, so that the two are resolved = the same, therefore, the reference clock signal fREF is delayed by the signal generated by the frequency division unit, or the output signal is delayed by the signal generated by the axis unit 212, and cannot be used. If the clock signal clki generated by the clock generator 21〇 is not processed, it is used as the clock generator, and the input signal, (4) pulse signal clki may not meet the input of the clock generator 22G. It is required, for example, that the clock signal CLK1 is 200 megahertz (Mega Hz), and the input of the clock generator 220 is required to be 1 〇〇 10,000 Hz. Furthermore, since the clock generation 220 and the clock generator 21 The operating clock phase @, the clock generator CLK2 generated by the clock generator is also due to the problem of the Weiming (4), and the clock signal CLK1 from time to time. Therefore, the embodiment_clock synchronization device 230 will be the clock. The signal CLK2 is synchronized with the clock signal CLK1. FIG. 2C is a schematic diagram of the clock synchronization device of FIG. 2A according to an embodiment of the present invention. [Please refer to FIG. 2A and FIG. 2C, the clock synchronization device 23 includes delay locking. Loop (dday_i〇cked i〇op, DLL) 24〇 and phase lock The circuit (PhaSe-l〇cked l00p, PLL) 25〇. The delay lock loop 24〇 receives the clock signal CLK1 and the pulse signal CLK2, which generates a reference signal &amp; according to the phase relationship between the two, thereby compensating the clock generator The phase skew caused by the coupling of 210 and 220. The phase-locked loop 25〇 is coupled to the delay-locked loop 240' to receive the reference signal &amp; and the phase-locked loop 200921322 0960163 24390twf.d〇c/ as shown in FIG. 2B above. The reference signal f2 is generated by the operation of p, and is fed back to the input of the clock generator 220 with the reference signal 6. 2D illustrates the intent of the delay locked loop 240 of FIG. 2C in accordance with an embodiment of the present invention. Referring to FIG. 2C and FIG. 2D, the delay lock loop 240 includes a phase detecting unit 241, a delay unit 242, and a low pass filtering unit 243. The phase price measuring unit 241 is coupled to the clock generators 210 and 220, which compares the phase relationship between the clock signal CLK1 and the pulse signal Clk2, and outputs a detection signal D, wherein the detection signal D1 is the clock signal CLK1 and the pulse. The phase difference of the signal CLK2. The low pass; the wave early element 243 is connected between the phase detecting unit 241 and the delay unit 242 for low-pass filtering the detection signal D1 and transmitting it to the delay unit 242. At this time, the delay unit 242 is controlled by the detection signal D1 to delay the day sigma g_CLK1 and generate a reference signal &amp; In the present embodiment, the delay lock loop 240 functions to phase lock the ϋ reference signal 6 and the clock signal CLK2 in a delay manner according to the phase difference between the pulse signal CLK1 and the clock signal CLK2. The internal components of the phase-locked loop 250 are the same as the phase-locked loops 2ΐ of the above-mentioned FIG. 2β, so the operation of the phase-locked loop 25〇 will be described with the same reference numerals. Referring to Fig. 2B, the phase locked loop 250 includes frequency dividing units 213 to 214, a phase detecting unit 215, a low pass wave unit 217, and a hard current unit 2ΐ6. The frequency dividing unit commits the reading end to receive the reference money fi. For example, the phase-locked loop is called the operation description, and the output end of the voltage-controlled vibrating element 216 generates f2, wherein the reference signal f2 is fed back to the phase measuring unit 215 via the frequency dividing unit 214. Its one input. The shell hand is called 200921322 0960163 243y〇twf.d〇c/p Since the clock synchronization device 230 is connected to different clock generators = 〇, 220, its input and output must accept any - non-fixed frequency range f: therefore The phase-locked loop 25G is programmed by the system management bus to eliminate the frequency of the single-segment = 213, 214, respectively, the factor M2, N2, so that the clock synchronization device can receive and output any-frequency_, and then make the reference signal &amp; The input requirements of the clock generator 220 can be met, wherein the factors M2 and N2 are positive integers. Ο

According to the closed-loop phase-locked loop principle, when the system is in steady state, the reference signal &amp; of the phase-locked loop 250 is synchronized with the input sequence fin generated by the frequency-dividing unit, wherein the reference signal fi is the locked loop 240. L is obtained from the late sequel to the clki, to adjust the signal delay caused by the frequency division units 212, 213 in the clock generator. The clock synchronization device 230 and the clock generator 22 of the embodiment also form a closed loop circuit.

When the system is in steady state, the input source of the clock generator 22 is equal to the reference money f2 of the wheel a of the clock synchronization device I', so that the clock money CLK2 can be the same as the clock signal cua. In addition, please continue to refer to FIG. 2β. In another embodiment of the present invention, the phase-locked loop 25G may further include a frequency dividing unit 212 having a division of positive integers=P2. At this time, the internal component_relation of the phase-locked loop 250 is different from the phase-locked phase in that the round-trip terminal of the voltage-controlled oscillating unit 216 is only the input terminal of the frequency=212 and generates an oscillating signal to the frequency-dividing unit 212. Into the end. Moreover, the output end of the frequency dividing unit 212 is connected to the input end of the frequency dividing unit 214. The impurity removal processing and the non-programming processing factor are divided by the factor P2, and the vibration value is f; For 12 oo 200921322 WOUiOJ ^4jy〇twf.d〇c/p

Hi then detects the input of the early 7G 215 from the feed to the phase frequency via the decode unit 214. n f is - the assumption that the 'hybrid tree' is assumed to be two different clocks: the provided clock is a step, but the general knowledge in the art is applied to other ranges. For example, the problem that the outputs of the plurality of sets of buffers in the integrated circuit are not synchronized can also be bridged by the clock synchronization apparatus of the embodiment of the present invention to achieve the result of multiple sets of buffer synchronization. "Study from the above several embodiments, which can be referred to as the following method 3 It 7F - The clock synchronization method of the embodiment of the present invention. Please refer to FIG. 3, first, receive the clock signal CLK1 and The clock signal CLK2 (step S301). Next, as described in the delay lock loop, the phase difference between the clock signal CLK1 and the clock signal CLK2 is detected to generate the detection signal D1 (step S3〇2), and according to the detection signal m delays the phase of the clock signal CLK1 to generate the reference signal f] (step S3〇3). / In addition, as explained by the phase-locked loop 250, the debt measurement input signal ^ and the return pure number fFB _ difference 'domain city The reference signal &amp; (step 4), wherein the input signal f〗 n and the feedback signal fFB are obtained by dividing the reference signal f! and the reference signal 4, respectively. Finally, the reference signal is generated according to the reference signal The clock synchronization device 23 of the embodiment of the present invention bridges the two clock generators 210, 220, which are respectively provided by the clock signal CLK1 synchronized with the clock signal CLK1 (step S305). The relationship between the phase signals CLiU and CLK2' will be the clock signal CLK1 Synchronized place 13 200921322 uyouiaj ^yutwf.d〇c/p After the clock is generated as the clock source! I 22G is the source of the input. The phase loop will use the lock clock in the clock signal CLK step w CLK2tnm: slant The circuit is locked late to lock the phase of the two. Thus - the result of the frequency and phase locking is achieved by the monthly b. The clock synchronization device of the time is not only the application of an independent oo phase, but also the bridge circuit between The same problem can be solved by the problem that the money of multiple locks in the clock generator is not synchronized, or the problem that multiple numbers of f ϊ1 are not synchronized in the integrated circuit can be solved. In addition, the same: 奘ί needs When multiple sets of the same clock signal are used, it is also possible to use the current pulse to bridge each of the two clock generators in series, so that the clock signals of the seven and the evening groups can be simultaneously extracted. ρρ The present invention has been improved. The disclosure is as above, but it is not intended to be used in the present invention, and any one of ordinary skill in the art may, in the spirit and scope of the present invention, be able to make some modifications and refinements. Depending on the application of the _ _ _ _ _ 1 is a schematic diagram of a clock generator. FIG. 2 is a schematic diagram of a clock generation apparatus according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a clock generator of FIG. FIG. 2D is a schematic diagram of a delay locked loop in FIG. 2C according to an embodiment of the present invention. FIG. 3 illustrates one embodiment of the present invention. Flowchart of the clock synchronization method of the embodiment. [Description of main component symbols] fcom, f〇ut, [D1, fD2, [FB, f〇·signal fR, fkjEF. Reference clock glitch, f2: reference signal D1: detection signal CLK CLK2: clock signal 100, 130, 210, 220: clock generator 111, 112: frequency divider 120, 211, 250: phase-locked loop 140: quartz oscillator 200: clock generation device 212 to 214: frequency division unit 215: phase frequency detection unit 216: voltage control oscillation unit 217, 243: low-pass filter unit 230: clock synchronization device 240: delay lock loop 241: phase detection unit 242: delay unit S301 -S303: clock synchronization method according to an embodiment of the present invention Step 15

Claims (1)

200921322 υνουιο^ ^^vutwf.doc/p X. Applying for a patent: 1·, the clock synchronization device - the second clock generator, the day-to-day generation of the pulse signal, the day _ step device includes 1 - spray And a second signal, f receives the relationship between the first clock signal and the second clock and the B-bit to generate a first reference signal; the test signal lock loop 'to receive the first-parameter The test s#u is given to the second clock generator, and its number meets the input requirement of the second clock generation 11. The delay (four) 1 Lai Shi Shizaki device, wherein the detecting unit compares the relationship between the first clock signal and the second clock tiger = phase and generates a first detection signal; and 0 a sooner or later S 'transmission The phase side unit is connected to the (fourth) first-clock pulse to delay the first-clock signal by the number detection signal, and the delay time is as described in the second time item of the second time item, wherein... a brother-low pass a unit, the phase gamma unit and the delay delay=the first detection signal is subjected to a low-pass wave processing, and the clock of the lock range is set to be in the first step, wherein 16 200921322 0960163 243yUtwf.d〇c/p The phase between the reference signals =::: the first: the reference signal and the second one is a second detection signal; and the second detection; f;,: = is connected to the phase frequency detecting unit, receiving the finding The second detecting the clock synchronization device described in item 4 of the lock range, wherein the oscillation is controlled: the element is coupled to the phase frequency detecting unit and the pressure is pressed, and ====: The detection signal is low-locked: the clock synchronization device described in the fourth item, wherein the signal consumption The voltage-controlled oscillating unit receives the oscillating test signal, and _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The detecting unit is configured to: "u" remove the test" and (4) to the phase frequency to measure the phase-synchronization device described in item 4 of the phase-locked range, wherein the letter, the object I 丨»» In the 'frequency unit' facet between the voltage-controlled oscillations -rt ^, _ two reference letters i:== 17 200921322 uy ου i bi ζ^ό y Otwf. d〇c/p feedback to the phase frequency detection The measuring unit 9. The first unit includes a seeding day pulse generating device, configured to generate a plurality of synchronization time-sending signals, generate a clock signal in the first clock, and generate a first second according to a reference clock signal The clock generator is based on a first sigmoid clock signal; and the % sign 'generates the Ο rr 产 taste: the device' • the first time - the clock generates 11 and the second time, the generation, the reception - the clock The signal and the two-clock signal are based on the phase _ between the two, and the signal is detected. 1 mate tongshen 1 = as described in item 9 of the scope of patent 4, the clock synchronization device comprises: a garment directly in a circuit, receiving the first clock signal and the second clock based on the second The phase of the phase is generated - the second reference signal. The test:; phase back: 'connect the delay lock loop' to receive iii Bean II as claimed in the first scope. The timepiece production referred to in the item=, wherein the delay lock loop comprises: ο之Π!贞醉元' tastes the first-time record and the second phase of the slave phase _, and produces - the first check Difficult number; and π ^ early 70 ' lack of the phase side unit, connected to the _th-clock and generate the second reference signal. * f pulse Wu' 18 200921322 uyouiojs z^jyutwf.doc/p The clock generation device described in the U item, the unit: unit and the delay output to the (four) unit. Incorporating the low-collar wave processing, and the clock generating device described in the 1st item of the coffee, the O-phase frequency dog detecting unit compares the phase relationship between the first and the cup number _ Mai Khao signal' And generating a second detection 'number: to; the first-detection 荡 元 , coupled to the phase frequency detecting unit, receiving the == whole: the mH1111 帛 13 lying in the position of the occupational device, its control oscillation Ϊ :Ϊ: Filter the phase two frequency detection unit and the pressure, and rotate to the voltage control oscillation $元&quot;; perform the low-pass chopping at the clock generation device of the '13 item, the signal 1:: 1 The single-turn 1 is coupled to the voltage-controlled oscillation unit, and receives the oscillation test b number. °&quot;Zhenhongcheng performs frequency division processing, and generates the rotation device described in the first reference in the first item f13, which is 200921322 υνου 103 ^ ^ vOtwf.doc/p a second frequency division unit, phase. — The second reference signal enters the wheel = early, to use the unit. From the out to the § hai phase frequency detection in the device, the Ο: the third frequency division unit, connected between the voltage control _ early yuan, used to the first reference mark = two: The frequency is fed back to the phase frequency detecting unit. Α 频 处理 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The pulse signal 'the clock synchronization method described in Item 18 of the middle production range, the step of generating the first reference signal, comprising the steps of: detecting the first clock signal and the second clock signal a phase difference to generate a first detection signal; performing a low pass filtering process on the first detection signal; and delaying a phase of the first clock signal according to the first detection signal to generate a first reference signal, and The first reference signal is generated according to the second reference signal. The clock synchronization method of claim 19, wherein the step of generating the reference/reference signal according to the reference signal comprises 20 200921322 Uyouio^ z^+^yutwf.doc/p The following steps: dividing the frequency of the second reference signal by Μ, and generating a first input signal, where Μ is a positive integer; detecting the first input signal and one time Signal a phase difference is generated to generate a second detection signal; the second detection signal is subjected to low-pass filtering processing; and an oscillation signal is generated according to the second detection signal to adjust a phase of the first reference signal.