200929494 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種用於半導體裝置之導線架，特別 疋有關於包含多個裸露之焊替(exposed pa(j)之導線架封裝 友其製造方法。 ❹【先前技術】 先别技術之半導體晶粒（die)係裹覆（enclose)於塑料封 裝中，塑料封裝提供針對惡劣環境的防護，並且啓用半導 體晶粒與基座（substrate)之間的電性互連，例如，基座為印 刷電路板(Printed CircuitBoard，以下簡稱為PCB)。這樣的 積體電路封裝包含金屬導線架，半導體晶粒與連接線卬⑽廿 wire)。半導體晶粒安裝於導線架之單一晶粒座上，並且連 Q 接線將半導體晶粒上的連接塾(bond pad)電性轉接至導線 架之單獨的導腳。最後，導線架與半導體晶粒係封裝於模 製材料(molding compound)中。 後端封裝産業（back-end packaging industry)之技術趨 勢能夠總結為“更小空間中的更多功能”。積體電路晶片 (chip)之功能變得越來越複雜，使得導線架封裝之外部連接 針腳(pin)的數量增加。隨着針腳數量的增加，封褒各晶粒 的成本相應增加。為避免由於連接針腳或者導腳數目增多 200929494 而引起的所不希望之封裝大小的增加，可以採用降低導腳 間距(lead pitch)的方法。然而，縮減導腳間距會導致由封 裝之導腳産生之互感（mutual inductance)與互容（mutual capacitance)水平的提高。因為相對較高之電感與電容可能 干擾所傳輸的訊號，所以一般認為導線架封裝並不適用於 以高速來傳輸訊號的高速半導體晶粒。200929494 VI. Description of the Invention: [Technical Field] The present invention relates to a lead frame for a semiconductor device, and particularly to a lead frame package including a plurality of exposed solder joints (exposed pa(j) Manufacturing Method ❹ [Prior Art] Prior art semiconductor die is enclosed in a plastic package that provides protection against harsh environments and enables semiconductor die and substrate The electrical interconnection, for example, the pedestal is a printed circuit board (PCB). Such an integrated circuit package includes a metal lead frame, a semiconductor die and a connection line (10). The semiconductor die is mounted on a single die pad of the leadframe, and the Q-junction electrically connects the bond pads on the semiconductor die to the individual leads of the leadframe. Finally, the leadframe and the semiconductor die are encapsulated in a molding compound. The technological trends of the back-end packaging industry can be summarized as "more features in smaller spaces." The function of integrated circuit chips has become more and more complicated, resulting in an increase in the number of external connection pins of the lead frame package. As the number of pins increases, the cost of sealing each die increases accordingly. In order to avoid an increase in the undesired package size caused by the increase in the number of connection pins or pins 200929494, a method of reducing the lead pitch can be employed. However, reducing the pitch of the leads results in an increase in the level of mutual inductance and mutual capacitance produced by the lead pins of the package. Because relatively high inductances and capacitances can interfere with the transmitted signal, it is generally believed that the leadframe package is not suitable for high speed semiconductor dies that transmit signals at high speeds.
❹ 考慮到上述問題，一般地，許多配備能夠傳輸高頻訊 號之半導體晶粒的行動通訊裝置（例如行動電話）與個人通 訊裝置係採用適應此種半導體晶粒之球柵陣列（Ball Grid Array ’以下簡稱為BGA)封裝。假若上述半導體晶粒係安 裝或者封裝於導線架封裝中，則會産生明顯的訊號損失或 者雜訊問題’例如交流雜訊(AC noise)問題。 然而，BGA封裝之缺陷在於，相較於導線架封裝，BGA 封裝較貴’並且BGA封裝之産品轉返時間 (Tum-Around-Time，以下簡稱為TAT)較長。此外，發展射 頻系統晶片（Radio-Frequency System-〇n_chip，RF-SoC)之 挑戰在於.難以降低射頻與類比電路之功率消耗，並且難 以降低被動元件以及類比電晶體之大小。 因此，業界亟需改進之導線架結構以及導線架封裝， 以具有成本效益，並且特別適用於高速半導體晶粒，以及 當傳輸高頻訊號時，能夠降低訊號損失或者雜訊。 【發明内容】 200929494❹ In view of the above problems, in general, many mobile communication devices (such as mobile phones) and personal communication devices equipped with semiconductor dies capable of transmitting high-frequency signals adopt a ball grid array (Ball Grid Array ' adapted to such semiconductor dies. Hereinafter referred to as BGA) package. If the semiconductor die is mounted or packaged in a leadframe package, significant signal loss or noise problems such as AC noise can occur. However, the drawback of the BGA package is that the BGA package is more expensive than the lead frame package and the Tum-Around-Time (hereinafter referred to as TAT) is longer. In addition, the challenge of developing a Radio-Frequency System-〇n_chip (RF-SoC) is that it is difficult to reduce the power consumption of the RF and analog circuits, and it is difficult to reduce the size of passive components and analog transistors. Therefore, there is an urgent need for an improved leadframe structure and leadframe package that is cost effective and particularly suitable for use in high speed semiconductor dies and to reduce signal loss or noise when transmitting high frequency signals. [Abstract content] 200929494
V 為解决上述傳輸高頻訊號時，導線架及導線架 生^或者訊號損失的問題，本發明提出—種導線架與 線架封裝’能夠降低訊號損失或者雜訊。 、 本發明提供—種導線架封裝，包含晶粒座、半導體晶 粒導腳帛一與第二裸露焊塾部分、導線以及模製材料。 半=體晶粒_於晶粒座。導腳沿着晶粒座之四個外圍邊 緣又f帛一裸露焊墊部分設置於導腳與晶粒座之間。第 ❹二裸料墊部分料―減料部分分關，並且設置於 第一稞露焊塾部分與晶粒座之間。多條導線分別電性據 並且延伸至半導體晶粒與各導腳、第-裸露焊墊部分及第 -裸露焊墊部分之間^模製材料至少部分封裝晶粒座、導 第裸露焊塾部分與第二裸露焊替部分以及導線，其 中曰曰粗座、第一裸露焊墊部分與第二裸露焊塾部分之底面 未被模製材料覆蓋。 ❹ 立本發明提供一種導線架，包含晶粒座、導腳、第一焊 以及第二料部分。於晶粒座上安裝半導體晶粒。 腳係沿着晶粒座之四個外圍邊緣^置。第—料部分設 5於導腳與晶粒座之間，其t第—焊墊部分自晶粒座之外 =邊緣伸出。第二料部分與第—焊墊部分分隔開並且 第一焊墊部分設置於第-焊墊部分與晶粒座之間。 4+壯上述導線架及導線架封裝能夠藉由在導線架及導線架 、于裝中’設置於導腳與晶粒座之間的第—焊墊部分斑設置 於第一焊墊部分與晶粒座之間並且與第-焊墊部分分隔開 200929494 的第二焊墊部分，形成分開的接地系統，從而避免了雜訊， 並且減少訊號損失。 【實施方式】 後文所述之改進的導線架封裳結構所適用之應用範圍 包含’但不限定於：低高度四方扁平封裝(Lqw p福ie Quad 腕Pack ’以下簡稱為LQFP)封裝、薄型四方爲平封裝（Thin ❹Quad黯Pack，以下簡稱為TQFp)封裝、四方形扁平無導 腳(Quad Flat Non-leaded，以下簡稱為qFN )封装、雙排 爲平無導腳(Dual Flat No-lead ’以下簡稱為DFN)封裝、 多區域QFN以及多晶粒覆晶（multi_die flip chip)封裝。 本發明能夠藉由減少用於打線接合(wire b〇nd)至接地 墊(gnnmd pad)、電源墊或者封裝半導體晶粒上一些訊號墊 之導腳的數目或者使上述導腳空閑以用於其他地方，來改 進先前技術導線架封裝之效能。此外，本發明能夠藉由利 ❹用晶粒座上分開的接地系統來改進積體電路封裝之電性效 能。 苐1圖為導線架封裝1〇之頂透視圖（perspective top view)。如第1圖所示，導線架封裝10包含半導體晶粒12， 即安裝於晶粒座14上之範例半導體裝置.提供多個連接墊 13於半導體晶粒12之上表面。各連接塾13通過連接線18 電性耗接至相應導腳16。 連接墊13亦被稱為輸入/輸出墊或者I/O墊。一般地， 200929494 連接塾13包含電源墊13a、13b、13c、13d、13e與13f、 接地墊13g與13h、以及訊號墊等。電源墊13a〜13f通過連 接線18(即訊號線)與各自的導腳16a、16b、16c、16d、16e、 16f相連接。接地墊13g與13h通過連接線26與晶粒座14 相連接。 導腳16係沿着晶粒座14之四邊設置。導腳16最後係 安裝於PCB之插座（socket)上。半導體晶粒12、晶粒座14、 導腳16之内端(inner end)與連接線18封裝於模製材料 (molding compound)20 中。 本範例中，晶粒座14為單一的矩形平面區域，包含四 個自晶粒座Η之四角向外延伸的細支桿（supp〇rdng bar)15。但是’ s青注意，其他形狀的晶粒座，例如沒有四 個細支桿之晶粒座，亦可應用於本發明。晶粒座14之底面 (圖未示)雜意縣於封裝體巾，散半導體晶粒以斤 産生之熱量，it亦稱為裸露晶粒座(Exp〇seddiepad，以下 簡稱為E-pad)配置結構。一船祕，曰^r产t / , 何 力又地，日日粒座14之稞露底面係 電性耦接至PCB之接地層。 、-些系統晶片應用中，半導體晶粒12包含類比/數位 一電路並且i夠傳輸高頻訊號。然而，由於數位接地 雜訊會對類比訊號路徑產生不利影響，這些系統晶片期 在力地吆。 〜 請參閱第2圖盥箪吐〜 ' 圖。第2圖為根據本發明一實施 例之導線架封裝l〇a的伯泳彳日m # 的頂透視圖。第3圖為導線架封裝1〇a 200929494 沿A-A方向之剖面示意圖。本發明之附圖中，相同的教〜 標號代表相似之元件、區域或者層。 如第2圖與第3圖所示，導線架封裝10a包含安巢& 晶粒座14之上的半導體晶粒12。晶粒座14為銅或者麵人 金’例如標號為C7025、A192的銅合金。相似的，提供夕 個連接墊13於半導體晶粒12之上表面上。一些連接塾 係通過連接線18電性耦接至相應導腳16。 ❹ 連接墊13包含電源墊13a〜13f、數位接地墊i3g與 13h、類比接地螯13i與13j、與訊號塾等。本發明之一獨 特的特性在於：電源墊13a〜13f通過較短的連接線28與分 離之焊塾部分14a相連接，而非與導腳i6a〜16f相連接。 由此’能夠將原來與各自之電源墊13a〜13f相連接之導腳 16a〜16f節省下來，用於其他用途，例如，耦接於半導體晶 粒12上的其他訊號塾，或者僅省略導卿i6a〜I6f以減少導 腳數目，從而降低導線架封裝l〇a之大小與成本。 ❹ 從一方面看，導線架封裝l〇a之效能可藉由省略導腳 16a〜16f而得以提高，其中導腳16a〜16f原來用於耦接半導 體晶粒12上的電源墊13a〜13f。這是因為導腳間距得以增 加，亦因為晶粒與PCB之間的訊號傳輸路徑變得更短。 本發明之另一獨特的特性在於：自晶粒座14分割的分 離之焊墊部分（separate pad segment)14a未與晶粒座Μ直 接接觸，並且完全與晶粒座14隔離。此外，分離之焊墊部 刀14a未與任何導腳16直接接觸，或者由任何導腳Μ支 200929494 9 援。因此分離之焊墊部分14a未佔用任何導腳16。相似於 曰日粒座14,分離之焊墊部分14a之底面亦裸露於封裝體 中，以使得分離之焊墊部分14a能夠電性耦接至pCB之電 源層，電源層例如為雙倍資料速率（D〇ub丨eDataRate，以下 簡稱為DDR)電源層，用以提供電源訊號至半導體晶粒12。 本發明之又一特性在於：半導體晶粒12上的數位接地 墊13g與13h通過連接線26與晶粒座14相連接，並且半 ❹導體晶粒U上的類比接地墊i3i與13j通過連接線36與分 離之焊塾部分14b相連接。 根據本發明，晶粒座14耦接於數位接地訊號，而分離 之焊墊部分14b搞接於類比接地訊號。這種晶粒座上的分 離接地系統能夠防止數位電路雜訊影響類比訊號路徑。此 外，類比接地塾13i與13j接地，並且打線接合至分離之焊 整部分1仆’意味著此實施例之訊號傳輸路徑較通過導腳 16之訊號傳輸路徑更短。 ❹ 相似的，自晶粒座14分割的分離之焊墊部分14b未與 日日粒座14直接接觸，並且完全與晶粒i 隔離。 如第3圖所示，與分離之烊墊部分丨扣相似，分離之 焊塾部分Mb未與任何導腳16直接接觸。更明確的說，分 離之焊塾部分14b不需要任何來自導腳16或者晶粒座 之結構支援。分離之焊墊部分14a與晶粒座14之間的縫隙 =a以及分離之焊墊部》i 4 b與晶粒座i 4之間的縫隙她 皆填充環氧樹脂(epoxy)模製材料2〇。 200929494 上的多個部分可分為_，即Μ 係分離主要部分與:U彳八。^ ”。分離部分 _ …要二=:::= =:自，粒座14之主要部分分離次要部分(例:分 離之焊墊部分14a與14b)。 刀 ❹ 分離之痒墊部分14b之底面裸露於封袭體中，以使得 勿離之焊塾部分14b能夠電性輕接於pcB之類比接地層。 曰曰粒座Μ之裸露底面_於數位接地層。如前所述，這種 晶粒座上的分離接地系統能_錢位電路雜訊影響類比 訊號路徑。 第4圖為根據本發明導線架封裝1〇a之分離之焊墊部 分14b與圍繞分離之焊墊部分14b之縫隙4%沿b b方= 之放大剖面示意圖。如第4圖所示’電鍍責金屬(細d noble metal)層52a(例如，貴金屬為金、銀、鈀、鉑、銥、 鍊、釕、餓、鎳銀、鎳金或其組合物）係設置於晶粒座14 與分離之焊墊部分14b之模製的上面（upper side)(晶粒面） 上。晶粒座14與分離之焊墊部分i4b之裸露底面（PCB面） 皆塗有貴金屬層52b。被動元件60可跨越縫隙40b，安裝 於晶粒座14與分離之焊墊部分14b之間，用於去耦、靜電 釋放（electrostatic discharge)或者其他特定電路（例如過渡 或匹配）之設計目的。 本發明之另一特性在於：縫隙40b(或者縫隙40a)包含 11 200929494 反向τ形剖面。環氧樹脂模製材料2〇填充反向τ形縫隙 40b，由此改善導線架主體之可靠度及變形程度。由於反向 T形縫隙40b，注入的模製材料2〇能夠將懸浮之分離之焊 墊部分14b牢固地保持在其位置上。 第5圖為縫隙40b(或者40a)的變形例。如第5圖所示， 沙漏狀縫隙40b包含位於模製的上面或者晶粒面上的梯形 之上面部分。第6圖為縫隙40b(或者40a)的另一變形例。 ❹如第6圖所示，分離之焊墊部分14b包含類似鋸齒形邊緣 7〇。這提高了分離之焊墊部分14b與填充於縫隙4〇b中之 模製材料20之間的粘附程度。 第7圖為根據本發明之晶粒座14以及晶粒座丨4上之 範例電感部分82與84的示意圖。迂回形的電感部分82 與螺旋狀的電感部分84與導線架之晶粒座形成一整體，其 中迂回的電感部分82與螺旋狀的電感部分料能夠用於形 ❹成墊上電感（〇n-pad inductor)»迂回形的電感部分82與螺 旋狀的電感部分8 4未與晶粒座14直接接觸。更明確地說，' 電感部分82與84不需要任何來自導腳μ或者晶粒座14 之結構支援。 環氧樹脂模製材料被填充至迂回形的電感部分82與 晶粒座14之間的縫隙82a内’並且被填充至螺旋二的電感 部分84與晶粒座η之間的縫隙84a内。鲦险Λ 硬隙82a與84a 可包含如第4圖所示的反向T形剖面。 因為電感部分82與84未與任何導腳16耦接，電感部 12 200929494 分82與84的電感具有高品質因數(quality Q fact〇r)，減小 的寄生電容以及較低的共振頻率。 Ο ❹ 第8圖為根據本發明之包含多個裸露之焊墊的導線架 封裝之製造過程的流程示意圖。從一方面，本發明之導線 木可利用一卩6餘刻法製造。也就是說，於第一階段1 〇〇期 間，由導線架製造群組對晶粒座進行第一半蝕刻（first half-etched)(如標號102所示之晶粒座上第一姓刻之步 驟），亦稱為“初步蝕刻”。並且，於完成封裝模製之後， 第二階段200期間，由後續裝配車間對晶粒座進行第二半 蝕刻（如標號202所示之第二蝕刻之步驟），亦稱為“分離 蝕刻。如第8圖所示，除去步驟“背面標記’，、“移除 背面標記”以及“模製”之後的“餘刻”之外，可以使用 先前技術導線架封裝的裝配程序。“背面標記，，為將工藝 圖（artwork)或者光致抗钱劑（ph〇t〇resist)列印於底部金屬之 連接杯上以達成防止電鑛（plating resistant)之目的。於 除去連接桿之外的封裝被電賴或者貴金屬之後，包含裸 露導線架之模製封裝得到保護，並且能夠防腐#。接著， 移除連接桿底面之:^藝圖或者光致抗㈣。連接桿於光化 子（ph〇t〇chemical)機器中被餘刻掉，並且各裸露之焊塾 、，邑緣的帛一半餘刻將分離之焊塾部分14a與咐自主晶 ;座4上;^並且分隔開。或者，可利用鑽孔 咖雕刻_對連接桿進行或者關。 請參閱第9圖、第10圖、第㈣、第12圖與第η 13 200929494 圖，並且請同時參閱第8圖。第9圖-第13圖為根據本發 明之於使用二階蝕刻法製造導線架封裝期間，中間步驟中 導線架封裝剖面示意圖。請注意’出於簡潔的目的，第9 圖-第13圖省略了一些元件或者層（layer)。如第9圖所示， 蝕刻（或者壓印）及電鍍之後，得到導線架300。導線架3〇〇 包含早一晶粒座314與週邊導腳316。晶粒座314之兩面 皆塗有餘刻膜322 ’例如貴金屬、金屬合金或者光致抗触 ❹劑。餘刻膜322包含缝隙孔324。縫隙孔324設定待轉變 為基本晶粒座314之獨立（isolated)焊墊式樣350。 如第10圖所示’於晶粒面上執行第一半蝕刻程序，以 通過蝕刻膜322之縫隙孔來蝕刻預定厚度之晶粒座314。 如别所述’第一半钮刻程序能夠於導線架製造群組中完 成。接著，運送半蝕刻後的導線架300至裝配車間。 如第11圖所示，裝配車間中，將半導體晶粒312粘附 於晶粒座314上。提供連接線318與336，以形成連接墊 ® 313與導腳316之間的電性連接以及半導體晶粒312上的 連接墊313與晶粒座314之間的電性連接。 如第12圖所示，於打線接合之後，使用熱硬化性材料 (thermosetting C〇mpOund)320模製第11圖所示的全部裝配 元件。熱硬化性材料可為低溫硬化樹脂。隨後，對模製封 裝進行加工程序（curing process)。如特別指出的，模製封 裝之底面或者PCB面係裸露的。In order to solve the problem of the lead frame and the lead frame being damaged or the signal loss when the high frequency signal is transmitted, the present invention proposes that the lead frame and the wire frame package can reduce signal loss or noise. The present invention provides a leadframe package comprising a die pad, a semiconductor wafer pin and a second bare pad portion, a wire, and a molding material. Half = body grain _ in the die pad. The lead pins are disposed between the lead pins and the die pad along the four peripheral edges of the die pad and the exposed pad portion. The second part of the bare pad is divided into a material-reducing part, and is disposed between the first dew-welding portion and the die holder. The plurality of wires are respectively electrically extended and extend between the semiconductor die and each of the lead pins, the first exposed pad portion and the first exposed pad portion. The molding material at least partially encapsulates the die pad and the exposed bare pad portion And the second bare soldering portion and the wire, wherein the bottom surface of the thickened seat, the first bare pad portion and the second bare solder portion are not covered by the molding material. The present invention provides a lead frame comprising a die pad, a lead leg, a first weld, and a second material portion. A semiconductor die is mounted on the die pad. The foot is placed along the four peripheral edges of the die pad. The first material portion is disposed between the lead pin and the die pad, and the t-pad portion protrudes from the outer edge of the die pad. The second material portion is spaced apart from the first pad portion and the first pad portion is disposed between the first pad portion and the die pad. The above-mentioned lead frame and lead frame package can be disposed on the first pad portion and the crystal by the first pad portion disposed between the lead frame and the lead frame in the lead frame and the lead frame. The second pad portion of the 200929494 is separated from the pad and spaced apart from the first pad portion to form a separate grounding system, thereby avoiding noise and reducing signal loss. [Embodiment] The application range of the improved lead frame sealing structure described later includes 'but is not limited to: low-height quad flat package (LQw pie Quad Bike Pack 'LQFP) package, thin type The square is a flat package (Thin ❹Quad黯Pack, hereinafter referred to as TQFp) package, Quad Flat Non-leaded (hereinafter referred to as qFN) package, double row is flat without lead (Dual Flat No-lead) 'hereinafter referred to as DFN) package, multi-region QFN, and multi-die flip chip package. The present invention can reduce the number of leads used for wire mats to the ground pad (gnnmd pad), the power pad or package some of the signal pads on the semiconductor die or idle the pin for other Where to improve the performance of prior art leadframe packages. Moreover, the present invention is capable of improving the electrical performance of an integrated circuit package by utilizing a separate grounding system on the die pad. The 苐 1 picture shows the perspective top view of the lead frame package. As shown in Fig. 1, the leadframe package 10 includes a semiconductor die 12, i.e., an exemplary semiconductor device mounted on a die paddle 14. A plurality of bond pads 13 are provided on the upper surface of the semiconductor die 12. Each of the ports 13 is electrically connected to the corresponding lead 16 via a connecting wire 18. The connection pad 13 is also referred to as an input/output pad or an I/O pad. In general, the 200929494 port 13 includes power pads 13a, 13b, 13c, 13d, 13e, and 13f, ground pads 13g and 13h, and a signal pad. The power pads 13a to 13f are connected to the respective lead pins 16a, 16b, 16c, 16d, 16e, 16f via a connecting wire 18 (i.e., a signal line). The ground pads 13g and 13h are connected to the die pad 14 via a connecting wire 26. The lead pins 16 are disposed along the four sides of the die pad 14. The lead 16 is finally mounted on a socket of the PCB. The semiconductor die 12, the die pad 14, the inner end of the lead 16 and the connecting wire 18 are encapsulated in a molding compound 20. In this example, the die pad 14 is a single rectangular planar region containing four thin struts 15 extending outward from the four corners of the die pad. However, it is noted that other shaped die holders, such as die holders without four thin struts, can also be used in the present invention. The bottom surface of the die pad 14 (not shown) is in the package body towel, and the heat generated by the semiconductor die is jin, which is also called the exposed die pad (Exp〇seddiepad, hereinafter referred to as E-pad) configuration. structure. A ship secret, 曰^r produced t /, and the force is again, the surface of the granules 14 is electrically coupled to the ground plane of the PCB. In some system wafer applications, the semiconductor die 12 includes an analog/digital circuit and is capable of transmitting high frequency signals. However, since digital grounded noise can adversely affect the analog signal path, these system chips are constantly embarrassing. ~ Please refer to Figure 2 盥箪 〜 ~ 'Figure. Fig. 2 is a top perspective view of a bobbin day m# of a lead frame package 10a according to an embodiment of the present invention. Figure 3 is a cross-sectional view of the lead frame package 1〇a 200929494 along the A-A direction. In the drawings of the present invention, the same reference numerals are used to refer to the similar elements, regions or layers. As shown in FIGS. 2 and 3, the leadframe package 10a includes semiconductor die 12 over the nest & die pad 14. The die pad 14 is made of copper or a face gold, such as a copper alloy designated C7025, A192. Similarly, a mat 13 is provided on the upper surface of the semiconductor die 12. Some of the connections are electrically coupled to the respective leads 16 via the connecting wires 18. ❹ The connection pad 13 includes power pads 13a to 13f, digital ground pads i3g and 13h, analog ground pins 13i and 13j, and signal 塾. A unique feature of one of the present invention is that the power pads 13a to 13f are connected to the separated pad portion 14a by a short connecting wire 28 instead of the pins i6a to 16f. Thus, the leads 16a to 16f which are originally connected to the respective power pads 13a to 13f can be saved for other purposes, for example, other signals coupled to the semiconductor die 12, or only the guide is omitted. I6a~I6f reduce the number of leads, thereby reducing the size and cost of the lead frame package l〇a. ❹ On the one hand, the performance of the lead frame package 10a can be improved by omitting the lead pins 16a to 16f, wherein the lead pins 16a to 16f are originally used to couple the power pads 13a to 13f on the semiconductor die 12. This is because the pitch of the leads is increased and because the signal transmission path between the die and the PCB becomes shorter. Another unique feature of the present invention is that the separate pad segment 14a split from the die pad 14 is not in direct contact with the die pad and is completely isolated from the die pad 14. In addition, the separate pad portion cutter 14a is not in direct contact with any of the guide pins 16, or is supported by any of the guide legs. Therefore, the separated pad portion 14a does not occupy any of the lead pins 16. Similar to the crucible 14, the bottom surface of the separated pad portion 14a is also exposed in the package, so that the separated pad portion 14a can be electrically coupled to the power layer of the pCB, for example, a double data rate. A power layer (D〇ub丨eDataRate, hereinafter abbreviated as DDR) is used to supply power signals to the semiconductor die 12. Yet another feature of the present invention is that the digital ground pads 13g and 13h on the semiconductor die 12 are connected to the die pad 14 via a connection line 26, and the analog ground pads i3i and 13j on the semiconductor conductor die U pass through the connection line. 36 is connected to the separated solder fillet portion 14b. In accordance with the present invention, the die pad 14 is coupled to the digital ground signal and the separate pad portion 14b is coupled to the analog ground signal. This separate grounding system on the die pad prevents digital circuit noise from affecting the analog signal path. In addition, the analog grounding turns 13i and 13j are grounded, and the wire bonding to the separate soldering portion 1 means that the signal transmission path of this embodiment is shorter than the signal transmission path through the pin 16. Similarly, the separate pad portion 14b split from the die pad 14 is not in direct contact with the sunroof 14 and is completely isolated from the die i. As shown in Fig. 3, the separated bead portion Mb is not in direct contact with any of the lead pins 16, similarly to the separated pad portion. More specifically, the separate solder fillet portion 14b does not require any structural support from the lead 16 or the die pad. The gap between the separated pad portion 14a and the die pad 14 = a and the gap between the separated pad portion "i 4 b and the die pad i 4 are filled with an epoxy molding material 2 Hey. The various parts of 200929494 can be divided into _, that is, the main part of the separation is: U彳八. ^". Separation part _ ...to two =:::= =: Since the main part of the granule 14 is separated from the secondary part (for example, the separated pad portions 14a and 14b). Knife 分离 Separated itch pad portion 14b The bottom surface is exposed in the sealing body so that the soldering portion 14b can be electrically connected to the grounding layer such as pcB. The bare bottom surface of the Μ Μ _ is in the digital ground layer. The separate grounding system on the die pad can affect the analog signal path. The fourth figure shows the gap between the separated pad portion 14b of the lead frame package 1A and the surrounding pad portion 14b according to the present invention. 4% along bb square = enlarged cross-sectional view. As shown in Figure 4, 'plated metal (fine d noble metal) layer 52a (for example, precious metals are gold, silver, palladium, platinum, rhodium, chain, sputum, hungry, Nickel silver, nickel gold or a combination thereof is disposed on the upper side (grain surface) of the die pad 14 and the separated pad portion 14b. The die pad 14 and the separated pad portion The exposed bottom surface (PCB surface) of i4b is coated with a precious metal layer 52b. The passive component 60 can be mounted on the die pad 14 across the slit 40b. Between the separated pad portions 14b, for the purpose of decoupling, electrostatic discharge or other specific circuits (such as transition or matching). Another feature of the present invention is that the slit 40b (or the slit 40a) comprises 11 200929494 Reverse τ-shaped profile. The epoxy molding material 2〇 is filled with the reverse τ-shaped slit 40b, thereby improving the reliability and deformation degree of the lead frame body. Due to the reverse T-shaped slit 40b, the injected molding material 2〇 The suspended pad portion 14b can be firmly held in its position. Fig. 5 is a modification of the slit 40b (or 40a). As shown in Fig. 5, the hourglass-shaped slit 40b is contained in the molded case. The upper portion of the trapezoid on the upper or the die face. Fig. 6 is another modification of the slit 40b (or 40a). As shown in Fig. 6, the separated pad portion 14b includes a zigzag-like edge 7?. This improves the degree of adhesion between the separated pad portion 14b and the molding material 20 filled in the slit 4〇b. Fig. 7 is an example of the die pad 14 and the die pad 4 according to the present invention. Schematic representation of inductive portions 82 and 84 The meandering inductive portion 82 and the helical inductive portion 84 are integral with the die pad holder, wherein the bypassed inductive portion 82 and the helical inductive portion can be used to form a pad on the inductor (〇n- The pad inductor) 82 and the spiral inductor portion 82 are not in direct contact with the die pad 14. More specifically, the inductor portions 82 and 84 do not require any lead or μ pad 14 Structural support. The epoxy molding material is filled into the gap 82a between the meandering inductive portion 82 and the die paddle 14' and is filled into the gap between the inductive portion 84 of the spiral two and the die pad n Within 84a.硬 Λ The hard slots 82a and 84a may comprise an inverted T-shaped profile as shown in FIG. Because the inductive portions 82 and 84 are not coupled to any of the leads 16, the inductance of the inductive portion 12 200929494 points 82 and 84 has a high quality factor (quality Q fact〇r), reduced parasitic capacitance, and a lower resonant frequency. ❹ ❹ Fig. 8 is a flow chart showing the manufacturing process of a lead frame package including a plurality of bare pads according to the present invention. In one aspect, the wire of the present invention can be fabricated using a one-and-a-half-step process. That is, during the first phase 1 ,, the die holder is first half-etched by the lead frame manufacturing group (as indicated by the first address in the die pad shown by reference numeral 102) Step), also known as "preliminary etching." Moreover, after the package molding is completed, during the second stage 200, the second half of the die pad is etched by the subsequent assembly shop (as shown by the second etching step indicated by reference numeral 202), also referred to as "separation etching." As shown in Fig. 8, the assembly procedure of the prior art lead frame package can be used in addition to the steps "back mark", "removal of the back mark", and "remaining" after "molding". "Back mark, in order to print the artwork or ph〇t〇resist on the connection cup of the bottom metal to achieve the purpose of preventing plating resistance. After the package is electrically insulated or precious metal, the molded package containing the exposed lead frame is protected and can be preserved. Then, the bottom surface of the connecting rod is removed: ^Art image or photo-resistance (4). In the machine (p〇t〇chemical), the machine is engraved, and each of the bare solder joints, the rim of the rim of the rim, will separate the soldered portion 14a and the 咐 autonomous crystal; the seat 4; Or, you can use the drilled coffee engraving _ to open or close the connecting rod. Please refer to Figure 9, Figure 10, (4), 12th and η 13 200929494, and please refer to Figure 8. Figure 9 - Figure 13 is a schematic cross-sectional view of the leadframe package in the intermediate step during the manufacture of the leadframe package using the second-order etching method according to the present invention. Please note that for the sake of brevity, Figure 9 - Figure 13 omits some Element or layer, as shown in Figure 9. After etching (or embossing) and electroplating, a lead frame 300 is obtained. The lead frame 3 includes an early die pad 314 and a peripheral lead leg 316. Both sides of the die paddle 314 are coated with a residual film 322 'eg precious metal, Metal alloy or photo-anti-contact agent. The residual film 322 includes slit holes 324. The slit holes 324 define an isolated pad pattern 350 to be converted into a basic die pad 314. As shown in Fig. 10 A first half etching process is performed on the grain surface to etch a predetermined thickness of the die pad 314 by etching a slit hole of the film 322. The first half buttoning process can be completed in the lead frame manufacturing group. The semi-etched leadframe 300 is transported to the assembly shop. As shown in Fig. 11, in the assembly shop, the semiconductor die 312 is adhered to the die pad 314. Connection wires 318 and 336 are provided to form the connection pad® The electrical connection between the 313 and the lead 316 and the electrical connection between the connection pad 313 on the semiconductor die 312 and the die pad 314. As shown in Fig. 12, after the wire bonding, a thermosetting material is used. (thermosetting C〇mpOund) 320 molding 11th All mounting elements shown. Thermosetting resin material may be cured at a low temperature. Subsequently, the molded package machining program (curing process). As particularly pointed out in, or the bottom surface of the PCB surface mount molded closed system exposed.
如第13圖所示，模製之後，對模製封裝之裸露pcB 200929494 面進行第二半蝕刻程序’以通過蝕刻膜322的對應縫隙孔 324來敍刻剩餘厚度之晶粒座314，由此形成自晶粒座叫 为割的分離之烊墊部分314a。分離之輝墊部分3i4a完全 與晶粒座314隔離，並且未與晶粒座314直接接觸。第二 半蝕刻程序可由雕刻機器所執行的雕刻程序所替代，雕刻 程序能夠於PCB上的雕刻圖樣(carving pattern)上執行。As shown in FIG. 13, after molding, a second half etching process is performed on the exposed pcB 200929494 side of the molded package to "etch the remaining thickness of the die pad 314 through the corresponding slit hole 324 of the etching film 322, thereby A split pad portion 314a is formed from the die pad, which is called a cut. The split glow pad portion 3i4a is completely isolated from the die pad 314 and is not in direct contact with the die pad 314. The second half of the etch process can be replaced by an engraving program performed by the engraving machine, which can be executed on a carving pattern on the PCB.
第14圖、第15圖、第16圖與第17圖為根據本發明 另了實施例之具有第4圖所示反向τ形縫隙之導線架封裝 的製造期間，t間步驟時導線架封裝的剖面示意圖。如第 Μ圖所示，蝕刻（或者壓印）及電鍍之後，得到導線架3〇〇。 導線架则包含單晶粒座3Μ與週邊導腳3心晶粒座 314之兩面皆塗有姓刻膜322。裸露的底面上，姓刻膜奶 包含支樓桿（圖未示）的式樣以臨_接於分離之焊塾部分 31如與晶粒座3Μ之間。餘刻膜η?可由貴金屬、金屬合 金或者光致抗_製成。钱刻臈322包含縫隙孔324。: 324 &定待轉變為基本晶粒座314之獨立焊塾式樣 心後如第15圖所不，於晶粒座314之雙面上皆執行 1_序（包含自晶粒面開始的—半㈣程序以及自 ==314之底面開始的另外一半_程序），以通職刻 :之縫隙孔來餘刻掉全部厚度之晶粒座314，由此形 。τ形縫隙孔34G與分離之焊塾部分㈣。此階段 Μ臨時的支撐桿仍耗接於分離之焊塾部分3Ua與晶 15 200929494 粒座314之間，以防止分離之焊墊部分314&自晶粒座 上掉落。帛-餘刻程序可以完成於導線架製造群组中。接 著，導線架300被傳送至裝配車間。 如第16圖所示，裝配車間中，將半導體晶片312粘附 於晶粒座3】4上。提供連接線爪與336，以形成連接塾 313與導腳316之間的電性連接以及半導體晶粒312上的 連接墊313與分離之焊替部分M4a之間的電性連接。 〇 如第17圖所示，於打線接合之後，接著使用熱硬化性 材料32〇來模製第I6圖所示的全部裝配元件。熱硬化性材 料可為低溫硬化樹脂。隨後，對模製封裝進行加工程序。 如特別指出的’模製封裝之底面或者PCB面係裸露的。 根據本發明之另一實施例，導線架封裝為多晶片模組 (Multi-Chip Module，MCM)或者系統級封裝 (SyStem-in-Package，以下簡稱為Sip)。系統級封裝包含多 〇個半導體晶粒與被動元件於單一封裝中。第18圖為帅導 線架封裝之頂視圖。如第18圖所示，sip導線架封裝4⑻ 包含安裝於主要晶粒座414上的第一半導體晶粒412。主 要晶粒座414包含四個自主要晶粒座414之四角向外延伸 的細支桿415。主要晶粒座414的底面裸露於封裝體中， 以驅散第一半導體晶粒412所産生之熱量。主要晶粒座414 之裸露底面可電性耦接至PCB之接地層。 第一半導體晶粒412包含位於其上的多個連接墊 413。連接墊413通過連接線418電性耦接各自的導腳 16 200929494 416。^導線架封裝_更包含次要晶粒座514。第二半 導體晶粒512係安裝於次要晶粒座514上。次要晶粒座 係自主要晶粒座414分割，並且未與主要晶粒座4M直接 接觸。第二半導體晶粒512上的一些連接墊513通過連接 線518電性輕接各自的導腳仙。根據本發明第一半導 體晶粒412為數位晶片，並且第二半導體晶粒$ i 2為類比 晶片。 似的’次要晶粒座514之底面裸露於封裝體中，以 驅散第二半導體晶粒512所産生之熱量。次要晶粒座514 之裸露底面可電_接至接地層（例如PCB之類比接地）， 此種設置能_止數位電路雜訊影響類比訊號路徑。此 外，提供多個分離之焊塾部分614於主要晶粒座414上， 分離之焊墊部分614包含與第3圖至第6圖所示的分離之 焊墊部分14b相同的分隔墊結構。 〇 ㈣之焊姨分614之功⑽提供高速差動訊號至第 二半導體晶粒512’以使得能夠建立更短的電性路徑以及 達到更少訊號損失之目的。分離之焊墊部分614與主要晶 粒座414分離，並且不需要任何來自主要晶粒座4M或: 導腳416的結構支援。 可選擇的，將被動元件56〇跨越縫隙54〇來安裝於主 要晶粒座414與次要晶粒座514上，縫隙54〇係位於主要 晶粒座414與次要晶粒座514之間。一些連接墊413通過 連接線618打線接合至第二半導體晶粒512上之各自的連 17 200929494 接塾513第一半導體晶粒512上的-些連接塾513係通 過連接線718打線接合至分離之焊墊部分614。由模製材 料420封裝或者模製全部裝配元件。 第19圖與第2〇圖為根據本發明另一實施例之覆晶 (叫chip)導線架封裝_的示意圖。帛19圖為覆晶導: 架封裝900之平面圖。第2〇圖為覆晶導線架封裝9⑼之剖 面示意圖。如第19圖與第20圖所示’覆晶導線架封裝9〇〇 ❹包含晶粒座914。晶粒座914包含四個自晶粒座914之四 角向外延伸的細支桿（SUpp〇rting bar)9l5。晶粒座914之底 面裸露於封裝體中。舉例而言，晶粒座914之裸露底面電 性耦接至PCB之數位接地層。於晶粒座914之另一面（即 與晶粒座914之裸露底面相反的晶粒面）上提供凸起塊 (bump)或者銲料珠(s〇ider ball)924 ’以在主要晶粒座與安裝 於晶粒面上的覆晶912之間形成電性連接。 覆晶導線架封裝900更包含多個懸浮之焊墊部分 (suspended pad segment)914a、914b、914c 與 914d，每一 懸浮之焊墊部分耦接一特定訊號。例如，懸浮之焊墊部分 914a耦接於VDD1電源訊號，懸浮之焊墊部分914b耦接於 VDD2電源訊號，懸浮之焊墊部分914c耦接於vDD3電源訊 號’並且懸浮之焊墊部分914d耦接於類比接地訊號。凸起 塊924a、924b、924c與924d係設置於各懸浮之焊墊部分 914a〜914d上，以於懸浮之焊墊部分與覆晶912之間進行 電性連接。 18 200929494 如前所述’懸浮之焊墊部分914a〜914d係自晶粒座914 分割，並且未與晶粒座914直接接觸。更進一步地説，懸 浮之焊墊部分914a〜914d與多個導腳916之任一導腳相分 離。縫隙940a、940b、940c、940d可包含第4圖所示的反 向T形剖面。各懸浮之焊墊部分的底面914a〜914d係裸露 的014 , 15 , 16 , and 17 are leadframe packages during the t-step manufacturing process of the lead frame package having the reverse τ-shaped slit shown in FIG. 4 according to another embodiment of the present invention. Schematic diagram of the section. As shown in the figure, after etching (or embossing) and plating, the lead frame 3 is obtained. The lead frame includes a single die pad 3 Μ and a peripheral lead pin 3. Both sides of the die pad 314 are coated with a surname film 322. On the bare bottom surface, the surnamed film containing the support bar (not shown) is attached to the separated weld bead portion 31, such as between the die pad and the die pad. The residual film η? can be made of a noble metal, a metal alloy or a photo-resistance. The money engraving 322 includes a slit hole 324. : 324 & is determined to be converted into the independent die-shaped core of the basic die pad 314. As shown in Fig. 15, the 1_order is executed on both sides of the die pad 314 (including from the die face). The half (four) program and the other half of the program starting from the bottom of the == 314 are etched out of the slot hole to etch away the full thickness of the die pad 314. The τ-shaped slit hole 34G and the separated solder joint portion (4). At this stage, the temporary support rod is still consumed between the separated bead portion 3Ua and the crystal 15 200929494 to prevent the separated pad portion 314 & from falling off the die pad. The 帛-remainder program can be completed in the lead frame manufacturing group. The leadframe 300 is then transferred to the assembly shop. As shown in Fig. 16, in the assembly shop, the semiconductor wafer 312 is adhered to the die pad 3]. Connecting claws 336 are provided to form an electrical connection between the connection 313 and the lead 316 and an electrical connection between the connection pad 313 on the semiconductor die 312 and the separate pad portion M4a. 〇 As shown in Fig. 17, after the wire bonding, all of the assembled components shown in Fig. 6 are molded using the thermosetting material 32〇. The thermosetting material may be a low temperature curing resin. Subsequently, the molding package is processed. As indicated in particular, the bottom surface of the molded package or the PCB surface is bare. According to another embodiment of the present invention, the lead frame package is a Multi-Chip Module (MCM) or a system-in-package (SyStem-in-Package, hereinafter referred to as Sip). System-in-packages contain multiple semiconductor dies and passive components in a single package. Figure 18 is a top view of the handsome wireframe package. As shown in FIG. 18, the sip leadframe package 4(8) includes a first semiconductor die 412 mounted on a main die paddle 414. The main die pad 414 includes four thin struts 415 that extend outwardly from the four corners of the main die pad 414. The bottom surface of the main die pad 414 is exposed in the package to dissipate the heat generated by the first semiconductor die 412. The exposed bottom surface of the main die pad 414 can be electrically coupled to the ground plane of the PCB. The first semiconductor die 412 includes a plurality of connection pads 413 thereon. The connection pads 413 are electrically coupled to the respective lead pins 16 200929494 416 via a connection line 418. The lead frame package _ further includes a secondary die pad 514. The second semiconductor die 512 is mounted to the secondary die pad 514. The secondary die paddle is split from the main die pad 414 and is not in direct contact with the main die pad 4M. Some of the connection pads 513 on the second semiconductor die 512 are electrically connected to the respective leads through the connection line 518. The first semiconductor die 412 is a digital wafer in accordance with the present invention, and the second semiconductor die $i 2 is an analog wafer. The bottom surface of the 'secondary die pad 514 is exposed in the package to dissipate the heat generated by the second semiconductor die 512. The exposed bottom surface of the secondary die pad 514 can be electrically connected to the ground plane (e.g., analog grounding of the PCB). This arrangement enables the digital circuit noise to affect the analog signal path. In addition, a plurality of separate solder fillet portions 614 are provided on the main die pad 414, and the separated pad portion 614 includes the same spacer structure as the separate pad portions 14b shown in Figures 3 through 6. The work of the solder joint 614 (10) provides a high speed differential signal to the second semiconductor die 512' to enable a shorter electrical path to be established and to achieve less signal loss. The separate pad portion 614 is separated from the primary crystal holder 414 and does not require any structural support from the primary die pad 4M or: the pilot foot 416. Alternatively, the passive component 56 is mounted across the slot 54 to the primary die pad 414 and the secondary die pad 514, the slot 54 being located between the primary die pad 414 and the secondary die pad 514. Some of the connection pads 413 are wire bonded to the respective junctions 17 on the second semiconductor die 512 by the connection wires 618. The connection pads 513 are connected to the first semiconductor die 512 via the connection wires 718. Pad portion 614. All of the assembled components are encapsulated or molded from molding material 420. Fig. 19 and Fig. 2 are schematic views showing a flip chip package called a chip package according to another embodiment of the present invention. Figure 19 is a flip-chip guide: a plan view of the rack package 900. Figure 2 is a cross-sectional view of the flip-chip leadframe package 9 (9). As shown in Figures 19 and 20, the flip-chip leadframe package 9A includes a die pad 914. The die pad 914 includes four thin struts 9l5 extending outwardly from the four corners of the die pad 914. The bottom surface of the die pad 914 is exposed in the package. For example, the exposed bottom surface of the die pad 914 is electrically coupled to the digital ground plane of the PCB. A bump or solder ball 924 ' is provided on the other side of the die pad 914 (ie, the die face opposite the exposed bottom surface of the die pad 914) to serve the main die pad An electrical connection is formed between the flip chip 912 mounted on the die face. The flip-chip leadframe package 900 further includes a plurality of suspended pad segments 914a, 914b, 914c and 914d, each of which is coupled to a particular signal. For example, the floating pad portion 914a is coupled to the VDD1 power supply signal, the floating pad portion 914b is coupled to the VDD2 power supply signal, and the floating pad portion 914c is coupled to the vDD3 power supply signal 'and the floating pad portion 914d is coupled. For analog grounding signals. The bumps 924a, 924b, 924c, and 924d are disposed on the floating pad portions 914a-914d to electrically connect the floating pad portion and the flip chip 912. 18 200929494 As previously described, the suspended pad portions 914a-914d are split from the die pad 914 and are not in direct contact with the die pad 914. More specifically, the floating pad portions 914a-914d are separated from any of the plurality of legs 916. The slits 940a, 940b, 940c, 940d may include a reverse T-shaped cross section as shown in Fig. 4. The bottom surfaces 914a to 914d of each of the suspended pad portions are bare 0
導脚916係沿着晶粒座914之四邊設置。凸起塊916a 係設置於各導腳916上，以於導腳916與覆晶912之間進 行電性連接。除去其底面，覆晶912、晶粒座914、懸浮之 焊墊部分914a〜914d與導腳916係封裝於模製材料920 中。模製材料920填充縫隙940a〜940d，由此將懸浮之焊 墊部分914a〜914d牢固地保持在其位置上。 請參閱第21圖、第22圖、第23圖、第24圖與第25 圖。第21圖為根據本發明之導線架封裝側面的内部示意 圖。第22圖為根據本發明之導線架的範例佈侷（iay〇ut)的 不意圖。第23圖至第25圖為第22圖所示之導線架之一側 的放大頂視圖。如第21圖所示，導線架封裝2⑻可為LQFp 裸露焊塾封裝（LQFP exposed pad package)。LQFP 裸露焊 墊封裝包含單一晶粒座214，粘附於晶粒座214之半導體 阳粒212、多個沿著晶粒座214之四個外圍邊緣設置的導 二216、多個設置於晶粒座214與多個導腳216之間的裸 路之焊墊部分(exPosed Pad segment)224、多條電性耦接并 且延伸至半導體晶粒212與各導腳210之間的導線218、 200929494 多條電性搞接并且延伸至半導體晶粒212與多個裸露之悍 墊部分224之間的導線228、以及模製材料22〇，模製材料 22〇至少部分封裝晶粒座m、導線216、裸露之焊塾部分 224、導線218與導線228。晶粒座214之底面與裸露之焊 墊部分224之底面係裸露於模製材料22〇内。裸露之焊塾 部分224可沿著晶粒座214之四個外圍邊緣的其中之一與 内向導腳216延伸。裸露之焊墊部分224的跨距(span)取決 ❹於半導體晶粒212上連接墊阳的電特性。例如，半導體 晶粒212上的兩個或者三個訊號墊(例如數位電源墊）可打 線接合於單一裸露之焊墊部分（例如第22圖所示之M2)， 用以接收數位電源。 如第22圖所示，根據本發明，範例導線架21〇包含單 一晶粒座Ml。晶粒座Ml係設置於導線架210之中央開孔 内。由四個支樓桿215支援之晶粒座Ml包含方形配置， 方形配置設定四個實質上長度相等的外圍邊緣。多個焊墊 ◎ 部分 M2、M3、M4、M5、M6、M7、M8、M9、M10、Ml 1、 M12、M13、M14、M15、M16、M17、M18、M19、M20、 M21、M22、M23、M24、M25、M26、M27、M28、M29、 M30、M31、M32、M33、M34、M35、M36、M37、M38、 M39、M40 ' M41、M42、M43、M44、M45、M46、M47、 M48、M49、M50、M51、M52、M53 延伸至晶粒座 Ml 之 四個外圍邊緣與内向導腳216之間。焊墊部分M2〜M53可 由耦接桿支援，例如耦接焊墊部分M2〜M6與晶粒座Ml 20 200929494 的搞接桿C2、C3、C4、C5、C6。可選擇地，焊塾部分可 由如第27圖所示之障礙桿(dam bar)230所支援。於之後的 裝配或者封裝階段，可藉由餚射、鋸、蝕刻、雕刻或者去 緯/去膠(dejunk/trim)方法將耦接桿切掉，以使各焊塾部分 相互間電性絕緣。 如第23圖所示，焊墊部分M2非常相似於新生地 (reclaimed land)，焊墊部分M2佔據導腳216與晶粒座Mi ❹之四個外圍邊緣其中之一之間很大的開放區域。焊墊部分 M2包含一個邊緣233，邊緣233符合由導腳216之内端所 設定的形狀。本發明之一特點在於：焊墊部分M2包圍至 少一個小區域的焊墊部分，例如M3與]V14。焊墊部分]v[2 大於被包圍的焊塾部分M3或者M4，也就是説，焊塾部分 M2的表面區域大於被包圍的焊墊部分M3或者M4的表面 區域。如第23圖所示，焊塾部分m3或者M4設置於焊塾 M2與晶粒座Μ1之間。根據本發明，焊墊部分電性耦 ❹接於第一訊號，並且被包圍的焊墊部分電性耦接於第二訊 號，其中相較於第一訊號，第二訊號對雜訊更敏感。根據 本發明，相較於第二訊號，第一訊號具有更低的狀態切換 率。例如，第-訊號可為職數位電源，而第二訊號可為 DDR參考電源(VREF)或者類比電源。另一種狀況下第二 訊號可為控制訊號或者差動訊號。焊墊部分M2可包含z 字形側面的邊緣235，邊緣235與相鄰焊塾部分(例如焊塾 部分M5與M6)之對應Z字形邊緣相配合。 200929494 如第24圖所示’焊墊部分Mil與Ml3共同包圍敏感 的焊墊部分M7。藉由這種配置，電源或者接地的焊墊部分 MU與MU保護敏感的焊墊部分M7，例如焊墊部分M7 為類比電源或者類比接地訊號時，為焊墊部分M7遮蔽雜 訊訊號。相似的，第24圖中，受保護之敏感的焊墊部分包 含焊墊部分M14、M19與M22。第25圖為多個設置於導 腳與晶粒座Ml之間之帶狀的焊墊部分M51〜M53。受保護 ❹之敏感的焊墊部分包含焊墊部分M44〜M47與M49，其中 敏感谭塾部分M44〜M47由焊墊部分M10與M12保護，並 且敏感焊墊部分M49由焊墊部分M48與M50保護。如第 25圖所示’焊墊M49設置於焊墊m5〇與晶粒座M1之間。 第26圖為連接墊213、焊墊部分M30〜M32與導線228之 不意圖。本發明一實施例中，多個裸露之焊墊部分224包 含大的表面區域，足夠用於多於四條導線228之打線接 並且電源/接地電感與熱阻抗得到減小。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍’任何熟習此項技藝者，在不脫離本發明之 精神寿範圍内’當可做些許的更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範園所界定者為準。 【圖式簡單說明】 第1圖為導線架封褒之頂透視圖。 第2圖為根據本發明 實施例之導線架封裝的頂透視圖。 22 200929494 ^圖為導線架封m-A方向之剖面示意圖。 部::::::發明之分離之焊墊部分與圍繞分離之焊墊 _B方向之放大剖面示意圖。 第5圖為縫隙的變形例。 第6圖為縫隙的另-變形例。 ❹ =據本發明之晶片㈣及一範例電感部 :::二本:明之包含多個裸綱的導線架封裝之 ί明二ί:圖、第U圖、第12圖與第13圖為根據本 導 =::::法製造導線___的 、第15圖、第16圖與第17圖為根據本發明另- 期門二3第4圖所不反向τ形縫隙之導線架封裝製造 ㈣’中間步驟時導線架封裝的剖面示意圖。 第18圖為Sip導線架封裝之頂視圖。 第19圖為覆晶導線架封裝之平面透視圖。 第2〇圖為覆晶導線架封裝之剖面示意圖。 ^ 21圖為根據本發明之導線架封裝的剖面示意圖。 f 22圖為根據本制之導線㈣範例佈侷的示意圖。 八放士圖第24圖與第25圖為第22圖所示之導線架之部 刀放大頂透視圖。 第26圖為連接墊、焊墊部分與導線之示意圖。 23 200929494 第27圖為範例導線架之障礙桿(dam bar)之示意圖。 【主要元件符號說明】 10、10a〜導線架封裝 12、 312、212〜半導體晶粒 13、 313、413、513、213〜連接墊 14、 314、414、514、914、214〜晶粒座 秦 15、415、915〜細支桿 〇 16、16a、16b、16c、16d、16e、16f、316、416、916、216 〜導腳 13a、13b、13c、13d、13e、13f〜電源塾 13g、13h〜接地塾 18、26、28、36、318、336、418、618、718、518〜連接 線 14a、14b、314a、614〜分離之焊墊部分 ❹ 40a、40b、82a、84a、540、940a、940b、940c、940d〜縫 隙 52a、52b〜貴金屬層 60〜被動元件 70〜鋸齒形邊緣 82、84〜電感部分 100〜第一階段 200〜第二階段 24 200929494 102、202〜步驟 300〜導線架 3 22〜姓刻膜 324〜縫隙孔 350〜焊墊式樣 320〜熱硬化性材料 420、920、220〜模製材料 爲 560〜被動元件 512〜第二半導體晶粒 412〜第一半導體晶粒 900〜覆晶導線架封裝 924〜銲料珠 914a、914b、914c、914d〜懸浮之焊墊部分 924a、924b、924c、924d、916a〜凸起塊 912〜覆晶 ν 224〜裸露之焊墊部分 228、218〜導線 230〜障礙桿 25The lead pins 916 are disposed along the four sides of the die pad 914. The bumps 916a are disposed on the respective lead pins 916 to electrically connect the lead pins 916 and the flip chip 912. The bottom surface is removed, and the flip chip 912, the die pad 914, the floating pad portions 914a to 914d and the lead pins 916 are encapsulated in the molding material 920. The molding material 920 fills the slits 940a to 940d, thereby holding the suspended pad portions 914a to 914d firmly in their positions. Please refer to Fig. 21, Fig. 22, Fig. 23, Fig. 24 and Fig. 25. Figure 21 is an internal schematic view of the side of the leadframe package in accordance with the present invention. Figure 22 is a schematic illustration of an exemplary layout of a leadframe in accordance with the present invention. Fig. 23 through Fig. 25 are enlarged top views of one side of the lead frame shown in Fig. 22. As shown in Fig. 21, the lead frame package 2 (8) may be an LQFp exposed pad package. The LQFP exposed pad package includes a single die pad 214, semiconductor bumps 212 adhered to the die pad 214, a plurality of leads 216 disposed along four peripheral edges of the die pad 214, and a plurality of pads disposed on the die The bare hole between the 214 and the plurality of leads 216 is electrically coupled and extends to the wires 218 and 200929494 between the semiconductor die 212 and each of the leads 210. The strip electrically extends and extends to the wire 228 between the semiconductor die 212 and the plurality of exposed pad portions 224, and the molding material 22, and the molding material 22 〇 at least partially encapsulates the die pad m, the wire 216, The exposed solder fillet portion 224, the wire 218 and the wire 228. The bottom surface of the die pad 214 and the bottom surface of the exposed pad portion 224 are exposed in the molding material 22''. The exposed solder fillet portion 224 can extend along one of the four peripheral edges of the die pad 214 with the inner guide leg 216. The span of the exposed pad portion 224 depends on the electrical characteristics of the connection pads on the semiconductor die 212. For example, two or three signal pads (e.g., digital power pads) on semiconductor die 212 can be wire bonded to a single exposed pad portion (e.g., M2 as shown in Figure 22) for receiving a digital power supply. As shown in Fig. 22, an exemplary lead frame 21A includes a single die pad M1 in accordance with the present invention. The die pad M1 is disposed in the central opening of the lead frame 210. The die pad M1 supported by the four masts 215 includes a square configuration, and the square configuration sets four peripheral edges of substantially equal length. Multiple pads ◎ Part M2, M3, M4, M5, M6, M7, M8, M9, M10, Ml 1, M12, M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23 , M24, M25, M26, M27, M28, M29, M30, M31, M32, M33, M34, M35, M36, M37, M38, M39, M40 'M41, M42, M43, M44, M45, M46, M47, M48 M49, M50, M51, M52, M53 extend between the four peripheral edges of the die pad M1 and the inner guide leg 216. The pad portions M2 to M53 can be supported by the coupling rods, for example, the pad portions M2 to M6 and the paddles C2, C3, C4, C5, and C6 of the die pad Ml 20 200929494. Alternatively, the weld bead portion may be supported by a dam bar 230 as shown in Fig. 27. In the subsequent assembly or packaging stage, the coupling rods can be cut away by means of a dish, saw, etch, engrave or dejunk/trim method to electrically insulate the solder joints from each other. As shown in Fig. 23, the pad portion M2 is very similar to the reclaimed land, and the pad portion M2 occupies a large open area between the lead pin 216 and one of the four peripheral edges of the die pad Mi ❹ . The pad portion M2 includes an edge 233 that conforms to the shape set by the inner end of the pin 216. One feature of the present invention is that the pad portion M2 surrounds at least one small portion of the pad portion, such as M3 and V14. The pad portion]v[2 is larger than the surrounded solder tab portion M3 or M4, that is, the surface area of the solder tab portion M2 is larger than the surface region of the surrounded pad portion M3 or M4. As shown in Fig. 23, the bead portion m3 or M4 is disposed between the pad M2 and the die pad 1. According to the invention, the pad portion is electrically coupled to the first signal, and the enclosed pad portion is electrically coupled to the second signal, wherein the second signal is more sensitive to noise than the first signal. According to the present invention, the first signal has a lower state switching rate than the second signal. For example, the first signal can be a digital power supply and the second signal can be a DDR reference power supply (VREF) or an analog power supply. In the other case, the second signal can be a control signal or a differential signal. The pad portion M2 may include a zigzag side edge 235 that mates with a corresponding zigzag edge of an adjacent pad portion (e.g., pad portions M5 and M6). 200929494 As shown in Fig. 24, the pad portions Mil and M13 together surround the sensitive pad portion M7. With this configuration, the power pad or ground pad portion MU and MU protect the sensitive pad portion M7, for example, when the pad portion M7 is an analog power source or an analog ground signal, the pad portion M7 shields the noise signal. Similarly, in Figure 24, the protected sensitive pad portion includes pad portions M14, M19 and M22. Fig. 25 is a view showing a plurality of strip-shaped pad portions M51 to M53 which are disposed between the pin and the die pad M1. The portion of the pad that is sensitive to the protection includes the pad portions M44 to M47 and M49, wherein the sensitive portion M44 to M47 are protected by the pad portions M10 and M12, and the sensitive pad portion M49 is protected by the pad portions M48 and M50. . As shown in Fig. 25, the pad M49 is disposed between the pad m5 and the die pad M1. Fig. 26 is a view showing the connection pads 213, the pad portions M30 to M32, and the wires 228. In one embodiment of the invention, the plurality of exposed pad portions 224 comprise a large surface area sufficient for wire bonding of more than four wires 228 and the power/ground inductance and thermal impedance are reduced. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention. The scope of protection of the present invention is defined by the scope of the patent application. [Simple description of the drawing] Figure 1 is a top perspective view of the lead frame sealing. Figure 2 is a top perspective view of a leadframe package in accordance with an embodiment of the present invention. 22 200929494 ^The figure shows the cross section of the lead frame in the m-A direction. Part::::::Invented separate pad portion and enlarged cross-section of the _B direction around the separated pad. Fig. 5 is a modification of the slit. Fig. 6 is a further modification of the slit. ❹ = wafer (4) according to the invention and an example inductor part::: two: the wire frame package containing a plurality of bare wires is clearly shown in the figure: the figure, the U figure, the 12th picture and the 13th figure are based on The lead =:::: method for manufacturing the wire ___, the 15th, 16th, and 17th drawings are the lead frame package of the non-reversed τ-shaped slit according to the fourth embodiment of the present invention. Manufacturing (4) Schematic diagram of the lead frame package in the 'intermediate step'. Figure 18 is a top view of the Sip leadframe package. Figure 19 is a plan perspective view of a flip-chip leadframe package. The second drawing is a schematic cross-sectional view of the flip-chip lead frame package. Figure 21 is a schematic cross-sectional view of a leadframe package in accordance with the present invention. Figure f 22 is a schematic diagram of the example layout of the wire (4) according to the system. Fig. 24 and Fig. 25 of Fig. 8 are enlarged top perspective views of the lead frame of the lead frame shown in Fig. 22. Figure 26 is a schematic view of the connection pad, the pad portion and the wire. 23 200929494 Figure 27 is a schematic diagram of a dam bar of an example lead frame. [Main component symbol description] 10, 10a~ lead frame package 12, 312, 212~ semiconductor die 13, 313, 413, 513, 213~ connection pad 14, 314, 414, 514, 914, 214 15, 415, 915~ thin strut 〇 16, 16a, 16b, 16c, 16d, 16e, 16f, 316, 416, 916, 216 - lead pins 13a, 13b, 13c, 13d, 13e, 13f ~ power supply 塾 13g, 13h~grounding pads 18, 26, 28, 36, 318, 336, 418, 618, 718, 518~ connecting wires 14a, 14b, 314a, 614~ separate pad portions ❹ 40a, 40b, 82a, 84a, 540, 940a, 940b, 940c, 940d~ slit 52a, 52b~ precious metal layer 60~ passive element 70~ zigzag edge 82, 84~ inductive part 100~ first stage 200~ second stage 24 200929494 102, 202~ step 300~ wire Rack 3 22 ~ surname film 324 ~ slot hole 350 ~ pad pattern 320 ~ thermosetting material 420, 920, 220 ~ molding material 560 ~ passive element 512 ~ second semiconductor die 412 ~ first semiconductor die 900~ flip-chip lead frame package 924~ solder beads 914a, 914b, 914c, 914d~ suspended pad portions 924a, 9 24b, 924c, 924d, 916a~ bump block 912~ flip chip ν 224~ bare pad portion 228, 218~ wire 230~ barrier bar 25