200926589 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種等化器（Equalizer)之製作方法，且 * 特別是有關於一種傳輸線等化器之製作方法。 【先前技術】 隨著信號傳輸速率之增加，傳輸線所造成之損耗，成 為信號損耗之主要因素。為了避免嚴重的傳輸線損耗使信 0 號波型失真，甚至造成邏輯位準的誤判而使電路誤動作， 一般會利用被動等化器（passive equalizer)來補償傳輸線所 造成之高頻損耗。 被動等化器具有咼通渡波之特性，主要由電阻、電感 或電容等被動元件構成《由於傳輸線呈現低通濾波之效 應’若與一高通濾波之等化器串接，則信號經過傳輸線以 及等化器之後’頻譜比例仍會與原始信號之頻譜比例近 似，因而改善了信號失真的問題。 ® 然而在傳統的被動等化器製作過程當中，並沒有一套 有效的方法，來預估等化器各元件阻抗值，只能夠嘗試各 種不同的阻抗值，然後依靠電路模擬分析，找出補償效果 較佳的阻抗值。這種嘗試方法不但耗費人力，更無法精確 地補償傳輸線之損耗。 因此需要一種新的等化器製造方法，能夠改善等化器 之製造流程，並精確地補償傳輸線之輸出信號。 200926589 【發明内容】 因此本發明之之一方面就是在提供一種傳輸線等化器 之製造方法，能夠預估等化器元件之阻抗值，改善等化器 ' 之製造流程，並能夠精確地補償傳輸線之輸出信號。 • 依照本發明之一實施例，傳輸線等化器製造方法首先 量測傳輸線之一傳輸線s參數，接著對傳輸線s參數、頻 域函式、一理想增益值以及一等化器S參數進行一積分運 算以及一微分運算，藉以求得等化器之複數個阻抗值。然 〇 後選取具上述阻抗值之元件，製造一等化器實體電路。 根據上述實施例，傳輸線等化器之製造方法能夠改善 等化器之製作流程，減少不必要之電路模擬分析；更能夠 精確地補償傳輸線輸出信號之損耗。 【實施方式】 以下實施例之傳輸線等化器製造方法，係以一等化器 電性連接傳輸線，來補償傳輸線所造成之信號損耗。此一 Ο 等化器製造方法，能夠針對一般信號以及預先放大/預先衰 減信號，來改善等化器之製作流程，減少不必要之電路模 擬分析，並精確地補償傳輸線所造成之損耗。 請同時參照第1A圖以及第1B圖，其繪示本發明一實 施例數位信號之時域波形圖。在高速傳輸下，傳輸線會使 原始數位信101產生衰減，因此現行的匯流排系統，例如 週邊元件連接介面（PCI)、週邊元件連結快捷介面 (PCI-Express)、串列先進技術接取介面（SATA)，或平行先 200926589 進技術接取介面（PATA)等，除了提供原始數位信號101以 外，還提供預先衰減信號l〇3a \預先放大信號103b，以及 由原始數位信號101與預先衰減信號103a \預先放大信號 • 103疊加而得之疊合數位信號105，來供後續電路使用，以 * 補償傳輸線所造成之信號衰減。 在此第1A圖以及第1B圖中，原始數位信號101之時 域\頻域函式分別為F(〇與F(®)。預先衰減信號103a以及預 先放大信號l〇3b，均為原始數位信號101經衰減\放大以及 Ο 平移後之信號。預先衰減信號l〇3a之時域\頻域函式分別為 ⑺=(1 - «V⑺-Θ以及心叩⑻=(1 - a)F⑻-π㈣W。預先放 大信號 l〇3b 之時域\頻域函式則為 4P(0 = (l + a)F(〇-aF(卜:r)\F_⑻= (1 + «)F⑻’ 其中 r為延 遲時間（平移時間），α為衰減參數。 請參照第2圖，其繪示本發明一實施例之信號頻率響 應。在此第2圖中，傳輸線S參數201隨頻率增加而遞減， 呈現低通效應。等化器S參數203以及預先衰減信號\預先 Ο 放大信號211則隨頻率增加而遞增，呈現高通效應。乘積 函式209為傳輸線S參數201與預先衰減信號\預先放大信 號211之乘積。為了避免補償後數位信號207之相位超過 臨界值，使得信號不穩定，因此我們挑選乘積函式209於 頻率之增益值為理想增益值205。 等化器S參數203,會隨著等化器各元件之阻抗值不同 而改變。舉例來說，當等化器電阻之電阻值改變，等化器S 參數203也會隨著改變。由於傳輸線所傳遞之數位信號， 200926589 同時受到乘積函式209以及等化器S參數203之影響，藉 由調整等化器元件之阻抗值，能夠調整補償後之數位信號 207。所以可以調整等化器元件之阻抗值，來使補償後之數 • 位信號207，在頻率小於之增益曲線接近理想增益值 - 205 ° 請參照第3圖，其係繪示本發明一實施例傳輸線等化 器之製作流程圖。首先依照一預定尺寸製作傳輸線（步驟 301)，其中，不同尺寸之傳輸線具有不同之傳輸線S參數。 © 接著使用網路分析儀，量測此一傳輸線之傳輸線S參數（步 驟303)。然後取得此傳輸線S參數與預先衰減函式\預先放 大函式之乘積，並取得此一乘積在頻率•處之增益值（步 驟305)，此一增益值即為理想增益值。 在取得傳輸線S參數、理想增益值之後，可以使用數 學軟體（例如Matlab)對傳輸線S參數、理想增益值、等化 器S參數，以及傳輸線所傳遞數位信號之頻域函式，進行 一積分運算以及一微分運算，來求得等化器各元件之阻抗 Ο 值（步驟307)。 在等化器元件阻抗值之估算過程當中，積分運算 (/)xlpC/>^^(/))-U/)丨# = ，係選擇具特定阻 0200926589 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for fabricating an equalizer, and * particularly relates to a method for fabricating a transmission line equalizer. [Prior Art] As the signal transmission rate increases, the loss caused by the transmission line becomes a major factor in signal loss. In order to avoid serious transmission line loss, the signal waveform of the signal is distorted, and even the logic level is misjudged to cause the circuit to malfunction. A passive equalizer is generally used to compensate for the high frequency loss caused by the transmission line. The passive equalizer has the characteristics of a 咼-pass wave, which is mainly composed of passive components such as resistors, inductors or capacitors. “Because of the effect of low-pass filtering on the transmission line”, if it is connected in series with a high-pass filter equalizer, the signal passes through the transmission line and etc. After the chemist, the spectral ratio will still approximate the spectral ratio of the original signal, thus improving the problem of signal distortion. ® However, in the traditional passive equalizer production process, there is no effective way to estimate the impedance values of the equalizer components. Only different impedance values can be tried, and then the circuit simulation analysis is used to find the compensation. A better impedance value. This method of trial is not only labor intensive, but also incapable of accurately compensating for the loss of the transmission line. There is therefore a need for a new equalizer manufacturing method that improves the equalizer manufacturing process and accurately compensates for the output signal of the transmission line. SUMMARY OF THE INVENTION Accordingly, it is an aspect of the present invention to provide a method of manufacturing a transmission line equalizer capable of estimating an impedance value of an equalizer element, improving a manufacturing process of the equalizer, and accurately compensating for a transmission line The output signal. • According to an embodiment of the present invention, a transmission line equalizer manufacturing method first measures a transmission line s parameter of a transmission line, and then integrates a transmission line s parameter, a frequency domain function, an ideal gain value, and an equalizer S parameter. The operation and a differential operation are used to obtain a plurality of impedance values of the equalizer. Then, the component having the above impedance value is selected to manufacture a first equalizer physical circuit. According to the above embodiment, the manufacturing method of the transmission line equalizer can improve the manufacturing process of the equalizer, reduce unnecessary circuit simulation analysis, and accurately compensate the loss of the output signal of the transmission line. [Embodiment] The method for manufacturing a transmission line equalizer in the following embodiments is to electrically connect a transmission line with an equalizer to compensate for signal loss caused by the transmission line. The Ο equalizer manufacturing method can improve the equalizer manufacturing process for general signals and pre-amplify/pre-fade signals, reduce unnecessary circuit simulation analysis, and accurately compensate for losses caused by transmission lines. Referring to FIG. 1A and FIG. 1B simultaneously, a time domain waveform diagram of a digital signal according to an embodiment of the present invention is shown. In high-speed transmission, the transmission line will attenuate the original digital signal 101, so the current bus system, such as peripheral component connection interface (PCI), peripheral component fast interface (PCI-Express), serial advanced technology access interface ( SATA), or parallel first 200926589 into the technology access interface (PATA), etc., in addition to providing the original digital signal 101, also provides a pre-attenuation signal l 〇 3a \ pre-amplified signal 103b, and from the original digital signal 101 and the pre-attenuated signal 103a \Preamplified signal • 103 superimposed and superimposed digital signal 105 for use by subsequent circuits to compensate for signal attenuation caused by the transmission line. In the first picture 1A and the first picture BB, the time domain\frequency domain functions of the original digital signal 101 are respectively F (〇 and F(®). The pre-attenuation signal 103a and the pre-amplified signal l〇3b are both original digits. The signal 101 is attenuated\amplified and Ο translated. The time domain\frequency domain function of the pre-attenuated signal l〇3a is (7)=(1 - «V(7)-Θ and 叩(8)=(1 - a)F(8)- π(四) W. The time domain\frequency domain function of the pre-amplified signal l〇3b is 4P (0 = (l + a)F(〇-aF(卜:r)\F_(8)= (1 + «)F(8)' where r is Delay time (translation time), α is the attenuation parameter. Please refer to Fig. 2, which shows the signal frequency response according to an embodiment of the invention. In Fig. 2, the transmission line S parameter 201 decreases with increasing frequency, and the representation is low. The equalizer S parameter 203 and the pre-attenuation signal\pre-amplification signal 211 are incremented as the frequency increases, exhibiting a high-pass effect. The product function 209 is the product of the transmission line S parameter 201 and the pre-attenuation signal\pre-amplified signal 211. In order to avoid the phase of the compensated digital signal 207 exceeding the critical value, the signal is unstable, so we choose The gain function of the product function 209 at the frequency is the ideal gain value 205. The equalizer S parameter 203 changes with the impedance value of each element of the equalizer. For example, when the resistance value of the equalizer resistance changes The equalizer S parameter 203 will also change. Due to the digital signal transmitted by the transmission line, 200926589 is affected by the product function 209 and the equalizer S parameter 203 at the same time, by adjusting the impedance value of the equalizer component, The compensated digital signal 207 is adjusted. Therefore, the impedance value of the equalizer element can be adjusted so that the compensated number bit signal 207 is close to the ideal gain value at a frequency less than the gain curve - 205 °, refer to FIG. 3, A flow chart of a transmission line equalizer according to an embodiment of the present invention is shown. First, a transmission line is formed according to a predetermined size (step 301), wherein different size transmission lines have different transmission line S parameters. © Next, using a network analyzer, Measure the transmission line S parameter of the transmission line (step 303), and then obtain the product of the transmission line S parameter and the pre-attenuation function\pre-amplification function, and obtain the multiplication The gain value at the frequency • (step 305), the gain value is the ideal gain value. After obtaining the transmission line S parameter and the ideal gain value, the mathematical software (such as Matlab) can be used to transmit the S parameter, the ideal gain value, The equalizer S parameter, and the frequency domain function of the digital signal transmitted by the transmission line, perform an integral operation and a differential operation to obtain the impedance Ο value of each element of the equalizer (step 307). In the process of estimating the value, the integral operation (/) xlpC/>^^(/))-U/)丨# = , selects a specific resistance.
抗值之等化器元件，使補償後之數位信號與理想增益值之 差距最小，其中«⑺為傳輸線S參數，⑺為數位信 號經預先衰減\預先放大之頻域函式，為等化器SThe value-independent equalizer component minimizes the difference between the compensated digital signal and the ideal gain value, where «(7) is the transmission line S parameter, and (7) is the frequency domain function of the digital signal pre-attenuated/pre-amplified, which is the equalizer S
200926589 參數’ K/)為理想增益值，min則為最小正數值。 微分運算㈣ df -，則進— 步挑出特定之阻抗值，具有此此 倍 力二阻抗值之兀件，能使補償 後之數位㈣在頻率小於1處之增益轉料固定，或 是使增益曲線之斜率小於等於零1在此一微分式中， U)為傳輸線s參數，^/)為數位㈣經預先衰減\ 預先放大之頻域函式，為等化器s參數。 由於積分運算雖然能使補償後之數位信號與理想增益 值之差距最小，但，經積分運算求得之阻抗值，可能^數 位信號在頻率小於>L·處出現峰值（有最大值\最小值），而 非一單調遞減曲線，因此需要微分運算，進一步挑選具特 定阻抗值之元件，使補償後之數位信號呈現單調遞減。 在求得等化器各元件之阻抗值之後，接著對具有此阻 抗值之等化器以及傳輸線，進行電路模擬分析（步驟309)， 來確認頻率補償的效果，也就是確認數位信號經傳輸線以 及等化器傳遞之後，是否近似於原始數位信號^最後則選 取具上述阻抗值之元件（例如電阻以及電感），來製作等化器 之實體電路（步驟311)。 凊參閱第4圖，其係繪示本發.明一實施例之傳輸線及 其等化器電路示意圖。傳輸線所傳遞之差動信號4〇5\4〇7 由匯流排系統提供。匯流排系統會對此差動信號進行預先 放大或預先衰減，然後透過傳輸線401、電容c以.及.傳輸 200926589 線〇3傳遞至等化器409。等化器4〇9包括串接之電感L 以及電阻R。刍并 ^ 周戰2則串接於等化器409。經等化器補償之 號則由。輪出。在此—實施例中，我們選用5〇 Ω之 電阻作為負載ζ〇 在等化器與傳輸線達成阻抗匹配之條件下（反射係數 等於零）’得到等化器S來盤U/)$技2(尺+7蛾） ' Z0+2(Re+j2^e) 其中尽為電阻R之電阻值，4為電感L之電感值，z。為電 負載Z之阻抗值。傳輸線s參數可由網路分析儀量測而得。 接著使用數學軟體對傳輸線S參數、等化n s參數、數位 信號之頻域函式，以及理想增益值，造行上述之積分運算 以及微分運算’可得等化器電阻R與電感L之阻抗值。 請同時參閱第5A圖以及第5B圖，其係分別繪示本發 明兩實施例補償後之預先衰減信號時域波形圖。在第5A圖 以及第5B圖中，5Gbps、400mv之數位信號係透過長度為 36inchs之傳輸線傳遞。在第5A圖中，數位信號係預先衰 減3.5db後，再由傳輸線傳遞。經數學軟體進行上述之積分 運算以及微分運算，可得等化器電阻R與電感L之阻抗值 分別為119Ω以及68nH。較之傳輸線上未經補償之數位信 號（眼高與眼寬分別為73.7 mv與93.16 ps)，經等化器補償 後數位信號之眼高與眼寬已大幅改善，分別為195 92 mv 與 155.07 ps。 第5B圖之數位信號則预先衰減6db後，再由傳輸線傳 200926589 遞。經數學軟體進行上述之積分運算以及微分運算，可得 等化器電阻R與電感L之阻抗值分別為300Ω以及i72nH。 較之未經補償之數位信號，經等化器補償數位信號之眼高 ' 與眼寬已大幅改善，分別為218.89 mv與160.53 ps。 * 請同時參閱第6A圖以及第6B圖，其係分別繪示本發 明兩實施例補償後之預先放大信號時域波形圖。在第6A圖 以及第6B圖中，5Gbps、400mv之數位信號係透過長度為 36 inchs之傳輸線傳遞。在第6A圖中，數位信號係預先放 〇 大3.5db後，再由傳輸線傳遞。經數學軟體進行上述之積分 運算以及微分運算，可得等化器電阻R與電感L之阻抗值 分別為105Ω以及57nH。較之未經補償之數位信號（眼高與 眼寬分別為73.7 mv與93.16 ps)，經等化器補償數位信號 之眼高與眼寬已大幅改善，分別為251.16 mv與161.49 ps。 第6B圖之數位信號則預先放大6db後，再由傳輸線傳 遞。如上所述，可求得等化器電阻R與電感L之阻抗值分 別為119Ω以及68nH。較之未經補償之數位信號，經等化 © 器補償數位信號之眼高與眼寬已大幅改善，分別為304.18 mv 與 165.20 ps 〇 由上述實施例可知，傳輸線等化器之製造方法能夠事 先預估所需等化器元件之阻抗值，精確地補償傳輸線所造 成之信號損耗，並減少電路模擬分析之時間與次數。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何在本發明所屬技術領域中具有通常知 識者，在不脫離本發明之精神和範圍内，當可作各種之更 11 200926589 動與潤飾’因此本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1A圖係繪示本發明一實施例之數位信號時域波形 圖。 第圖係繪示本發明另一實施例之數位信號時域波 形圖。 第2圖係繪示本發明一實施例之信號頻率響應。 第3圖係繪示本發明一實施例傳輸線等化器之製作流 程圖。 第4圖係繪示本發明一實施例之傳輸線及其等化器電 路示意圖。 第5 A .圖係繪·示本發明一實施例補償後之預先衰減信 號時域波形圖。 第5B圖係繪示本發明另一實施例補償後之預先衰減 信號時域波形圖。 第6A圖係繪示本發明一實施例補償後之預先放大信 號時域波形圖。 第6B圖係繪示本發明另一實施例補償後之預先放大 12 200926589 信號時域波形圖 Ο 主要元件符號說明】 101 :原始數位信號 103b :預先放大信號 201 :傳輸線S參數 205 :理想增益值 211 :預先衰減信號\預先放大信號 3〇1〜311 :等化器製造步驟 l〇3a :預先衰減信號 1〇5 :疊合數位信號 203 :等化器S參數 207 :補償後之數位信號 4〇1 :傳輸線 405 :差動信號 409 :等化器 L:電感 Z :負載 V。：補償後數位信號輸出端 403 :傳輸線 407 :差動信號 C :電容 R :電阻 13200926589 The parameter 'K/) is the ideal gain value and min is the minimum positive value. Differential operation (4) df -, then step-by-step to select a specific impedance value, which has the condition of the double-impedance value of the double force, so that the compensated digit (4) can be fixed at a gain of less than 1 frequency, or The slope of the gain curve is less than or equal to zero. In this differential equation, U) is the transmission line s parameter, ^/) is the digit (4) pre-attenuation\pre-amplified frequency domain function, which is the equalizer s parameter. Since the integral operation can minimize the difference between the compensated digital signal and the ideal gain value, the impedance value obtained by the integral operation may cause the peak value to appear at a frequency less than > L· (the maximum value / the minimum value Value), rather than a monotonically decreasing curve, therefore requires a differential operation to further select the component with a specific impedance value, so that the compensated digital signal is monotonically decreasing. After obtaining the impedance value of each component of the equalizer, circuit simulation analysis (step 309) is performed on the equalizer and the transmission line having the impedance value, thereby confirming the effect of the frequency compensation, that is, confirming the digital signal through the transmission line and After the equalizer is transmitted, whether it is approximate to the original digit signal ^ Finally, the component having the above impedance value (for example, resistance and inductance) is selected to fabricate the physical circuit of the equalizer (step 311). Referring to Figure 4, there is shown a schematic diagram of a transmission line and its equalizer circuit of the present invention. The differential signal 4〇5\4〇7 transmitted by the transmission line is provided by the busbar system. The bus system pre-amplifies or pre-attenuates the differential signal, and then transmits it to the equalizer 409 through the transmission line 401, the capacitor c, and the transmission 200926589 line 〇3. The equalizer 4〇9 includes a series connected inductor L and a resistor R.刍 and ^ Zhou 2 is connected in series to the equalizer 409. The number compensated by the equalizer is determined by . Take out. In this embodiment, we use a 5 Ω resistor as the load ζ〇 under the condition that the equalizer and the transmission line achieve impedance matching (reflection coefficient is equal to zero)' to obtain the equalizer S to disk U/)$ technique 2 ( Ruler +7 moth) 'Z0+2(Re+j2^e) where is the resistance value of resistor R, 4 is the inductance value of inductor L, z. It is the impedance value of the electric load Z. The transmission line s parameters can be measured by a network analyzer. Then, using the mathematical software to the transmission line S parameter, the equalization ns parameter, the frequency domain function of the digital signal, and the ideal gain value, the above integral operation and the differential operation are performed to obtain the impedance value of the equalizer resistance R and the inductance L. . Please refer to FIG. 5A and FIG. 5B simultaneously, which are diagrams showing the time domain waveforms of the pre-attenuated signals after compensation in the two embodiments of the present invention. In Fig. 5A and Fig. 5B, the 5 Gbps, 400 mV digital signal is transmitted through a transmission line having a length of 36 inches. In Figure 5A, the digital signal is pre-decreased by 3.5 db and transmitted by the transmission line. The above-mentioned integral operation and differential operation are performed by the mathematical software, and the impedance values of the equalizer resistance R and the inductance L are 119 Ω and 68 nH, respectively. Compared with the uncompensated digital signal on the transmission line (eye height and eye width are 73.7 mv and 93.16 ps respectively), the eye height and eye width of the digital signal after the equalizer compensation have been greatly improved, respectively 195 92 mv and 155.07. Ps. The digital signal of Figure 5B is pre-attenuated by 6 db and then transmitted by the transmission line 200926589. The above-mentioned integral operation and differential operation are performed by the mathematical software, and the impedance values of the equalizer resistance R and the inductance L are 300 Ω and i72 nH, respectively. Compared with the uncompensated digital signal, the eye height and eye width of the digital signal compensated by the equalizer have been greatly improved, respectively, at 218.89 mv and 160.53 ps. * Please refer to FIG. 6A and FIG. 6B simultaneously, which are diagrams showing the time domain waveforms of the pre-amplified signals after compensation in the two embodiments of the present invention. In Figures 6A and 6B, the 5Gbps, 400mv digital signal is transmitted through a transmission line of 36 inches. In Figure 6A, the digital signal is preamplified by 3.5 db and transmitted by the transmission line. The above-mentioned integral operation and differential operation are performed by the mathematical software, and the impedance values of the equalizer resistance R and the inductance L are 105 Ω and 57 nH, respectively. Compared with uncompensated digital signals (eye height and eye width are 73.7 mv and 93.16 ps, respectively), the eye height and eye width of the equalizer compensated digital signal have been greatly improved, respectively 251.16 mv and 161.49 ps. The digital signal of Fig. 6B is preamplified by 6 db and then transmitted by the transmission line. As described above, the impedance values of the equalizer resistance R and the inductance L can be found to be 119 Ω and 68 nH, respectively. Compared with the uncompensated digital signal, the eye height and eye width of the equalized signal are greatly improved, which are 304.18 mv and 165.20 ps respectively. As can be seen from the above embodiments, the manufacturing method of the transmission line equalizer can be Estimate the impedance of the required equalizer components, accurately compensate for the signal loss caused by the transmission line, and reduce the time and frequency of circuit simulation analysis. Although the present invention has been disclosed in a preferred embodiment as described above, it is not intended to limit the invention, and any of the ordinary skill in the art to which the invention pertains may be made without departing from the spirit and scope of the invention. Further, the scope of protection of the present invention is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; Signal time domain waveform diagram. The figure is a time-domain waveform diagram of a digital signal according to another embodiment of the present invention. Figure 2 is a diagram showing the signal frequency response of an embodiment of the present invention. Fig. 3 is a flow chart showing the manufacture of a transmission line equalizer according to an embodiment of the present invention. Figure 4 is a schematic diagram of a transmission line and its equalizer circuit in accordance with an embodiment of the present invention. Fig. 5A is a diagram showing the time domain waveform of the pre-attenuation signal after compensation according to an embodiment of the present invention. Figure 5B is a diagram showing the time domain waveform of the pre-attenuated signal after compensation according to another embodiment of the present invention. Fig. 6A is a diagram showing the time domain waveform of the preamplified signal after compensation according to an embodiment of the present invention. 6B is a pre-amplification of the compensation according to another embodiment of the present invention. 12 200926589 Signal Time Domain Waveform Ο Description of Main Component Symbols 101: Original Digital Signal 103b: Pre-amplified Signal 201: Transmission Line S Parameter 205: Ideal Gain Value 211: pre-attenuation signal\pre-amplification signal 3〇1 to 311: equalizer manufacturing step l〇3a: pre-attenuation signal 1〇5: superimposed digital signal 203: equalizer S parameter 207: compensated digital signal 4 〇1: Transmission line 405: Differential signal 409: Equalizer L: Inductance Z: Load V. : Compensated digital signal output 403 : Transmission line 407 : Differential signal C : Capacitor R : Resistor 13