200913311 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種發光二極體結構，尤指關於一 種在基板上自然形成一餘刻遮罩，透過選擇性钱勉， 形成不同凹凸面的不規則幾何形狀於該基板表面，藉 由該凹凸面改變半導體層之光波導方向，提高外部量 子效率的發光二極體及其製造方法。 【先前技術】 為了實現固態照明，開發以及改善發光二極體之發光 效率便成為當務之急。改善發光二極體之發光效率的方式 可分成兩部分：其一為提高發光二極體的内部量子效率； 其二為增加發光二極體之光萃取效率（光取出率）。 在内部量子效率方面’改善蟲晶材料品質對於内部量 子效率有最直接且明顯的提升，其中一種側向成長技術 (Epitaxial Lateral Overgrowth ; ELOG)可改善磊晶材料 品質，主要是利用側向再成長氮化鎵層於二氧化矽條紋圖 案化之基板上’以減少穿透位錯（Threading Dislocation) 之缺陷，進而提升内部量子效率。 另一種技術係美國專利US6,870，193所揭露的橫向磊 晶法（Lateral Epitaxial Pattern Substrate ; LEPS)，該技術利 用乾式或濕式蝕刻的方式來進行基板上圖案樣式的蝕 刻，達到與ELOG類似的效果，其好處不僅製程容易，而 且可以降低磊晶成長的時間。利用此方法能有效地降低氮 化鎵層中的穿透位錯（Threading Dislocation)，能有效提 升發光二極體的發光效率。 在光萃取效率方面，因為一般半導體材料與封裝材料 200913311 的折射率相差甚多’使得全反射角小，所以發光二極體所 產生的光到達與空氣的界面時，大於臨界角的光將產生全 反射回到發光二極體晶粒内部。光子在交界面離開半導體 的機率變小，讓光子只能在内部全反射直到被吸收殆盡， 使光轉成熱的形式，造成發光效果不佳。 因此，改變基板的幾何形狀是一個有效提升發光效率 的方法一在光萃取效率方面。根據美國專利US6,870,193， 該案所揭露的技術係一種具備凹部及/或凸部結構形成於 基板之半導體發光元件，相較於平坦基板情況下，此種結 構的光在半導體層的橫方向傳播時，光可藉由凹部或凸部 產生散射或繞射效果，可大幅提高外部量子效率。此外， 於基板的凹部及/或凸部結構處，透過侧向成長技術，可降 低氣化鎵層的穿透位錯，同時提升發光二極體之内部量子 效率。 但是，該技術對於基板製備成具有凹部或凸部幾何 形狀之方法，係先形成一鈍化層結構於基板上方，再利 用使用黃光微影方式，圖案定義出凹部或凸部幾何形狀 之外形，再利用乾蝕刻或濕蝕刻方式對基板蝕刻出凹部 或凸部結構。此種製造過程較為繁瑣，亦會增加成本， 相當不符合發光二極體的商業應用。 【發明内容】 於是為解決上述之缺失，本發明係提供一種發光二極 體之結構及其製造方法，其表面自然形成一化學反應層， 以化學反應層為自然蝕刻遮罩，透過濕蝕刻或乾蝕刻法， 形成不同凹凸面的不規則幾何形狀於該基板表面上，同時 挺升發光二極體之外部篁子欵率以及内部量子效率。 200913311 本發明的發光二極體的製造方法，至少包括：先提供 一基板，該基板係為藍寶石（Al2〇3)、碳化矽(Sic)、矽（Si)、 砷化鎵（GaAs)和氮化鋁（A1N)、氮化鎵（GaN)基板其中之 一。，將該基板放置於一第一溶液内進行反應，使其表面自 然形成一化學反應層，然後以該化學反應層11〇作為遮 罩，對該基板100進行乾式蝕刻法、濕式蝕刻法及其混合 使用法其中之一的選擇性蝕刻，使該基板上方無該化學反 應層之處形成複數具有凹部與上方有該化學反應層的凸 部。再將該基板放置於一第二溶液内蝕刻，除去該化學反 應層，形成具有該些凹部與凸部的高度差為微米至Μ 微米的不，則幾何形狀於該基板表面，且將該基板表面清 潔乾淨。最後於該基板表面上形成一半導體發光結構，且 利用側向成長磊晶技術使該半導體發光結構填平前述的 凹部且無任何孔洞形成。 其中，該第一溶液和第二溶液係為酸性溶液族群、鹼 性溶液族群至少一材料及其族群之組合其中之一。該酸性 溶液族群係氫氟酸(HF)、硫酸(HJO4)、鹽酸(HC1)、磷酸 (H3P〇4)、硝酸(ΗΝ〇3)、王水(Aqua regia)、二氧化矽蝕刻 劑（Buffered Oxide Etch，BOE)、鋁蝕刻液㈧ Etcham)、過 氧化氫(Η"2)、甲酸(hcooh)、乙酸(CH3C00H)、丁二酸 (C4H6〇4)及檸檬酸(Citric Acid)。該鹼性溶液族群係氫氧化 鉀(KOH)、氫氧化納(Na0H)、氫氧化舞(Ca(〇H)2)、氫氧化 敍(顧4〇印、氫氧化四甲基敍溶液（tetramethylamm〇nium hydroxide，TMAH)。而該基板放置於該第一溶液與該第二 溶液的時間係為1秒鐘至200分鐘。 其中，該半導體發光結構係依序磊晶結合至少一 n型 200913311 活性層與至少一p型半導體層，其中該活性 "為發先區形成於該半導體層與該P型半導體層之 間且該P型半導體層與一 p型歐姆接觸電極電性連接， 該η型半導體層與—n型歐姆接觸電極 電性連接，用以提 供一順向偏壓。 j基板在置入該第—溶液前進一步尚可包括一預先 處理製程。該縣處理製程包括成長—厚度為iAi 基板表面上，再將該基板置人該第一溶液。 ”材料可為矽、氮化矽、氧化石夕、氧化紹、金 苯環丁烯、聚亞醯胺之單層、多層結構 及其所組合之族群之—。 円索對祕化層進—步經由黃絲f彡製程週期性 Θ /、 露部份該基板表面，再將該基板置入該第一溶 液。/、中該鈍化層的週期性圖案為圓形、多邊行及其 之門週期性圖案，週期性圖案的寬度為0.1微米至1、5 微未’間距為0.1微米至15微米。 鈍化層進—步經由黃光微影製程週期性 ’對該基板外露的表面進行侧形成複數個凹 槽’且除去魏化層後，再㈣基板置人該第—溶液，使 該基板的表面凹凸更明顯。 該預先處理製程也可以是成長一厚度為1Α至10μ1η 的磊晶層於該基板表面上，再將該基板置入該第一溶液。 其中該磊晶層材料為包含氮化鎵、氮化銦、氮化鋁及宜 所混和組合材料之族群之一。 ' 也可以對該磊晶層進一步經由黃光微影製程週期性 圖案化，外露部份該基板表面，再將該基板置入該第一溶 200913311 液。其中該磊晶層的週期性圖案為圓形、多邊行及其 組合之週期性圖案’週期性圖案的寬度為〇1微米至 15微米，間距為0.〗微米至15微米。 經由上述方法所形成的發光二極體之結構，其包括該 基板該基板具有触卿成凹部與凸部的不^幾何^ 狀，以及;5« ΘΒ形成於前述基板的表面的該半導體發社 構、，該半導體發光結構係依序蟲晶結合該η型半導體層、° =活f生層與該ρ型半導體層，其中該活性層作為發光區形 f於該11型半導體層與該P型半導體層之間，且該p型半 導體層與該p型歐姆接觸電極電性連接’該〇型半導體芦 與該η型歐姆接觸電極電性連接，用以提供 : 且該η型半導體層填平前述的凹部與凸部 ^ 體層無任何孔洞形成。 制4牛導 料ίΐ:該凹部與凸部的高度差為0·1微米至15微米。 ;其^2雙異f接面構造、單量子井結構及多量子井 自然於穎製程方式… 逆化學反應層為自然韻刻 遮罩透過濕蝕刻或乾蝕刻法，形 則幾何形狀於該A柘矣品·^丄个u凹凸面的不規 對發光精該些凹部與凸部結構 導部光的散射、繞射效果，可減少半 射的二ί之界面中的光橫向傳播的情況，減少全反 凸面的不規則幾何形狀於該=上方1 升内V量子：：透位錯’提升磊晶材料的品質，進而提 。子效率。且本發明因為製成簡單，可降低生產 200913311 成本，適合產業大量生產。 【實施方式】 兹有關本發明之詳細内容及技術說明，現以實施例 來作進一步說明，但應瞭解的是，該等實施例僅為例示 说明之用’而不應被解釋為本發明實施之限制。 第一實施例： 請參閱第1圖至第5圖所示’為本發明之第一實施例 的示意圖。本發明的製造方法至少包括：首先提供一基板 100 ’该基板100係為藍寶石、碳化;^、碎、；5申化鎵和氮 化鋁基板其中之一（如第1圖所示）。 然後將該基板100放置於一第一溶液内進行反應，使 該基板100表面自然形成一高密度奈米等級的化學反應層 110。該基板100放置於該第一溶液的時間係為1秒至2⑻ 分鐘’然後以該化學反應層110作為遮罩，對該基板100 進行選擇性姓刻，可使用係乾式餘刻法、濕式银刻法及其 混合使用法其中之一的選擇性钱刻，使該基板1〇〇表面無 該化學反應層110之處形成複數凹部120與上方有該化學 反應層110的凸部130(如第2圖所示）。 以該基板1〇〇是藍寶石基板（ai2o3)為例（以下說明 該基板100都以藍寶石基板（A1203)為說明例），將藍寶 石基板（Al2〇3)放置於硫酸（H2S〇4) (96%)中（以硫酸做 為第一溶液），液體溫度約25〜400 °C，反應時間從1秒至 200分鐘，該基板100的表面會形成高密度奈米等級的該 化學反應層 no (ai2(so4)3 或 A12(S04) · 17H20 等）。然後 以該化學反應層110作為遮罩，對該基板1〇〇進行乾蝕刻 200913311 法或濕姓刻法的選擇性蝕刻。 ' 以濕式餘刻藍寶石基板（Al2〇3)為例，可使其表面形 成凹部120與凸部13〇。又以改變藍寶石基板在第一溶液 如硫酸（H2S〇4)的钱刻時間為例，從2.5分鐘至20分鐘， 該基板100可以形成不同的平均姓刻深度（average etching deeP)平均顆粒大小（average grain size)，密度（density)， 以及表面粗糙度根均方值（RMS roughness)的基板100。 經由原子力顯微鏡觀察基板100表面，整理如下表： 蝕刻時間 (min) 平均深度 (um) 平均顆粒 大小（um) 密 度 (1/um2) 表面粗 度根均方 值(nm) 2.5 0.360 5.36 0.0092 106.24 5.0 0.683 6.04 0.0096 207.30 10.0 1.759 12.30 0.0108 471.15 20.0 2.351 15.03 0.0080 700.77 再將被蝕刻後的基板1〇〇放置於一第二溶液内蝕刻， 用以除去該化學反應層110,形成具有凹部12〇與凸部13〇 的不規則幾何形狀於該基板1〇〇表面（如第3圖所示）。以 該第二溶液為磷酸（H3P〇4)為說明例，該磷酸溫度為25。〇 至400°C ’該基板1〇〇放置於該第二溶液的時間係為〇」 分鐘至200分鐘’以將該化學反應層11()去除乾淨為主， 且將該基板100表面清潔乾淨。 最後於該基板100表面上形成一半導體發光結構 200，該半導體發光結構200係依序磊晶結合至少一 η型 11 200913311 半導體層210、一活性層220與至少一 p型半導體層23〇(如 第4圖所示）。其中該活性層22〇做為發光區形成於該n 型半導體層210與該ρ型半導體層23〇之間，且該ρ型半 導體層230與一 ρ型歐姆接觸電極231電性連接，該η型 半導體層210透過一接觸窗240與一 η型歐姆接觸電極211 電性連接，用以提供一順向偏壓（如第5圖所示）。 經由上述方法所形成的發光二極體之結構，其包括該 基=100，該基板1〇〇具有被蝕刻形成複數個凹部12〇與 凸部130的不規則幾何形狀；以及磊晶形成於前述基板1〇〇 的表面的該半導體發光結構2〇〇，該半導體發光結構2〇〇 係依序磊晶結合該η型半導體層21〇、該活性層22〇與該 Ρ型半導體層230。 ’ 其中該活性層220做為發光區形成於該η型半導體層 21〇與該ρ型半導體層230之間，且該ρ型半導體層23〇 與該Ρ型歐姆接觸電極231電性連接，該η型半導體層21〇 透過該接觸窗240與該！！型歐姆接觸電極211電性連接， 用以提供一順向偏壓。且該η型半導體層21〇填平前述的 凹部120與凸部13〇 ’使該η型半導體層21〇無任何孔洞 形成。而該凹部⑽)與凸部的高度差為G1微米至15微 f。該活性層220係為雙異質接面構造、單量子井結構及 夕量子井結構其中之一。 本發明係利用側向成長蟲晶技術，經由改變半導體層 ^蟲晶溫度及壓力達成側向成長速度高於縱向成長速 =可使該半導體發光結構2〇〇中厚度較厚的η型半導體 曰210填平則述的凹部12〇將該基板1⑼表面的該些凹部 〇 ”凸4 13G的落差填平’使該基板1GG表面的該些凹 12 200913311 部120與凸部130結構無任何孔洞形成，可得到高品質低 穿透位錯（Threading Dislocation)的蟲晶材料。例如成長 氮化鎵（約3.5 um)做為該η型半導體層210填平前述的 凹部120將該基板100表面的凹部120與凸部130，該基 板100表面的該些凹部120與凸部130經由EPD( Etching pits density)、PL(Photoluminescence)、XRD 量測分析整 理如下表：200913311 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a light-emitting diode structure, and more particularly to a natural mask formed on a substrate, which is formed by selective moting to form different concave and convex surfaces. The irregular geometry is on the surface of the substrate, and the light-emitting diode of the semiconductor layer is changed by the uneven surface to improve the external quantum efficiency and the method of manufacturing the same. [Prior Art] In order to realize solid-state lighting, it is imperative to develop and improve the luminous efficiency of a light-emitting diode. The manner of improving the luminous efficiency of the light-emitting diode can be divided into two parts: one is to increase the internal quantum efficiency of the light-emitting diode; the other is to increase the light extraction efficiency (light extraction rate) of the light-emitting diode. In terms of internal quantum efficiency, 'improving the quality of insect crystal materials has the most direct and obvious improvement of internal quantum efficiency. One of the Epitaxial Lateral Overgrowth (ELOG) can improve the quality of epitaxial materials, mainly by using lateral growth. The gallium nitride layer is on the chopper striped patterned substrate to reduce defects in threading dislocation, thereby improving internal quantum efficiency. Another technique is the Lateral Epitaxial Pattern Substrate (LEPS) disclosed in U.S. Patent No. 6,870,193, which utilizes dry or wet etching to etch pattern patterns on a substrate to be similar to ELOG. The effect, not only the process is easy, but also can reduce the time of epitaxial growth. By using this method, the Threading Dislocation in the gallium nitride layer can be effectively reduced, and the luminous efficiency of the light-emitting diode can be effectively improved. In terms of light extraction efficiency, since the refractive index of the general semiconductor material and the packaging material 200913311 are much different, the total reflection angle is small, so when the light generated by the light-emitting diode reaches the interface with the air, light larger than the critical angle will be generated. Total reflection back into the interior of the luminescent diode die. The probability that a photon will leave the semiconductor at the interface becomes smaller, so that the photon can only be totally reflected inside until it is absorbed, and the light is converted into a hot form, resulting in poor illumination. Therefore, changing the geometry of the substrate is a method for effectively improving the luminous efficiency in terms of light extraction efficiency. According to U.S. Patent No. 6,870,193, the disclosure of the present application is a semiconductor light-emitting device having a recessed portion and/or a convex portion formed on a substrate. In the case of a flat substrate, the light of such a structure is in the lateral direction of the semiconductor layer. When propagating, light can be scattered or diffracted by concave or convex portions, which can greatly improve external quantum efficiency. In addition, through the lateral growth technique at the concave portion and/or the convex portion structure of the substrate, the threading dislocation of the gallium hydride layer can be reduced, and the internal quantum efficiency of the light-emitting diode can be improved. However, the method for preparing a substrate having a concave or convex geometry is to first form a passivation layer structure on the substrate, and then use a yellow lithography method to define a concave or convex geometric shape and reuse the pattern. The substrate is etched into a recess or a convex structure by dry etching or wet etching. This manufacturing process is cumbersome and will increase the cost, and is quite incompatible with the commercial application of the light-emitting diode. SUMMARY OF THE INVENTION In order to solve the above-mentioned defects, the present invention provides a structure of a light-emitting diode and a manufacturing method thereof, wherein a chemical reaction layer is naturally formed on the surface, a chemical etching layer is used as a natural etching mask, and a wet etching or The dry etching method forms irregular geometries of different irregularities on the surface of the substrate while simultaneously raising the external enthalpy efficiency and internal quantum efficiency of the light-emitting diode. 200913311 The method for manufacturing a light-emitting diode of the present invention comprises at least providing a substrate which is sapphire (Al2〇3), tantalum carbide (Sic), germanium (Si), gallium arsenide (GaAs) and nitrogen. One of aluminum (A1N) and gallium nitride (GaN) substrates. The substrate is placed in a first solution to react to form a chemical reaction layer on the surface, and then the chemical reaction layer 11 is used as a mask, and the substrate 100 is subjected to dry etching and wet etching. The selective etching of one of the mixed use methods forms a plurality of convex portions having the concave portion and the chemical reaction layer thereon without the chemical reaction layer above the substrate. And placing the substrate in a second solution to remove the chemical reaction layer, forming a height difference between the concave portion and the convex portion of micrometers to 微米 micrometers, geometrically forming the surface of the substrate, and the substrate The surface is clean. Finally, a semiconductor light emitting structure is formed on the surface of the substrate, and the semiconductor light emitting structure is filled with the recesses without any holes by lateral growth epitaxy. Wherein the first solution and the second solution are one of a combination of an acidic solution group, an alkali solution group, at least one material, and a group thereof. The acidic solution group is hydrofluoric acid (HF), sulfuric acid (HJO4), hydrochloric acid (HC1), phosphoric acid (H3P〇4), nitric acid (ΗΝ〇3), aqua regia, and cerium oxide etchant (Buffered). Oxide Etch, BOE), aluminum etching solution (8) Etcham), hydrogen peroxide (Η"2), formic acid (hcooh), acetic acid (CH3C00H), succinic acid (C4H6〇4) and citric acid (Citric Acid). The alkaline solution group is potassium hydroxide (KOH), sodium hydroxide (Na0H), hydrogen hydride dance (Ca(〇H)2), and hydrazine (Gu 4〇印, tetramethylammonium hydroxide solution (tetramethylamm) The substrate is placed in the first solution and the second solution for a period of from 1 second to 200 minutes. The semiconductor light-emitting structure is sequentially epitaxially bonded to at least one n-type 200913311 activity. a layer and at least one p-type semiconductor layer, wherein the active " is formed between the semiconductor layer and the P-type semiconductor layer, and the P-type semiconductor layer is electrically connected to a p-type ohmic contact electrode, the η The semiconductor layer is electrically connected to the -n-type ohmic contact electrode to provide a forward bias. The j substrate may further include a pre-treatment process before being placed in the first solution. The county processing process includes growth-thickness. The substrate is placed on the surface of the iAi substrate, and the substrate is placed on the first solution. The material may be a single layer or a multilayer structure of tantalum, tantalum nitride, oxidized stone, oxidized, gold benzocyclobutene, polyamidamine. And the group of its combination - The layer advances through a yellow wire to periodically circumscribe the surface of the substrate, and then places the substrate into the first solution. The periodic pattern of the passivation layer is circular, polygonal, and The periodic pattern of the gate, the width of the periodic pattern is 0.1 micron to 1, 5 micro-not pitched from 0.1 micron to 15 micron. The passivation layer is stepped through the yellow photolithography process to periodically 'side the exposed surface of the substrate After forming a plurality of grooves' and removing the Weihua layer, the (4) substrate is placed on the first solution to make the surface unevenness of the substrate more obvious. The pretreatment process may also be to grow an epitaxial layer having a thickness of 1 Α to 10 μ1η. And depositing the substrate into the first solution on the surface of the substrate, wherein the epitaxial layer material is one of a group comprising gallium nitride, indium nitride, aluminum nitride, and a suitable combination material. The epitaxial layer is further periodically patterned by a yellow lithography process to expose a portion of the substrate surface, and then the substrate is placed in the first solution 200913311. The periodic pattern of the epitaxial layer is a circular, polygonal row. And its combination The periodic pattern 'periodic pattern has a width of 〇1 μm to 15 μm and a pitch of 0.1 μm to 15 μm. The structure of the light emitting diode formed by the above method includes the substrate and the substrate has a touch a non-geometric shape of the concave portion and the convex portion, and a semiconductor structure formed on the surface of the substrate, the semiconductor light-emitting structure sequentially bonding the n-type semiconductor layer, °=live f a green layer and the p-type semiconductor layer, wherein the active layer is formed as a light-emitting region between the 11-type semiconductor layer and the P-type semiconductor layer, and the p-type semiconductor layer is electrically connected to the p-type ohmic contact electrode The 半导体-type semiconductor reed is electrically connected to the n-type ohmic contact electrode to provide: and the n-type semiconductor layer fills the recess and the protrusion layer without any holes. 4 cattle guide ΐ: The difference between the height of the concave portion and the convex portion is from 0.1 micrometer to 15 micrometer. The ^2 double-iso n junction structure, single quantum well structure and multi-quantum well natural in the process of the process... The reverse chemical reaction layer is a natural rhyme mask through the wet etching or dry etching method, the shape geometry is in the A柘矣 · 丄 u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u Reducing the irregular geometry of the total anti-convex surface within the 1 liter above the V-quantum:: Translocation dislocations enhance the quality of the epitaxial material and further increase. Sub-efficiency. Moreover, the invention is simple in manufacture, can reduce the cost of production 200913311, and is suitable for mass production in the industry. DETAILED DESCRIPTION OF THE INVENTION The detailed description and technical description of the present invention will be further described by the embodiments, but it should be understood that these embodiments are merely illustrative and should not be construed as The limit. First Embodiment: Please refer to Figs. 1 to 5 for a schematic view of a first embodiment of the present invention. The manufacturing method of the present invention at least includes first providing a substrate 100' which is one of sapphire, carbonized, pulverized, and 5 gallium nitride and aluminum nitride substrates (as shown in Fig. 1). Then, the substrate 100 is placed in a first solution for reaction, so that the surface of the substrate 100 naturally forms a high-density nano-grade chemical reaction layer 110. The substrate 100 is placed in the first solution for a period of 1 second to 2 (8) minutes. Then, the chemical reaction layer 110 is used as a mask, and the substrate 100 is selectively surnamed, and the dry-type remnant method and the wet method can be used. The selective etching method of one of the silver engraving method and the mixed use method forms a plurality of concave portions 120 and convex portions 130 having the chemical reaction layer 110 thereon without the chemical reaction layer 110 on the surface of the substrate 1 Figure 2). The substrate 1A is a sapphire substrate (ai2o3) as an example (hereinafter, the substrate 100 is exemplified by a sapphire substrate (A1203)), and the sapphire substrate (Al2〇3) is placed in sulfuric acid (H2S〇4) (96). In the %) (with sulfuric acid as the first solution), the liquid temperature is about 25 to 400 ° C, and the reaction time is from 1 second to 200 minutes, the surface of the substrate 100 forms a high-density nano-grade chemical reaction layer no ( Ai2(so4)3 or A12(S04) · 17H20, etc.). Then, the substrate 1 is dry-etched by the chemical reaction layer 110 as a mask, and the selective etching of the wet film is performed by the method of the method of 200913311. Taking the wet residual sapphire substrate (Al2〇3) as an example, the concave portion 120 and the convex portion 13〇 may be formed on the surface. Taking the time of changing the sapphire substrate in the first solution such as sulfuric acid (H2S〇4) as an example, the substrate 100 can form different average etching deeP average particle sizes from 2.5 minutes to 20 minutes ( The average grain size), the density, and the RMS roughness of the substrate 100. The surface of the substrate 100 was observed through an atomic force microscope, and the following table was prepared: Etching time (min) Average depth (um) Average particle size (um) Density (1/um2) Surface roughness root mean square value (nm) 2.5 0.360 5.36 0.0092 106.24 5.0 0.683 6.04 0.0096 207.30 10.0 1.759 12.30 0.0108 471.15 20.0 2.351 15.03 0.0080 700.77 The etched substrate 1 〇〇 is placed in a second solution for etching to remove the chemical reaction layer 110 to form a recess 12 and a convex portion. The 13 不 irregular geometry is on the surface of the substrate 1 (as shown in Figure 3). Taking the second solution as phosphoric acid (H3P〇4) as an illustrative example, the phosphoric acid temperature is 25. 〇 to 400 ° C 'The substrate 1 〇〇 is placed in the second solution for 〇 minute to 200 minutes to remove the chemical reaction layer 11 (), and the surface of the substrate 100 is cleaned. . Finally, a semiconductor light emitting structure 200 is formed on the surface of the substrate 100. The semiconductor light emitting structure 200 is sequentially epitaxially bonded to at least one n-type 11 200913311 semiconductor layer 210, an active layer 220 and at least one p-type semiconductor layer 23 (eg Figure 4). The active layer 22 is formed as a light-emitting region between the n-type semiconductor layer 210 and the p-type semiconductor layer 23, and the p-type semiconductor layer 230 is electrically connected to a p-type ohmic contact electrode 231. The semiconductor layer 210 is electrically connected to an n-type ohmic contact electrode 211 through a contact window 240 for providing a forward bias (as shown in FIG. 5). a structure of the light-emitting diode formed by the above method, comprising the base = 100, the substrate 1 has an irregular geometry etched to form a plurality of recesses 12 and convex portions 130; and epitaxial formation is formed in the foregoing The semiconductor light-emitting structure 2 on the surface of the substrate 1 〇〇 is sequentially epitaxially bonded to the n-type semiconductor layer 21, the active layer 22, and the germanium-type semiconductor layer 230. The active layer 220 is formed as a light-emitting region between the n-type semiconductor layer 21 and the p-type semiconductor layer 230, and the p-type semiconductor layer 23 is electrically connected to the germanium-type ohmic contact electrode 231. The n-type semiconductor layer 21 〇 passes through the contact window 240 and the! ! The ohmic contact electrode 211 is electrically connected to provide a forward bias. Further, the n-type semiconductor layer 21 is filled with the recess 120 and the projection 13'' so that the n-type semiconductor layer 21 is formed without any holes. The height difference between the concave portion (10) and the convex portion is G1 μm to 15 μf. The active layer 220 is one of a double heterojunction structure, a single quantum well structure, and an annihilation quantum well structure. The invention utilizes the lateral growth crystal technology to achieve a lateral growth rate higher than a longitudinal growth rate by changing the temperature and pressure of the semiconductor layer, and a thicker n-type semiconductor germanium in the semiconductor light-emitting structure 2 The recessed portion 12 of the surface of the substrate 1 (9) fills the gaps of the concave portions 凸 "convex 4 13G" on the surface of the substrate 1 GG to make the concave portions of the surface of the substrate 1GG and the convex portion 130 without any holes. A high quality low Threading Dislocation crystal material can be obtained. For example, a grown gallium nitride (about 3.5 um) is used as the n-type semiconductor layer 210 to fill the recess 120 of the substrate 100. 120 and the convex portion 130, the concave portions 120 and the convex portions 130 on the surface of the substrate 100 are sorted and analyzed by EPD (Etching pits density), PL (Photoluminescence), XRD measurement and analysis as follows:
Sample GaN on Sapphire Sapphire substrate Etch time (min.) Etch pit density (cm'2) XRD-FWHM (arcsec) PL intensity (a.u.) PL FWHM (meV) Etch deep (urn) Average Grain RMS size rough, (ittn) (nm) Screw & Mix type Edge type (002) (105) ΙβέΑύι 0 3.62xl0§ 2.58xl〇S 201.0 272.9 2.07 6S 2.5 2.66xl〇S 1.72xl〇S 181.3 238.8 6.07 62 0.36 5.03 106.24 5 1.94x1〇8 9.4x10? 177.7 196.5 9.05 58 0.68 6.04 207.30 因為降低該些凹部120與凸部130結構對該活性層 220的影響’可良好的保持該活性層22〇(發光區域）的結晶 性，減少穿透位錯的因素，使内部量子效率提升。而藉由 該些凹部120與凸部130結構，該半導體發光結構2〇〇内 部活性層220所發出的光將會被該些凹部120與凸部130 結構散射或繞射’減少η型半導體層210與基板1〇〇之界 面中光橫向傳播的情況’減少全反射的機率，射向基板1〇〇 上方或下方的光束增加’可提高發光二極體之光取出率， 增加總發光量。 第二實施例： 13 200913311 請參閱第6圖至第8圖所示，為本發明之第二實施例 的示意圖。該實施例的製造方法以第一實施例為基本，但 該基板100在置入該第一溶液前先進行一預先處理製程。 該預先處理製程係成長一厚度為1人至ΙΟμιη的鈍化層300 於該基板100表面上（如第6圖所示）。該鈍化層300材料 可為矽、氮化矽、氧化矽、氧化鋁、金屬、光阻、 苯環丁烯、聚亞醯胺之單層、多層結構及其所組合 之族群之一。 然後將該基板100放置於該第一溶液内進行反應，使 該基板100表面的鈍化層300内自然形成高密度奈米等級 的化學反應層110，然後以該鈍化層300與該化學反應層 110作為遮罩，對該基板1〇〇進行選擇性蝕刻，使該基板 100表面無該鈍化層300與該化學反應層110之處形成複 數凹部120與上方有該化學反應層110及該鈍化層300的 凸部130、131 (如第7圖所示）。 再將被蝕刻後的基板100放置於該第二溶液内蝕刻， 用以除去該化學反應層11〇,形成具有凹部120與凸部130 的不規則幾何形狀於該基板100表面，然後除去該鈍化層 3〇〇露出該些凸部131，且將該基板表面清潔乾淨（如第8 圖所示）。最後如同第一實施例，於該基板1〇〇表面上形成 該半導體發光結構200(如第4圖與第5圖所示）。 第三實施例： 請參閱第9圖至第13圖所示，為本發明之第三實施 例的示意圖。該實施例的製造方法以第二實施例為基本， 該預先處理製程一樣是成長該鈍化層300於該基板1〇〇表 200913311 面上（如第9圖所示）。然後將該鈍化層300進一步經由黃 光微影製程週期性圖案化，外露部份該基板1〇〇表面，其 中該鈍化層的週期性圖案為圓形、多邊行及其組合之 週期性圖案，週期性圖案的寬度為01微米至15微米， 間距為0.1微米至15微米（如第1〇圖所示）。 然後將該基板100放置於該第一溶液内進行反應，使 外露的該基板100表面自然形成高密度奈米等級的化學反 應層110(如第11圖所示）^然後以該鈍化層3〇〇與該化學 反應層110作為遮罩，對該基板10〇進行選擇性蝕刻，使 該基板100表面無該鈍化層3〇〇與該化學反應層no之處 形成複數個凹部120與上方有該化學反應層110及該鈍化 層300的凸部13〇、131(如第12圖所示）。 再將被敍刻後的基板100放置於該第二溶液内蝕刻， 用以除去該化學反應層110,形成具有凹部120與凸部130 的不規則幾何形狀於該基板1〇〇表面，然後除去該鈍化層 300露出該些凸部131 ’且將該基板表面清潔乾淨（如第 13圖所不）。最後如同第一實施例，於該基板100表面上 形成該半導體發光結構2〇〇(如第4圖與第5圖所示）。 第四實施例： 請參閱第14圖至第18圖所示，為本發明之第四實施 例的示意圖。該實施例的製造方法以第三實施例為基本， 該巧先處理製程係成長該鈍化層300於該基板100表面上 (如第圖所示）。然後將該鈍化層300進一步經由黃光微 影製程週期性圖案化，外露部份該基板議表面（如第15 圖所不）。然细該基板⑽外露的表面進行侧形成複數 15 200913311 個凹槽101 ’且除去該鈍化層300露出該些凸部131(如第 16圖所示）。 然後將該基板100放置於該第一溶液内進行反應，使 該基板100上的該些凸部13〗與凹槽1〇1表面自然形成— 高密度奈米等級的化學反應層110(如第17圖所示）。 然後以該化學反應層110作為遮罩，對該基板1〇〇進 行選擇性钕刻’使該基板100表面無該鈍化層與該化 學反應層110之處形成複數凹部12〇與上方有該化學反應 層110的凸部130、131，形成一落差明顯的凹凸面。再將 被蝕刻後的基板100放置於該第二溶液内蝕刻，用以除去 該化學反應層110，形成具有凹部120與凸部130、131的 不規則幾何形狀於該基板100表面（如第18圖所示）。 最後如同第一實施例，於該基板1〇〇表面上形成該半 導體發光結構200(如第4圖與第5圖所示）。 第五實施例： °月參閱第19圖至第21圖所示，為本發明之第五實施 例的示意圖。該實施例的製造方法以第一實施例為基本， 但該基板1〇〇在置入該第一溶液前先進行一預先處理製 程。該預先處理製程係成長一厚度為lA至10μηι的磊晶 層400於該基板1〇〇表面上（如第19圖所示）。該磊晶層 40(^材料可為包含氮化鎵、氮化銦、氮化鋁及其其所混和 =σ材料之族群之一，以後續製程中該半導體發光 結構2〇〇中厚度較厚的該η型半導體層210材料為主要選 擇。 然後將該基板100放置於該第一溶液内進行反應，使 16 200913311 该基板100表面的該磊晶層400内自然形成高密度奈米等 級的化學反應層110’然後以該磊晶層4〇〇與該化學反應 層no作為遮罩，對該基板100進行選擇性蝕刻，使該基 板100表面無該蠢晶層400與該化學反應層11〇之處形成 複數凹部120與上方有該化學反應層11〇及該磊晶層400 的凸部130、132(如第20圖所示）。 再將被蝕刻後的基板100放置於該第二溶液内蝕刻， 用以除去該化學反應層11〇，形成具有凹部丨2〇與凸部 130、132的不規則幾何形狀於該基板1〇〇表面（如第21 圖所不）。最後如同第一實施例，在具有該磊晶層4〇0的基 板100表面上直接再形成該半導體發光結構2〇〇的各層磊 晶層與製程(如第4圖與第5圖所示）。 第六實施例： 请參閱第22圖至第26圖所示，為本發明之第六實施 例的示意圖。該實施例的製造方法以第五實施例為基本’ 該預先處理製程係成長該磊晶層4〇〇於該基板1〇〇表面上 (如第22圖所示）。然後將該磊晶層4〇〇進一步經由黃光微 影製程週期性圖案化，外露部份該基板1〇〇表面，其中該 蟲晶層400的週期性圖案為圓形、多邊行及其組合之 週期性圖案’週期性圖案的寬度為01微米至15微米， 間距為0.1微米至15微米（如第23圖所示）。 然後將該基板100放置於一第一溶液内進行反應，使 外露的該基板100表面自然形成一高密度奈米等級的化學 反應層11〇(如第24圖所示）。然後以該磊晶層400與該化 學反應層110作為遮罩，對該基板100進行選擇性蝕刻， 17 200913311 使該基板100表面無該蠢晶層400與該化學反應層110之 處形成複數凹部120與上方有該化學反應層110及該磊晶 層400的凸部130、132(如第25圖所示）。 再將被蝕刻後的基板100放置於該第二溶液内蝕刻， 用以除去該化學反應層110,形成具有凹部120與凸部 130、132的不規則幾何形狀於該基板100表面（如第26 圖所示）。最後如同第一實施例，在具有該磊晶層400的基 板100表面上直接再形成該半導體發光結構200的各層磊 晶層與製程(如第4圖與第5圖所示）。 本發明以自然形成的該化學反應層作為自然蝕刻 遮罩，透過乾式蝕刻法、濕式蝕刻法及其混合使用法其 中之一，即可以形成具凹部120與凸部130結構幾何外 形於該基板100的表面，藉由該些凹部120與凸部130 結構，可以使發光二極體元件内部光於該些凹部120與 凸部130產生散射、繞射效果，可減少該η型半導體層 210與該基板100之界面中光橫向傳播的情況，減少全 反射的機率，提高發光二極體之光取出率。且本發明因 為製成簡單，可降低生產成本，適合產業大量生產。 惟上述僅為本發明之較佳實施例而已，並非用來限 定本發明實施之範圍。即凡依本發明申請專利範圍所做 的均等變化與修飾，皆為本發明專利範圍所涵蓋。 18 200913311 【圖式簡單說明】 第1圖〜第5圖，為本發明之第一實施例的示意圖。 第6圖〜第8圖，為本發明之第二實施例的示意圖。 第9圖〜第13圖，為本發明之第三實施例的示意圖。 第14圖〜第18圖，為本發明之第四實施例的示意圖。 弟19圖〜弟21圖’為本發明之第五實施例的示意圖。 第22圖〜第26圖’為本發明之第六實施例的示意圖。 【主要元件符號說明】 100 基板 101 凹槽 110 化學反應層 120 凹部 130 ' 131、132 :凸部 200 半導體發光結構 210 η型半導體層 211 η型歐姆接觸電極 220 活性層 230 Ρ型半導體層 231 Ρ型歐姆接觸電極 240 接觸窗 300 純化層 400 蠢晶層 19Sample GaN on Sapphire Sapphire substrate Etch time (min.) Etch pit density (cm'2) XRD-FWHM (arcsec) PL intensity (au) PL FWHM (meV) Etch deep (urn) Average Grain RMS size rough, (ittn) (nm) Screw & Mix type Edge type (002) (105) ΙβέΑύι 0 3.62xl0§ 2.58xl〇S 201.0 272.9 2.07 6S 2.5 2.66xl〇S 1.72xl〇S 181.3 238.8 6.07 62 0.36 5.03 106.24 5 1.94x1〇8 9.4x10? 177.7 196.5 9.05 58 0.68 6.04 207.30 Since the influence of the structure of the concave portion 120 and the convex portion 130 on the active layer 220 is lowered, the crystallinity of the active layer 22 (light-emitting region) can be well maintained, and the penetration position can be reduced. The wrong factor increases the internal quantum efficiency. By the structures of the recesses 120 and the protrusions 130, the light emitted by the inner active layer 220 of the semiconductor light emitting structure 2 will be scattered or diffracted by the recesses 120 and the structures of the protrusions 130. The case where the light is laterally propagated at the interface between the 210 and the substrate 1 'reduces the probability of total reflection, and the light beam incident on the upper or lower side of the substrate 1 ' increases the light extraction rate of the light-emitting diode and increases the total amount of light emitted. Second Embodiment: 13 200913311 Please refer to Figs. 6 to 8 for a schematic view of a second embodiment of the present invention. The manufacturing method of this embodiment is basically the first embodiment, but the substrate 100 is subjected to a pre-treatment process before the first solution is placed. The pre-treatment process is to grow a passivation layer 300 having a thickness of 1 person to ΙΟμιη on the surface of the substrate 100 (as shown in Fig. 6). The material of the passivation layer 300 may be one of a group of tantalum, tantalum nitride, hafnium oxide, aluminum oxide, metal, photoresist, benzocyclobutene, polyamidene monolayer, multilayer structure, and combinations thereof. Then, the substrate 100 is placed in the first solution for reaction, so that a high-density nano-grade chemical reaction layer 110 is naturally formed in the passivation layer 300 on the surface of the substrate 100, and then the passivation layer 300 and the chemical reaction layer 110 are used. As a mask, the substrate 1 is selectively etched to form a plurality of recesses 120 on the surface of the substrate 100 without the passivation layer 300 and the chemical reaction layer 110, and the chemical reaction layer 110 and the passivation layer 300 are formed thereon. The convex portions 130, 131 (as shown in Fig. 7). The etched substrate 100 is further etched in the second solution to remove the chemical reaction layer 11 〇 to form an irregular geometry having the concave portion 120 and the convex portion 130 on the surface of the substrate 100, and then the passivation is removed. The layer 3 exposes the protrusions 131 and cleans the surface of the substrate (as shown in Fig. 8). Finally, as in the first embodiment, the semiconductor light emitting structure 200 is formed on the surface of the substrate 1 (as shown in Figs. 4 and 5). Third Embodiment: Referring to Figures 9 to 13, there is shown a schematic view of a third embodiment of the present invention. The manufacturing method of this embodiment is basically the second embodiment. The pre-processing process is the same as growing the passivation layer 300 on the surface of the substrate 1 (shown in FIG. 9). Then, the passivation layer 300 is further periodically patterned through a yellow lithography process to expose a portion of the substrate 1 , surface, wherein the periodic pattern of the passivation layer is a periodic pattern of a circle, a polygonal row, and a combination thereof, periodically. The pattern has a width of from 01 micrometers to 15 micrometers and a pitch of from 0.1 micrometers to 15 micrometers (as shown in Figure 1). Then, the substrate 100 is placed in the first solution for reaction, so that the exposed surface of the substrate 100 naturally forms a high-density nano-grade chemical reaction layer 110 (as shown in FIG. 11), and then the passivation layer 3 The substrate and the chemical reaction layer 110 are used as a mask, and the substrate 10 is selectively etched to form a plurality of recesses 120 on the surface of the substrate 100 without the passivation layer 3 and the chemical reaction layer no. The chemical reaction layer 110 and the convex portions 13A and 131 of the passivation layer 300 (as shown in Fig. 12). The substrate 100 after being etched is placed in the second solution for etching to remove the chemical reaction layer 110, forming an irregular geometry having the concave portion 120 and the convex portion 130 on the surface of the substrate, and then removing The passivation layer 300 exposes the protrusions 131' and cleans the surface of the substrate (as shown in FIG. 13). Finally, as in the first embodiment, the semiconductor light emitting structure 2 is formed on the surface of the substrate 100 (as shown in Figs. 4 and 5). Fourth Embodiment: Referring to Figures 14 to 18, there is shown a schematic view of a fourth embodiment of the present invention. The manufacturing method of this embodiment is based on the third embodiment, which processes the passivation layer 300 on the surface of the substrate 100 (as shown in the figure). The passivation layer 300 is then periodically patterned further via a yellow light lithography process to expose portions of the substrate surface (as shown in Figure 15). Then, the exposed surface of the substrate (10) is subjected to side formation of a plurality of layers 15 200913311 grooves 101' and the passivation layer 300 is removed to expose the protrusions 131 (as shown in Fig. 16). Then, the substrate 100 is placed in the first solution for reaction, so that the convex portions 13 on the substrate 100 and the surface of the groove 1〇1 are naturally formed—a high-density nano-grade chemical reaction layer 110 (such as Figure 17 shows). Then, the chemical reaction layer 110 is used as a mask, and the substrate 1 is selectively etched to form a plurality of recesses 12 on the surface of the substrate 100 without the passivation layer and the chemical reaction layer 110. The convex portions 130 and 131 of the reaction layer 110 form a concave-convex surface having a sharp drop. The etched substrate 100 is placed in the second solution for etching to remove the chemical reaction layer 110 to form an irregular geometry having the concave portion 120 and the convex portions 130, 131 on the surface of the substrate 100 (such as the 18th Figure shows). Finally, as in the first embodiment, the semiconductor light emitting structure 200 is formed on the surface of the substrate 1 (as shown in Figs. 4 and 5). Fifth Embodiment: Fig. 19 to Fig. 21 are a schematic view showing a fifth embodiment of the present invention. The manufacturing method of this embodiment is basically the first embodiment, but the substrate 1 is subjected to a pre-treatment process before being placed in the first solution. The pre-treatment process is performed by growing an epitaxial layer 400 having a thickness of from 1 to 10 μm on the surface of the substrate (as shown in Fig. 19). The epitaxial layer 40 (the material may be one of a group including gallium nitride, indium nitride, aluminum nitride, and the mixed = σ material thereof, in the subsequent process, the semiconductor light emitting structure 2 厚度 thicker The material of the n-type semiconductor layer 210 is mainly selected. The substrate 100 is then placed in the first solution for reaction, so that 16200913311 naturally forms a high-density nano-scale chemistry in the epitaxial layer 400 on the surface of the substrate 100. The reaction layer 110 ′ is then selectively etched by using the epitaxial layer 4 〇〇 and the chemical reaction layer no as a mask, so that the surface of the substrate 100 is free of the stray layer 400 and the chemical reaction layer 11 . Whereas the plurality of recesses 120 and the chemical reaction layer 11 and the protrusions 130 and 132 of the epitaxial layer 400 are formed (as shown in Fig. 20). The etched substrate 100 is placed in the second solution. Inner etching, for removing the chemical reaction layer 11〇, forming an irregular geometry having concave portions 〇2〇 and convex portions 130, 132 on the surface of the substrate 1 (as shown in FIG. 21). Finally, as the first Embodiment, in the substrate 100 having the epitaxial layer 4〇0 Each layer of the epitaxial layer and the process of the semiconductor light emitting structure 2A are directly formed on the surface (as shown in FIGS. 4 and 5). Sixth embodiment: Please refer to FIGS. 22 to 26, A schematic diagram of a sixth embodiment of the present invention. The manufacturing method of the embodiment is based on the fifth embodiment. The pre-processing process grows the epitaxial layer 4 on the surface of the substrate 1 (Fig. 22). The epitaxial layer 4 is further periodically patterned by a yellow lithography process to expose a portion of the surface of the substrate, wherein the periodic pattern of the crystal layer 400 is circular, polygonal, and The combined periodic pattern 'periodic pattern width is from 01 micrometers to 15 micrometers, and the pitch is from 0.1 micrometers to 15 micrometers (as shown in Fig. 23.) The substrate 100 is then placed in a first solution for reaction. The exposed surface of the substrate 100 naturally forms a high-density nano-grade chemical reaction layer 11〇 (as shown in Fig. 24). The epitaxial layer 400 and the chemical reaction layer 110 are then used as a mask to the substrate. 100 selective etching, 17 200913311 On the surface of the substrate 100, the plurality of recesses 120 and the convex portions 130 and 132 of the chemical reaction layer 110 and the epitaxial layer 400 are formed at the same place as the chemical reaction layer 110 (as shown in FIG. 25). The etched substrate 100 is placed in the second solution for etching to remove the chemical reaction layer 110 to form an irregular geometry having the concave portion 120 and the convex portions 130, 132 on the surface of the substrate 100 (eg, 26th Finally, as in the first embodiment, each layer of the epitaxial layer and the process of the semiconductor light emitting structure 200 are directly formed on the surface of the substrate 100 having the epitaxial layer 400 (as shown in FIGS. 4 and 5). ). In the present invention, the naturally formed chemical reaction layer is used as a natural etching mask, and one of the dry etching method, the wet etching method, and the mixed use method thereof, that is, the structural shape of the concave portion 120 and the convex portion 130 can be formed on the substrate. The surface of the surface of the recessed portion 120 and the convex portion 130 can cause the internal light of the light emitting diode element to scatter and diffract the concave portion 120 and the convex portion 130, thereby reducing the n-type semiconductor layer 210 and In the case where the light is laterally propagated at the interface of the substrate 100, the probability of total reflection is reduced, and the light extraction rate of the light-emitting diode is improved. Moreover, the present invention is simple in manufacture, can reduce production costs, and is suitable for mass production in the industry. The above is only the preferred embodiment of the invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the patent application of the present invention are covered by the scope of the invention. 18 200913311 [Simplified description of the drawings] Figs. 1 to 5 are schematic views showing a first embodiment of the present invention. 6 to 8 are schematic views showing a second embodiment of the present invention. 9 to 13 are schematic views showing a third embodiment of the present invention. 14 to 18 are schematic views showing a fourth embodiment of the present invention. 19 is a schematic view of a fifth embodiment of the present invention. 22 to 26 are schematic views of a sixth embodiment of the present invention. [Main component symbol description] 100 substrate 101 recess 110 chemical reaction layer 120 recess 130' 131, 132: convex portion 200 semiconductor light emitting structure 210 n-type semiconductor layer 211 n-type ohmic contact electrode 220 active layer 230 germanium-type semiconductor layer 231 Type ohmic contact electrode 240 contact window 300 purification layer 400 stray layer 19