200912929 九、發明說明： 【發明所屬之技術領域】 r 本發明是有關於一種用於内容可定址記憶體之雙 槔AND型比對線電路，尤指一種可利用一個記憶體空 間儲存及查詢兩份查詢表，以大幅提升記憶體電路之 面積使用率，且使用時可達到低功率消耗及搜尋速度 高之功效者。 【先前技術】 目前内容可定址記憶體（c〇ment Addressable Memory，簡稱CAM)是組成高速搜尋引擎的重要元 件二該内容可定址記憶體除了可以記憶資料外，還 具資料比對的功能，故其記憶體細胞元中除了記 路外，尚具備比對用的電晶體。 〜 其中該記憶體細胞元中的資料與外部輸入^ 比對結果將透過比對、線電路（matcMinecircuit)輪 所以除了記憶體細胞元之電路外，比對線電路」ξ :容可定址記憶體設計的重點，該比對線電: 大致分為職型比對線電路與NAND型比對線^ 兩種裝置：該勵D型比對線電路裝置雖具有= ::::但是搜尋速度相當慢、，型 :具有嗔尋的特性，但功率消耗卻十分可觀1 =職型比對線電路較常被採用，因為搜 ^ 視比對線電路的速度。 ’丨擎較重 200912929 然而，目前現有技術中，從NAND型比對線電路 衍伸出來的綱型比對線電路似乎可以一並解決功 率消耗與比對速度的問冑；如第丄圖係為現有的 T>F-CDPD(Pseudo-f〇〇tless clock-and-data precharged y細c)細邏_電路丄0丄，其巳被用來設計内 谷可定址記憶體的比對線電路丄〇 〇 ;其中該記情體 細胞元1 0 2於圖令只顯示部份電路而簡化表示方 式；在此比對線電路令每_級的求值動作乃取決於上 一級的比對結果，只要其中—級動態娜型邏輯閘電 路1 0]比對資料不吻合’則其後面所有的動態麵 型邏輯閘1 0 1均不做求值動作，且此比對線電路型 態具有劃D邏輯閘的精神，所以功率消耗極低；另 一方面，因為所有的記憶體細胞元丄0 2巾N型電晶 體1 0 WNM0S..N型金屬氧化半導體）的閉極G輸入 皆在動態AND型；短1 η 1 4·· I i —.^ 1璉輯閘i 〇 1求值動作前就已確 疋文若I ..及所有細胞元中的N型電晶體1 0 3閉 極G輸入皆為邏輯「i」（即單一級所有資料比對吻合）， 則N型電晶體丄◦ 3的沒級D與源級s皆為「w零 電，」，所以有如虛擬接地般的效果，使得pF_CDpj) ，每-級都如同僅有兩個反相器般’速度即可大幅提 幵甚至大於nor型的比對線電路。 f設計内容可定址記憶體之設計技術中，除了提 升搜哥逮度與降低消耗功率外，記憶體面積也是設計 200912929 的一大考量，因為内容可定址記憶體細胞元所使用的 電晶體數目比一般隨機存取記憶體多出許多；而許多 搜尋引擎因為内容可定址記憶體的大面積，因而捨棄 龙用内容可定址記憶體來降低成本，因此，面積也是 内容j定址6己彳思體设計技術的—人問題；而目前也有 使用動態記憶體細胞元來設計内容可定址記憶體，但 因為動態記憶體細胞元需要特殊製程，所以其應用範 圍則不廣泛’且整合性也很低。 【發明内容】 本么〜之主要目的係在於增加可定址内容記憶體 的面積使用率，並降低其功率消耗。 為達上述之目的，本發明係一種用於内容可定址 記憶體之雙琿AND型比對線電路，係由記憶體細胞元 群組與AND閘之動態電路組成雙埠動態aNd閘’該 。己It體細胞元群組包含數個内容可定址記憶體細胞 元，忒内谷可定址記憶體細胞元群組係由多數記憶體 田胞元串聯組成，且該記憶體細胞元群組係分別具有 一端連接到GND，另外一端連接到AND閘之動態電 路之二端點；而該AND閘之動態電路係包含一設定電 路、兩引導電路與兩AND動態輸出電路。 【貫施方式】 凊參閱『第2〜1 1圖』所示，本發明提出了雙 埠比對線電路的設計，以提高内容可定址記憶體的面 200912929 積使用率與降低功率消耗。 由於三元内容可定址記憶體（Ternary C〇ntent-addressable_mem〇ry，以下 t白匕稱為丁ca⑷除了 可儲存〇，1之外，尚可儲存”don，t care，，。因此，其記 憶體細胞元的面積比起二元内容可定址記憶體— C〇ntent-addressable-memory，以下皆稱為 BicA⑷龐 大許多，也相對的增加了功率消耗與搜尋時間。本發 明設計了雙埠的比對線電路，可提高tcam的儲存率 以減少因為儲存”don，t care，，而浪費的空間。除此之 ’也大大的降泜了大量的功率消耗如第2，所示， 係將單料内容可定址記憶體2 0 1、2 q 2儲存資 料按照其資料之字首長度（prefix丨ength)排列後，可將 整個§己憶體陣列區分為兩個區域，而儲存二元資料2 0 4的部份為比對區域，儲存，，d〇n，t care”資料2 〇 5 的部份為不比對區域，因為儲存”d〇n，t care，，的記憶體 細胞元在比對過程中是被忽略的，因&，不比對區域 對於整個TCAM是沒有任何作用，並且會佔據面積與 消耗大量的功率，而本發明之特點乃是利用電路技巧 將内容可定址記憶體2 〇 2的需要比對的資料儲存到 内容可定址記憶體2 0 1令的不比對區域；然本發明 所k出的TCAM(2〇j)便是儲存了内容可定址記憶體2 〇 1、2 0 2兩塊記憶體的資料，在記憶體陣列中， 每個小區塊可以個別設定其資料是屬於内容可定址記 200912929 憶體2 0 1、2 0 2。而在第2圖的範例中，為 以清楚的說明’虛擬的界線2 i 〇將記憶體陣列中; 有區塊設定為兩區域211、212’其中區 1被設定為可以儲存内容可定址記憶體2 〇丄的次 料，而區域2 1 2則被設定為可以储存内容^貝 憶體202的資料’將兩個内容可定址記憶：Π 1、2 0 2中需要比對的資料分別儲存於所屬區域？ 1 1、2 1 2後，記憶體陣列中健存”阶”的記 憶體細胞元之資料2 〇 5則已經大量減少 個 記憶體陣列的空間儲存兩個記憶體的資料，可以大: 的節省丁CAM的使用面積與功率消耗。 區域電路具有兩個輸出埠， 出，其為輸出痒=線電路2。8輸 邊的比對線電路2 0 1 2的比對結果會從右 殊的電路設計m 2 ’其為輸料2;因為特 結果不會互相衝突，；2 Η與區域2 1 2的比對 果屬於哪個輸出i阜，、要將記憶體區塊設定其比對結 埠。 比對結果就會輸出至對應的輸出 請參閱第 要分為兩部分 細胞元群3 〇 記憶體細胞元 圖’該雙埠動態AND邏輯閘3 〇 1主 77別是動態電路部份3 0 2與記憶體 A °己1~思體細胞元群3 0 3包含數個 〇 4 記憶體細胞元3 0 4的數目可 200912929 由設計者自行決定；而記憶體細胞元3〇 資料與外部輸入資料比對的& 的儲存 T们t果會反映在電晶髀卩η 5的閘極〇 ;若資料比對 3 0 ^古'•住 τ刃σ 閘極G會破充電至雪 [问準位，電晶體3〇5則處於導通狀態，若^ =不吻合1極G會似電至電壓料位， 0 5則處於關閉狀態， 曰収〇 的資料皆比對吻人，節胞元群303 即點X會被全部導通的電晶體3 0 5放電至電壓低準 ：曰曰體3 位，由節點X的電壓準位= 則維持在高準 〇 3是否比對吻…1可仔知#憶體細胞元群3 and邏輯閘3 〇 ;的：：悲電路3 0 2是雙埠動態 個部分，負責將記憶體細胞 到比對線UMLIM 3 丁'口果而傳运 3〇 丄）或疋比對線2(ML2)則透過設定電路 ， 叹疋。設定電路3 0 6有記憶功能，在雷跋 -始化時即可設定該雙二 比對結果是屬於比㈣" 、铒閘3 0 1的 3 〇 6 U 1或是比對線2 ·，該設定電路 則為電壓低二：#;輸出’若Set-P為電壓高準位，… 輯閘3 0 i比對結果：：反;若欲將雙埠動態AND邏 為電壓低準位。。又叱至比對線卜則sei-p應設定 ~^ m半位’此 8與引導電路？ “，路3 1 6中的電晶體3 〇 引導電路3]X 電晶體3〇9為關閉狀態’ 中的電晶體31() = ΐ體3〇7與引導電路315 〇則為v通狀態·，若比對線丨上一級 200912929 的雙蟑動‘態AND閘比對結果為吻合， 3 1 3中的輸入端3 2 〇即為電壓高準位二出電路 細胞元群3 ◦ 3的比對結果則透過引導帝^記憶體 ’體3 1 0與動態輸出電路3 1 3中的電Γ的電晶 送至節點nl，進而傳送到動態輪出電心 丄1傳 出端3 2 1。本發明精神乃是將記情體 ^的輸 在記憶體2的，Wtcare，，區域，因為該級的：： 胞元群3 0 3儲存資料屬於比對線！的部份 2則會認定該級的記憶體細胞元群3 〇 3 = =tCare”；因此，該級在比對線2的部份則“ 略不比’不論記憶體細胞元群303的比對结；： 何，該級的比對結果在比對線2 、果為 結果透過導通電晶體3 〇 7血 =日，锕&，此比對 ϋ (與關閉電晶體3 〇 8來 成’因為電晶體3 0 8關閉，記憶體細胞 得比對結果料會傳送到節點心。若比對線2上—1 的雙璋動態爆閘比對結果為吻合，則動態輸出電路 314中的輸入端322即為電壓高準位，而該節點 Π2的電壓會透過導通的電晶體312與3 0 7放電至 電璧低準位，進而傳接j丨丨知At 寻到動恶輸出電路3 1 4中的輸 出端3 2 3 ’即其比對結果皆為吻合。 心定電路3 0 6可用SRAM之記憶體細胞元或 正反器等儲存元件來完成。該第4圖為設定電路3 〇 6可肊的’'她例’泫實施例中係利用6顆電晶體的 200912929 SRAM記憶體細胞元來實現。圖中WL代表字元線 (w〇rd line)’ WBLP與WLBN代表寫入位元線 bn-nne)’字元線和寫人位址線與熟知化心設計技術 >目同，在此不再贅述。 利用比對線電路的基本單元3 〇 i可組成完整的 比對線電路，言亥第5圖為本發明之比對線電路的第一 較佳實施例，比對線！的構成乃是透過連結線5〇工 將該級之第-埠輸出端3 2 1|%次—級之第一璋輸入 端3 2 0連結起來，而比對線2的構成乃是透過連結 線5 0 2將該級第-埠之輸出端3 2 3與次—級第一 皐之輸入端3 2 2連結起來。比對線電路是以動態 and閘電路構成，故其電路行為與—般動態電㈣ 同，分為預充電相位與求值相位；該預充電相位與求 值相位的時間皆為半個時脈週期（halfci〇ckcyck)，前 ^固時脈週期為預充電相位，此時的㈣與邱訊號 =電壓低準位；因此’所有動態AND問的輸出端3 3 2 3與輸入端3 2 0、3 2 2皆為電壓低準 位:所有的記憶體細胞元304在預充電相位做資料 =的動作’亚將輯結果傳送至節點X，若是該級 的屺憶體細胞元3 〇 4資料比對皆吻合，節 則曰被拉至電壓低準位，而後半個時脈週期為求值相 二進：求值相位時，_與_的電壓會由低準位 -怨至、準位。若第一級資料比對吻合，π第一級的 200912929 輸出端3 2 i、3 2 3亦會轉態為高準位 位訊號傳送到第二級的輸入端32〇、32γ= 厂級貝料比對亦吻合’高準位訊號則會繼續傳送到第 三級，依此類推。比對線1的電路動作是由最；邊: 動態—開開始動作，由左而右依序求值， 對線電路資料皆吻合，則” ML1Resuh，，會輸出邏輯卜 :對：:的電路動作是由最右邊的動態AND閑開始動 ’由右而左料求值，若整行比對線電路資料皆吻 Π MrResult”會輸出邏輯1;兩條比對線的訊號 相衝突’此現象已在前面的段落說明’在此 再參閱第6圖，係將比對線丨與比對線2再行分 =提高電路運作的平行度。比對線的分支 :路運：速度則越快’分支數的設計可由電路設計者 仃决疋’㈣6 ®為分支數二的實㈣彳，設計者可 匕類推’设计出分支數三或更高的比對線電路，而 :路的動作並不因為分支數的多募而改變，第6圖的 “路動作與第一較佳實施例相同，在此不再贅述。 么而第7圖之電路佈局圖（lay〇ut)中只須將記憶體 =2 3 〇 4、設定電路3 〇 6與雙埠動態AND閘的 ή路3 G 2之佈局高度設計為相@ ’整個比 點路即可亚貼’在佈局設計上也是具有容易設計的特 200912929 5亥第8圖中字元線（worcMine)由位址解碼器8 〇 2所產生，搜尋與寫入緩衝器8 〇 1在内容可定址記 憶體執行寫入動作（write operation)與比對動作（match operation)時’負責將外部資料送入記憶體細胞元中， 並由第9圖及第i ϋ圖觀之，當内容可定址記憶體執 行寫入動作時，”wirte”訊號會設定為高準位，此時外 部資料藉由搜尋與寫入緩衝器8 〇 i送入寫入位址線 (WBLP/WBLN)，而位址解碼器8 〇 2也同時執行位址 解碼動作，並將相對應字元線的電壓拉至高準位，而 資料得以寫入相對應的記憶體細胞元3 〇 4，當内容 可定址記憶體執行比對動作時，”match，，訊號會設定 為高準位’在時脈週期的正半週日寺，外部的資料透過 搜尋與寫入緩衝器8 0 1被送入至搜尋位址線 (SBLP/SBLN)且與記憶體細胞元内部資料作比對，此 時比對電路處於預充電相位’在時脈週期的負半週 時，比對電路的觸發訊號phil肖咖會轉態為高準 位’並讓比對電路進人求值相位，比對電路依照各級 動態A N D閘的比對結果傳遞比對訊號，若整行的記情 體細胞以料比對吻合，則該行輸出結果即為邏輯/ ----儿門令定址記憶體細胞六 (_aryCAMceU)的特性來設計，但是也可以搭配— 凡内容可定址記憶體細胞元（birmy⑽ 憶體的面積更加的縮小。而第i丄圖中該内容可定^ 200912929 記憶體1 1 0 1字元寬度為32位元，並將其分為8個 具4個記憶體細胞元的雙埠動態AND閘（丨1〇7，】丨⑽ ^與1109) ’透過上述的設定電路3 〇 6 ,將記憶體陣列 1104分為區域ι105與區域11〇6，而該區 域1 105 、1丄〇6和第2圖中的區域2丄丄、2 1 2之設計概念相同；在區域丄χ 〇 5中，因字首的 8位兀的記憶體細胞元確定不會儲存，，d〇n,t 的資 料，所以字首& 8位it的記憶體細胞元可置換成具4 個，元記憶體細胞元的動態AND閘，而其他記憶體細 胞7L依然使用二兀的設計以增加儲存資料的彈性，而 雙埠動態侧邏輯閘_乃是將其儲存資料設定為 區域卜雙埠動態、AND邏輯閘11〇9則是將其儲存資 枓設定為區域2，其中該雙埠動態通邏輯閘i i 〇 8、1 1 0 9係具4-個三元記憶體細胞元，且該實施 =包含了搜尋與寫入緩衝器11〇2與位址解 杰 1 1 0 3。 個記t::i雙二動::广對電路設計’以- 料，大大的裎古二可儲存兩個記憶體陣列的資 所嫌來。租面積的利用率。使得使用tcam 所可來的大面積問題得以解決。 200912929 产的提出的雙淳比對線電路不僅具有高比對速 二匕起」：且記憶體的資料輸出率(即—_ >體敕：的比對線電路也大大的提升，有助於記 u體鲨體效能的提升。 功率==_型比對線電路，天生已經具有低 的資料# * 4又因為雙料電路設計，使得每次 到兩筆结果，讓每筆資料結果的搜 厅而功率4耗更能大幅的降低。 尋表ίΓ月=己憶體空間可以儲存兩份搜尋表。在搜 設^w q部份相當具有彈性，可讓使用者自由 WTC·的發明使設計更自由化，可自由搭配二 二：定址記憶體細胞元做最佳化設計，使 仔面積與功率更近—步的縮小。使 相當ίϊ的佈局設計，使得實現本發明的比對線電路 綜上所述，本發 娜型比對線電路可，内谷可定址記憶體之雙埠 用一個記憶體空 9’文改善習用之種種缺點，可利 升記憶體電路之面=及查詢兩份查詢表，以大幅提 消耗及搜尋速度5=用率’且使用時可達到低功率 進步、更實用、更符進而使本發明之産生能更 、5 ’肖費者使用之所須，確已符合 200912929 申請。 實施例而已， ’凡依本發明 發明專利申請之要件，爰依法提出專利 惟以上所述者，僅為本發明之較佳 當不能以此限定本發明實施之範圍；故 申請專利範圍及發明說明書内容所作之簡單的等效變 化與修飾’皆應仍屬本發明專利涵蓋之範圍内。 200912929 【圖式簡單說明】 第1圖，係習用之邏輯閘電路示意圖。 ^第2圖’係本發明之基本架構示意圖。 第3圖’係本發明所提出的雙埠動態AND邏輯閘示 意圖。 第4圖，係本發明設定電路之實施例示意圖。 第5圖’係本發明比對線電路之第一實施例示意圖。 第6圖，係本發明比對線電路之第二實施例示意圖。 第7圖，係本發明電路佈局圖之第一實施例示意圖。 第8圖，係本發明雙埠比對線電路實現於内容可定址 5己憶體之洋細電路示意圖。 第9圖，係本發明搜尋與寫入緩衝器之較佳實施例示 意圖。 第1 0圖，係本發明内容可定址記憶體之動 意圖。 第1 1圖，係本發明之比對線電路之内容200912929 IX. Description of the invention: [Technical field to which the invention pertains] r The present invention relates to a double-槔 AND type comparison line circuit for content addressable memory, and more particularly to a memory space for storing and querying two A look-up table to greatly increase the area usage of the memory circuit, and can achieve low power consumption and high search speed when used. [Prior Art] Currently, content addressable memory (CAM) is an important component of a high-speed search engine. In addition to being able to memorize data, the content-addressable memory also has a function of data comparison. In addition to the path, the memory cell elements have a matching crystal. ~ The data in the memory cell and the external input ^ will be compared through the alignment, line circuit (matcMinecircuit) round, in addition to the memory cell circuit, the comparison circuit "ξ: capacitive addressable memory The focus of the design, the comparison of the line power: roughly divided into the job type comparison line circuit and the NAND type comparison line ^ two devices: the excitation D type comparison line circuit device has = :::: but the search speed is equivalent Slow, type: has the characteristics of seek, but the power consumption is very impressive 1 = the type of line circuit is more commonly used, because the speed of the comparison line circuit. '丨擎重重200912929 However, in the current state of the art, the analog-to-pair line circuit derived from the NAND type comparison line circuit seems to solve the problem of power consumption and comparison speed; For the existing T>F-CDPD (Pseudo-f〇〇tless clock-and-data precharged y fine c) fine logic_circuit 丄0丄, the 巳 is used to design the alignment line circuit of the inner valley addressable memory丄〇〇; wherein the sympathetic cell element 1 0 2 simplifies the representation by showing only part of the circuit; the comparison line circuit makes the evaluation of each _ level depends on the comparison result of the previous stage. As long as the -level dynamic Na-type logic gate circuit 1 0] does not match the data, then all the dynamic surface-type logic gates 1 0 1 are not evaluated, and the comparison line circuit type has a stroke D logic gate spirit, so the power consumption is extremely low; on the other hand, because all the memory cell elements 丄 0 2 towel N-type transistor 10 WNM0S.. N-type metal oxide semiconductor) the closed-pole G input are dynamic AND type; short 1 η 1 4·· I i —.^ 1琏 闸 i i 〇 1 before the evaluation action is confirmed Wen Ruo I.. and all cell types in the N-type transistor 1 0 3 closed-pole G input are logical "i" (that is, a single level of all data alignment), then the N-type transistor 丄◦ 3 Both D and source s are "w zero," so there is a virtual ground-like effect, making pF_CDpj), each level is as fast as two inverters, and can be greatly improved or even larger than nor Alignment line circuit. f design content can be addressed memory design technology, in addition to improving the search and reduce power consumption, memory area is also a major consideration in the design of 200912929, because the content can address the number of transistors used in memory cells Generally, there are many random access memory; many search engines can address the large area of the memory, so they can use the content-addressable memory to reduce the cost. Therefore, the area is also the content j. The technical-human problem; however, there are also the use of dynamic memory cells to design content-addressable memory, but because dynamic memory cells require special processes, their application range is not extensive and the integration is low. SUMMARY OF THE INVENTION The main purpose of this is to increase the area usage of addressable content memory and reduce its power consumption. To achieve the above object, the present invention is a double-珲 AND type comparison line circuit for content addressable memory, which is composed of a memory cell group and a dynamic circuit of an AND gate. The so-cell somatic cell group contains several content-addressable memory cell elements, and the 忒内谷-addressable memory cell group is composed of a plurality of memory cell elements in series, and the memory cell group is separately The dynamic circuit of the AND gate has a set circuit, two guiding circuits and two AND dynamic output circuits. [Continuously applied] 凊 Referring to the "2nd to 1st 1st" diagram, the present invention proposes a design of a double-twist comparison line circuit to improve the surface usage of the content addressable memory and reduce the power consumption. Since the ternary content can be addressed to the memory (Ternary C〇ntent-addressable_mem〇ry, the following t-white is called Dingca (4). In addition to storing 〇, 1 can still be stored as "don, t care,". Therefore, its memory The area of the somatic cell is larger than the binary content addressable memory - C〇ntent-addressable-memory, which is called BicA (4), which increases the power consumption and the search time. The present invention designs the ratio of the double 埠. For the line circuit, the storage rate of tcam can be increased to reduce the space wasted because of storing "don, t care,". In addition, it also greatly reduces the power consumption as shown in the second, as shown in the figure. The content of the material can be addressed to the memory. 2 0 1 , 2 q 2 The stored data is arranged according to the prefix length (prefix丨ength) of the data, and the entire § memory array can be divided into two regions, and the binary data is stored. The part of 0 4 is the comparison area, the storage, the d〇n, the t care" part of the data 2 〇5 is the unmatched area, because the memory cells of the storage "d〇n, t care," are It is ignored in the process, because &, no more than The area has no effect on the entire TCAM, and it occupies an area and consumes a large amount of power, and the present invention is characterized by using circuit techniques to store the content of the content addressable memory 2 〇 2 to the content addressable memory. The unmatched area of the body 2 0 1 command; however, the TCAM (2〇j) produced by the present invention stores data of two pieces of memory of the content addressable memory 2 〇 1, 2 0 2 in the memory array. In each block, each cell block can be individually set to belong to the content addressable record 200912929, and in the example of FIG. 2, in order to clearly explain the 'virtual boundary 2 i 〇 In the memory array; the block is set to two areas 211, 212', wherein the area 1 is set to store the content addressable memory 2 次, and the area 2 1 2 is set to store the content ^ Recalling the data of the body 202 'The two contents can be addressed in the memory: Π 1, 2 0 2 need to compare the data stored in the region? 1 1, 2 1 2, the memory array in the "order" Memory cell data 2 〇5 has been a large number Reducing the space of a memory array to store two memory data can be large: to save the use area and power consumption of the CAM. The regional circuit has two outputs 埠, which is the output itch = line circuit 2. 8 lose The comparison result of the edge comparison circuit 2 0 1 2 will be from the right circuit design m 2 'which is the material 2; because the special results do not conflict with each other; 2 比 is compared with the area 2 1 2 Which output i阜 belongs to, and the memory block is set to match the balance. The comparison result will be output to the corresponding output. Please refer to the section to divide into two parts of the cell group. 3 〇 Memory cell diagram 'The double 埠 dynamic AND logic gate 3 〇 1 main 77 is the dynamic circuit part 3 0 2 And the memory A °1~1 body cell group 3 0 3 contains several 〇4 memory cell number 3 0 4 can be determined by the designer at the time of 200912929; and the memory cell element 3 〇 data and external input data The comparison of the & storage T will reflect the gate 〇 of the crystal 髀卩 5 5; if the data is compared to 3 0 ^ ancient '• live τ blade σ gate G will be charged to the snow [question Bit, transistor 3〇5 is in the on state, if ^ = does not match 1 pole G will appear to the voltage level, 0 5 is in the closed state, the data collected are compared to the kisser, the cell group 303, point X will be discharged by the all-conducting transistor 3 0 5 to the low voltage level: the body is 3 bits, and the voltage level of the node X is maintained at the high level 〇 3 is the comparison kiss... 1 #忆体细胞元群3 and Logic Gate 3 〇;:: The sad circuit 3 0 2 is the dynamic part of the double ,, responsible for the memory cells to the comparison line UMLIM 3 'The fruit is transported 3〇 丄) or 疋 对 2 (ML2) through the setting circuit, sigh. The setting circuit 306 has a memory function, and the result of the pairwise alignment can be set to be 3 〇 6 U 1 or the comparison line 2 · when compared with (4) " The setting circuit is the voltage low two: #; output 'If Set-P is the voltage high level, ... the gate 3 0 i comparison result:: reverse; if the double-turn dynamic AND logic is the voltage low level. . Also 叱 to the comparison line sei-p should be set ~ ^ m half-digit '8 and the boot circuit? ", transistor 3 〇 guiding circuit 3 in way 3 16 6] X transistor 3 〇 9 is in the closed state ' transistor 31 () = ΐ body 3 〇 7 and guiding circuit 315 〇 is v-pass state If the ratio of the double-swing 'state AND gate comparison of the previous stage of 200912929 is the same, the input end of 3 1 3 is the ratio of the high-level two-out circuit cell group 3 ◦ 3 The result is transmitted to the node n1 through the electric crystal that guides the electric body in the memory body 3 1 0 and the dynamic output circuit 3 1 3, and then transmitted to the dynamic wheel output power card 1 output terminal 3 2 1 . The spirit of the present invention is to input the morphological body ^ in the memory 2, Wtcare, and the region, because the level of the :: cell group 3 0 3 stores the data belonging to the comparison line! The level of memory cell population 3 〇 3 = = tCare"; therefore, the portion of the level in the alignment line 2 is "slightly no more than the comparison of the memory cell group 303;: The comparison result is in the comparison line 2, and the result is transmitted through the conduction current crystal 3 〇 7 blood = day, 锕 &, this comparison ϋ (with the closing of the transistor 3 〇 8 into ' because the transistor 3 0 8 is turned off, and the result of the comparison of the memory cells is transmitted to the node core. If the result of the double-twist dynamic damper comparison on line 2 is matched, the input terminal 322 in the dynamic output circuit 314 is the voltage. a high level, and the voltage of the node Π2 is discharged to the low level of the power through the turned-on transistors 312 and 307, and then the output of the active output circuit 3 1 4 is transmitted. 3 2 3 'that is the result of the comparison. The heart-shaped circuit 3 0 6 can be completed by using storage elements such as SRAM memory cells or flip-flops. Figure 4 shows the setting circuit 3 〇6 肊The 'her example' embodiment is implemented using the 200912929 SRAM memory cell element of 6 transistors. WL represents the word line (w〇rd line) 'WBLP and WLBN represent the write bit line bn-nne The 'character line and the write address line are similar to the well-known design technique>, and will not be repeated here. The basic unit 3 〇i of the comparison line circuit can be used to form a complete comparison line circuit. Figure 5 is a first preferred embodiment of the comparison line circuit of the present invention, the alignment line is constructed by connecting the lines 5 Completion is connected to the first 璋 input terminal 3 2 0 of the first 埠 output of the stage, and the comparison line 2 is constructed by connecting the line 5 0 2 The output terminal 3 2 3 of the first-stage is connected with the input terminal 32 2 of the first-stage first-order. The comparison line circuit is composed of a dynamic and gate circuit, so the circuit behavior is the same as that of the general dynamic electricity (four). The pre-charging phase and the evaluation phase; the pre-charging phase and the phasing phase are both half-clock cycles (halfci〇ckcyck), and the pre-fixed clock cycle is the pre-charging phase, at this time (4) and Qiu signal = voltage low level; therefore 'all dynamic AND's output 3 3 2 3 and input 3 2 0, 3 2 2 are voltage low level: all memory cell 30 in the pre-charge phase do data = The action 'sub-combination results are transmitted to node X. If the data of the level is equal to the data, the node is pulled to the low voltage level, and the second half of the clock period is evaluated. Phase two: When evaluating the phase, the voltage of _ and _ will be low level - resentment and level. If the first level data match, π first stage 200912929 output 3 2 i, 3 2 3 will also be converted into high level position signal transmitted to the second stage input 32 〇, 32 γ = factory level The material comparison also coincides with the 'high level signal will continue to be transmitted to the third level, and so on. The circuit action of the comparison line 1 is the most; the edge: dynamic-open start action, the value is evaluated from left to right, and the line circuit data is consistent, then ML1Resuh, will output the logic: the circuit of:: The action is started by the rightmost dynamic AND idle 'from the right and left. If the whole line is matched to the line circuit data, MrResult will output logic 1; the signals of the two comparison lines will conflict. As explained in the previous paragraphs, 'Refer to Figure 6 here, the line 丨 and the comparison line 2 are further divided = the parallelism of the circuit operation is improved. The branch of the comparison line: road transport: the faster the speed, the design of the number of branches can be determined by the circuit designer. (4) 6 ® is the real number of the branch number (4), and the designer can design the number of branches three or more. The high-aligning line circuit, and the action of the road is not changed by the multi-funding of the number of branches. The "road action" of Fig. 6 is the same as that of the first preferred embodiment, and will not be described here. In the circuit layout diagram (lay〇ut), only the memory height = 2 3 〇 4, the setting circuit 3 〇 6 and the double-turn dynamic AND gate ή 3 G 2 layout height are designed as phase @ 'the whole ratio point road It can be used in the layout design. It is also easy to design. The character line (worcMine) is generated by the address decoder 8 〇2. The search and write buffer 8 〇1 is available in the content. When the address memory performs a write operation and a match operation, it is responsible for sending external data into the memory cell, and viewing it from the 9th and the i-th map, when the content can be addressed. When the memory performs a write operation, the "wirte" signal is set to a high level. The data is sent to the write address line (WBLP/WBLN) by the search and write buffer 8 〇i, and the address decoder 8 〇 2 also performs the address decoding operation and the corresponding word line The voltage is pulled to a high level, and the data is written into the corresponding memory cell 3 〇4. When the content addressable memory performs the comparison action, "match, the signal will be set to a high level" in the clock cycle. The positive half-week temple, the external data is sent to the search address line (SBLP/SBLN) through the search and write buffer 80 1 and compared with the internal data of the memory cell, and the comparison circuit is The pre-charge phase 'in the negative half cycle of the clock cycle, the trigger signal of the comparison circuit will turn into a high level' and let the comparison circuit enter the phase of the comparison, the comparison circuit according to the dynamic AND of each level The comparison result of the gate transmits the comparison signal. If the whole line of the sensible somatic cells is matched by the material, the output of the line is the logic / ---- the characteristics of the occupant-addressed memory cell six (_aryCAMceU) Designed, but can also be used with - content can be addressed to memory cells Birmy(10) The area of the memory is more reduced. In the i-th diagram, the content can be determined. 200912929 Memory 1 1 0 1 character width is 32 bits, and it is divided into 8 cells with 4 memory cells. Double-turn dynamic AND gate (丨1〇7, 丨(10)^ and 1109) 'The memory array 1104 is divided into a region ι105 and a region 11〇6 through the above-mentioned setting circuit 3 〇6, and the region 1 105 , 1丄〇6 and the area 2丄丄, 2 1 2 in Figure 2 have the same design concept; in the area 丄χ 〇5, the memory cells of the 8th 兀 memory of the prefix are determined not to be stored, d〇 n, t data, so the memory cells of the first & 8-bit it can be replaced with a dynamic AND gate with four, meta-memory cell elements, while other memory cells 7L still use the design of the two-dimensional to increase The flexibility of the data is stored, and the dynamic side logic gate of the double 埠 is to set its storage data to the area 埠 埠 dynamic, AND logic gate 11 〇 9 is to set its storage 为 to area 2, where the 埠 dynamic Logic gate ii 〇 8, 1 1 0 9 with four ternary memory cell elements, and the implementation = contains search and write And the address solution is washed 11〇2 Jay 1103. A record t::i double two move:: wide on the circuit design 'to-materials, the big two can store two memory arrays. Utilization of rented area. The large-area problem that can be solved with tcam is solved. 200912929 The proposed double-twist comparison circuit not only has a high ratio of speed to two speeds: and the data output rate of the memory (ie, the -_ > body: the comparison line circuit is also greatly improved, which helps The performance of Yujiu body shark body is improved. Power ==_ type comparison line circuit, born with low data # * 4 and because of the dual material circuit design, so that each time to two results, let each data result search The power consumption of the hall can be greatly reduced. The search table Γ = month = the memory space can store two search tables. The search for ^wq part is quite flexible, allowing users to freely design WTC · to make the design more Freedom, can be freely matched with two or two: address memory cells to optimize the design, so that the area of the child is closer to the power - the step is reduced. Make the layout design quite reasonable, so that the comparison line circuit of the present invention can be realized. According to the above, the fascia type comparison circuit can be used, and the memory of the internal memory can be used to improve the conventional disadvantages of a memory empty 9' text, and can improve the surface of the memory circuit = and query two queries. Table to greatly increase consumption and search speed 5= The use rate 'can be achieved when using low power, more practical, and more in order to make the invention more effective, and the need to use it is indeed in accordance with the application of 200912929. The requirements of the invention patent application, the patents are filed according to law, but the above description is only preferred, and the scope of the invention cannot be limited thereto; therefore, the simple equivalent change of the patent application scope and the contents of the invention specification And the modifications should be within the scope of the patent of the present invention. 200912929 [Simple description of the diagram] Figure 1 is a schematic diagram of a conventional logic gate circuit. ^ Figure 2 is a schematic diagram of the basic architecture of the present invention. A schematic diagram of a double-turn dynamic AND logic gate proposed by the present invention. Fig. 4 is a schematic view showing an embodiment of a setting circuit of the present invention. Fig. 5 is a schematic view showing a first embodiment of a comparison line circuit of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a schematic view showing a first embodiment of a circuit layout diagram of the present invention. FIG. 8 is a double-twist comparison line of the present invention. The circuit is implemented in a schematic diagram of the fine-grained circuit of the content addressable memory. Figure 9 is a schematic diagram of a preferred embodiment of the search and write buffer of the present invention. Figure 10 is an addressable memory of the present invention. The intention is to describe the contents of the comparison circuit of the present invention.
體示意圖。 L 【主要元件符號說明】 (習用部分） 内容可定址記憶體的比對線電路i 0 0 AND邏輯閘電路1 〇 1 200912929 記憶體細胞元1 0 2 N型電晶體1 〇 3 (本發明部分） 内容可定址記憶體？ CM 、2 0 2 TCAM2 0 3 資料 2 0 4、2 0 5 比對線電路2 0 8、2 0 9 界線2 1 0 區域2丄1 、2丄2 雙埠動態AND邏輯閘3 0 1 動態電路部份3 0 2 記憶體細胞元群3 0 3 記憶體細胞元3 0 4 電晶體305'307、308 電晶體309、310、311 電路3 0 6 動態輸出電路3 1 3 動態輸出電路3 1 4 引導電路3 1 5 引導電路3 1 6 200912929 輸入端320、322 輸出端321、323 連結線5〇1、5 0 2 仿址解碼器8 0 2 搜尋與寫入緩衝器8〇1 内容可定址記憶體1 1 0 1 搜尋與寫入緩衝器1 1 0 2 位址解碼器1 1 0 3 記憶體陣列丄丄0 4 區域1 1 0 5、1 1 0 6 動態AND邏輯閘1 1 〇 7 雙埠動態AND邏輯閘1 1 〇 8、1 1 0 9 20Body diagram. L [Description of main component symbols] (Available part) Content comparison memory circuit for addressable memory i 0 0 AND logic gate circuit 1 〇1 200912929 Memory cell element 1 0 2 N type transistor 1 〇3 (part of the present invention ) Content can address memory? CM, 2 0 2 TCAM2 0 3 Data 2 0 4, 2 0 5 Compare line circuit 2 0 8、2 0 9 Boundary line 2 1 0 Area 2丄1, 2丄2 Double-turn dynamic AND logic gate 3 0 1 Dynamic circuit Part 3 0 2 Memory Cell Group 3 0 3 Memory Cell 3 0 4 Crystal 305'307, 308 Transistor 309, 310, 311 Circuit 3 0 6 Dynamic Output Circuit 3 1 3 Dynamic Output Circuit 3 1 4 Pilot circuit 3 1 5 Pilot circuit 3 1 6 200912929 Input terminal 320, 322 Output terminal 321, 323 Connection line 5〇1, 5 0 2 Imitation decoder 8 0 2 Search and write buffer 8〇1 Content addressable memory Body 1 1 0 1 Search and Write Buffer 1 1 0 2 Address Decoder 1 1 0 3 Memory Array 丄丄 0 4 Area 1 1 0 5, 1 1 0 6 Dynamic AND Logic Gate 1 1 〇7 Double 埠Dynamic AND logic gate 1 1 〇 8, 1 1 0 9 20