200910305 九、發明說明： 【發明所屬之技術領域】 本贫明係關於-種液晶_示器及其驅動方法，特別是一種雙 邊閘極驅動式之液晶顯示器及其驅動方法。 【先前技術】 第1圖係秘艘賴極絲料器__膜電晶體液晶 减=之電路示意0。如第】圖所示，雙伽極位移暫存器驅動 的溥膜電晶體液晶顯示器的資料線3l_㈣數量為傳統單邊 閘極驅動式薄膜電晶體液晶顯示器之—半。 閘極線卿gate line)由左側的第一位移暫存器㈣ 動，第二職線21(even gate㈣則由右側的第二位移暫存器如 «’左右兩侧極驅動訊號呈交錯排列。每—級位移暫存哭旦 有四個輸人及-個輸出，分別絲如下：极為直流參考電壓， st為輸入起始脈波訊號，CK為輸入時脈訊號，xck為輸入反相 時脈訊號，N為輸出訊號。 第2圖係為雙邊閘極驅動器之位移暫存器輸入訊號與輸出訊 號之時序轉®。Μ 2圖解，STL為左麵蝴_㈣的 起始脈波職，CKL為左讎咖峨，沈虹為左麵 流排的反树脈喊，STR為右麵流制妙脈波訊號，〔狀 為右側匯流排的時脈訊號，XCKR 4右側匯流排的反相時脈訊 號。CKL、XCKL、CKR與XCKR的責任週期比均為篇，观、 CKR與XCKR較STL、CKL與XCKL延遲⑷寺脈週期，所輸 出的閘極驅動訊號依序為第一閘極驅動訊號⑷G1L、第二閑極驅 200910305 動訊號(细R、第鶴觸句处、第二開極驅動訊號 (右)G2R、第-閑極驅動訊號（左）疏、第二閑極驅動訊號 (右XbR··，，且各難驅動訊號分職前—級位移暫存器的輸出 訊號重璧1，'2卩雜脈波訊號的時間長度(H)。由於任—時刻皆有兩 個輸出脈波訊號，故任—時刻每—資料線3〗會同時對相鄰兩個畫 素充電’造絲先供料邊晝钱充轉触部份麵到相鄰的 旦素中’使仔各晝素若要達到高充電率所需要的充電電流較原先 的大，所以其耗電量會較高。 因此，如何能提供-種較省電的驅動方式成為研究人員待解 決的問題之一。 【發明内容】 髮於以上的問題，本發明提供—種雙相極驅賦之液晶續 不益及其鶴方法，透綱麵較術使位㈣存雜出的開掩 驅動訊號㈣序缝疊，藉_免_驅動雜重㈣兩晝素同 時充電而造成功率消耗的問題，進而降低雙邊雜驅動式 顯示器的耗電量。 aa 本發明所揭露之雙邊閘極驅動式之液晶顯示器包含有複數 鱗-位移暫存器，接收-驅動訊號，並產生—對應驅動訊號之 4序的第-閘極驅動訊號；及複數個第二位移暫存器，接收驅動 訊破並產生-對應驅動訊號之時序的第二間極驅動訊號.其中 各個第-婦暫存H與各㈣二位移键㈣純之轉訊號具 1/4週期脈歧度，各娜_位移暫存器與各個第二位移暫存哭梗 據驅動訊號之時序，產生具1/4週期脈波寬度之第1極驅= 200910305 ‘、布ιχ控制複數個麵電錄之導通味間。 方'土 =Γ絲之雙制極鶴叙液轉示器之驅動 二暫包括有Μ個薄膜電晶體、具有複數個第- 之卜腿驅動器，以及具有複數個第二 之弟二閘極驅動器，該驄 夕曰仔口。 期A m " 4 έ、有：調變驅動訊號之責任週 第if 變後之驅動訊號至各個第一位移暫存器與各個 弟一位私暫存益；各個第 據輸入之,_訊叙時序纽| /4存:翔k轉暫存器根 動訊號與第二難欄脈波寬度之第—閑極驅 位移暫存諸位料衫與各個第二 驗一，以控制各個薄膜電晶體之導通時間。 谷個 猎由這種雙細極鶴叙液晶顯衫及 輸入至位移暫存器的旬號夕主，、 /、驅動方法，係將 存器輸出的間極驅動訊號調變至25% ’以使位移暫 重射兩畫素同時充電而造極购訊號 極驅動式之液晶顯示器的耗電量，==而降低雙_ 概之責㈣概_至大於25%㈣、於· _暫存器的 态輸出的閘極驅動訊號可接 Β使位移暫存 解決間極㈣賴树5鱗畫錢找電，《 題。 倾奴中產生形變導致充電率不足的問 有關本發明的特徵與實— f實施方式】 圖式詳細說明如下。 .第】圖係為使用雙邊閘極企 7 -存态驅動的薄M電晶體液晶 200910305 '扣〜包路示思圖。如第1圖所示，液晶顯示器包含有複數個 第位^夕暫存益10、複數個第二位移暫存器20、資料驅動器30、 複數條資料線31、複數條第-酿線II、複數㈣二_線21 與複數個薄獏電晶體4〇。 複數個弟一位移暫存器1〇接收左侧匯流排的驅動訊號，並200910305 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a double-sided gate-driven liquid crystal display and a driving method thereof. [Prior Art] Fig. 1 shows the schematic diagram of the circuit of the secret lyotropic filament __membrane transistor liquid crystal minus =. As shown in the figure, the number of data lines 3l_(4) of the 溥-membrane transistor liquid crystal display driven by the double gamma shift register is half of that of the conventional single-sided gate-driven thin film transistor liquid crystal display. The gate line is moved by the first displacement register (4) on the left side, and the second line 21 (even gate (4) is staggered by the second displacement register on the right side such as «'. Each level shift temporarily has four inputs and one output, which are as follows: extremely DC reference voltage, st is the input start pulse signal, CK is the input clock signal, and xck is the input inversion. Pulse signal, N is the output signal. Figure 2 is the timing shift of the input signal and output signal of the displacement register of the bilateral gate driver. Μ 2 diagram, STL is the starting pulse of the left butterfly _ (four), CKL is the left-handed curry, Shen Hong is the anti-tree pulse of the left-side flow, and STR is the right-hand flow of the wonderful pulse signal, [the clock signal of the right busbar, the reverse of the busbar of the right side of XCKR 4 Clock signal. The duty cycle ratios of CKL, XCKL, CKR and XCKR are all articles. CKR and XCKR are delayed compared to STL, CKL and XCKL. (4) Temple pulse period. The output gate drive signals are sequentially the first gate. Drive signal (4) G1L, second idle drive 200910305 motion signal (fine R, Dihe touch sentence, second open drive Signal (right) G2R, first-idle drive signal (left), second idle drive signal (right XbR··, and each difficult drive signal before the division - the output signal of the stage shift register is reset 1 , the length of time of the '2 noisy pulse signal (H). Since there are two output pulse signals at any time, any time - each data line 3 will charge the adjacent two pixels simultaneously The wire first supplies the money and charges the partial surface to the adjacent denim. 'The charging current required to achieve the high charging rate is higher than the original one, so the power consumption will be higher. Therefore, how to provide a more power-saving driving method has become one of the problems to be solved by the researcher. [Disclosed from the above] The present invention provides a liquid crystal for a dual-phase pole drive. The method of the crane, the transmissive surface is more than the interrupted driving signal (4), and the power is dissipated by the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The power consumption of the display is aa. The bilateral gate-driven liquid crystal display disclosed in the present invention The device includes a plurality of scale-displacement registers, a receive-drive signal, and generates a first-gate drive signal corresponding to the 4th order of the drive signal; and a plurality of second shift registers, the receive drive breaks and generates - Corresponding to the timing of the driving signal, the second interpole driving signal. Each of the first female temporary storage H and each (four) two displacement key (four) pure transcoding signal has a quarter cycle pulse disparity, each _ displacement register and each The second displacement temporarily stores the crying stalk according to the timing of the driving signal, and generates the first pole drive with a 1/4 cycle pulse width = 200910305 ', and the cloth ιχ controls the conductive sensation of the plurality of surface electric records. The driver of the dual-system crane liquid relay device includes a thin film transistor, a plurality of the first-brieze driver, and a plurality of second brothers and two gate drivers. mouth. Period A m " 4 έ, has: the responsibility of the modulation drive signal week after the change of the driving signal to each of the first displacement register and each of the brothers a private temporary deposit; each of the input of the data, _ Sequence Timing | /4 Storage: Xiang k turn register root signal and the second difficulty column pulse width - idle drive displacement temporary storage of the shirt and each second test to control each thin film transistor Turn-on time. The valley hunting is made up of the double-small cranes and the input to the displacement register. The /, driving method is to change the inter-polar drive signal output from the memory to 25%. The displacement temporarily re-emphasizes two pixels while charging, and the power consumption of the extremely driven liquid crystal display is reduced. == and the double _ is reduced (4) _ to more than 25% (four), _ _ register The gate drive signal of the state output can be connected to make the displacement temporary storage solve the interpolar (4) Lai Shu 5 scales to find money, ". The problem of the deformation caused by the deformation in the slave is insufficient. The present invention is described in detail below. The first figure is the use of a double-gate transistor 7-state-driven thin M-crystal liquid crystal 200910305 'deduction ~ package road map. As shown in FIG. 1, the liquid crystal display includes a plurality of first-order temporary memory benefits 10, a plurality of second displacement registers 20, a data driver 30, a plurality of data lines 31, and a plurality of first-strand lines II. The complex (four) two-line 21 and a plurality of thin germanium transistors 4 〇. a plurality of brothers and one shift register 1 receives the driving signal of the left bus, and
.產生焉應驅動訊號之時序的第一閘極驅動訊號(例如，gil、咖、 G3L、G4T ° ••等）。驅動訊號包含有直流參考電壓、起始脈 波汛唬、時脈訊號與反相時脈訊號。 複數個第二位移暫存器2〇接收右側匯流排的驅動訊號，並 產生對應驅紐號之料的第二閘極,_訊號(例如，G1R、G2R、 G)R G4R、G5R…等）。驅動訊號包含有直流參考電壓、起始脈 波訊號、時脈訊號與反相時脈訊號。各個第一位移暫存器10與各 個第一仇移暫存器20所接收之驅動訊號具1/4週期的脈波寬度， 而各個第—位移暫存器10與各個第二位移暫存器根據接收白)驅 動二唬之日寸序，產生具週期的脈波寬度之第一閘極驅動訊號 與第=閘極驅動訊號，以控制複數個薄臈電晶體4〇之導通時間。 -第3圖係為本發明第一實施例之雙邊閘極驅動器之位移暫存 器輸入訊號與輸出訊號之時序示意。如第3圖所示，CKL、XCKL、 CKR與Xckr的週期為τ，閘極驅動訊號的時間長度為狀、 刀別較CKL、XCKL延遲1/4時脈週期。stl、STR、CKL、 XCKL、CKR與XCKR具有1/4週期的脈波寬度。 1透過》周，交CKL、XCKL、CKR與xCKR的責任週期比為 2：>/〇以使任意兩個閘極驅動訊號（例如，第一閘極驅動訊號 200910305 (c)GiL、第二閘極驅動訊號（右)G〗R、_ (左）G2L、第：閘極驅動訊號（右)G次…〜驅動訊號 (左)G3L、第二間極驅動訊號(右)G3R)的時卜閘喊驅動訊號 動訊號時序可避免開極驅動訊號重疊時兩書^重疊。此種間極驅 率消耗的問題。 /'同日7充電而造成功 第4圖係為閑極訊號與資料訊號之 ▲ 弟4圖所不’理想_極驅動訊號ιι〇與資:：:圖二如 有效充雷日丰严日1 FH，办?奋阶 就構成的第— 產—::==== 由裒弟一有效充電時 充電時間Η卜致使畫素的等效充電時間縮 === Κ，對於較大畫素電容而言’可能會發生充電不足的；： 因此’处過將間極訊驅動號的開啟時間提前 =可達::最大充電時間。因不同一抗= ㈣號延遲，因鱗間長度-為可變，為了使畫切最大充電 %間及雜難職時序錢造賴功轉 開㈣間需為可任意調變，以達到最大充電效率。動^的 弟:> 圖係為本發明第二實施例之雙邊閑極驅動器之位 器輸入訊號與輪出訊號之時序示意。如第5圖所示馈、xc^ ⑽與XCKR的週期為T，CKR與XCKR分別較CKL與XCKL 延遲1/4的時脈週期。 將CKL XCfCL、CKR、XCKR的責任週期比調變為大於％% 200910305 但小於50%之間，且CKL和CKR相差1/4相仗，XCKL與X(：KR 相差1/4相位，相鄰的兩個閘極驅動訊號的重疊時間為△ Ή，_ / 疊時間ΔΗ與責任週期比的關係如下列式子(1): △ Η=責任週............................. 其中Τ為週期，且當重疊時間ΑΗ與時間長度Aic相等時， 具有最大的晝素充電效率。如此，透過調整位移暫存器的輪出閑 極驅動訊號之時序重疊時間，可改善因閘極驅動訊號的波形头直 造成的晝素充電時間延遲所導致的充電率不足的問題，且因閘極 驅動訊號之時序重疊時間較短，仍可避免過多功率消耗。 第6圖係為本發明第一實施例之驅動方法步驟流程圖。本發 明之雙邊’鶴式之液晶顯示II包括有複數個_電晶體、^ 有複數個第-位移暫存H之第—閘極驅動B與具有複數個第二位 移暫存器之第二職鶴器，該鶴方法包含打列步驟·· 並輸入調變後之 首先，調變驅動訊號的責任週期比為25%， :動訊號至各個第—位移暫存器與各個第二位移暫存器（步驟 ^其中驅動輯包含有直流參考糕、起始脈波訊號 訊唬與反相時脈訊號。 ⑼位料钟與各轉二轉暫存雜據輪入 產生具1/4週氣波寬度之第—酿驅動訊 、弟一閘極驅動訊號(步驟201)。 各個第-位移暫存器與各個第二位移暫存器 _訊號與第二_縣 ^ ， 模電晶體之導通時間(步驟逝）。W’咖各個薄 200910305 第7圖係為本發明筮-誉 7岡, 弟一貫^例之驅動方法步驟流程圖。如第 0所不，本發明之雙邊閘極, _ ^ ^ ^ 薄膜電晶體、具有複數式之液日日顯^包括有複數個 有複數個第二位移暫存tr㈣暫存器之第1極驅動器與具 步驟： 。°弟—驅動益，該驅動方法包含有下列 錢，!!_狀責任職為大於25%但小於篇之 ^ ’亚輸人至各級第—位移暫存器與各級第二位移暫存器（步驟 〇)。驅動訊號包含有直流參考電壓、起始脈波職 與反相時脈訊號。 訊號 伸暫存器煞辦二帅暫翻根據驅動 -門二二…登時間小於1/2但大於1/4週期脈波寬度之第 ”驅動峨與第二·驅動訊號(步驟3〇1)。 各個第轉暫存器與各個第二位移暫存器傳輸第 第:閉極訊號至複數個薄膜電晶體，以控制各個薄膜電晶 月立之導通時間(步驟3〇2)。 另外，假設理想的閘極驅動訊號n〇的電阻-電容延遲時 =day time_。鞋_歧轉娜，㈣姻足下喊 =0.99· yp(^ = o)+|iDs，dt .(2) 其中乂為_線的電位，VD為資料線的電位，Vp為晝素 的電位，L為充電電流，Cp為液晶電容，Cs為晝素電容(如第8 圖所示）’因此’若要達到充電率為99%，則_電晶體40所需 200910305 =_動訊號之導物竭—有效充電 電容延遲時間td。 刀上电丨且- 、τ'上所述’本發明之雙邊開極驅動式之液晶顯示器及与動 =:射輯4姆縣器軌號之責純耻健地= 、、。，叹位移暫存轉出的_驅動減之時序無重疊 :Γ=:驅動訊號重疊時兩晝素同時充電而造成功率消耗的; =進叫低雙邊閘極驅動式之液晶顯示器的耗電量，另外，將 訊號之責任週期比調變至大於25%但小於 4㈣存讀㈣閑極驅動訊號可S早—段時間門 :=:::她―輸過程二 定本=本彳述之較佳實施例揭露如上，然其並非用以限 内，何作此補者，在不脫離侧之精神和範圍 本說明書制飾，因此本剌之專利健範圍須視 曰、申明專利範圍所界定者為準。 【圖式簡單說明】 第1圖係為習知技術中使用雙邊閘極— 電晶體液晶顯示器之電路示額； e…動的溥膜 第2圖係為習知技術中雙邊間極驅動器之 號與輸出訊號之時序示意圖； 娜叩輸入祝 哭於盘^本裔明第一貫施例之雙邊問極驅動器之位移暫存 扣輸入甙唬與輪出訊號之時序示意圖； 第4圖係為問極訊號與資料訊號之充電時間比較示意圖； 12 200910305 第5圖係為本發明第二實施例之雙邊閘極驅動器之位移暫存 器輸入訊號與輸出訊號之時序示意圖； 第6圖係為本發明第一實施例之驅動方法步驟流程圖； 第7圖係為本發明第二實施例之驅動方法步驟流程圖；及 第8圖係為本發明之薄膜電晶體之電路不意圖。 【主要元件符號說明】 10 第一位移暫存器 11 第一閘極線 20 第二位移暫存器 21 第二閘極線 30 貧料驅動斋 31 資料線 32 資料訊號 40 薄膜電晶體 110 理想的閘極驅動訊號 120 形變的閘極驅動訊號 cp 液晶電容 cs 晝素電容 CICL 左側匯流排的時脈訊號 CKR 右側匯流排的時脈訊號 G1L 第一閘極驅動訊號(左） - G1R 第二閘極驅動訊號(右）A first gate drive signal (eg, gil, coffee, G3L, G4T ° ••, etc.) that produces the timing of the drive signal. The driving signal includes a DC reference voltage, a starting pulse 汛唬, a clock signal, and an inverted clock signal. A plurality of second displacement registers 2 receive the driving signal of the right bus and generate a second gate corresponding to the material of the driving number, _ signal (for example, G1R, G2R, G) R G4R, G5R, etc.) . The drive signal includes a DC reference voltage, a start pulse signal, a clock signal, and an inverted clock signal. Each of the first shift register 10 and the driving signal received by each of the first hash registers 20 has a pulse width of 1/4 cycle, and each of the first shift register 10 and each of the second shift registers According to the receiving white, the first gate driving signal and the first gate driving signal having a periodic pulse width are generated to control the conduction time of the plurality of thin transistors. - Figure 3 is a timing diagram of the input and output signals of the shift register of the double-side gate driver of the first embodiment of the present invention. As shown in Figure 3, the period of CKL, XCKL, CKR, and Xckr is τ, the length of the gate drive signal is shaped, and the tool is delayed by 1/4 clock period from CKL and XCKL. Stl, STR, CKL, XCKL, CKR, and XCKR have a pulse width of 1/4 cycle. 1 Through the week, the duty cycle ratio of CKL, XCKL, CKR and xCKR is 2:>/〇 to make any two gate drive signals (for example, the first gate drive signal 200910305 (c) GiL, the second Gate drive signal (right) G〗 R, _ (left) G2L, first: gate drive signal (right) G times... ~ drive signal (left) G3L, second polarity drive signal (right) G3R) Buzzer drives the signal signal timing sequence to avoid overlap between the two books when the open drive signals overlap. The problem of such extreme displacement consumption. / 'The same day 7 charging and success 4th picture is the idle signal and the data signal ▲ Brother 4 picture is not 'ideal _ pole drive signal ιι〇 and capital::: Figure 2 as effective for the day of the thunder FH, do the first step of the composition - production:::==== When the charging time of the younger brother is charged, the equivalent charging time of the pixel is reduced === Κ, for larger pixel capacitance In fact, 'there may be insufficient charging;: Therefore, the opening time of the inter-driver drive number is advanced = reachable:: maximum charging time. Because of the different primary antibody = (four) delay, because the length of the scale - is variable, in order to make the maximum cut charge of the painting and the miscellaneous duty time, the money is turned around (four) can be arbitrarily adjusted to achieve maximum charge effectiveness. The brother: > is a timing diagram of the input signal and the round-out signal of the double-side idler driver of the second embodiment of the present invention. As shown in Fig. 5, the period of feeding, xc^(10) and XCKR is T, and CKR and XCKR are delayed by 1/4 of the clock period of CKL and XCKL, respectively. The duty cycle ratio of CKL XCfCL, CKR, XCKR is adjusted to be greater than %% 200910305 but less than 50%, and CKL and CKR are 1/4 phase difference, XCKL and X(:KR are 1/4 phase difference, adjacent The overlap time of the two gate drive signals is Δ Ή, and the relationship between the _ / stack time Δ Η and the duty cycle ratio is as follows (1): △ Η = responsibility week...... ................. where Τ is the period, and when the overlap time 相等 is equal to the time length Aic, it has the largest pixel charging efficiency. Thus, by adjusting the displacement register The timing overlap time of the idle-driving driving signal can improve the charging rate shortage caused by the delay of the pixel charging time caused by the waveform head of the gate driving signal, and the timing overlap time of the gate driving signal is higher. Shortly, excessive power consumption can still be avoided. Fig. 6 is a flow chart showing the steps of the driving method according to the first embodiment of the present invention. The bilateral 'hip type liquid crystal display II of the present invention includes a plurality of _ transistors, ^ has a plurality of The first-displacement temporary storage H-gate drive B and the second positional loader with a plurality of second displacement registers, the crane The method includes the step of arranging and after inputting the modulation, firstly, the duty cycle ratio of the modulation drive signal is 25%, and the motion signal is sent to each of the first displacement register and each second displacement register (step ^ The driver series includes the DC reference cake, the initial pulse signal signal and the inverted clock signal. (9) The material clock and the two rotations of the temporary storage wheel are inserted to produce the first 1/4 cycle air wave width. Drive signal, brother-gate drive signal (step 201). Each first-displacement register and each second displacement register_signal and second_county^, the on-time of the die transistor (step elapsed). 'Cai's thin film 200910305 Fig. 7 is a flow chart of the driving method steps of the invention 筮 誉 誉 冈 , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The liquid-day display with a plurality of types includes a plurality of first-pole drivers having a plurality of second-displacement temporary storage tr(four) registers and a step: the brother-driver, the driving method includes the following money! !_ The responsibility of the job is greater than 25% but less than the ^ 'Asian input to the first level - displacement register and each The second displacement register (step 〇). The driving signal includes a DC reference voltage, a starting pulse wave and an inverted clock signal. The signal extension register is operated by the second handsome according to the driver-door two two... The first "drive" and the second drive signal (step 3〇1) with a log-on time less than 1/2 but greater than 1/4 of the pulse width. Each of the first transfer registers and each of the second shift registers transmits the first : Closed-circuit signal to a plurality of thin-film transistors to control the on-time of each thin-film electron crystal (step 3〇2). In addition, assume that the ideal gate drive signal n〇 has a resistance-capacitance delay = day time_. Shoes _ 转 转娜, (4) screaming under the marriage = 0.99 · yp (^ = o) + | iDs, dt. (2) where 乂 is the potential of the _ line, VD is the potential of the data line, Vp is the potential of the halogen, L is the charging current, Cp is the liquid crystal capacitor, and Cs is the halogen capacitor (as shown in Figure 8). Therefore, if the charging rate is 99%, then the transistor 40 needs 200910305 = _ signal guide Exhaustion—effective charging capacitor delay time td. The knives are powered on and - τ' is described above. The bilateral open-drive liquid crystal display of the present invention and the motion of the mobile phone are the responsibility of the singer. The sinus displacement is temporarily transferred out of the _ drive minus the timing without overlap: Γ =: when the drive signal overlaps, the two halogens are simultaneously charged to cause power consumption; = low power of the double-sided gate-driven liquid crystal display In addition, the duty cycle ratio of the signal is adjusted to be greater than 25% but less than 4 (4) deposit (4) idle drive signal can be S early - time gate: =::: she - the process of the second process = better The embodiments are disclosed above, but they are not intended to be used in any way, and the present invention is not limited to the spirit and scope of the specification. Therefore, the scope of patents of this patent is subject to the definition of patent scope. quasi. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a bilateral gate-transistor liquid crystal display used in the prior art; the second diagram of the e-moving diaphragm is the number of the bilateral interpole driver in the prior art. Schematic diagram of the output signal and the timing of the output signal; Na叩 input wish to cry in the disk ^ The first time the case of the local application of the displacement of the temporary drive button input 甙唬 and the turn-off signal timing diagram; Figure 4 is asked Schematic diagram of the charging time of the polar signal and the data signal; 12 200910305 FIG. 5 is a timing diagram of the input signal and the output signal of the displacement register of the bilateral gate driver according to the second embodiment of the present invention; FIG. 6 is the present invention FIG. 7 is a flow chart showing the steps of the driving method of the second embodiment of the present invention; and FIG. 8 is a circuit diagram of the thin film transistor of the present invention. [Main component symbol description] 10 First shift register 11 First gate line 20 Second shift register 21 Second gate line 30 Lean drive zail 31 Data line 32 Data signal 40 Thin film transistor 110 Ideal Gate drive signal 120 Deformation gate drive signal cp Liquid crystal capacitor cs Alizarin capacitor CICL Clock signal on left side bus CKR Clock signal on right side bus G1L First gate drive signal (left) - G1R Second gate Drive signal (right)
G2L 第一閘極驅動訊號(左） 13 200910305 G2R 第二閘極驅動訊號(右） G3L 第一閘極驅動訊號(左） G3R 第二閘極驅動訊號(右） Η 時間長度 Η1 第一有效充電時間 Η2 第二有效充電時間 IDS 充電電流 STL 左側匯流排的起始脈波訊號 STR 右侧匯流排的起始脈波訊號 T 週期 ΝΌ 貢料線的電位 V。 閘極線的電位G2L first gate drive signal (left) 13 200910305 G2R second gate drive signal (right) G3L first gate drive signal (left) G3R second gate drive signal (right) Η time length Η 1 first effective charge Time Η 2 Second effective charging time IDS Charging current STL The starting pulse signal of the left busbar STR The starting pulse signal of the right busbar T period ΝΌ The potential V of the tributary line. Potential of the gate line
Vp 晝素内的電位 XCKL左側匯流排的反相時脈訊號 XCKR右側匯流排的反相時脈訊號 ΔΗ 重疊時間Potential in Vp pixel XCKL Inverted clock signal on the left busbar XCKR Inverted clock signal on the right busbar ΔΗ Overlap time
Ate 時間長度 14Ate length of time 14