200917436 九、發明說明： 【發明所屬之技術領域】 有較-種具電㈣接結構之料基板及 接Γί’/更詳而言之，係有1於—種於封録板之電性連 作方/成導f柱’以供接置錫球之電性連接結構及其製 【先前技術】 目前半導體封裝技術包括打線式（Wire bQnding)及 嫌ri(FIip Chip)半導體封裝技術，其中打線式封裳結 ^用辉線來將半導體晶片電性連接至封震基板，覆晶 式封裝結構其所封裝之半導體晶片係以主動面朝下之倒 ΐ!"式安置於封裝基板上，並藉由複數個凸塊（β_)焊接 對應電性連接封裝基板之焊錫凸塊。 明夢閱第1Α至1F圖所示，係為習知封裝基板表面植 设焊錫凸塊之製法剖視示意圖；首先，提供一具有第—表 面l〇a及第二表面1〇b之封裝基板本體1〇，且該第一表& 面l〇a及第二表面1〇b分別具有複數第一及第二電性連接 墊lla’llb,於該封裝基板本體1〇之第一表面1〇&及第 :電性連接墊Ua表面形成一第一絕緣保護層12a，且該 =一絕緣保護層12a表面形成有複數第一開孔12〇a，以" 露出各該第一電性連接墊之部分表面Ua之部份表面，又 於該封裝基板本體1()之第二表面1Qb及第二電性連接塾 表面升y成第一絕緣保護層12b，且該第二絕緣保護 層12b表面形成有複數第二開孔12〇b，以露出各該第二 110416 5 200917436 電it連接墊llb之部份表面，纟中，該第一電性連接塾 Ua與該第二電性連接墊llb係藉由該封裝基板本體1〇 2之内線路層（圖未示）進行導接（如第u圖所示）；於該 第-絕緣保護層12a表面及第一電性連接塾iia表面形成: 助焊層14(如第1B圖所示）；之後於該第一絕緣保護層 12a之各該第—開孔12Qa中置人—錫球15，使該錫球^ 设於該第一電性連接墊lla表面（如第lc圖所示然 (後，該錫球15及助焊層14經迴焊製程以形成—係為焊錫 凸塊之導電元件15,，且該導電元件15，並電性連接 :電性連接墊lla(如第1D圖所示）；最後，移除該第一 、’巴緣保—護層12a表面之助焊層14，即於該封裝基板本體 10之第一電性連接墊lla表面形成外露之導電元件u， (如第1E圖所示）；之後於該第二電性連接塾爪表面以 印刷形成焊球16(如第1F圖所示），以供接置印刷電路板。 奸惟’該錫球15係置於該第一開孔^中，因為該 t/第一電性連接塾lla低於該第一絕緣保護層⑵，且該錫 球15之大小尺寸及第一絕緣保護層⑵之第一開孔服 大小非均- ’使該些錫球15纟必能良好接觸於該第一電 =接塾11a的表面’當該錫球15經迴焊製程而成為液 悲時’部分錫球15因絕緣保護層有拒縮錫的效應，使該 錫球15因流動而不易定位於該第一絕緣保護層m之第 -開孔120a中，導致製程中必須進行修補的動作，而揷 加製程中的困難度；且該半導體元件接置於封裝基板本曰 體後，因導電元件15,之高度較低，使該半導體元件與封 Π0416 6 200917436 衣基板本體之間的間隙較小，導致用以供作底部填充的底 部封膠（underfill)不易填入，如此即造成空隙，容易於 後續熱循環製程中產生爆米花效應（p〇pc〇rn)，使得該 =裝基板本體與半導體元件之間易產生脫離的情況，進而 影響該封裝基板本體與半導體元件的封裝品質。 、因此，如何提升植球良率，縮短生產時間以降低生產 成本並避免造成應力不均及進行底部填膠不確實，生 ，產生爆米花效應之缺失，實為業界㈣思考之課題/ 【發明内容】 、 鑒於以上所述習知技術之缺點，本發明之一 =種具電性連接結構之封裝基板及其製法，植 球良率，以縮短生產製程時間。 植 本發明之另一目的為提供一 裝基板及其萝夺，俨滅A * 裡，、电性連接結構之封 土极及具衣法，侍避免底部填膠不確 米花效應之缺失。 、 化成產生爆 為達上揭目的’本發明提供_種具電 板，係包括··封裝基板本體，係具之封 連接墊之部分表面；導妹，係奸 ^各該弟-電性 連接該第一電性連接墊，且今、〜第開孔中並電性200917436 IX. Description of the invention: [Technical field to which the invention pertains] There are more than one type of material substrate and connection structure with electric (four) connection structure. In more detail, there is an electrical continuous operation of the type of the sealing board. Square/guided f-pillar' for electrically connecting the solder ball and its system [Prior Art] At present, semiconductor packaging technology includes wire bQnding and ip (FIip Chip) semiconductor packaging technology, in which wire bonding The semiconductor wafer is electrically connected to the sealed substrate by a bright wire, and the semiconductor wafer packaged by the flip-chip package is placed on the package substrate with the active surface facing downwards. Solder bumps corresponding to the electrical connection of the package substrate are soldered by a plurality of bumps (β_). FIG. 1 is a schematic cross-sectional view showing a method of implanting solder bumps on a surface of a conventional package substrate. First, a package substrate having a first surface 10a and a second surface 1〇b is provided. The first surface & surface 10a and the second surface 1〇b respectively have a plurality of first and second electrical connection pads 11a'11b on the first surface 1 of the package substrate body 1 A first insulating protective layer 12a is formed on the surface of the 〇& and the electrical connection pad Ua, and a plurality of first openings 12a are formed on the surface of the insulating protective layer 12a to expose the first electric a part of the surface of the surface Ua of the connecting pad is further raised to the first insulating protective layer 12b on the second surface 1Qb and the second electrical connecting surface of the package substrate body 1 (), and the second insulating protection A plurality of second openings 12〇b are formed on the surface of the layer 12b to expose a portion of the surface of each of the second 110416 5 200917436 electrical connection pads 11b, wherein the first electrical connection Ua and the second electrical The connection pad 11b is guided by a circuit layer (not shown) inside the package substrate body 1〇2 (as shown in FIG. a surface of the first insulating protective layer 12a and a surface of the first electrical connection 塾iia are formed: a soldering layer 14 (as shown in FIG. 1B); and then the first opening of the first insulating protective layer 12a The hole 12Qa is placed in the tin ball 15 so that the solder ball is disposed on the surface of the first electrical connection pad 11a (as shown in the figure lc) (after the solder ball 15 and the solder layer 14 are reflowed) The conductive element 15 is formed as a solder bump, and the conductive element 15 is electrically connected: an electrical connection pad 11a (as shown in FIG. 1D); finally, the first, 'ba margin is removed The solder layer 14 on the surface of the protective layer 12a forms an exposed conductive element u on the surface of the first electrical connection pad 11a of the package substrate body 10 (as shown in FIG. 1E); The surface of the claw is connected to form a solder ball 16 (as shown in FIG. 1F) for attaching the printed circuit board. "The solder ball 15 is placed in the first opening ^ because the t/ The first electrical connection 塾lla is lower than the first insulating protective layer (2), and the size of the solder ball 15 and the size of the first opening protective layer of the first insulating protective layer (2) are non-uniform- The solder ball 15 must be in good contact with the surface of the first electric connection port 11a. 'When the solder ball 15 is turned into a liquid sorrow through the reflow process, the partial solder ball 15 has a tin-reducing effect due to the insulating protective layer. The solder ball 15 is not easily positioned in the first opening 120a of the first insulating protective layer m due to the flow, so that the repairing process must be performed in the process, and the difficulty in the process is added; and the semiconductor component is connected. After the substrate is packaged, the height of the conductive element 15 is low, so that the gap between the semiconductor element and the body of the package 0416 6 200917436 is small, resulting in a bottom seal for underfilling. ) It is not easy to fill in, so that voids are formed, and popcorn effect (p〇pc〇rn) is easily generated in the subsequent thermal cycle process, so that the detachment between the substrate body and the semiconductor element is easily caused, thereby affecting the package. The package quality of the substrate body and the semiconductor component. Therefore, how to improve the yield of the ball, shorten the production time to reduce the production cost and avoid the unevenness of the stress and the inaccurate bottom filling, the lack of the popcorn effect, and the industry (4) the subject of thinking / [invention In view of the above-mentioned shortcomings of the prior art, one of the present inventions is a package substrate having an electrical connection structure and a method for fabricating the same, and the ball yield is reduced to shorten the production process time. Another object of the present invention is to provide a substrate and a substrate, a annihilation A*, a sealing structure of the electrical connection structure and a coating method, and to avoid the lack of the under-filling effect. The present invention provides a slab with an electric board, which includes a package substrate body, a part of the surface of the sealing pad of the device; a sister, a traitor, each of the brothers-electrical connection The first electrical connection pad, and the current, the first opening and the electrical
面，廿於道+ 龙出於該第—絕緣伴★舊展I 面，亚於導電柱頂面具有凹陷區 緣保。美層表 於該凹陷區中。 及¥包元件，係結合 依上述結構’復包括一 導電層係設於該電性連接墊與 Π0416 7 200917436 導電柱之間。 本發明復提供一種具電性連接結 法’係包括：提供一具有第一表面之。、衣土板‘ 封衣基板本體，於該 弟表面具有複數第-電性連接塾， 層並形成複數第一開孔，以露出 弟心緣保k 性2墊之開孔中分別形成電性連接至該第一電 突出於該第—絕緣保護層表面，並 …，¥電柱頂面形成凹陷區；於各該 分別形成黏著声.以另访兮、曾兩守电柱之凹表面 岸分別接署怨Γ 該¥電柱之凹陷區表面的黏著 i:: 牛:ί:經迴厚製程使該黏著層及錫球形成導 %兀件以結合至該凹陷區。 依上述製法，復包括於該絕緣保護 :形:助焊層—該錫球、黏著層及助焊層= 场成係為焊錫凸塊之導電元件，且該導電元件係位 焊=導電柱之凹陷區中’最後移除該絕緣保護層表面之助 -^依土述之製法’該導電柱之製法，係包括：於該第 形：導：：層表面、第一開孔表面及第一電性連接墊表面 層，於該導電層表面形成第一阻層，且該第一阻 =形成有第1口以露出位於該第—絕緣保護層及其 孔中之導電層的部份表面；於該第一阻層之第一開 及弟—絕緣保護層之第—開孔中的導電層表面電鑛形 成该導電柱’且該導電柱之周圍高於中心部位，以於該導 t &頂面形成該凹陷區；以及移除該第一阻層及其所覆蓋 110416 8 200917436 之導電層以露出該導電柱。 本發明之具電性連接結構之 電柱係突出於該絕緣保護層表面^ &其製法，該導 該凹陷區，於該凹㈣中具有 ':广導電柱頂面具有 形狀及助焊層之沾溼性 x〒曰，猎由該凹陷區之 中，俾以提”吉… 能順利定位於該凹陷區Face, 廿 in the road + dragon out of the first - insulation with the old exhibition I side, the top of the conductive column has a concave area edge protection. The beauty layer is in the recessed area. And the package component, according to the above structure, includes a conductive layer disposed between the electrical connection pad and the conductive pillar of Π0416 7 200917436. The present invention provides an electrical connection method comprising: providing a first surface. The cover plate body of the dressing board has a plurality of first-electrical connection ports on the surface of the brother, and a plurality of first openings are formed in the layer to form electrical properties respectively in the openings of the pad 2 Connected to the first electric protrusion on the surface of the first insulating protective layer, and ..., the top surface of the electric pole forms a concave area; respectively, the adhesive sound is formed respectively, and the concave surface of the two electric fences is separately visited. The grievance of the surface of the recessed area of the electric pole i:: cattle: ί: The thick layer is made to form the adhesive layer and the solder ball to form a guide element to be bonded to the recessed area. According to the above manufacturing method, the insulation protection is included: shape: the soldering layer - the solder ball, the adhesive layer and the soldering layer = the field forming is a conductive member of the solder bump, and the conductive element is a spot welding = a conductive column In the recessed area, the last method of removing the surface of the insulating protective layer is the method of manufacturing the conductive column, which comprises: forming the surface: the surface of the layer, the surface of the first opening, and the first a surface layer of the electrical connection pad, forming a first resist layer on the surface of the conductive layer, and the first resistor is formed with a first opening to expose a portion of the surface of the conductive layer located in the first insulating protective layer and the hole thereof; Electrolyzing the surface of the conductive layer in the first opening of the first resist layer and the first opening of the insulating layer to form the conductive pillar 'and the periphery of the conductive pillar is higher than the central portion, so that the conductive <RTIgt; The top surface forms the recessed region; and the first resistive layer and the conductive layer covered by 110416 8 200917436 are removed to expose the conductive pillar. The electric column with the electrical connection structure of the present invention protrudes from the surface of the insulating protective layer, and the concave portion has a shape in the concave (four): the top surface of the wide conductive column has a shape and a soldering layer Humidity x 〒曰, hunting from the depression area, 俾 to mention "ji... can be positioned in the depression
评以杈呵植球良率，進而降 ㈢L 迴焊製程中形成該導仫成本，且該錫球經 中，該導電桎頂面具有凹& , 等电柱之凹陷區 四虿凹fe £且突出於該絕 面，故利於導電元件定位 保濩層表 玲道帝a θ 其上’俾以增加植球良率，曰 ^電柱具有較高之高度’於該封裝基板本體盘半 件之間传保持較大之空隙，以供填入底部填腰 疋 (underfill)，俾以避免產 、/ 缺失。 兄座生工㈣致產生爆米花效應之 【實施方式】 定的㈣實施例說明本發明之實 式，戶 1 屬技術領域中具有通常知識者可由本說明書所揭示 之内谷輕易地瞭解本發明之其他優點與功效。 »月 > 閱第2Α至2 J圖所示，本發明具電性連 封裝基板製法之示意圖。 構之 如第2Α圖所示，提供一具有第一表面20a及第二表 面20b之封裝基板本體2〇，於該第一表面2〇a及第二表 面湯分別具有複數第—及第二電性連接墊21a，21b，1 於該第一表面20a及第一電性連接墊21a表面形成有第一 絕緣保護層22a，於該第—絕緣保護層22a中形成有第一 110416 9 200917436 開孔22_露出該第—電性連接墊…之部份表面，又 於該第二表面2〇b及第二 二 奶終仅γ a 冤〖生連接墊21b表面形成有第 、、、巴、、“瘦s 22b’於該第二絕緣保護層咖中形成有第— =孔220b以露出該第二電性連接墊犯之部份表面，里 電性連接墊21a與該第二電性連接墊灿係藉 由該封:基板本體2〇中之内線路層（圖未示）進行導接。 如第2B圖所示，接著，利用物理沈積或化學沈積等 方=例如雜（Sputtering)、蒸 _vapQmi〇n)、、電 八 Vap〇r deP〇slti〇n)、離子束濺鍍（I〇n beam sputtering)、雷㈣散沈積（Laser ablati〇n deP〇sltlQn)、㈣促進之化學氣相沈積及無電解電鑛等 ^三於該第-絕緣保護層22a表面、第—開孔心表 面及弟-電性連接墊21a表面形成導電層23，且於 電層23表面形成有第一阻層仏，又該第一阻層…經 由曝光(Exp0Sure)、顯影(Devel〇pment)等圖案化製程形 成有複數有第-開口 2術以露出位於該第—絕緣保護層 及其第-開孔22〇a中之導電層23的部份表面；接 著，於該第二絕緣保制22b表面及第二電性連接塾灿 表面形成有第二阻層24b。 —如第2C圖所示，於該第一阻層24a之第一開口 24〇a 及第一絕緣保護層22a之第一開孔220a中的導電層23 表面電鍍形成一導電柱25’且該導電柱25之周圍二於中 ^位以於B亥導電柱25頂面形成一凹陷區250;該凹 陷區250係利用控制電鐘液中之酸度與金屬含量兩者之 110416 10 200917436 1 9 tb例所H例如可藉由提高電錢液之酸度並降低金 屬含量以形成該凹陷區25〇。 如弟2D圖所示，夕雜 、赶 之後於遠導電柱25之凹陷區250 表面形成係如化鍍錫或電鍍錫之黏著層251。 :第2E圖所示’移除該第—阻層2乜及其所覆蓋之 導毛層23以露出該導電柱25。 及斑=2F ^所7F ’ ·然後於該第—絕緣保護層22&表面 毒者層251表面形成助焊層（nux)26。 助焊Π/圖所示，於該導電柱25之凹陷區250表面之 中。 ，使该錫球27位於該凹陷區25〇 如第2H圖所示，該錫球27、黏 經迴焊製程以形成係為焊錫凸塊之㈣元 該導電柱25之凹㈣25G卜㈣讀27，且位於 如第21圖所示’最後’移除該第'絕 表面之助焊a 衫、，，. 水饰！臂Z2a 26;接菩，:，係 活性劑或溶劑清除該助焊層 年夕除該第二絕緣保護層| ρ 曰 24b以露出該第二電性連接墊21b b表面之弟二阻層The evaluation of the ball yield, and then the (three) L reflow process to form the guide cost, and the solder ball through the middle, the conductive dome has a concave & And it is prominent in the faint surface, so it is advantageous for the conductive element to locate the 濩 layer of the 玲 帝 帝 帝 a θ on the '俾 to increase the ball yield, 曰 ^ electric column has a higher height 'in the package substrate body half Intermittently maintain a large gap for filling the bottom of the underfill, to avoid production, / missing. [Embodiment] (4) The embodiment of the present invention is described in the technical field of the present invention. Those having ordinary knowledge in the field of households can easily understand the present invention by the inner valley disclosed in the present specification. Other advantages and effects. »月> Read Figures 2 to 2J show a schematic diagram of a method for fabricating an electrically conductive package substrate of the present invention. As shown in FIG. 2, a package substrate body 2 having a first surface 20a and a second surface 20b is provided, and the first surface 2a and the second surface soup respectively have a plurality of first and second electricity The first connection surface 21a and the first electrical connection pad 21a are formed with a first insulating protective layer 22a, and the first insulating layer 22a is formed with a first 110416 9 200917436 opening. 22_ expose a part of the surface of the first electrical connection pad, and at the second surface 2〇b and the second second milk, only γ a 冤 the surface of the raw connection pad 21b is formed with a first, a, and a The thin s 22b' is formed with a first hole 220b in the second insulating protective layer to expose a part of the surface of the second electrical connecting pad, and the inner connecting pad 21a and the second electrical connecting pad The can is guided by the inner circuit layer (not shown) in the substrate body 2〇. As shown in FIG. 2B, next, physical deposition or chemical deposition is used, for example, sputtering, steaming. _vapQmi〇n), electric eight Vap〇r deP〇slti〇n), ion beam sputtering (I〇n beam sputtering), thunder Dispersion (Laser ablati〇n deP〇sltlQn), (4) promoted chemical vapor deposition and electroless electrowinning, etc. on the surface of the first-insulating protective layer 22a, the first-opening core surface and the younger-electrical connection pad A conductive layer 23 is formed on the surface of the surface 21a, and a first resist layer is formed on the surface of the electric layer 23. The first resist layer is formed by a patterning process such as exposure (exposure) and development (Develpment). Opening 2 to expose a portion of the surface of the conductive layer 23 located in the first insulating protective layer and the first opening 22a; and then, the surface of the second insulating protective 22b and the second electrical connection A second resist layer 24b is formed on the surface. - as shown in FIG. 2C, the surface of the conductive layer 23 in the first opening 24A of the first resist layer 24a and the first opening 220a of the first insulating protective layer 22a Electroplating forms a conductive pillar 25' and the periphery of the conductive pillar 25 is at a middle position to form a recessed area 250 on the top surface of the BH conductive pillar 25; the recessed zone 250 utilizes the acidity and metal content in the control electric clock liquid. 110416 10 200917436 1 9 tb example H can be raised, for example, by increasing the acidity of the money liquid and reducing the gold The content is formed to form the recessed region 25〇. As shown in the 2D figure, an adhesive layer 251 such as tin or tin plating is formed on the surface of the recessed region 250 of the far conductive pillar 25 after the rush. Showing 'removing the first-resistive layer 2乜 and the covered layer 23 thereof to expose the conductive pillars 25. And spots = 2F ^ 7F ' and then on the first insulating protective layer 22 & surface toxic layer A 251 surface forms a solder layer (nux) 26. The solder fillet/figure is shown in the surface of the recessed region 250 of the conductive post 25. The solder ball 27 is located in the recessed area 25, as shown in FIG. 2H. The solder ball 27 is adhered to a solder reflow process to form a (four) element which is a solder bump. The conductive pillar 25 is concave (four) 25G (four) read 27 And located in the 'final' as shown in Figure 21 to remove the 'absolute surface of the welding a shirt,,,. Water! The arm Z2a 26; the diapir, the active agent or the solvent removes the soldering layer, except the second insulating protective layer | ρ 曰 24b to expose the second resistive layer on the surface of the second electrical connecting pad 21b b
刷形該第二電性連接墊训表面以印 取坪球28，以供接置印刷電路板， P 成焊：找係為成熟之技術，於此不再:文中賛述該印刷形 發明缺供-種具電性連接結構梦其 封農基板本體20,於該第__表 裝基板’係包 連接塾叫，且該第-表面_覆,_第=有複數電性 弟一絕緣保護層 π Π0416 200917436 夂丈弟開孔220a以露出各該第一電 墊之部分表面21a ;導雷衽舛〆 电注運接 導电柱25 ’係设於該第一開孔Brushing the second electrical connection pad training surface to print the flat ball 28 for receiving the printed circuit board, P welding: finding the system as a mature technology, no longer: the text is succinct Providing an electrical connection structure dreaming of the agricultural substrate body 20, the __table substrate is attached to the squeaking squeak, and the first surface _ _ _ _ _ _ _ _ _ _ _ _ _ _ Layer π Π 0416 200917436 夂 弟 开 220 220 220a to expose a part of the surface 21a of each of the first electric pad; guide Thunder electric injection connection conductive column 25 ' is set in the first opening
中並電性連接該第一電性連 2〇S 綾保〇。 电’生運接墊2ia，且突出於該第一絕 、，彖保5瘦層22a表面，並於暮雪知9ς ' V迅柱25頂面具有凹陷區250 ; 以及V電兀件27，’係結合於該凹陷區25〇中。 連二述復包括一導電層23係設於該第-電性 運接塾21a與導電柱25之間。 ^ =發明之具電性連接結構之封裝基板及其製法，由於 二柱25係突出於該第一絕緣保護層％表面，並於 遠導電柱25頂面具有該凹陷區250，且於該凹陷區25〇 中具有該助焊層26，藉由該凹陷區250之形狀及助焊層 々^刀子之間的吸引力，使該錫球27能順利定位於該凹 區25。巾’俾以提高植球良率，進而降低生產成本。 又該導電元件27,有較高的高度，使該封裝基板本體 一接置半導體元件之後，於該封裝基板本體20與半導體 〇兀件之間得保持較大之空隙，以供填入底部填勝，俾以避 免產生空隙導致產生爆米花效應之缺失。 惟以上所述之具體實施例，僅係用以例釋本發明之特 點及功效，而非用以限定本發明之可實施範疇，在未脫= 本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申請專利 乾圍所涵蓋。 【圖式簡單說明】 請參閱第1A至1F圖所示，係為習知封裝基板植設焊 110416 12 200917436 球之製法之示意圖；以及 第2A至2 J圖係顯示本發明具電性連接結構之封裝基 板製法之示意圖。 【主要元件符號說明】 10、20 封裝基板本體 10a' 20a 第一表面 10b 、 20b 第二表面 11a、21a 第一電性連接墊 lib 、 21b 第二電性連接墊 12a、22a 第一絕緣保護層 120a 、 220a 第一開孔 12b 、 22b 第二絕緣保護層 120b 、 220b 第二開孔 14、26 助焊層 15、27 錫球 15,、27， 導電元件 16、28 焊球 23 導電層 24a 第一阻層 240a 第一開口 24b 第二阻層 25 導電柱 250 凹陷區 251 黏著層 13 110416The first electrical connection is electrically connected to the first electrical connection. The electric 'sports pad 2ia, and protrudes from the surface of the first layer, the surface of the thin layer 22a, and has a recessed area 250 on the top surface of the V-Xun column 25; and the V-electrode piece 27, ' It is incorporated in the recessed area 25〇. The second embodiment includes a conductive layer 23 disposed between the first electrical interface 21a and the conductive post 25. ^ = Invented package substrate with electrical connection structure and method for manufacturing the same, since the two pillars 25 are protruded from the surface of the first insulating protective layer, and have the recessed region 250 on the top surface of the far conductive pillar 25, and the recess The solder layer 26 is provided in the region 25, and the solder ball 27 can be smoothly positioned in the recess region 25 by the shape of the recess region 250 and the attractive force between the solder layer and the knife. Towels are used to increase the yield of the ball, which in turn reduces production costs. Moreover, the conductive element 27 has a high height, so that after the package substrate body is connected to the semiconductor component, a large gap is maintained between the package substrate body 20 and the semiconductor component for filling the bottom portion. Win, 俾 to avoid the creation of voids leading to the lack of popcorn effect. The specific embodiments described above are merely used to illustrate the features and functions of the present invention, and are not intended to limit the scope of the present invention. Equivalent changes and modifications made by the disclosure of the present invention should still be covered by the following patent application. [Simple description of the drawings] Please refer to FIGS. 1A to 1F for a schematic diagram of a method for manufacturing a conventional package substrate implant 110416 12 200917436; and FIGS. 2A to 2J show an electrically connected structure of the present invention. Schematic diagram of the method of manufacturing the package substrate. [Major component symbol description] 10, 20 package substrate body 10a' 20a first surface 10b, 20b second surface 11a, 21a first electrical connection pad lib, 21b second electrical connection pad 12a, 22a first insulation protection layer 120a, 220a first opening 12b, 22b second insulating protective layer 120b, 220b second opening 14, 26 soldering layer 15, 27 solder ball 15, 27, conductive element 16, 28 solder ball 23 conductive layer 24a a resistive layer 240a first opening 24b second resistive layer 25 conductive pillar 250 recessed region 251 adhesive layer 13 110416