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TW200917400A - Chip packaging process including simplification and mergence of burn-in test and high temperature test - Google Patents

Chip packaging process including simplification and mergence of burn-in test and high temperature test

Info

Publication number
TW200917400A
TW200917400A TW096137594A TW96137594A TW200917400A TW 200917400 A TW200917400 A TW 200917400A TW 096137594 A TW096137594 A TW 096137594A TW 96137594 A TW96137594 A TW 96137594A TW 200917400 A TW200917400 A TW 200917400A
Authority
TW
Taiwan
Prior art keywords
test
burn
high temperature
mergence
pmc
Prior art date
Application number
TW096137594A
Other languages
Chinese (zh)
Other versions
TWI339871B (en
Inventor
Li-Chih Fang
Wen-Jeng Fan
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW096137594A priority Critical patent/TWI339871B/en
Publication of TW200917400A publication Critical patent/TW200917400A/en
Application granted granted Critical
Publication of TWI339871B publication Critical patent/TWI339871B/en

Links

Classifications

    • H10W72/0198—
    • H10W72/073—
    • H10W72/075—
    • H10W72/865—
    • H10W90/734—
    • H10W90/754—

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Disclosed is a chip packaging process including simplification and mergence of burn-in test and high temperature test. One or more memory chips are disposed on one or more substrate units of a substrate strip. The substrate strip has a plurality of trace-removal areas so that the outer pads between different units are electrically isolated. After finishing electrically connecting and encapsulating steps, a post mold curing (PMC) step is performed, meanwhile, burn-in test is performed. If necessary, a high temperature test is merged in the PMC step. Accordingly, the chips pass through the burn-in test in substrate strip level in advance prior to the package-singulating step and is combined into the PMC step, so that the sequent testing time is reduced.
TW096137594A 2007-10-05 2007-10-05 Chip packaging process including simplification and mergence of burn-in test and high temperature test TWI339871B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096137594A TWI339871B (en) 2007-10-05 2007-10-05 Chip packaging process including simplification and mergence of burn-in test and high temperature test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096137594A TWI339871B (en) 2007-10-05 2007-10-05 Chip packaging process including simplification and mergence of burn-in test and high temperature test

Publications (2)

Publication Number Publication Date
TW200917400A true TW200917400A (en) 2009-04-16
TWI339871B TWI339871B (en) 2011-04-01

Family

ID=44726384

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096137594A TWI339871B (en) 2007-10-05 2007-10-05 Chip packaging process including simplification and mergence of burn-in test and high temperature test

Country Status (1)

Country Link
TW (1) TWI339871B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI398949B (en) * 2009-07-29 2013-06-11 勝開科技股份有限公司 Image-forming image sensor package structure manufacturing method and package structure
TWI467589B (en) * 2010-03-31 2015-01-01 First Byte Technology Co Ltd Testing system for a dimm, memory unit for testing, and temperature controlled chip thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI398949B (en) * 2009-07-29 2013-06-11 勝開科技股份有限公司 Image-forming image sensor package structure manufacturing method and package structure
TWI467589B (en) * 2010-03-31 2015-01-01 First Byte Technology Co Ltd Testing system for a dimm, memory unit for testing, and temperature controlled chip thereof

Also Published As

Publication number Publication date
TWI339871B (en) 2011-04-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees