TW200915339A - Electronic data flash card with various flash memory cells - Google Patents

Abstract

An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input/output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

Description

200915339 IX. Invention: [Technical field of invention] The present invention relates to an electronic data flash memory card, especially to a =1! multiple flash memory unit flashing electronic data: recalling "internal control" Flash memory system and method [Prior Art] D ^ in the floppy disk or the personal data slot 7 transmitted through the network to ensure the security of the file by password or encryption code, personal text security or compression After being packaged, it will be sent. "In the transmission = process, the profile and the file are likely to be damaged due to the destruction of the password, encryption code, or security package, resulting in unauthorized access to personal information. With the development of P-pass flash memory technology, flash memory will gradually replace the magnetic disk as a storage medium for moving wires. Flash memory has significant advantages over floppy disk G 1 hard disk, such as high G impedance and Low power consumption. Due to the entity: smaller 'flash memory is also more conducive to mobile systems. In general, the flash potential j has become a development factor due to its high capacity and low consumption characteristics: for various performance, cost, and capacity requirements, many types of recording devices have emerged, so when one is only adapted to one The problem of moving the flash body card flash $ appears. The W-compatible (IV) memory-compatible PC card technology has been developed to combine flash memory with a standard architecture. Thanks to the XJSB standard, it is easier to implement and universal for 200915339. The development trend of flashing sensation. In addition to replacing the hard drive, it will replace the floppy _ flash memory can be connected to the floppy disk, because of the speed. (4) Disks for more storage capacity and faster access. Several features of the material standard such as fixed face time, processing package::? Processing and other requirements require additional processor resources. , better: , 込 〇 〇 p parts have been applied to a variety of dedicated integrated circuit.取 Speed == = = The speed of the storage is slow, and the storage of the _ interface is much slower than the Benjamin Driver's (IDE) interface. The above-mentioned coffee standard includes the additional resources required for the package. The introduction of the official order and the handshake can be slowed down - also the complaint, for only 2 of the Saki-Kissing Agreement - Bay Source but only when (10) transmission is idle. It shows the limitations introduced by the USB standard and some limitations. The first I has been programmed to write the U flash read body. There is also a fixed lifetime before the reprogramming. The lifetime of the magnetic region is limited, for example, two:: before == the number of magnetic regions. Correspondingly, according to the pre-write erasure feature, the memory is fast, and the erasure will destroy the flash memory. 2. It will solve the USB standard flash memory speed. The small computer system interface (scsi) and firmware can be used. For example, similar to the large capacity of the magnetic hard disk, the flash memory device is widely used as a storage medium before the SCSI:: flash memory

It is a standard large capacity device. Accordingly, the USB standard has been applied to the agreement for managing flash memory. m σ SCSI 200915339 SCSI Μ, ^ Λ, The disadvantage of 疋 是 is that they do not have an erase command to solve the pre-write copy of the flash memory. Therefore, the erase management is handled by the host system, and the Pm 15 will occupy the host resources. One solution is to introduce new USB package definitions, such as write flash, hidden 4 flash memory, and erase flash memory definitions. However, these definitions are not – the ‘H # effective way to handle flash memory, because of an additional agreement that requires additional host processing resources.

At the same time, they also cannot solve the magnetic domain loss problem. Another solution is to provide a driver for flash memory write processing. This is a different subroutine. In general, first read the data that is kissed and ask for the address of the memory. If there is already data in the address, the strike will execute an erase command. At this time, if the erase command is executed correctly & the implementation performs a write request. However, the driver takes advantage of the agreement that requires additional host processing resources. Solution: Provide a flash memory area format with two areas: data area and spare area. The redundant area contains: control data for managing the magnetic area mark. However, when the host system writes to the magnetic zone, the tag adds ASIC complexity. Disadvantages of the above methods and other known devices are the inclusion of additional host system resources for processing proprietary protocols and processing time for managing flash memory. Therefore, it is necessary to develop an electronic data flash memory card with a smart processing unit that supports the type of flash memory. An improved 2009 2009339 system and method for controlling flash memory must also be developed. The system and method can be applied to the USB standard, can adapt to the ASIC hardware, and can be easily 'economical and convenient to adapt to the existing technology. SUMMARY OF THE INVENTION p Ο . The invention provides an electronic data flash memory card including a flash memory device, a fingerprint sensor, an input/rounding interface circuit and a processing unit, and a flash memory card which can be used by a host computer such as a personal computer. Take notes or other electronic host device access. Due to the flash memory of electronic data: portable and durable 'Personal data can be stored in encrypted form in the flash memory device, so that it can only be accessed, for example, by setting fingerprint sensing on the card body To ensure that unauthorized users cannot misuse the card. Unit 0 invention - the embodiment, the flash memory controller is processed into part 'for controlling the operation of the flash memory device. The processing unit is connected to the flash memory ❹f 输出 output interface circuit. The flash memory ticker includes a flash memory type for detecting whether the flash memory device is flash type = ΓΓ supported flash memory type: dynamic memory of the personal storage flash memory detection algorithm code = In the case of at least one flash memory device, it can not only enable flash printing, but also enable the new fast body to change only the fast alpha body detection stored in the flash memory. The dynamic part of the algorithm does not need to be supported. This saves the total cost and the savings. When the development is unnecessary, according to the present invention, the flash memory controller is a component of the 200915339 unit for controlling the flash memory. The device is running, and the flash memory controller is generally compatible with most of the flash memory on the market. • The chip can store its dynamic flash memory algorithm in the u flash memory and only Keep a small part of the code in R〇M. The code in r〇m is mainly used to start the processing unit and load the dynamic code part onto the chip. ', on-chip code RAM' in R The code in 〇M can identify the flash memory by reading commands or other characters of the flash memory, so it is itch by the correct time; + everyone 〇^ Λ A command that can read the batting and/or load code from the flash memory to the flash memory. According to another embodiment of the present invention, the processing unit of the electronic data flash memory card has three options: a selection option, a programmable temple mode, a data recovery mode, and a reset mode. In the programmable mode β _ show, Bu processing, start the input / output interface circuit to obtain personal data from the host in the personal shell file, and store it in the flash memory. In the data recovery mode, the system will start the input/output interface circuit to transfer the data file to the main machine in the data reset mode, data file, case (and related fingerprint data) 〇^^ Beike) Wipe from a flash memory device. _, _6, RISC, aL =, the processing unit is 8 ° 51, any kind of microprocessor. A first USB interface circuit in accordance with the present invention in a milk or digital signal processor. The input/output interface circuit is a second method for using the BOT comb ear in accordance with the present invention, and the USB flash memory device uses the BOT protocol to negotiate between the host and the right side. The B0T is a ratio. The CBI is more effective and faster than the speed of the agreement, because the B0T transmission command, the resources of 200915339, the state is dependent on the default control end point coffee. According to another embodiment of the present invention;: for receiving from the host system to the small -, U memory controller package memory controller also includes a processor containing ^ requests. Flash index. The processor uses the index to determine the 'flash memory footprint'. The present invention: the rewriting or reading operation device further includes a memory control unit for recycling the used magnetic domain. Reprogrammed FIFO According to the foregoing system and method, the host system does not require a flash memory to match the ring, and the portion can interact with the flash memory controller. As a result, the speed of writing and reading data from flash memory is significantly improved when flash memory compatible with standard and ASIC configurations. [Embodiment] FIG. 1 is a schematic structural view of an embodiment of the present invention. As shown in FIG. 1 , an electronic data flash memory card 10 can pass through an interface bus 13 , a card reader 12 or other peripheral devices ( Not shown in the figure) is accessed by the host 9, including the card body 1, the processing unit 2, one or more flash memory devices 3, the fingerprint sensor 4, the input/output interface circuit 5, and an optional display unit 6. , a power source (such as a battery) 7 and a function key setting unit 8. The flash memory device 3 is disposed on the card body 1 and stores one or more data files, related password information, and related fingerprints by scanning one or more electronic data flash memory cards 1 〇 authorized users in a known manner. Fingerprint information. Only authorized users can access these stored data files. Data file 10 200915339 can be a graphic file or a text file. The fingerprint sensor 4 is set on the card body! On, it is used to scan electronic data flashing. The memory card 1〇 user's fingerprint to generate fingerprint scanning data. An example of a fingerprint sensor 4 that can be used in the present invention is disclosed in U.S. Patent No. 6,547,130, entitled "Integrated Circuit Card with Fingerprint Verification," the technical content of which is hereby omitted. DETAILED DESCRIPTION The fingerprint sensor disclosed in the above patent includes a scanning unit array for defining a fingerprint scanning space. The fingerprint scanning data includes a plurality of scanning line data obtained by scanning a corresponding scanning unit array row. The scanning unit array row passes through the array. The row direction scans the direction of the dentition. When detecting the fingerprint high level on the card body, each scanning unit generates a first logic signal, and vice versa generates a second logic signal. The input/output interface circuit 5 is disposed on the card body. 1 can be activated to establish communication with the host 9 via the interface bus 13 or the card reader 12 via a suitable interface. In a mode of the present invention, the input/output interface circuit 5 includes a D-through interface. The busbar 13 or the card reader 12 is connected to the host interface circuit of the host 9, the MMC card interface circuit, the CF interface circuit, the (10) interface circuit, and the pCI-Express interface. Road, coffee interface circuit, 8 kinds of interface circuit. The single 702 sighs on the card body 1, through the transmission line on the card body 1 and the flash memory device 3, the fingerprint sensor 4 and the input/output interface circuit $ Connection. In one embodiment of the present invention, the processing unit 2 employs a type of 8 051, 8052, 80286 microprocessor + T, such as that produced by Intel Corporation. Another implementation of the present invention t. The processing unit includes RISC, ARM, 200915339 = s2:: bit 2 processor. According to the aspect of the present invention, the portion is stored in the fast control, so that the program mode in the processing unit 3 is processed. In this mode, the processing unit 2 starts the mode: (D is written to receive the data slot from the host 9 and the phase: the fingerprint is output: the surface circuit 5 is stored in the flash memory device 3, 5, 5, and After storing it, the processing unit 2 starts the input/rounding 2:: mode 'in this mode, the data in the flash memory device 3 is stored in the fast mode, in this mode, f(4) case # / reset mode Erase in the middle. In the running, the host 9 pass ^^ flash memory card reader The face bus 13 or the card reader 12 and the input data flash memory card 10 of the access processing unit 2 send the write and read two "face circuit 5 to the electric memory controller (not shown) to one Or;: sequentially use the flash 3 read or write operation. One embodiment of the present invention: flash: memory device security protection, when it detects the access to the device from the last authorized access When the booking time of the auditor is consumed, the location=memory setting starts to run the data reset mode. The early optional automatic power supply 7 is set on the card body and is connected to other units for supplying power. 兀2 and The optional function key setting 8 on the card body 1 is disposed on the card body, and is operable to start the processing unit 2 to operate in the processing unit 2, in the data recovery mode or the data reset mode. Optional, optional programming mode, = used to provide an input to the processing unit 2, can be entered into the password and flash memory set 3 stored early 7 " 2 than the town-related password information, 12 200915339 verified password In accordance with the relevant password, the authorization operation of the electronic data record card 1 is activated. , ' 可选 可选 optional display unit 6 is set on the card ..., connected to the processing unit processing unit 2 control, for aunt a field.;. Do not exchange data file with the host 9 and Ray early data flash memory card 10 running status. The advantages of the present invention are as follows: • Bit* — The younger one, the electronic shell material flash memory card is small in size, large in capacity, and the data is transmitted in the round. (4) Ten thousand one, because each person's fingerprint Ο 疋 ,, electronic data The flash memory card only allows authorized users to access the data files within it, enhancing security. Other features and advantages of the present invention will be described below. Fig. 2 is a block diagram showing the structure of an electronic memory-free sensor and a user-type memory card 1A in another verification process of the present invention. The L-flash memory card consists of a single 2-input memory controller 21 that is processed by the -input/output interface to reduce the cost of high integration. Input / give φ people two two Α eight α circuit 5 Α including - transceiver module, " face motor group, data buffer, register and interrupt logic. Input/Output Interface Circuit Output > 5Α, Combine an internal bus so that the input/=1= components can communicate with the flash memory controller (4) ==. The flash memory controller 21 includes - a micro-processing code logic flash δ hex memory controller logic, a correction error, ^) logic. An embodiment of the present invention, such as a good power supply (PG), ^ write Γρ, γ for status display, ratio

device. Shutter Flash memory activity, etc., and other I/O determinations (four) material! I21 combines one or more flash memories 13 200915339 Device 3. In this embodiment φ, the soil secrets • «Α者一工一机9Α "" includes a function key setting unit or two. The flash memory card is connected through the interface bus '$ ° ? 早 早 Α 2 Α. The function key setting unit 8 is used to set an optional operation mode of the electronic bedding flash memory card 1 : a programmable mode, a data recovery mode, or a data reset mode. The function key setting unit 8 is also operable to provide a turnkey password to the host computer. The processing unit Μ D compares the input password with the related password information stored in the flash memory device 3, and activates the authorization operation of the flash memory card 当 when the verification of the round-up password and the related password information is consistent. In this embodiment, the host 9A includes a display unit 6 (four) flash memory card 10A running through the interface bus or read; and the device is connected to the early το 2A. The display unit is a schematic block diagram of the internal structure of the processing unit 2A from the operating state 0 for display and the host from = data file exchange and electronic data flash memory card, electronic data ::::: card 10A Including - for the processing of single ... for =, body card; 0A: power regulator 22, the power can be flashed according to the electronic data. Power requirements for the relevant units of the cassette A

In the voltage-stabilized capacitor (in the figure, the dry-thunder voltage is included with the sentence η η), the flash memory card i〇A. A reset circuit 23 for providing a reset signal to the processing unit 2A is turned on, and after being powered on, the reset signal is sent to all the units. When the internal voltage is stable, the reset number stops transmitting, and the resistor and capacitor (not shown) are used for proper reset timing adjustment. Electronic Data Flash Memory 14 200915339 The card l〇A also contains – the PLL in the quartz crystal vibration recovery unit 2A provides the fundamental frequency. + not shown, for resetting the circuit 23 according to an embodiment of the present invention, and the power conditioner: the input/output interface circuit 5A, the element 2, the high integration is greatly reduced, and the partial integration is processed. Single cause this. Room and space, complexity and system size and cost are mobile devices such as 〇

The key factor in memory card. The current technical electronic data flash flash material is divided into the ICF poem (four) technology and interface lightning, installed, such as input and output | analog analog and digital hybrid circuits, MCP package. The tongue is integrated into the dad with the processing unit. The reset circuit and the power supply adjustment can be used in the MCP package with the processing unit. The special circuit of the Kunhe signal integrated circuit technology ^^ ^ analog circuit and data. integrated. Therefore, the two integrations can be incorporated into the same mold of the processing unit 2A including the input/output y path 5A, the flash memory controller 2 reset circuit, and the power supply unit 22. In another embodiment of the present invention, the processing unit 2A, the input wheel output circuit 5A, the power conditioner 22 and the reset circuit 23 pass through. Technology or mixed-signal integrated circuit technology is integrated or partially integrated. The advantages of flash memory technology have created a large number of flash memory devices that accommodate different months of cost and capacity. For example, an mbc flash memory device or a multi-level cell (Multi_Level Cel BLC) flash memory device has the same shape factor as an SBC flash memory device or a single-level cell (SLC) flash memory device. However, the capacity is further 15 200915339. Generally speaking, the flash memory unit of the SLC form is more reliable and has a higher data transmission rate, and the flash memory unit of the MLC form has lower reliability and lower reliability. Data transfer rate, but cheaper. The memory unit of the SLc type may include a small block SLC (SSLC) and a large block SLC (LargeBl〇ckSLC, LSLC). Similarly, the memory unit in the form of MLC may include a cell block MLC (a MLC, SMLC) and a large block (MVLC).

C

Flash memory with SMLC is typically arranged as 5i2+i6 bytes per page, while flash memory with LMLC is arranged for 2〇48+64 bits per page' where +16 bytes and + The 64-bit tuple is page backup (4) (4) The area ' 'page is the difference between the page size for data access (data readout) and data writing (data writing), and the large block data is written (data is written) Data can be written in a small block (data writing) four times faster. MLC 记 罝 罝 : : 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓 仓The data 1 transmission rate is much faster than the MLC memory unit. Around NAND flash memory phase = property rights issue, AND or Super_AND flash memory can be created 5 large 'size (2k bytes) flash memory smaller page size (5U bytes) flash memory The body has better writing performance and the rapid development of the body, making the equipment 掖° 槪 也 also... To support such a wide variety of flash suffix types, I access them. U-hidden controllers need to be able to detect or due to the above-mentioned potential lack of flexibility. In fact, the only point and cost of the original 'find flash memory method is to access each different fast 16 200915339 flash memory Body type. Therefore, it is very important that the Boss *. prisoner handles a processing unit with a smart algorithm to detect and access different types of fast 夬 夬 s 己 己 。. Mu-p/, the flashback S-memory device contains an ID code to verify its flash memory type, the system of the system, and the characteristics of the flash memory such as page size, block structure size, Rong Jin Stee Leigong signed W and so on. According to the current embodiment of the present invention, the processing unit of the flash memory card is executed when the system power is turned on.

C Ο 1 has a hidden check operation to determine whether the flash memory controller supports one or more flash memory devices of the electronic flash memory card. 4A |^| D I have j ', a corresponding flash memory detection algorithm of the present invention first 'processing single S is re-determined (block 4 (8), then _ reading to verify the flash 呤 grid rule j.. ^ K hidden The body type (block 420). The read ID is used to compare with the flash memory type table in the ^^ memory controller.

I does not support the flash memory type (block 435), the fast memory controller will not; w J ύ l:S . , <K flash memory, incompatibility will be displayed through a control state output port LED - I * ,, in the controller circuit or firmware days ► vibration, this disjoint secret + It can also be returned to the Card host via a card interface agreement, so the + κ 士 撒 some action. Reward and execute a cry...$ Flash memory type, flash memory control Clear /, ^ to the corresponding flash memory type access mode (block 45 〇). ', 'Flash memory controller starts to access flash memory (block's private flash memory card is a flash memory system using flash memory to store data, ^ ... system, system. 4Β中*, Electronic Data Flash Memory Card 10Α Contains Side: Tian Si _ Unit 2 Α, Flash Memory 3 a, Random Access 17 200915339 Ο Ο Memory Area (RAM) 24 and with Startup Code (BC ) One operating system, (〇S) read-only memory (R0M) 25. Once the power is turned on, the processing unit 2A takes out the boot code in rOM25 and executes it, thereby initializing the components of the system and loading the 〇s code in ROM25. Go to ram24. Once 〇s is loaded into RAM2", it will gain control of the system. 〇s contains drivers for basic tasks such as controlling and allocating memory, prioritizing and processing instructions, and controlling input output. (10) Of course, the code also includes the flash. The hidden data and the variable data of the flash memory. Because the data stored in the ROM is permanent, the flash memory card is supported in the conventional type of electronic data. Investing in production The software in r 〇Μ is recorded, so it cannot support the type of flash memory on the market later. In this case, the flash memory controller that supports the new flash memory type is often developed. Responsible and time consuming. Again with respect to FIG. 4B, in accordance with another embodiment of the present invention, the electronic data flash memory card 1GA includes a flash code detection algorithm code that is separated into a static area % and a dynamic area 27. The static area 26 handles the current flash memory type, and the dynamic area 27 is used to disable the special flash memory in the static area (4) electronic data flash memory card: type control control processing. That is, when electronic data Flash memory = flash memory type when manufacturing, flash memory detection: the algorithm code identifies the flash memory ID after power-on, and uses the static area 26 to perform reading or nesting into the old Flash memory; on the contrary, it uses a new type of flash memory device (such as 3A, Figure 4 / power supply startup process & flash memory detection) The algorithm identifies 18 200915339 flash memory (1) and performs read and write to the new flash memory device 3A using the dynamic region 27. In this configuration, the static region 26 of the flash memory detection algorithm code is stored in R〇M25, but the dynamic area 27 of the flash memory detection algorithm code is stored in at least one of the flash memory devices 3A of the electronic material flash card 10A. By storing the dynamic area 27 and the data (not shown) In at least one of the flash memory sub-devices 3A, the size of the gROM 25 can be reduced, and the new flash memory can also be supported without replacement. That is, when a new flash memory is manufactured for some starting points When the body (ie, the static area is not supported), simply store the appropriate algorithm/algorithm 8 dynasty dynamic area in one or more flash memory devices without resetting the entire R〇M. Since the preset access and dynamic area reading have been incorporated into the execution of the flash memory detection algorithm code, the type of the dynamic area can be modified without affecting the operation of the flash memory detection algorithm code. . As a result, the overall manufacturing cost is reduced and unneeded development is reduced. The data stored in the flash memory device is to be accessed and verified, and it is an important parameter of this. . According to the fourth additional aspect of the implementation, in addition to using some existing methods, a two-channel parallel method and interlaced access (four) memory can be performed in the electronic data flash memory card to accelerate performance. The type uses a single-channel (8-bit) data bus to quickly record the flash memory card, as shown in Figure 5A. Through the two-way read Ge, the second row 'more data bits can be read from the flash memory or written to the body, gentleman, 1 $ memory, so the access speed is improved 19 200915339 High. For example, a two-channel bus (16-bit) can flash flash speed = double, four-channel (32-bit) can increase flash memory access, quadruple, and so on. Electronic data flash with dual channel data bandwidth 2: The body card can be realized by a 16-bit wide flash memory as shown in Figure 3, through the same single control of two 8-bit wide flash (Figure 5C ), or through two separate 8-bit flash memory bodies (Figure 5D). Oh. already

The electronic data flash memory card 1B as shown in Fig. 5D includes a separate controller and a wheel output connection corresponding to the flash memory 3B 1 and 3B2. The A' is used to alternate programming to increase speed and reduce power consumption. 】Flash memory in programming mode (write), data is transferred from the register page to the flash memory unit of the flash memory array, which is compared to other modules (eg 4 flash memory cells, Writing memory to the register page of an external device requires more power to be consumed. According to the current invention, the alternate programming of the flash memory devices 3B1 and 3B2 includes "alternate writing", wherein the flash memory controller 2 1B causes a flash memory device (such as the flash memory device 3B1) to Program (write) data from its page register into its flash memory array; at the same time another flash memory device (such as flash memory device 3B2) is limited to non-programming operations only (eg from The controller 21B receives the data into the page register, and when the flash memory device 3B i is performing a write operation, the memory device 3B2 does not eat *1 for writing operation. This avoids the simultaneous operation of the flash memory in the programming mode. Accessing each of the flash memory devices 3B1 and 3B2 increases the access speed and throughput of the flash memory to match the host interface standard 20 200915339 speed. In addition to the bare access speed, the alternate access method also avoids the t-force consumption due to simultaneous write operations to multiple flash memories. The various novelty described above may be performed by the same or separately while maintaining its substance and scope. For example, in accordance with still another embodiment of the present invention, FIG. 6 shows an electronic data flash memory card 10C (or electronic data storage, I quality, or integrated circuit card). Electronic data flash memory card (7) C j through an interface bus or card reader (that is, connection communication) to adapt Ο 主机 :: host 9A' which contains card body lc, one containing the description described in the foregoing embodiment The flash memory controller 21C, the input/output circuit ^ and the processing unit 2c of the one or more memory devices 3C, the flash memory card (10) may be the function subsystem of the above electronic data flash memory card i〇A It can also be used as a functional subsystem for other applications. The flash memory controller 21C stores the data rights in the flash memory device through the command memory device 3C it generates. The above processing unit 2C is connected to the flash memory device, and the flash memory controller 21C controls the flash memory device 3C by one or more of the above methods. In a real control test, the flash memory device 21C performs a flash memory type algorithm to determine whether the static area of the flash memory controller logic stored in * 支援 supports the body = The device 3C' reads the dynamic area of the flash memory controller logic that is stored in the flash memory m if the type is new. On the other hand, the input/output interface circuit 5C is activated to pass the second! 9A establishes USB bulk transfer (b〇t) communication. Main 2...Responsive device USB interface circuit (later becomes (10) device) 21 200915339 There are four communication data flows between Y斲, block and synchronization 〇 传输 transmission is The data flow in the control pipeline from the host to the USB device, which is responsible for configuring and controlling the USB device information; interrupt transmission is a small amount of data, non-cyclical 'guaranteed response period' is usually the device initiates communication to notify the host USB device needs Service; large movements through the USB interface circuit in the block transfer wheel have no time to authenticate the response; synchronous transfer provides periodic, continuous communication for the host and USB devices. USB interface circuits are usually Supports two data transfer protocols: Control/Block/Interrupt (CBI) protocol and Block Transfer Protocol (BOT). The Otani Memory CBI Transport Specification is approved for use with full-speed floppy drives instead of high-speed capable devices, or other A device that exceeds the floppy disk drive (according to the USB protocol and an embodiment of the present invention: the USB device and the host transmit high-speed data only using a block transfer protocol (BOT). The BOT is more efficient and faster than the CBI protocol because of the transfer command, The data and status are echoed to the block end point and the preset control end point. In the foregoing embodiment, the processing unit 2 (: is optional in the programming mode, processing the single S 2C causes the input and output interface circuit % to receive the data from the host 9A' and The host 9A issues a write command to the fast memory controller μ to store the data to the flash memory device 3c; the data recovery=below: the processing unit 2C is stored by the host from the flash memory controller. Read the command to receive the data in the flash memory device 3C and store the data file in the flash memory device 3C, and output the interface circuit 5C Input to the main mode 2 data (4) will be erased from the flash memory device %. The advantages of the smart processing unit 2C corresponding to the present invention include: 22 200915339 (1) Provider integration, fully reducing the overall space occupation At the same time, the complexity and manufacturing cost are reduced; (2) using a smart algorithm to detect and access different types of flash memory, broadening the source and supply of flash memory; (3) soft programming part and The flash memory data is put together to reduce the cost of the controller;

(4) The use of more advanced flash memory control logic can improve the throughput of flash memory access. According to another embodiment of the present invention, a system and method are provided in an electronic data flash memory card to control flash memory. The system and method used by the flash memory controller includes a processor for receiving at least one request from the host system, a query containing L (LUTs), and an entity usage table (Ρυτ) @ index. The index converts the logical block 4 addresses (LSAs) used by the host into the physical block addresses of the flash memory. The stomach t includes (4) memory configuration information. The processor optionally utilizes the index to ensure that the flash memory can be used for programming, reprogramming, and reading, and the area flash flash 3 memory controller also includes a renewable first in first out (deletion), which can be f The blocks make them available for reprogramming. The recycling details include copy and erase operations, which are executed in the background so see the host :: see. Correspondingly, the flash memory management and the flash memory controller body:: Hui replaces the host, and the result, the host system does not need flash memory. 掊 ☆ ☆ 酉 酉 交互 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 This greatly increases the speed of reading or nesting flash memory based on the USB or ASIC architecture. 23 200915339 The following definitions of the proper nouns appearing in the present invention define β block _ basic storage erase units, each block containing a certain number of magnetic regions 'e.g. 16, 16, 32, 64, and the like. If any of the sectors encounter a write error, the entire block will be defined as a bad block, and all valid sectors of the block will be relocated to the other blocks. Magnetic area: The subunit of the block. Each zone typically has two zones, a data zone and a spare zone. 〇 Old Magnetic Area: The magnetic area that has been programmed to be written and the data is then updated. After the S data is updated, the old data is retained in the old magnetic area, and the new data is written into the new magnetic area which immediately becomes the effective magnetic area. Invalid block: A block with an old magnetic area. Valid magnetic area: _ a magnetic area programmed to be written to the data, and the data is not expired, for example, the current data. Average Known Algorithm. A method for evenly distributing the number of erases of blocks in flash memory to extend the life of the flash memory. The number of wipes of the 0 block in the flash memory is limited. For example, the typical erase maximum number of NAND flash memories is one million. The spare block. The flash memory is reserved for the memory block, and the spare block allows the flash memory system to be used by the bad block. Attack: It is the material magnetic field used by the line as (4) to take indicators to improve the performance of the memory. In small-capacity memory operation, usually two

The combination of the data areas, the guard B, also the minimum value of the size unit. The cluster size of a typical small block of memory (for example, 512 bits per parent b) is a byte, and the larger block has a hidden body (for example, 2112 bytes per magnetic area). 24 200915339 has a family size of 4K bytes. FAT · A file allocation table with link address indicators. The cluster is the smallest unit of ρ Α τ, for example, FAT16 is a cluster address of 16 bits. Directories and subdirectories: File metrics defined by the operating system. Master Boot Record (MBR): — A storage root metric and a fixed location for the relevant boot slot that can be started. This fixed position may be the last magnetic region of the first block, and may be the last magnetic region of the second block if the first block is broken.包 Package · A variable length format for the USB Basic Processing Unit. The general processing in a typical uSB specification consists of three types of packages: a token package, a data package, and a signal exchange/handshake package. The token package has the form of input, output, and configuration; a packet size is variable 'eg 64-bit tuple in USB 1.1, 512-bit in USB 2. ACK and handshake ACK and handshake The NAK form tells the host that the processing is complete. Screen: When USB communication is not busy, block processing using a high finite level of 会 is used. Block processing can also wait for the next page when USB communication is busy. Terminal points: Three terminal points include control, block input, and block round-out. The control end point is used for the initial enumeration of the system, and the block input end point is used for the host system read channel 'block output end point for the host system write channel.

Command Block Encapsulation (CBW): - A packet contains command status and related information, such as data transfer length (5丨2 bytes such as from 8-11 bytes), a CBW usually starts at a packet boundary and Transfer a short packet with a precision of 31 bytes. 'All CBW transmissions should be sorted first by LSB (〇 ) )) excellent 25 200915339. Command State Encapsulation (csw): csw is the beginning of the scope of the package.

Reduce Block Command (RBC) SCSI Protocol: A 1-byte command descriptor. Figure 7 is a block diagram of an electronic data storage card (flash memory system) (10) incorporating the corresponding flash memory controller ιι〇 and flash memory device 112 of the present invention. The host system 52 provides read and write processing resources, and the erase operation is controlled by flash memory!! 110 implementation. The flash memory controller ιι is connected to the host system 52 via the host system interface 116. Host system 52 can be a PC or other type of computer system. The operating system of the host system 52 may be windows, MACOS, but is not limited to these operating systems. In this detailed embodiment, the flash memory system 1 is compliant with the "large capacity" and the host interface 116 is a 亀 connection. The deletion specification can be 1.1, 2·ο or above. The flash memory controller u〇 and flash memory U2 can be either bus-bar powered or self-powered, or used as a mass storage device. The advantages of being a mass storage device are low power consumption, portability, and much larger capacity than traditional floppy disks. The flash memory controller Π0 contains a device transceiver 12〇 that converts the analog signal into a digital stream and provides a phase loop lock (PPL) circuit to generate an accurate clock for the internal data latch. For the USB20, the ppL function is accurate and useful because it operates at 4 Hz. The flash memory controller 110 also includes a serial interface engine 122^, which can provide serial and parallel data conversion, packet decoding/generation, back=multiple code (CRC) generation/checking, non-return to zero ( NRZI) Codec and bit stuffing of the root USB standard. Endpoints 124 and 125 receive type information (e.g., mass storage device class), flash memory configuration information, and preset control information from host system 26 200915339 system 52; endpoint 126 receives read processing information from host system 52. The endpoint 128 receives write processing information from the host system 52. The block transfer (B〇T) unit 13A includes a transfer length register 132 and a logic block address register 134 to receive a command block package (CBW). An aspect of the invention, assigning from a physical block address to a logical block address

The entire process is performed by the flash memory controller 110, thus allowing the host system 52 to connect to the flash memory controller 11 without requiring a real physical location (configuration) of the data stored in the flash memory device 112. 〇 (such as performing read, write, and erase operations). That is, the flash memory controller uses all of the verification logic and data stored in the electronic data flash memory card (ie, not received from the host system, first 5) to identify the bad in the flash memory body 112. The block, the shirt ^ is assigned to the physical address of the good block in the logical block address 200, the ghost address, the unavailable block is recovered and the average loss algorithm is performed. Each command in the command is independent of the host system], because the operation is enhanced. The electronic data of the management of the invention and the application for another case is flashed... One of the memory control photos is disclosed in "No ^ μ, (4) Card with Flash Memory Bad Block". η (ie, check logic) 'here - and provide the magnetic field FIFO 140 to provide a town when the host 5 memory is at 112; ^ to flash flash w 15〇w FIFG non-empty towel break (four) 142 processor 150 interrupt processing (4) Chinese 27 200915339 The program responds to the host system 52 to determine that data is to be written to the flash memory Π2. At the same time, the processor 15 executes a write process. The write query table (LUT) 170, the read lookup table (LUT) 172, and an entity use table (PUT) 180 provide an index showing the construction of the flash memory 112. The flash memory controller uses the above verification logic to control the read and write lookup tables 170 and 172 and PUT 180. The read and write lookup tables 17A and 172 each facilitate read and write processing between the host system 52 and the flash memory i12, and the read and write tables 170 and 172 convert the host-provided logical block addresses (lBAs) to fast. Physical block addresses (PBAs) of flash memory 112. Ρυτι8〇 仃 The physical magnetic area is compared and provides a programmed magnetic area bitmap, such as the magnetic area that has been written into the data. The flash memory interface controller 186 with flash memory U2 executes commands from the processor 150, and the flash memory interface controller 186 receives logic from the read and write lookup tables 170 and 172 read and write request services. Entity block address. Ο ... FIFO Recycler 19 〇 Recover all blocks with expired magnetic zones, so that we can be programmed, for example to write new data. The reclamation operation is performed independently immediately after the write processing, and thus does not affect the write processing of the flash memory controller 110. In the best dedicated integrated circuit, the read and write lookup tables 17A and 172, the use table m, and the FIFO reclaimer all use non-volatile 2 access memory (RAM), such as synchronous random access. Memory (sram). The flash memory 112 can be implemented as one or more devices, and each can have one or more flash memory arrays. 28 200915339 For a 128M byte flash + 3 memory with 128K byte/block structure, it has a block, and the higher the density of the flash memory, the more blocks it has. Therefore, As the density of the flash memory increases, the RAM size of the write lookup tables (LUTs) 170, 172, and 180 can be expanded. For optimal ASIC implementation, the controller can consider defining a block group, such as a block. For a group, the read and write write lookup table (LUT) 17〇, 172 and 18〇 are designed as a group instead of the entire flash memory, which will make the RAM size fixed and the flash memory block The number is increasing in large numbers, so the ASIC die size can be controlled in an economical size. When the read/write action is changed from the address range of the current group to the address range of another group, the controller will load the target. The group's table is written to the lookup table (LUT). This loader takes some time but saves RAM. The controller balances performance and die size. Figure 8 shows in more detail a block diagram of the write query table ι7 〇, the read lookup table 172, the entity usage table 180, and the FIFO recycler 19 of Figure 7 of the present invention. The write lookup table 170 provides a flash memory index that translates the logical sector address of the host system into the physical block address in the flash memory in a write process. The write lookup table 170 contains the physical block addresses 3〇2a 3〇2b 3〇2c and 302d. To simplify the legend, each lookup table shows only four logical sector addresses. Each of the logical sector addresses 302a~3〇2d contains an optional block offset bit (bits 5 through 0). Each of the logical sector addresses 3〇2a to 302d in the block offset bit corresponding block is associated with the physical block addresses 304a to 304d. Correspondingly, each logical sector address a~d points to a 29 200915339 associated physical block address a~d. , .e ^ In this special case, the physical block address is 32 bits long. The magnetic zone region 306 contains the circumscribed magnetic regions in the ^. - A substring of bits shows an address. In the η solid special write process, the write query table 170 records only the logical block address. For example, if a subsequent write process requires two or more consecutive blocks, the write log table 17G records the starting logical block address. The buckle Φ table 172 provides a flash memory index in the read processing and converts to a physical block bit of the flash memory. § Bay lookup table 172 contains logical block addresses 302'a, 302, b, 302, c and ΓΗ. The read lookup table 172 and the write lookup table have the same area. After the parent write operation is completed, the read lookup table 172 is updated to reflect the changes to the write lookup table to distinguish the read and write lookup tables 17() and 172. Once the read lookup table LUT is updated, it can be used as an index for the read (four). - The entity uses the table PUT 180 to complete the physical volume comparison and provides a bitmap of the previously programmed magnetic regions (i.e., the magnetic regions have been written to the data). Regardless of when the write operation occurs, the entity uses the table ρυτΐ8〇 to record the usage information to display: the programmed magnetic area. This helps the processor write operation of the flash memory controller to determine which sectors can be programmed and reprogrammed based on PUT 180. The first in first out recycler 190 recovers the invalid blocks and performs the recycling process after each write operation succeeds. Whenever encountering a block with an old magnetic zone as a block, the physical address information is placed in FIF〇19〇 as an invalid block & After completing the valid bit copy relocation operation, the FIFO Recycler 19〇 Provides invalid block erase operation address information. The FIFO Recycler 19 uses a write indicator 192 as an invalid block to update the FIFO address, and reads indicators 30 200915339 and 196 as two read address related indicators. Read indicator II i96 is used to retrieve the read parameters in the background, and read indicator 194 as the parameter successfully completed by erasing the valid block. Reading indicator one 194 will never exceed reading indicator two 196, and reading 194 and 196 will not exceed the pointer 192. According to aspects of the current embodiment, the copy reset (the disc is still left with the available partitions) and the erase and recycle operations are done in the background, that is, independent of the write processing result, and does not affect the write processing.

Figure 9 is a block diagram showing a more detailed block diagram of Figure 7 of the present invention. The data structure of each physical block address of the flash memory 1U includes a data area 4〇2 and a spare area 404. Each zone maintains a certain number of bytes depending on the application. For example, the data area may have 512 bytes, 2112 bytes, or more bits 1 and the ambiguous area may have 1 664 or more bytes. The data area 402 stores the original data, and the spare area 4〇4 stores the memory management related information. The spare area Yang includes a bad block indication area, an error correction code (ECC) area 4〇8, an erase counter area 410, and a logical block address area 412. Because Zhao uses Table one... ,One. Storage: Easy = Invisible 'There' does not save valid volume information. The logical block address area M2 is used to reconstruct the read and write lookup table, I" and the entity usage table PUT180 during initialization after power down. The bad block indication area 406 indicates a bad block. When attempting to write or erase a special magnetic When the zone fails, a bad block is generated, and the bad block indicator area is positioned at the last block, which is convenient for fine reading, especially when each magnetic zone has one bit. In this particular embodiment In the middle, the physical block makes 31 200915339 bits to 5 recorded magnetic area write failure (64 bit block, group = 16 magnetic area = quarter - any ^ in the block means that the special rabbit is bad. In order to maintain Reliability, the last four blocks of the bad block that exist in the flash memory can also use less or ^ copy. In the current invention, almost no markup is required. The valid magnetic area mark in the lookup table

€ S has used the only mark to help the body make judgments. This also reduces the complexity of read and write processing. Figure 丨〇 is a high-order flow of the flash memory management method of the present invention. The first 'flash memory controller processor acquires at least one request from the host system (step lapse), which may be a write or read request. Thus, the magnetic regions of the flash memory that can be used for programming, reprogramming, or reading are determined by the index table and processor internal to the flash memory controller (step 504). The host system can act on the flash memory without flash memory configuration information. ...in the embodiment, the flash memory controller receives a request from the host system for a compatible USB large-capacity printer M|eight Valley summer memory, and the following legend describes the particular implementation. Fig. 11 is a flow chart showing the method of the USB large-capacity storage device type service request box of the present invention. f goes, strain m, ® n 圯 圯 控制器 控制器 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收 接收. The command can be written 颂δ月未. If the write request W element is a write process, as in step 60, U4, the step is the step 3 〇 4 for the capital 3 round; if it is a read request, the member J π becomes a read process, such as . 10 200915339 At step 606, the step is the data entry step 606. Once a write or read process is completed, the flash memory controller sends an acknowledgment packet to the host system to confirm that the process is complete. In step 608, the step is the state transfer step 608. Since the packet is sent from the host system, command pass step 602 and data output step 604 are typically block output transfers. Since the packet is sent to the host system, the data entry step 606 state transfer step 608 is typically a block incoming transfer. 12A-C show block diagrams of a Command Block Encapsulation (CBW) 702, a Reduced Block Command Read Format (RBC) 704, and a Command State Encapsulation (CSW) 706 of the present invention. Each request in the USB standard includes three types of packets: CBW702, RBC704, and CSW706. CBW 702, RBC 704, and CSW 706 are also commonly referred to as tokens, data, and acknowledgment handshake/shake packets, respectively, and are used for command transmission, data registration output, and status transmission, respectively, as shown in steps 602-608 of FIG. Still referring to Figures 12A-C, CBW 702 contains information to be followed by the host system data, CBW 702 is 31 bits long and contains command decode and range and a unique logical block address. The logic block in the CBW702 ‘address contains the file allocation table (FAT) and directory metrics. CB W702 also contains a 15-bit read/write range as part of the RBC command. The RBC704 contains data information written to the flash memory, which is a small computer system interface streamlined block command read format (SCSI RBC). The length of the data can be defined according to different versions of the USB standard. For example, USB 1.1 is a 64-bit tuple and USB 2.0 is defined as a 512-bit tuple. CSW706 contains 33 200915339 4 recognition process and processing end information, status bit m uses (four) tuple. Figure 13 is a flow chart of a method of reading, writing or erasing the present invention. Referring to FIG. 12A_C and FIG. 8, the request from the host system is first received (step 802). To comply with the USB standard, the request includes cb (4) 2, (4) ticks and CSW 706, and then the read or write request command is detected (step outline) Then (10) and the registers of the CSW are initialized (step 806). If the request is a write-requested write request, the flash memory controller 〇 magnetic zone FIFO is filled. When the 512-bit tuple is ready, the write indicator for the magnetic zone is incremented and an interrupt is sent to the flash memory control = (step 810). Then, the write process is performed (step 812). By the end, an acknowledgment packet is sent ί丨丨:t ΜA 4 is (step 814).丨 The host system confirms that the write process is successful. After successfully completing the write process, flash (4) (4) ^ the reward status (step (4)). If the loop is not empty, the loopback will reclaim the old volume (step 822). The read request is read by a read, and the logical block address in the CBW is used to compare with all the entries of the FIFO disk 5· and the magnetic region (step 828). If the matching data is written back to the host system ( Step 830). After a narrow, one machine system confirms that the 4 read processing has been successfully completed (step, mismatch, the requested data is read from the flash memory (step 834). The most line, T read out confirms that the read processing has been Success;: is sent to the host system, and succeeds (step 836). Figure 14 is a flowchart showing one-stage write processing, a second-stage write processing, - Read the package contains 34 200915339 - Recycling operation. First, the CBW is received (in step 902), and then it is judged whether it is a write request (step 9〇4). Then if the request is a write request, the FIF is checked. (Step 906), if the FIFO magnetic area is not empty, a write request is initiated. ^ In order to maintain the continuity of the block address and improve the write efficiency, the write process has two stages. In the first stage, the data is written to a person. A special number of magnetic regions and a confirmation packet is sent to the processor and host system of the flash memory controller to notify that the write process has been completed (step 910). If there are no subsequent unprocessed read requests, the second stage of the write process is Execution ^ Accordingly, the valid magnetic region is copied from the invalid block to the new address of another block (step 920). In order to maintain data consistency, step 92 is executed in the background. If it is judged to be read, please write and write At the end of the first phase (i), there is a read request, and the flash memory uses the real block address of the read lookup table # to retrieve the requested data (step 930). After the read request is executed, if There is a second unprocessed phase of the write request, this second-order name is executed (step 920). Step 940 +, when there is no request to process, loop f (four) back to 2 old magnetic regions. In a particular implementation When the loop is completed, the flash memory controller (4) can return to other requests from the host system. Figure 15A_D shows the typical write-process of the present invention in the first and second stages. A block diagram of the results. M Ma progresses to clarify the above characteristics of the present invention. The following example is provided. Figure DA-D shows a write request containing four 35 200915339 different string data, and Figure 15D shows a After the data is updated Write processing. For convenience of explanation, each block only displays 4 magnetic regions. Each block of the flash memory 112 two blocks (PBA 0 and Pba 1) has four magnetic regions. In the first write process The write query table 17 is written to the first 6 physical magnetic regions of the first physical block (pb A0 ) in the flash memory 112. In this example, 'assumed that the flash memory 112 is initially empty. For the purpose of the example, the label A0-A5 is again written in the first write process. The corresponding entity in the flash memory 112 uses the bit in the table pUT180 to display 1 to indicate which areas have been It is programmed to be occupied. The moving body of the flash memory controller uses PUT 1 80 to judge the available magnetic area. Corresponding locations can be read after the magnetic regions that have data that cannot be written before erasing. The write lookup table 170 writes the valid sectors of all 1 and the information of the read lookup table 172 is copied from the write lookup table 17 to reflect the most recent changes. Despite this, once the write phase is completed, the final synchronization of the table 17 is completed and the previous write lookup table 17 is copied to the read lookup table 172. The write lookup table 17 对应 corresponding to the blank area with all 0s will display the pre-update information until the read lookup table 172 is updated. For Figure 15B, the write lookup table 17 writes the new data B to the next available magnetic region in pBA1. This is the second deal. The write query table 17〇, the entity usage table PUT 1 80 and the flash memory block reflect this update. The read query table 172 has updated the last change, but has not been updated to reflect the current change. Regarding Fig. 15C, the write query table ι7〇 is written to the new data c〇 and C1 to 36 200915339 the next available magnetic area, __ _ 疋 the second write process. Note that the data <: 〇 and C1 and the data AO A5 - the sample is in the block range. The write query 〇 7〇 and the entity use table just and flash memory blocks to reflect this update again. Read 172 was updated to the last change but has not been updated to reflect the current change.

Regarding Fig. 15D, the write lookup table 17 〇 has been written to update the existing data A0-A4 to "This is the fourth process. In the first step t of the write process, since the blocks PBA0 and pBA1 need to be erased first. After being reprogrammed, the update data phase is written to the next available block of the same number of sectors, PBA3_4. Once the first write phase is completed, the acknowledgement packet is sent to the flash memory controller for processing. To confirm the completion of the first stage of the write process. Write the query 纟17〇, the entity uses the bribe and the 夬 5 己 己 己 己 己 己 反映 反映 反映 反映 反映 反映 反映 反映 己 己 己 己 己 己 己 己 己 己 己 己 己 己 己Not updated to reflect current changes. Blocks ΡΒΑ0 and PBA1 become invalid because some of their magnetic regions have expired. Accordingly, those blocks can be reclaimed by loop FIF019〇. Loop FO190 changes the corresponding bit to 显示 to display this Recycling. The write index 192 of the loop ριρ〇ΐ9〇 is incremented and points to the next available location stored in the next invalid block address. In the second phase of the write process, data A5, B, and C0 are copied to the new block write. Query table 170 In the continuous PBA 3-4, the write lookup table 170, the entity usage table PUT 180 and the flash memory block will reflect this update. The read lookup table 172 will be updated and reflect the current change. Both stages of the write operation are Upon completion, the 'write and read lookup tables 丨7〇 and 丨72 will have the same content. 37 200915339 Figure 16 shows a flow chart of the first stage of the process of performing physical block address and sector counter update in Figure 14 of the present invention, The main thing is to do an index comparison between a logical block address and a physical block address so that the read and write addresses can be kept tracked. Table 1 (described below) is a lookup table entry and FIF 〇 assumed in flash memory. A simplified example of a block of 8 magnetic regions means that the entry of β 1 means that the magnetic zone data is valid, and 0 means that the magnetic zone is available. Please note that the lookup table (reference table) uses LBAX as an indicator, but the FIFO is done using Wr_ptr and Rd_ptrs. Table 1 PBA W/O Magnetic magnetic magnetic magnetic magnetic magnetic field offset 13⁄4 Area 13⁄4 Area Area Area IS Area Area Domain Area Domain Area 0 1 2 3 4 5 6 7 ΡΒΑχ 1 0 0 1 1 0 0 0 Ο最初 Initially, the logical block address and the magnetic zone count from the host are estimated, as shown in step 1102. The logical block address offset bit is then encoded into a magnetic zone counter, as in step 1104 » Logical Block Pointing A physical block address of the flash memory. If the logical block address is 0010, 0101 and the number of magnetic regions is 16 ', then 〇1〇 is the initial [ΒΑχ block address of the two query table entry indicators. If the entity uses the table The magnetic zone area is 〇 (ie, the magnetic zone is available), then the magnetic zone counter register is equal to the CBW magnetic zone count, and the physical block address of the write lookup table will be loaded, as shown in step 11〇6. If the area of the magnetic area of the write table is 1, this means that the flash memory 38 200915339 is used by the programming, and the block pointed by the write indicator is to be erased, as shown in step 1108. Then, the entry of the loop FlF〇 pointed to by the write indicator is filled with the current file, as shown in step 111. During the reclamation operation, the block pointed to by the write indicator will be erased. Then, the magnetic region used by the entity is set as shown in step m2, where the physical block address shows that the magnetic region is being used. Then the number of magnetic regions increases, as shown in step aw. Next, the number of magnetic regions is compared to the extent of the block, as shown in step 1116. If the number of sectors matches the block range, the write indicator increases, as shown in step 1118. When the boundary of the fast memory block is reached, the logical block address in the write lookup table is incremented, as shown in step 112. The write lookup table for the correct number of locations is then updated, as shown in step 1122. If the number of magnetic regions is not in the range of blocks, step 1118 and η π are avoided, and then the write lookup table of the correct number of magnetic regions is updated, as step 1122 〇〇 + returns to step 1106 if the query table is written The magnetic zone area is 〇, then; the taste of the Shaanxi η 隐 hidden magnetic area has not been used by the previous programming, that is, the writing has not been completed. The magnetic zone count is then compared to the magnetic zone count of the CBW as shown in step 1124. If they are the same, the PBAX of the LBAx^ of the lookup table will be updated in step 1126 and then processed to step 1128. If the magnetic zone count register is not equal to the CBW's magnetic zone meter in step 1124: two lookup tables will be written The magnetic zone* of the data into the flash memory is set to 1. Next, the number of magnetic zones is increased. After successfully writing to the flash memory as shown in step (1) 8, the CBW magnetic zone count is subtracted, such as the step shoulder 39. 200915339 113 0 is shown. Next, the magnetic zone count is checked as shown in step 1132. If • The magnetic zone count is equal to 0, the first phase of the write process is terminated. If the zone count is not equal to 〇, this means that the host sent an incorrect amount of data. Accordingly, the magnetic zone FIF0 is checked to determine if there is more valid information, as shown in step 1134. If not, a timeout sequence is executed to mark, an exception process is terminated, and the FIF 〇 magnetic area will continue to check until enough data is available, as shown in step 1136, if there is more data available in the FIFO area. The number of magnetic regions will be compared to the range of the block, as shown in Figure 1116. Figure 17 is a flow chart showing a method of performing the second stage in the write process of Figure 14 corresponding to the present invention. First, the pointer values of the write and read pointers are compared, as in step 1202. The entry sector area pointed to by the read index of the loop FIFO indicates a valid sector that needs to be copied to the new block address to maintain continuity in the write lookup table. When the copy is complete, the read lookup table is updated (J to distinguish it from the write lookup table, as shown in step 1204. Next, the number of magnetic regions pointed to by the read indicator is checked, as shown in step 12: 6. If the number of magnetic regions is The data in the tile is copied to the new block, as shown in steps 12 and 8. Then, the number of magnetic regions in the lookup table is set to i, as shown in step 121. Next, write the query table magnetic region It is updated as shown in step 1212. Then, the read lookup table magnetic region is updated, as shown in step 1214. Next, the number of magnetic regions is increased. Going back to step 12〇6, if the number of magnetic regions is not 1 then magnetic The number of zones increases as shown in step 1216. As soon as the number of magnetic zones reaches the block range, the magnetic zone copying process is completed. 200915339 The number of magnetic zones is compared with the block range, as in step 12丨8 _ zone number matching block range The reading index is increased, as in the step ^. If the magnetic next 'read & pin and write indicator are compared, as in step (2) step 218, the number of magnetic regions does not match the block range, if the number of zones is checked, as in step 1206 Shown. S private magnetic

Figure 18 is a diagram of a corresponding read processing execution method of Figure 14 of the present invention. First, the CBW is received and recognized as a read request length, and the logical block address and the magnetic zone count of (10) are loaded as in step (10). Next, the logical block address of the write query table is converted to a corresponding physical block address and the number of magnetic regions, as in step 1304. Then, the magnetic zone area bit is checked, as in step 1306_ if the magnetic zone area bit is equal to 〗, the data is read, the magnetic zone counter is reduced, and the number of 4 zones is increased to prepare for the next read process, as in step 1308^ If the extent area bit is not equal to i, for example equal to 〇, the logical block address LB A of the read lookup table is converted to the corresponding physical block address, as shown in step 1309. The data is then read and the magnetic zone counter is reduced by the number of magnetic zones increased, as shown in steps 13-8. Next, an error correction code (ECC) calculation is completed, as in step 1310. The ECC interface is then used to compare with the flash memory spare area readout value' as in step 1312. If these values are the same, the sector counter is checked, as in step 1314. If the values are different, an Ecc correction will be performed 'as in step 1316' and then in step 1314, the sample sector counter will be checked. If the sector counter is close to 0, if equal to 〇, the read process is terminated. If the sector counter is not close to the 0' block range, it will be checked, as in step 1317. If the number of sectors does not match the range of blocks, the logic 41 200915339 block address in the read lookup table is incremented, as in step ( 32 (^ then the read lookup table is updated to the correct number of sectors, as shown in step 1318. A read process is performed immediately after the first phase. The read process has a higher priority than the second phase of the write process, which guarantees the best reflection of the flash memory system. The read process is better than the write process. It is much faster and the read processing does not cause bad block conditions (only possible during write processing and erase operations). 3 shell processing and disk cache functions are available whenever the magnetic area fIF〇 is available. The difference is that the disk cache concept can only occur when the logical block address in the read lookup table matches the logical block address of a write lookup table. It is borrowed from the hard disk concept and applied to small. The capacity is flashed and recalled. This feature is usually disabled to save the cache fee. This is the corresponding flowchart of the present invention. First, the loop FIF is checked, as shown in step 14〇2. The FIFO is not empty, the read indicator 2 is checked, as in step 14〇4, the background erase operation will occur under such conditions. Once the erase is successful, the read memory for the other two valid blocks is reprogrammed! These two reads will not exceed the write pointer. However, if two read pointers are executed: the pointer may return to its original starting position. If the read pointer 2: set the 'recycling operation is terminated. If the index 2 is read No more than write metrics: Use the corresponding bit in the table PUT to be emptied (ie 〇)' as shown in step 2 hex shows that the solid block is now available for reprogramming. Then, locate the block to be erased, as in step 14〇 8 * wr m 'read pointer 42 200915339 2 after successful erasure 掸. Write address check operation for the next two people, such as step (4) 〇 圈 FIFO metric comparison can be done by writing and adding - one or more Bits come to 1 "index again intestine entry _FIFC> contains 8 from 〇 to 7 but not 疋 three bits will be used for pointers 'write pointers will increase from υ to 7 and back to 〇. Write metrics. When they Equivalent ": always equal to or greater than the read ^, etc., meaning Circle F (four) is empty. Loop FIF0 Ο Ο balance ^ two the number will affect the line between the copy speed and the erase speed, so too few people σ will make the loop _ more unsatisfactory. Invented flash memory The controller can complete the flash memory device. The data of the 2-bit register of the Beko access and the memory of the memory must be written to the register and then written in the memory unit. Traditional fast The flash memory controller and the internal memory control system control the access period of the flash memory. The traditional flash memory memory - page registration ^ material to the fast m ^ ^ # ° 512 page register is filled Single block: material: eight his access to the flash memory. Therefore, the traditional flash memory controller using the 枓 access method limits the flash memory: according to the present invention 'flash memory controller Use Μ or larger pages to steal. The flash memory controller of the invention can simultaneously send multiple pieces of data to the flash memory Zhao to fill the page register with multiple access control=multiple; ^ greatly improve the performance of the data transfer wheel. Compared with the conventional single-chip data transmission controller which can only transmit one block at a time, the data transmission performance of the flash memory using the flash memory 43 200915339 of the present invention is greatly improved. Some flash δ hex memory chips have a structure of 2K bytes per page, 4K bytes per page or larger, for example, a typical multi-level memory cell (Multi-Level-Cel) The memory has 2 bytes per page and a total of 128 pages per block, which can be limited to writing only once after the block is erased, for example, if a physical block is erased and is in this area If the first page of the block is written, any writing of this page may result in the loss of the material (or the result of uncertainty), which is called N0P = 1 (Number WPr〇gramequalto 〇, in addition, this It also means that if a page is written to the part = the remaining space of the page can no longer be written, this is called Partial Write Pr〇hibited, because the traditional single block data transfer system Flash memory is written in 5 12-bits each time, which means that flash memory pages (2k bytes per page) can be written four times, which is not allowed in many typical flash memory devices. In an embodiment, the 'flash memory controller solves this problem in the following manner. In some embodiments, the flash memory controller utilizes a 2k戋 larger: page register, which means that the 4*512 bytes or more of the host can be buffered in the control. In the program, one-time execution - full page (仏 $ group or larger) is written 'instead of writing the page multiple times. In some embodiments, the flash memory control page is compared) to avoid the pair - large Pages multiple times = definition - 6 7-bit resolution, to flash by strengthening the coffee 17 〇 and 172:: segment 'page state, this 6-bit value (or 128 pages / section The 7-bit body is a logical page (or magnetic region) address (LpA), 44 200915339 In addition, the spare area of each physical page has a record of this 6-bit LPA and as shown in FIG. The LBA, for example, Table 2a is a reinforcement table, the physical magnetic zone 0 is for the logical magnetic zone 1, the physical magnetic zone 1 is for the logical magnetic zone 5, .... the physical magnetic zones 6 and 7 are marked as (binary 6'bllllll) means that the magnetic area is empty. Table 2 a PBA W/0 magnetic magnetic magnetic magnetic magnetic magnetic magnetic region offset location area area area area area area area area domain domain domain area 0 1 2 3 4 5 6 7 PBAx 1 5 63 63 63 63 63 63 Table 2b PBA W/0 Magnetic magnetic magnetic magnetic magnetic magnetic magnetic field offset area area area area 13⁄4 area area 13⁄4 domain domain domain domain domain domain 0 1 2 3 4 5 6 7 PBAx 1 5 8 63 63 63 63 63 45 200915339 Table 2c

PBA W/O magnetic magnetic magnetic magnetic magnetic 1~--- magnetic magnetic field offset 13⁄4 area area area area area area domain domain domain domain 0 1 2 3 4 5 6 7 -—.— PBAx 1 5 8 8 63 63 63 63 -----J here Ο

The example shows how to protect a multi-written magnetic area. Assume that the magnetic area 2 has 2k bytes of data space and is empty. As shown in Figure 20a and Table 2a, the write command is received. The 512-bit tuple of the region address 8 'the controller can find an empty physical magnetic region (such as the magnetic region 2 of this example) for writing, so in fact, the magnetic region 2 is partially written to the lk bit. The tuple data, as shown in Figure 2, is ribbed and the table is not. Then, another command is received to write the remaining space in the logical sector address 8, and the controller does not write the data to the physical magnetic area because this will result in Programming, the controller finds the next empty magnetic region (in this example, the physical magnetic region 3) as the target magnetic region' which reads the data previously written in the physical magnetic region 2 and associates it with The newly received data is merged, and then the entire 2k byte data is written to the magnetic zone 3 (target magnetic zone). The final state is shown in Table 2c and Figure 20c, and Figure 20d shows most of the MLC flash memory. Not supported and the controller should avoid the actions of the solution described here. When the received logical sector number is read from Table 2c, the controller 46 200915339 searches for the logical sector number only from the bottom to the top of Table 2C. The first matching magnetic region is the latest magnetic region, for example The physical magnetic region 3 has a value of 8' and _search 8" in the table 2c, which is the first magnetic region, so the physical magnetic region 3 is the magnetic region that is most updated to the logical magnetic region 8, and the entity The magnetic zone 2 can be regarded as an "obsolete" magnetic zone (i.e., useless readout data). However, in this way, a physical block having an N magnetic zone (page) (e.g., N = 128) may not have N Logical magnetic domain, because a logical magnetic domain occupies two or more physical magnetic regions. When the controller detects that a bottom block (the last) magnetic region of a block is written, for example, The value of the magnetic zone N in the table is not a magnetic zone indicating empty (for example, when N=128 is not equal to 127), the controller can find another empty block and move all the newly updated magnetic zones to the new block. And all "obsolete" magnetic regions are not copied, this program is called "magnetic zone merge'', merged in each magnetic zone Thereafter, each physical magnetic zone in the block is assigned a unique logical magnetic zone. In order to reply the magnetic zone/page control information to the start-up, the fast memory is in the per-magnetic zone/ The alternate position of the page has at least 6 bits, so the flash memory in FIG. 9 can be updated to the flash memory shown in FIG. 21 in which the logical page address 412A (LPA) is defined. The memory controller also provides dual channel processing to improve the performance of the flash memory system. The dual channel provides a second channel, or the known Xiaospeed Highway', to perform flash memory devices and flash memory. Processing between controllers. Traditional flash memory controllers can be connected to one or more flash memory devices using a single = memory bus. However, traditional architectures limit traditional flash memory. Body Control 47 200915339 The performance of the controller. According to the invention, the system uses at least 2 memory busbars to connect 4 dragon machine rows. The memory controller can be... Flash memory device. Flash memory is, two channels Access these separately Flash memory device. The speed at which the junction and processing are performed can be a memory bus. It can also shut down the memory stream (4) times. In addition, the female flash memory controller can also perform alternate operations. Ο Use one with - One or more flash memories 'two:::::::: row: wide so, traditional (four) remember this, value ΛΛ access to a flash memory device. Although the architecture like = limits the traditional flash The performance of the memory controller. The morphological control 'At least one or two sets of additional flash flashing... can be used. This, remember the hidden bus, at least right J J lb far $, ι # ^ The main memory has 2 flash memory devices to write memory bus. When a single-busy read or flash memory controller of the present invention can access a flash memory, the flash memory controller of the present invention can fully utilize the bus body bus, thereby greatly improving the performance. In addition, the number of flash control chats is also reduced by the shared memory wheeled output and output, which also reduces the manufacturing of flash memory devices. According to the present invention, integrated multi-block access and multi-cell alternate access can be implemented. Channel operation is integrated into a single memory-storage cycle to achieve performance optimization. 48 200915339 According to the present invention, the flash memory controller can use USB or a PCI Express plug-in and socket system. Of course, the flash memory controller can be implemented in other implementations including plug-in and socket systems such as SD, MMC, MS, CF, IDE, and STAT. The present invention provides a number of advantages in accordance with the systems and methods disclosed herein. For example, the flash memory management and other wisdom of the host are transferred from the host to the flash Z memory controller, so that the host system does not require the configuration of the flash memory, and the flash memory controller can interact with the flash memory controller; for example; The flash memory controller provides LBA_T〇_pBA conversion, old magnetic area recovery and average loss algorithm, etc. In addition, the recovery operation is executed in the background; in addition, the flash memory dedicated definition package and standard are also arranged. In addition, the flash memory controller provides multiple data access, multi-channel processing, and multi-cell alternate access. Therefore, while maintaining compatibility with the USB and ASIC architecture, flash memory writes and Reading data has grown tremendously. The present invention discloses a system and method for controlling a flash memory card. The system and method consists of an index that receives at least one request from the host, an index consisting of a lookup table and an entity usage table. This cable converts the logical block address from the host into a solid block of flash memory. The index also contains information that is configured as a flash memory. The processor can use the Emperor's 3D to calculate the flash memory for programming and re-editing.

Cheng and read magnetic ps·H

The πβ ° flash memory controller also includes a loop FIFO (FIFO, Field I) for recycling old magnetic areas so they can be used for reprogramming. The recycle operation package contains both copy and erase operations, which are done in the background 'and therefore are invisible to the host μi μ + system. Accordingly, the management speed is 49 Ο Ο 200915339 Flash memory and related wisdom are completed by the flash memory controller instead of the host system. As a result, the host system does not require the flash memory configuration information and the flash memory controller. Influence each other. Therefore, while maintaining the compatibility of the hacker and the ASIC architecture, the write and read data of the flash memory has been greatly increased. 'Although the invention described in the context of this document describes an electronic data flash memory card with or without fingerprint verification, the present invention may retain its spirit and paradigm in health_ applied to other types of systems. . Furthermore, although the invention described herein is described as standard in the context of the invention, the invention may be applied to other types of standards within the spirit and scope of the invention. Therefore, the method of giving a tribute to the poor moon can be done by means of humans, software, computer readable media containing program instructions or their multiplexes. Thus, departures may be made from the spirit of the invention and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing the structure of an electronic data flash memory card with a fingerprint verification function according to an embodiment of the present invention. Fig. 2 is a schematic block diagram showing the structure of a material circuit according to another embodiment of the present invention. Fig. 3 is a schematic block diagram showing the structure of a processing unit for a card according to another embodiment of the present invention.枓 枓 枓 兄 图 图 Figure 4A is a process flow diagram of the first embodiment of the present invention. Detecting (4) Flash Memory Type 50 200915339 Data Flash Memory Card FIG. 4B is a schematic block diagram showing the structure of an electronic portion in another embodiment of the present invention. Figure 5A is an 8-bit processor access block diagram. 8-bit data flash memory structure shows 16-bit data flash, hidden structure Figure 5B is a 16-bit processor access schematic block diagram. 〇 Figure 50 shows the structure of a 16-bit dual-channel processor that accesses the data flash memory through a single controller. Two 8-bit graphs 5D are the first type of real-ear implementation according to the present invention, using a 16-bit cross-talk processor to control two octaves through a separate control test. The structure of the day & ^ ^ J like δ 诅兀 诅兀 枓 枓 枓 枓 枓 〇 〇 6 6 6 6 6 6 另一 另一 另一 另一 另一 工 工 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ A schematic block diagram of the circuit module structure. The figure is a schematic block diagram of the structure of the (4) memory system of the memory controller and the flash memory.

FIG. 8 is a schematic block diagram showing the specific structure of the write lookup table, the read lookup table, the entity usage table, and the recycling FIFO unit of FIG. 7 of the present invention. FIG. 9 is a schematic block diagram showing the specific structure of the flash memory in FIG. 7 of the present invention. Figure 10 is a high level flow chart of a method for processing flash memory in accordance with the present invention. Figure 11 is a flow diagram of a method for transmitting a USB bulk capacity service request in accordance with the present invention. 12A, 12B, and 12C are block diagrams showing the structure of a command block wrap, a command read format simplified block, and a command status wrap, respectively. Figure 13 is a flow chart of a method for reading, writing, and erasing according to the present invention. 51 200915339 Figure μ is a high-order flow circle including the first phase of the write process, the second phase of the write process, the read process, and the recycle management method. Figure ba'hhc'bd is a schematic block diagram of representative results derived from the first and second phases of the write process, respectively, in accordance with the present invention. FIG. 16 is a flow chart of a method for implementing the first phase of the write processing of FIG. Figure 17 is a flow chart showing the method of implementing the second phase of the write process of Figure 14. Figure 18 is a flow chart for implementing the read processing method of Figure 14. 19 is a flow chart of a method of implementing the recovery management of FIG. Figures 20a-20d show an example of multiple time programming problems encountered in an MLC (MBC) flash memory system. Circle 21 shows an embodiment of a physical page. [Main component symbol description] '卞 2, 2A, 2C processing unit 3, 3A' 3B1, 3B2, 3C flash memory device 〇 interface circuit 4 fingerprint sensor 5, ^, % input / round out 6, 6A Display unit 7 Thunder 8, 8A function key setting unit 9, 9A host 1〇, l〇A, l〇B, 10c electronic data flash memory card 12 card reader 13 interface bus 21, 21B, 21C flash Memory controller 22 power conditioner 23 reset circuit 24 random access memory area, 152 read only memory 26 static area $ 27 dynamic area 52 200915339 52 host system 110 flash memory controller 116 host system interface 122 string Column interface engine 130 block transfer unit 134 logic block address register 140 magnetic area fifo 148 interrupt processor 1 70 write query table 180 entity use table 190 FIFO 194, 196 read indicator 404 spare area 406 bad block indication area 410 erase Counter area 702 command block package Ο 1 〇〇 flash memory system 112 flash memory 120 device transceiver 124, 125, 126, 126 endpoint 132 transfer length register 142 FIFO non-null interrupt signal 15 〇 processor 172 read query table 1 86 flash memory interface Controller 192 writes indicator 402 data area 414 special bad block indicator area 408 error correction code area 412 logical block address area 704 704 compact block command read format 706 and command status package 502, 504, 602, 604, 606, 608, 802, 804, 806, 810, 812, 814, 820, 822, 828, 830, 832, 834, 836, 902, 904, 906, 910, 920, 930, 940, 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 1122, 1124, 1126, 1128, 1130, 1132, 1134, 1136, 1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216, 1218, 1220, 1302, 1304, 1306, 1308, 1309, 1310, 1312, 1314, 1316, 1317, 1318, 1320, 1402, 1404, 1406, 1408, 1410 Step 53

Claims (1)

200915339 X. The scope of application for patents·· 1. The type of adaptation can establish a flash of screaming: the memory card, the electronic data flash memory beaker - the flash memory device on the card body: Large = non-volatile storage of the data storage case more than two = early? Included in at least one single-order memory list...C) class and a memory store early memory (MLC) class memory unit; Preparing two = one card body and electrically connecting the flash memory device and the flash memory controller of the input/output interface circuit; and an input/output interface circuit. The electronic data flash memory card of claim 1, wherein the SLC memory unit comprises a memory unit of every f2k bytes and a memory unit of 4k bytes per page. The electronic data flash memory card of claim 3, wherein the MLC memory unit comprises a memory unit of 2k bytes per page and a memory unit of 4k bytes per page. The electronic data flash memory card of claim 3, further comprising a plurality of flash memory controllers mounted on the electronic data flash memory card. The electronic data flash memory card of claim 1 , wherein the flash memory controller is configured to manage SLC s memory cells of 2k bytes per page, and SLC of 4k bytes per page. At least one of a memory unit, an MLC memory unit of 2k bytes per page, and an MLC recording unit of 4k bytes per page. 54 200915339 6. The electronic data flash memory card of claim 1, wherein the flash memory controller is for managing SLC and MLC memory units. 7. The electronic data flash memory card of claim 1, wherein the flash memory controller is configured to perform page comparison and magnetic zone merging to avoid writing the MLC type flash memory multiple times. One of the magnetic units of the body unit. 8. The electronic data flash memory card of claim 7, wherein the magnetic zone combination performed by the flash memory controller comprises: receiving data and writing the data to the MLC type flash memory. The part of the unit is required to be written into the physical magnetic zone; the response is required; the next empty physical magnetic zone of one of the MLC-type flash memory cells is designated as a target magnetic zone; the physical magnetic zone is read by the part to read the data; The data read by the partially written physical magnetic zone is combined with the received data to form a combined data; and the combined data is written to the target magnetic zone. 55