200903995 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種靜電放電偵測電路及其相關偵測方法，尤指 -種可以減少靜電放難路之晶#面積並延長—放電持續時 間的靜電放電偵測電路及其相關方法。 【先前技術】 請參考第1圖’ S 1圖是習知靜電放電保護電路10的示意圖。 靜電放電保護電路10包含具有電阻R與電容C之一低通據波器 11、一反向器12(其係由一 p型場效電晶體撕與一 n型場效電晶 體順所構成)以及一靜電籍制電路13(ESD Clamp Circuit)。當靜 電放電保魏路10的第—端點Na具有—靜電峨細時，由於 低通遽波器11的特性會使得第二端點抓之電壓暫時維持於—較 低的電麗’因此P型場效電晶體_會被開啟，而N型場效 體MN會被關閉。如此一來，靜電訊號Sesd會經由p型場效電曰 體MP而轉換為一電流訊號Ijdg，電流訊號㈤會觸發靜電^曰 制電路13來對第一端點Na上的靜電訊號_進行放電操作。狹 ^當第-端點Na上的電壓較正常的供應電壓娜高時(例Μ 的^=化貝^容C、Ρ型場效電晶體^與Ν型場效電晶體讀 此，靜電放電保護電路10無法承受電壓振幅較古的靜 電訊號⑽。更詳細的朗可參考制專利公錢“的靜 US20030076636A1 。 200903995 另-方面’根據美國專利號US5956219，其係揭露另一靜電放 電保護電路，該靜電放電雜電路軸可財受具有較高電屋振 幅的靜電纖’但是該靜電放電織電路係彻三重井(Triple wdi) 製程來加以實現。如此—來不但增加電路的製作成本，而且在應 用於較先軸奈級(NanG_seale)互補錢半導體製辦，其間極 偏壓技術(Gate-driven technique)將更加複雜。 此外’根據美國專觀US6954098，其另揭露了 一靜電放電保 護電路。臟的’該靜電放電職電路雖然可財受具有較高電 壓振幅的靜電訊號’但是該靜電放電賴電路除了使用一正常供 應電壓外，另需較低的供應電壓才得以正常操作。倘若該 正常供應縣和該較低的供應電壓沒有同時啟動，則會導致該靜 電放電保護電路内場效電晶體的閘極氧化層(Gate〇xid9eLayer)發 生損&因此為了避免產生此―問題，美國專利號腸％彻8 所提供的靜電放電保護電路就利用了較厚開極氧化層的製程來實 作，然而，此亦增加了電路的製作成本。 【發明内容】 因此本發明之目的之-在於提供—種靜電放電偵測電路及其 相關偵測方法，以解決上述所說的問題。 依據本發明之-實關，其_露了—種靜較電偵測電路 (ESD detection circuit)。該靜電放電债測電路係輕接於一第一電 200903995 氣訊號端與一第二電氣訊號端之間，並包含有一觸發電路、一偏 壓電路、一觸發控制電路以及一啟動控制電路。該觸發電路係用 來於該靜電放電偵測電路處於一靜電放電(ESD)模式時產生一靜 電放電觸發訊號。該偏壓電路係耦接於該觸發電路，並用來提供 至少一第一偏壓準位以及一第二偏壓準位，以控制該觸發電路之 操作。該觸發控制電路係耦接於該偏壓電路以及該觸發電路，其 用來於該靜電放電偵測電路處於該靜電放電模式時降低該第一偏 壓準位與該第二偏壓準位之間的電壓差，以控制該觸發電路所產 生之該靜電放電觸發訊號之一持續時間。該啟動控制電路係耦接 於該控制電路以及該觸發電路，並用來依據該第一電氣訊號端之 電壓準位來啟動該控制電路與該觸發電路進入該靜電放電模式。 依據本發明之另一實施例，其係揭露一種產生對應於一第一電 氣訊號端與一第二電氣訊號端之一靜電放電觸發訊號的方法。該 方法包含有下列步驟：轉該第―電氣訊號端之準位來啟動 -靜電放電(ESD)模式；提供—觸發電路，並制綱發電路以於 該靜電放賴式下產⑽靜電放侧發峨；提供至少一第一偏 壓準位以及ϋ壓準位來控繼觸發電路之操作丨以及於該 靜電放電模式巾，降健第—偏壓準仙及該第二偏壓準位之間 之-電縣以控繼靜電放觸發訊號之—持續時間。 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞囊來指稱 200903995 寺疋的兀件所屬領域中具有通常知識者應可理解，硬體製造商 會用网的名㈣來稱呼同—個元件。本書及後續的申請 利範圍並不以名稱的差異來作為區分元件的方式，而是以元件 在功能上的絲來作魏分的準則。在韻_書及後續的請求 項當中所提及的「包含」係為—開放式_語，故應解釋成「包 3不限定於」以外’「轉接」一詞在此係包含任何直接及間接 的電氣連接手段。因此，若文中描述―第-裝置減於-第二裝 置，則代賴第-裝置可直接賴連接_第二裝置，或透過其 他裝置或連接手段顺地魏連接至該第二装置。 :考第2圖第2圖疋本發明—實施例之靜電放電偵測電路 100的示意圖。靜電放電_電路100包含有-觸發電路⑼、一 偏壓電路ω2、-觸發控制電路脱以及一啟動控制電路⑽。靜 電放電偵測電路100係耗接於—第—電氣訊號端^㈤與—第二電 氣訊號端Ν_之間。觸發電路⑽係用來於靜電放電_電路⑽ 處於一靜魏賴_產生—靜電放侧發訊號。偏壓電路 102係轉接於觸發電路⑽，並用來提供-第-偏壓準位Vl、一第 -偏壓準位V2以及-第三偏壓準位％以控制觸發電路收的操 作。觸發控制電路103係輕接於偏壓電路102以及觸發電路101， 並用來於靜電放測電路綱處於靜電放電模式時降低第一偏 壓準位V,與第二偏壓準位％之間的電壓差v疏以控制觸發電路 ιοί所產生之靜電放電觸發訊號s啤㈣的一持續時間。啟動 控制電路1G4絲接测發控制電路103以及觸發電路1Q1，並依 200903995 據第一電氣訊號端nvdd之電壓準位VDD來啟動觸發控制電路1〇3 與觸發電路1〇進入靜電放電模式。請注意，為了更清楚描述本發 明之實施例靜電放電彳貞測電路100的精神所在，一靜電放電箝制 電路105(ESD Clamp Circuit)係另麵接於第一電氣訊號端Ν·、第 一電氣訊號端Ngnd之間以及觸發電路之間，並用來依據靜電 放電觸發訊號Strigger來對第一電氣訊號端NVDD進行一電荷放電的 操作。靜電放電箝制電路105包含有一 P型雙載子接面電晶體 (BJT)1051、一 N型雙載子接面電晶體1〇52、一 N井式電 阻1〇53、一 P井式(P-well)電阻1〇54以及複數個二極體·，其 連接方式請參考第2圖，在此不另贅述。 如第2騎示，偏壓電路1〇2係輕接於第一電氣訊號端^^· 與第—電氣sfL號端Ngnd之間，並包含有一第一、第二、第二、第 四第五、第/、一極體連接形式(di〇de_c〇nnecte(j)之p型場效電晶 體 MdI、Md2、Md3、Md4、Md5、Md6，其係以疊接(cascoded)的方 式辆接於第—魏訊號職vdd與第二魏城端N㈣之間，並 用來依據第-1氣訊號端Nv^與第二電氣訊號端之電壓準 位以產生第-麟準〗iVl、第二偏壓準位V2以及第三偏壓準位 V^。另-方面’在偏壓電路102中，並非每一二極體連接形式之 昜放％阳體的基底端均耦接於同一個二極體連接形式之場效電晶 ，的源極端。換句話說’為了設計所需，第—和第二p型場效電 di Md2之基底端係轉接於第一電氣訊號端Nvdd，而第三 第四P型場政電晶體Md3、Hw之基底端係搞接於第-偏壓準位 200903995200903995 IX. INSTRUCTIONS: [Technical Field] The present invention relates to an electrostatic discharge detecting circuit and a related detecting method thereof, and more particularly to a method for reducing the area of an electrostatic discharge and extending the discharge duration Electrostatic discharge detection circuit and related methods. [Prior Art] Please refer to FIG. 1A. FIG. 1 is a schematic diagram of a conventional electrostatic discharge protection circuit 10. The ESD protection circuit 10 includes a low-pass source device 11 having a resistor R and a capacitor C, and an inverter 12 (which is formed by a p-type field effect transistor tear and an n-type field effect transistor). And an ESD Clamp Circuit. When the first terminal Na of the electrostatic discharge Baowei Road 10 has an electrostatic capacitance, the voltage of the low-pass chopper 11 temporarily maintains the voltage of the second end point temporarily - a lower electric quantity. The type field effect transistor _ will be turned on, and the N type field effect body MN will be turned off. In this way, the electrostatic signal Sesd is converted into a current signal Ijdg via the p-type field effect MP, and the current signal (5) triggers the electrostatic circuit 13 to discharge the electrostatic signal _ on the first terminal Na. operating. When the voltage at the first-end point Na is higher than the normal supply voltage Na (example ^^=化贝容C, Ρ-type field effect transistor^ and Ν-type field effect transistor read this, electrostatic discharge The protection circuit 10 cannot withstand the electrostatic signal (10) with a relatively large voltage amplitude. A more detailed reference to the patent patent "Moving US20030076636A1. 200903995 Another aspect" according to the US Patent No. 5956219, which discloses another electrostatic discharge protection circuit, The electrostatic discharge circuit shaft can be subjected to an electrostatic fiber having a high electric house amplitude. However, the electrostatic discharge woven circuit is implemented by a Triple Wdi process. Thus, the circuit manufacturing cost is increased, and Applied to the more advanced nano-NanG_seale complementary semiconductor manufacturing, the Gate-driven technique will be more complicated. In addition, according to the US-specific US6954098, it also exposes an electrostatic discharge protection circuit. 'The electrostatic discharge job circuit can be used to receive electrostatic signals with higher voltage amplitude' but the electrostatic discharge circuit requires a lower supply voltage than the normal supply voltage. The voltage should be operated normally. If the normal supply county and the lower supply voltage are not activated at the same time, the gate oxide layer (Gate〇xid9eLayer) of the field effect transistor in the ESD protection circuit is damaged. Therefore, in order to avoid this problem, the electrostatic discharge protection circuit provided by U.S. Patent No. 8 has utilized a process of thicker open oxide layer to be implemented, however, this also increases the manufacturing cost of the circuit. Therefore, the object of the present invention is to provide an electrostatic discharge detecting circuit and a related detecting method thereof to solve the above-mentioned problems. According to the present invention, the actual closing, the _ exposed - kind of static electricity An ESD detection circuit is connected between a first electrical signal end of the first electrical unit and a second electrical signal end, and includes a trigger circuit, a bias circuit, and a a trigger control circuit and a start control circuit, wherein the trigger circuit is configured to generate an electrostatic discharge trigger signal when the electrostatic discharge detecting circuit is in an electrostatic discharge (ESD) mode The biasing circuit is coupled to the trigger circuit and configured to provide at least a first bias level and a second bias level to control operation of the trigger circuit. The trigger control circuit is coupled to The bias circuit and the trigger circuit are configured to reduce a voltage difference between the first bias level and the second bias level when the electrostatic discharge detecting circuit is in the electrostatic discharge mode to control The triggering circuit is coupled to the control circuit and the trigger circuit, and is configured to activate the control circuit according to the voltage level of the first electrical signal terminal. And the trigger circuit enters the electrostatic discharge mode. According to another embodiment of the present invention, a method for generating an electrostatic discharge trigger signal corresponding to a first electrical signal terminal and a second electrical signal terminal is disclosed. The method comprises the steps of: starting the electro-discharge (ESD) mode by turning on the level of the first electrical signal end; providing a trigger circuit, and preparing the circuit for the electrostatic discharge type (10) electrostatic discharge side Providing at least a first bias level and a pressure level to control the operation of the trigger circuit, and the electrostatic discharge mode towel, the first-biasing threshold and the second bias level In the case of the electricity - electricity county to control the relay to trigger the signal - duration. [Embodiment] In the specification and the subsequent patent application scope, some words are used to refer to the articles of the 200903995 temple. The general knowledge in the field of the temple should be understandable, and the hardware manufacturer will use the name of the network (four) to refer to the same - a component. This book and subsequent applications are not based on the difference in name as the way to distinguish between components, but in terms of the function of the components. The "contains" mentioned in the rhyme book and subsequent claims are open-type, so it should be interpreted as "package 3 is not limited to" and the term "transfer" is used in this section. And indirect electrical connections. Thus, if a "device-to-device"-second device is described herein, the device-dependent device can be directly connected to the second device, or via other devices or connection means. Fig. 2 is a schematic view showing an electrostatic discharge detecting circuit 100 of the present invention. The ESD_circuit 100 includes a -trigger circuit (9), a bias circuit ω2, a -trigger control circuit, and a start control circuit (10). The electrostatic discharge detecting circuit 100 is connected between the -first electrical signal terminal (5) and the second electrical signal terminal Ν_. The trigger circuit (10) is used for the electrostatic discharge_circuit (10) to be in a static state. The bias circuit 102 is coupled to the trigger circuit (10) and is configured to provide a -first bias level V1, a first bias level V2, and a third bias level % to control the operation of the trigger circuit. The trigger control circuit 103 is lightly connected to the bias circuit 102 and the trigger circuit 101, and is used to reduce the first bias level V between the electrostatic discharge mode and the second bias level. The voltage difference v is used to control the duration of the electrostatic discharge trigger signal s beer (4) generated by the trigger circuit ιοί. The start control circuit 1G4 is connected to the test and control circuit 103 and the trigger circuit 1Q1, and activates the trigger control circuit 1〇3 and the trigger circuit 1 to enter the electrostatic discharge mode according to the voltage level VDD of the first electrical signal terminal nvdd according to 200903995. Please note that in order to more clearly describe the spirit of the electrostatic discharge detecting circuit 100 of the embodiment of the present invention, an ESD Clamp Circuit 105 is additionally connected to the first electrical signal terminal, the first electrical Between the signal terminals Ngnd and the trigger circuit, and for performing a charge discharge operation on the first electrical signal terminal NVDD according to the electrostatic discharge trigger signal Strigger. The electrostatic discharge clamp circuit 105 includes a P-type bipolar junction transistor (BJT) 1051, an N-type bipolar junction transistor 1〇52, an N-well resistor 1〇53, and a P-well (P -well) Resistor 1〇54 and a plurality of diodes. For the connection method, please refer to Figure 2, which will not be described here. For example, in the second riding, the bias circuit 1〇2 is lightly connected between the first electrical signal end ^^· and the first electrical sfL end Ngnd, and includes a first, second, second, fourth The fifth, the /, one pole connection form (di〇de_c〇nnecte (j) p-type field effect transistors MdI, Md2, Md3, Md4, Md5, Md6, which is cascoded It is connected between the first Weixin vd and the second Weicheng N (four), and is used to generate the first-liner iVl and the second bias according to the voltage level of the first -1 air signal terminal Nv^ and the second electrical signal terminal. The pressure level V2 and the third bias level V^. In another aspect, in the bias circuit 102, not the base end of each of the diode connection forms is coupled to the same two The source terminal of the field-effect transistor of the polar body connection form. In other words, for the design, the base end of the first and second p-type field effect electric di Md2 is switched to the first electrical signal terminal Nvdd, and The base end of the third and fourth P-type field transistors Md3 and Hw is connected to the first-biasing level of 200003995
Vl ’第五和第六p型場效電晶體‘、^之基底娜_於第 -偏壓準位v2。啟動控制電路1()4包含有—電阻器Ri與容哭Vl 'the fifth and sixth p-type field effect transistors ', ^ is the base __ at the first - bias level v2. Start control circuit 1 () 4 contains - resistor Ri and Rong cry
Mcl，請^以串接切式分別輕接於第一電氣訊號訊號端。口 NVDD與電谷為Mcl之一第一端點。 觸發控制電路103包含有—第—P型場效電晶體Ml、-第二 p型場效電晶體m2、一第三P型場效 一 電晶體Msl、—開關場效 。第，場效電二 、有源極鳊耦接於第一電氣訊號 連私NVDD，一間極端搞接於電容器Mci之第一端點Ν =ΓΜ2具有一源極端叙接於第一場p型效電叫 一>及__端點Nl) ’ 1極端(亦即端點喻接於第一偏壓 =第三ρ型場效電晶體Μ3具有—源極端耗接於第二場效 電曰曰體Μ2之—汲極端(亦即端點Ν3)，—閘 一 _dm趣於第二電氣t_:妾 V!與啟動__(脚端_，H胁P偏壓準位 叫亦即，，-·端發電路 極端(亦即端點N3);第二開關p型場 2 及 耦接於筮_俏晬A 屯日日菔MS2具有一汲端點 端_， 卜Ν6) ’ -閘極端输於第三倾準位％(亦即端點 7 ^外’電壓準位控制電路咖_於第 曰曰體心_二瞻型場效電晶體^之汲極端之： 10 200903995 用來當靜電放錢測電路⑽處於該靜電放電模式時依據第二p 型場效電晶體地找極端上之1卿位％雜低第—偏壓準 位:以及第二偏鮮位v2之間之_ v。依據本發明之實施 例靜電放電偵測電路100，電壓準位控制電路腦包含有-第一 =器ω311以及一第四p型場效電晶體从，其中第一反向器 =⑽-P型場效電晶體與1型場效電晶體所構成，如第2 。第一反向器10311之—第—參考端點係麵接於第二P型 第t==閘極端(亦即端點N2)，-第二參考端點係祕於 _ ^ ,曰曰體M3之閘極端(亦即端，點N4)，一輸入端點係耦 ㈣雜電晶體 反向器10311之一輸出端點n8。 觸發電路101自令右—楚 場效電晶體·及一第效電晶體吣、-第六Μ 具有—源極蝴如細電晶麟 器Mc丨之第—端 。Λ _，一閘極端耗接於電容 晶體仏之源極端^以及一沒極端輕接於第一開關ρ型場效電 效電晶體之則ρ Β_5之雜端與第-·Ρ型場 體MS1之、及極端二間極端叙接於第—開關Ρ型場效電晶 型場效電晶體Μ ’以及一没極端輪於第二· 體^之_端(亦即端輯）。除此之外，第二反向 200903995Mcl, please connect to the first electrical signal signal end in series. Port NVDD and power valley are the first endpoints of Mcl. The trigger control circuit 103 includes a -P-type field effect transistor M1, a second p-type field effect transistor m2, a third P-type field effect transistor Msl, and a switching field effect. First, the field effect power, the active pole is coupled to the first electrical signal and the private NVDD, and one terminal is connected to the first end of the capacitor Mci Ν = ΓΜ 2 has a source terminal connected to the first field p-type The power is called a > and __end point Nl) '1 extreme (that is, the end point is connected to the first bias = the third p-type field effect transistor Μ3 has - the source terminal is consumed by the second field effect曰曰 Μ 之 之 汲 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二,,-·Terminal circuit extreme (ie, end point N3); second switch p-type field 2 and coupled to 筮_俏晬 A 屯日菔 MS2 has a 汲 end point _, Ν 6) ' The gate extremes are lost to the third tilt level % (that is, the end point 7 ^ outside 'voltage level control circuit coffee _ _ 曰曰 body core _ two-dimensional field effect transistor ^ 汲 extreme: 10 200903995 used When the electrostatic discharge measuring circuit (10) is in the electrostatic discharge mode, the second p-type field effect transistor is used to find the extreme 1st position, the low level, the first bias level, and the second fresh position, v2. _ v. Electrostatic discharge detection according to an embodiment of the present invention In circuit 100, the voltage level control circuit brain includes a first=device ω311 and a fourth p-type field effect transistor, wherein the first inverter=(10)-P type field effect transistor and the type 1 field effect power The crystal is formed as in the second. The first reference device 1011 is connected to the second P-type t== gate terminal (ie, the end point N2), and the second reference terminal system Secret _ ^, the gate of the M3 gate (ie, the end, point N4), an input terminal coupled (4) one of the transistor inverters 10311 output terminal n8. Trigger circuit 101 from the right - Chu Field effect transistor · and a first effect transistor 吣, - sixth Μ has - source butterfly such as fine electric crystal lining Mc 丨 第 端 Λ Λ 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一^ and a terminal that is not extremely lightly connected to the first switch ρ-type field effect electro-effect transistor, the ρ Β _5 terminal and the - Ρ field body MS1, and the extreme two extremes are connected to the first switch type The field effect electromorphic field effect transistor Μ 'and one without the extreme wheel in the second body _ end (ie end series). In addition, the second reverse 200003995
，考h點叙接於第六P型場效電晶體M 之祕端’-第二參考端點祕於第二電氣訊號端n_ , —ι 祕耦接於咖p型場效電晶趙Ms2之錄端，《及-輪出 端點Nl°用來輸出靜電放電觸發訊號Strigger。 本發明之靜電放電_電路議包含了兩個操作模式，即 電放電^以及—正常操作模式。當靜電放電偵測電路觸摔作 於該正㊉操作模式下時，第二反向器nm中之該N型場效電曰體 係用來將端點NlG之電壓維持於—接地 v_，而第一電氣\ 供_ Vdd。為了 _贿本發明之精 接也電壓VGND以及供應電壓Vdd分別為Qv和3 3 此’在該正常操作模式下偏麗電路1〇2中的第一偏縣位v 二偏壓準位V2以及第三·準位⑽輸出分別為2.2V、！ lv f 〇.6V。請注意，由於p型場效電晶體‘之 因此卿文電晶體Md6會具有基底效· 偏壓準位％為㈣，而具有㈣的第三偏壓準位t ^ 二開關觀電晶體Ms2。從第2圖可以得知，第二咖場The test point h is connected to the secret end of the sixth P-type field effect transistor M--the second reference end point is secreted to the second electrical signal end n_, —m is coupled to the coffee p-type field effect electric crystal Zhao Ms2 At the end of the recording, "and-round terminal Nl ° is used to output the electrostatic discharge trigger signal Strigger. The electrostatic discharge_circuit of the present invention includes two modes of operation, namely, an electrical discharge and a normal operating mode. When the electrostatic discharge detecting circuit is touched in the positive ten operation mode, the N-type field effect power system in the second inverter nm is used to maintain the voltage of the terminal N1G at - ground v_, and An electric \ for _ Vdd. In order to _ bribe the invention, the voltage VGND and the supply voltage Vdd are Qv and 3 3 respectively. In this normal operation mode, the first partial county level v in the normal operation mode 2 is the second bias level V2 and The third · level (10) output is 2.2V, respectively! Lv f 〇.6V. Please note that due to the p-type field effect transistor, the crystal transistor Md6 will have a substrate effect and a bias level of (4), and a fourth bias level of (4) t^2 switching the transistor Ms2. As you can see from the second picture, the second coffee field
Ms2會對、點&開始進行充電直到端點队上的電_達11 - 止。由於第二反向器麗中的該P型場效電晶體的卿·'、、、 差為〇‘v:因此該p型場效電晶_ ^ 4正_作板式下，靜電放電偵測電路100 就不會產生靜電放電觸發訊號s咖，而靜電放電箝制電路此則 200903995 處於一關閉的狀態。此外，由於第二反向器1011中之該N型場效 電晶體係處於開啟的狀態，因此可以增加靜電放電彳貞測電路1 〇〇 之相位邊際(Phase Margin)以確保觸發控制電路1〇3在該正常操作 模式時不會錯誤地觸發上述之靜電放電箝制電路1〇5。 另一方面，由於第一 P型場效電晶體以及第五p型場效電 晶體均偏壓於供應電壓VDD==3.3V，因此第一 p型場效電晶體 及第五P型場效電晶體Ms均處於關閉的狀態。換句話說， 在該正常操作狀態下，由Ρ型場效電晶體MrM2、Μ3所構成的 電流路徑是處於不導通的狀態，因此Ρ型場效電晶體Μ2係關閉 的。也就是說，Ρ型場效電晶體Μ:之源閘(source-gate)電壓小於一 1-2VP型場效電晶體的臨界電磨(Threshold Voltage，| Vtp丨）。因 此，端點N〗上的電壓會處於2.2V與2.2V+ | Vtp |之間。同樣地， P型場效電晶體Μ;也是關閉的，因此端點％上的電壓會處於i lv 和1.1V+ I V* I之間。當第一反向器10311之該p型場效電晶體 以及第一開關場效電晶體Msl都是開啟的時候，端點叫、N?上的 電壓就會是2.2V。此時第一反向器10311之該]S[型場效電晶體、 第四P型場效電晶體Μ*以及第六P型場效電晶體M6之源閑電麗 就會趨近於零而處於關閉的狀態。從以上所揭露的操作過程可以 得知’當本實施例之靜電放電偵測電路1〇〇操作於該正常操作模 式下且供應電壓Vdd=3.3V時，所有1.2V的場效電晶體之間極氧 化層(Gate-oxide layer)均可以正常地操作。 200903995 . _ $方面’請魏電翻電路丨⑻杨作於該正常操作模式 H在^電氣訊號端Nvdd上的供應雜Vdd係為GV。然而， 田月f電« sESD丨現於帛一電氣訊號端Ν·時，例如當供應電 壓vDD的電源被開啟的瞬間，第一電氣訊號端ν_上的電壓會突 然出現-脈衝訊號，該脈衝訊號之峰值往往會比正常操作下的 3.3V大，如此會導致連接於供應電壓I的電路系統發生損害。 為了更方触述本發明之精神所在，在本實施例巾將靜電訊號 SESD ,峰似6V作為鋼’也就是說#供應賴v㈤的電源被開 啟的瞬間帛t氣峨端Η·靜電訊號“是從GV快速上升 至6V(如第3圖所示）。第3圖是第2圖所示之靜電放電侧電路 _操作於該靜電放電模式時靜電訊號s、第—偏壓準位乂、 第二偏壓準位v2與端點電壓Vnb、％、I、％、I的時序圖。 當靜電訊號sESwtl上升達到6V時，由於啟動控制電路i〇4係 - RC低通紐ϋ，其會造成第—端輯上的—電壓Vnb之上升 速度相對的比靜魏號sESD來得慢，而造成在第—魏訊號端 NVDD與第-端點Nb會產生—電壓差，因此p型場效電晶體Μι、 Ms就會被開啟。當P型場效電晶體Μι、μ;就會被開啟後就會分 別對端點ΝΑ進行充電而使得端點Ni、N5的電壓％快速上升。 另-方面，由於在曰夺間t〇時在端點^化上的第一偏壓準位 V,、第二偏壓準位％與第一偏壓準位％均處於大致上接近〇v的 狀態’因此當具有靜電訊號SESD0fp型場效電晶體Mi、M;亦會 被開啟而分別對端點％、A進行充電，其令端點％、N6之電壓 Vn3、Vn0上升幅度大致上會相同於端點％&之電壓上升幅度。 14 200903995 接著帛—開關場效電晶體Ms2也會被開啟，這是因為當端點& 之電壓Vn6上升時’端點N7之電壓仍維持在相對於端點n6較低的 電壓Vn6。如此—來，端點N4的電壓Vn4就會被充電到與電壓Vn6 同樣的幅度’如第3圖所示。細，在實際操作上，第二開關場 效電晶體⑷的開啟電阻和端點叫上的寄生電容所造成的rc延 遲會使得^»點1^4上的電壓vn4先維持在-較低的賴，此較低的 縣就能夠確保第二·場效電晶體Ms2在有靜電訊號Sesd的期 ，能持、，的處於開啟的狀態。除此之外，該第-反向ϋ之該p型 昜放電aa體之閘極端電μ %3(亦即端點①)會比端點&的電壓 Λ /寻门Q此。亥卩型場效電晶體就會開啟而使得端點化之電壓 vnS與端點N4mA致上拥。接著，ρ型場效電晶體吣 會開啟而將端點N2上㈣-偏Μ準位％拉近至端點&上的第二 偏壓準位v2 ’此時第—偏壓準位Vi與第二偏壓準位v2之間的電 壓差Vdiff係P型場效電晶體M4的臨界電壓(Th郎祕ν〇ι_，丨 此外 ㈣放電偵測電路膽操作於該靜電放電模式時， 由於第一卿％效電晶體Ms2之端⑽卩端點⑹與源極端(亦 =點⑹之_觸權近嶋第：糊場效電晶體Ms2 關閉，因此就可以確保第—偏壓準位V1具有相對於電壓％更低 的電愿。從上㈣操作過程可以得知，觸發電路⑼中的p型場 ' P型場效電晶體W以及第二反向器则 磁電晶體之雜端Nb、N2鳴都可韓持在較低的電壓準位， 15 200903995 ， 如此一來靜電訊號SESD就可以快速地轉換成靜電放電觸發訊號 StHgger至端點N10。請注意，熟習此項技術者應可瞭解靜電放電觸 發δίΐ號Strigger係一電流§札號。另一方面，由於觸發控制電路中 的電壓準位控制電路1031係一數位控制電路，因此除了可以大幅 縮小所需的晶片面積之外，還可以減少當靜電放電偵測電路1〇〇 操作於该正常操作模式下的漏電現象。另外，熟習此項技藝者應 可輕易瞭解靜電放電箝制電路105之操作，在此不另贅述。再者， 須注意的是，觸發電路101、偏壓電路102、觸發控制電路丨⑽以 及啟動控制電路104係可利用具有實質上相同厚度之閘極電介層 (gatedielectric)的電晶體來加以實現之，此一設計亦屬於本發明的 範1#。 請參考第4圖’第4圖是依據本發明第二實施例一種產生對應 於-第-電氣訊號端與一第二電氣訊號端之一靜電放電觸發訊號 的方法流糊，該靜電放電觸發訊號方法係可料2圖所示之靜 電放賴測電路1〇〇來加以實作，因此為了更方便描述該靜電放 電觸發訊號方法的精神所在，以下所揭露之方法_將搭配靜電 放電偵測電路觸來作說明。另一方面，條若大體上可達到相同 的、I果’並不f要—定照第4圖所示之流程巾的步剩序來進行， 且第4圖所示之步驟不一定要連續進行，亦即其他步驟亦可插入 其中。該靜電放電觸發訊號方法包含有下列步驟： 步驟401 ··開始； 步驟402 : _靜電放飾㈣路_之操倾式，當靜電放 16 200903995 電债測電路100操作於該正常操作模式時，進行步 驟403 ’當靜電放電偵測電路100操作於該靜電放 電模式時，進行步驟406 ; 步驟403 :利用偏壓電路102依據第一電氣訊號端NVDD之供 應電壓VDD來產生第一偏壓準位Vl、第二偏壓準位 乂2以及第三偏壓準位V3 ; 步驟404 :利用觸發控制電路1〇3、啟動控制電路1〇4依據第 偏壓準位V〗、第二偏壓準位V2以及第三偏壓準 位V3來關閉觸發電路101 ; 步驟405 :關閉靜電放電箝制電路1〇5 ; 步驟406:利用啟動控制電路1〇4來啟動觸發電路1〇1以產生 靜電放電觸發訊號Strigger來觸發靜電放電箝制電路 105 ； 步驟407 ·•利用觸發控制電路103將端點N2上的第一偏壓準 位％拉近至端點N4上的第二偏壓準位乂2以延長靜 電放電觸發訊號Strigger的持續時間Ttrig# ; 步驟408 :利用靜電放電箝制電路1〇5快速地對第一電氣訊號 端NVDD之靜電訊號sESD進行放電操作。 在此須注意到，在步驟402中，當靜電放電偵測電路1〇〇不操 作於該正f操健式τ時，在第—電氣訊號端上的供應電屢 VDD係為0V。換句話說，當靜電訊號出現於第一電氣訊號端 NVDi^f，第一電氣訊號端Nvdd上的初始電壓亦是〇v。因此，在 200903995 步驟407 ’觸發控制電路1〇3會將端點N2上的第一偏壓準位％ 拉近至端點N4上的〇v。另一方面，觸發控制電路1〇3係利 壓準位控制電路1031來控制Ρ型場效電晶體Μ4以將端點Ν 第-偏壓雜Vl拉近至端點ν4上的第1壓雜ν2。 ' 以上所述僅為本發明之較佳實施例，凡依本發明申請 圍所做之解變化雜飾，皆麟本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知靜電放電保護電路的示意圖。 2 2本_—實施例之靜電放電制電路的示意圖。 二^ 2 ®所以靜魏電_電路操作於靜電 之靜電訊號、第-麟m&「 电姨稱 壓的時序圖。偏壓丰位第一偏壓準位與複數個端點電 第4圖為第2圖所示之靜電放賴測電路的操作流程圖。 【主要元件符號說明】Ms2 will charge, point & charging until the power on the end team reaches 11 - stop. Since the difference between the second type and the P-type field effect transistor of the second inverter is 〇'v: the p-type field effect transistor _ ^ 4 is _ plate type, electrostatic discharge detection The circuit 100 does not generate an electrostatic discharge trigger signal, and the electrostatic discharge clamp circuit is in a closed state. In addition, since the N-type field effect transistor system in the second inverter 1011 is in an on state, the phase margin of the electrostatic discharge detection circuit 1 can be increased to ensure the trigger control circuit 1〇 3 The above-described electrostatic discharge clamp circuit 1〇5 is not erroneously triggered in this normal operation mode. On the other hand, since the first P-type field effect transistor and the fifth p-type field effect transistor are both biased to the supply voltage VDD==3.3V, the first p-type field effect transistor and the fifth P-type field effect The transistors Ms are all in a closed state. In other words, in this normal operating state, the current path formed by the 场-type field effect transistors MrM2, Μ3 is in a non-conducting state, so the 场-type field effect transistor Μ 2 is turned off. That is to say, the source-gate voltage of the 场-type field effect transistor is less than the threshold electric resistance (|Vtp丨) of a 1-2VP type field effect transistor. Therefore, the voltage at the endpoint N is between 2.2V and 2.2V+ | Vtp |. Similarly, the P-type field effect transistor is also off, so the voltage at the terminal % will be between i lv and 1.1V + I V* I. When the p-type field effect transistor of the first inverter 10311 and the first switching field effect transistor Msl are both turned on, the voltage at the end point, N? is 2.2V. At this time, the source of the first inverter 10311, the S-type field effect transistor, the fourth P-type field effect transistor Μ*, and the sixth P-type field effect transistor M6, will approach zero. It is in a closed state. It can be known from the above-mentioned operation process that when the electrostatic discharge detecting circuit 1 of the present embodiment operates in the normal operation mode and the supply voltage Vdd=3.3V, all the 1.2V field effect transistors are in between. The gate-oxide layer can be operated normally. 200903995 . _ $ aspects Please ask Wei electric circuit 丨 (8) Yang Zuo in this normal operation mode H Supply noise Vdd on the electric signal terminal Nvdd is GV. However, when Tian Yue f electricity « sESD 丨 is present at the end of the electric signal, for example, when the power supply voltage vDD is turned on, the voltage on the first electrical signal terminal ν_ suddenly appears - the pulse signal, The peak value of the pulse signal tends to be larger than 3.3V under normal operation, which may cause damage to the circuit system connected to the supply voltage I. In order to further illustrate the spirit of the present invention, in the present embodiment, the electrostatic signal SESD, the peak like 6V as the steel 'that is, the supply of the power supply to the v (five) is turned on. It is a rapid rise from GV to 6V (as shown in Figure 3). Figure 3 is the electrostatic discharge side circuit shown in Figure 2 - the electrostatic signal s, the first bias level 操作, when operating in the electrostatic discharge mode, Timing diagram of the second bias level v2 and the terminal voltages Vnb, %, I, %, I. When the electrostatic signal sESwtl rises to 6V, since the start control circuit i〇4 system-RC low-pass, it will The rising speed of the voltage Vnb on the first-end series is slower than that of the static sESD, and the voltage difference between the NVDD and the first-end Nb at the first-end signal is generated, so the p-type field effect power The crystals Μι, Ms will be turned on. When the P-type field effect transistors Μι, μ; will be turned on, the terminal ΝΑ will be charged separately, so that the voltages of the terminals Ni and N5 rise rapidly. , the first bias level V on the endpoint, and the second bias level % and the first The bias level % is in a state substantially close to 〇v. Therefore, when there are electrostatic signals SESD0fp type field effect transistors Mi, M; they are also turned on to charge the terminals %, A respectively, which makes the terminal % The voltages of N6 and Vn0 increase substantially the same as the voltage rise of the end point %& 14 200903995 Next, the switch field effect transistor Ms2 is also turned on, because the voltage at the end point & When Vn6 rises, the voltage at the end point N7 is still maintained at a lower voltage Vn6 than the end point n6. Thus, the voltage Vn4 of the terminal N4 is charged to the same amplitude as the voltage Vn6 as shown in Fig. 3. In the actual operation, the rc delay caused by the on-resistance of the second switch field effect transistor (4) and the parasitic capacitance at the end point will cause the voltage vn4 at the point 1^4 to be maintained first. Low, this lower county can ensure that the second field effect transistor Ms2 can be held in the period of the static signal Sesd. In addition, the first-reverse The p-type 昜 discharge aa body gate extreme electrical μ % 3 (ie end point 1) will be compared to the end point & Λ / 寻门Q This. The 卩-type field effect transistor will be turned on so that the terminal voltage vnS and the terminal N4mA are on. Then, the ρ-type field effect transistor will be turned on and the terminal N2 will be on. (4) - the partial bias level % is drawn to the second bias level v2 at the end point & 'The voltage difference between the first biasing level Vi and the second biasing level v2 is Vdiff type P The threshold voltage of the field effect transistor M4 (Th lang 〇 〇 _ _ 丨 丨 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四Extreme (also = point (6) _ touch right 嶋 :: paste field effect transistor Ms2 is off, so it can be ensured that the first - bias level V1 has a lower power relative to the voltage %. It can be known from the above (4) operation process that the p-type field 'P-type field effect transistor W and the second inverter in the trigger circuit (9) can be held at a lower voltage by the miscellaneous terminals Nb and N2 of the magneto-optical crystal. Level 15, 15 200903995, so that the electrostatic signal SESD can be quickly converted into the electrostatic discharge trigger signal StHgger to the end point N10. Please note that those skilled in the art should be able to understand the electrostatic discharge trigger δίΐ Strigger line current § number. On the other hand, since the voltage level control circuit 1031 in the trigger control circuit is a digital control circuit, in addition to substantially reducing the required wafer area, it is also possible to reduce the operation of the electrostatic discharge detecting circuit 1 Leakage in normal operating mode. In addition, the operation of the electrostatic discharge clamp circuit 105 should be readily understood by those skilled in the art and will not be further described herein. Furthermore, it should be noted that the trigger circuit 101, the bias circuit 102, the trigger control circuit 丨(10), and the startup control circuit 104 can be implemented by using a transistor having substantially the same thickness of a gate dielectric. In realization, this design also belongs to Fan 1# of the present invention. Please refer to FIG. 4'. FIG. 4 is a flow chart of generating an electrostatic discharge trigger signal corresponding to one of the -first electrical signal end and a second electrical signal end according to the second embodiment of the present invention, the electrostatic discharge trigger signal The method can be implemented by the electrostatic discharge measuring circuit 1 shown in FIG. 2, so in order to more conveniently describe the spirit of the electrostatic discharge triggering method, the method disclosed below will be combined with the electrostatic discharge detecting circuit. Touch to explain. On the other hand, if the strip can be substantially the same, the result of the result is not the same as that of the step of the flow chart shown in Fig. 4, and the steps shown in Fig. 4 do not have to be continuous. It can be inserted, that is, other steps can be inserted. The ESD trigger signal method includes the following steps: Step 401 ··Start; Step 402: _ Electrostatic discharge (4) way _ tilting, when the electrostatic discharge 16 200903995 electric debt measurement circuit 100 operates in the normal operation mode, When the electrostatic discharge detecting circuit 100 is operated in the electrostatic discharge mode, step 406 is performed; step 403: using the bias circuit 102 to generate the first bias according to the supply voltage VDD of the first electrical signal terminal NVDD. a bit V1, a second bias level 乂2, and a third bias level V3; Step 404: using the trigger control circuit 1〇3, starting the control circuit 1〇4 according to the second bias level V, the second bias The trigger circuit 101 is turned off by the level V2 and the third bias level V3; Step 405: Turn off the electrostatic discharge clamp circuit 1〇5; Step 406: Start the trigger circuit 1〇1 by using the start control circuit 1〇4 to generate an electrostatic discharge Triggering the signal Strigger to trigger the electrostatic discharge clamp circuit 105; Step 407 • Using the trigger control circuit 103 to pull the first bias level % on the terminal N2 to the second bias level 乂 2 on the terminal N4 to Extend the electrostatic discharge The duration of the signal Strigger Ttrig #; Step 408: ESD clamp circuit using rapid electrostatic 1〇5 sESD signal of a first electrical signal terminal NVDD discharge operation. It should be noted here that in step 402, when the electrostatic discharge detecting circuit 1 does not operate in the positive f-operation type τ, the supply electric power VDD on the first electric signal terminal is 0V. In other words, when the electrostatic signal appears on the first electrical signal terminal NVDi^f, the initial voltage on the first electrical signal terminal Nvdd is also 〇v. Therefore, at 200903995, step 407' trigger control circuit 1〇3 pulls the first bias level % on endpoint N2 to 〇v on endpoint N4. On the other hand, the trigger control circuit 1〇3 controls the level control circuit 1031 to control the 场 field effect transistor Μ4 to draw the terminal Ν first-bias voltage V1 to the first voltage on the terminal ν4. Ν2. The above description is only a preferred embodiment of the present invention, and all the variations and modifications made by the application of the present invention are covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a conventional electrostatic discharge protection circuit. 2 2 Schematic diagram of the electrostatic discharge circuit of the embodiment. 2^ 2 ® so static Wei _ circuit operates on static electricity electrostatic signal, _ _ m & "Electric 姨 pressure timing diagram. Bias abundance first bias level and a plurality of end points electricity 4th It is the operation flow chart of the electrostatic discharge measuring circuit shown in Fig. 2. [Main component symbol description]
18 200903995 102 偏壓電路 103 觸發控制電路 104 啟動控制電路 105 靜電放電箝制電路 1011 第二反向器 1031 電壓準位控制電路 1051 P型雙載子接面電晶體 1052 N型雙載子接面電晶體 1053 N井式電阻 1054 P井式電阻 1055 二極體 10311 第一反向器 1918 200903995 102 Bias circuit 103 Trigger control circuit 104 Start control circuit 105 Electrostatic discharge clamp circuit 1011 Second inverter 1031 Voltage level control circuit 1051 P type double carrier junction transistor 1052 N type double carrier junction Transistor 1053 N well type resistor 1054 P well type resistor 1055 diode 1011 first reverser 19