200903672 υοιιυυο ^ / /otwf.doc/n 九、發明說明： 【發明所屬之技術領域】 關於一種岐錢路==及_，且特別是有 【先前技術】200903672 υοιιυυο ^ / /otwf.doc/n IX. Description of the invention: [Technical field to which the invention pertains] About a money road == and _, and especially there are [prior art]
Ik著紐電路晶片之接雜及接點密度的增加，用來Ik circuit circuit chip connection and contact density increase, used
^、as片之線路載板的接點密度及佈線密度亦必須能夠對 配合。除I晶片封裝用之線路載板以外，隨著電子產品 51化及;|型化，電子產品的主機板所使用的線路載板 ^逐漸朝向高佈線密度的趨勢發展。因此，高佈線密度之 線路載板的需求逐漸上升。 别線路載板的製作方式大致包括疊層法（ proc，）及，法⑼爾解―。 你士 '層法疋先將位在介電層之表面的圖案化線路層製 成之後，再將所需的圖案化線路層及介電層疊壓成為 ^豐層結構、，之後進行電鍍通孔（Plated thnmgh hole，即 'TH^步驟以連接位於科同層次_案化祕層。增層 法乃疋在一基板上依序形成圖案化線路層，並在依序製作 ==線路層的過程中—併製作連接前—層圖案化線路層 的 V 電孔（conductive via )。 【發明内容】 本發明提供-種内埋式線路結構製程，用以在介電層 200903672 ^ …咖Jtw£doc/ii 上髮作出埋入介電層之〜 過此介電層來連接介電層=線路圖案，並同時製作 本發明提供—種内兩面的線路圖案的導^ 電性連接其介電層之兩场=路結構，其具有導電^來 本發明提出-種内^兩内埋線路圖案。 道來 1 一線路圖案及—介電製程。提供-基被、 配置在基板之—基板表〃弟-線路職及介電爲 案。接著，經由雷射加工’二:層覆蓋第'線路； 陷圖案於介電層之一多：局：之介電層，以形成j -貫孔’其中貫孔暴露出第—線穿過介電層之至少 由電鍍將導電材料填人之局部。接著、 路圖案於凹陷圖案内， ，、、以形成—第二緩 移除第二線路圖案之超於貫孔内。接著， 線路圖案至介電表面。 _的‘ ’以平整化第二 之=實施例中’此製程更包括移除基板。 ^之—實施例中，移除第二線路圖宰之 方式包括_或研磨。 ⑽㈣之π分的 陷圖制中，經由咖_材料填、 ㈣二入二之步驟包括經由化學電鐘將導電材料全叫 的局面=、巧貫孔所暴… =電材料形成在電鐘種子層上，以填滿貫孔來 、亚填滿凹陷圖案來形成第二線路圖案。 在本發明之一實施例卜移除第二線路圖案之超出四 200903672 5twf.doc/n 陷圖案的部分更包括移除電鍍種子層 分’以平整化電鑛種子層至介電表f超出凹鳴圖案的部 、在本發明之-實施例中，移除 式包括蝕刻或研磨。 種子層之部分的方 本發明提出-種内埋式線路結 方 電案、一第二綠路圖〜ί;介電層、 ，、有弟—面及與之相對的—塗_ 導電孔道。八 埋入：電層之第一面。第二線路圖二面。第'缘路圖宰 面端道與第二線路圖案1成;里=電層之第： 在本發明之一實_中( 層’，位於介科及第二線&^包括1錢 居ί本發明之一實施财 θ二=及·導電孔道之間。更包括—電鍍種子 Ο 本發明道之^電趟種子 板二-第'線略圖案、一第：線:路結構製程。提供 —第二介電屑 線路圖案、—筮^ 基 板之—第;2 、線路圖案及第—介ί:層及 案其而第二線略圖案及第二介弟電::電層覆蓋第-線4 —基板表面的1二基板表面】層配置在基板之相對於第 =1:接著’經由雷射加；第f介!層覆蓋第二 v第—四陷圖案於第—介^局部之第-介電層， 卜 电層之一第—介電表面， 200903672 >twf.d〇c/n 亚形成穿過第—介電層之至少— 暴露出第-線路圖案之局部貫孔，其中第—貫孔 部之第二介電層，以形成—f㉟由雷射加工移除局 一第二介電表面，並形成穿;凹陷圖案於第二介電層之 孔，其中第二貫孔暴露出第』:介電層之至少—第二貫 由電鍍將導電材料埴入第一 /圖案之局部。接著，經 陷圖案及第二貫孔，、以形成、第1孔、第二凹 案内、-第-導電孔道於第、I—線略圖案於第—凹陷圖 第二凹陷圖案内、—第二導：孔内、-第四線路圖案於 移除第三線路圖案之超出第〜道於第二貫孔内。接著， 第三線路圖案至第—介電表7陷，案的部分，以平整化 之超出第二凹陷圖案的料，’移除第四線路圖案 二介電表面。 平1化第四線路圖案至第 在本發明之—實施例中， 方式包括蝕刻或研磨。 *'弟二線路圖案之部分的 在本發明之一實施例中 方式包括蝴或研磨。 **四祕_之部分的 在本發明之一實施例中，經 -凹陷圖案、第二凹陷圖案、第— 爾填入第 包括經由化學電鍍將導電材料全面貝性形成孔， 面、第-貫孔及受到第-貫孔所暴露電表 部的表面’以形成一第一電鍍 ：：的局 導電材料全面性形成在第二介=，由化學電麵將 -貝孔所暴狀第二線路圖案的局部的表面，以形成」| 200903672 5twf.d〇c/n 一電鍍種子層。接著’經由電解電鍍將 -電鑛種子層上，以填滿第—貫孔來形成第」=成在第 亚填滿第1關絲形成第三線路_ 2孔道， 成在第二電鍍種子層上，心電巧 路圖v電孔道，並填滿第二凹關案來形成 在本發明之一實施例中’移除第三線路 =案的部分更包括移除第1難子層之超^超出四 圖本的部分’以平整化第_電鑛凹陷 二本發明之一實施例中，移除第一電:=。 的方式包括蝕刻或研磨。 又種十層之部分 =發明之—實施例中，移除第四線 =_部分更包括移除第二電 ^超出四 圖案，分，以平整化第二電_子層至第陷 在本發明之一膏偷你丨由 电表面。 Ο 的方式包括_或研磨。，移除第二電錄種子層之部分 種;Γ式線路結構，包括―基板… 介電層、-第三線路圖案電層、-第二 導電孔道及至少—第二導心弟四線路圖案、至少一第-板之-第-基板表面：。：孔線路圖案配置在基 基板表_-第二基=路圖案，在基板之相對 第〜基板表面上，且第—介=上1—介電層配置在 介電層配置在第二基板表面Jθ覆隸二線路圖案。第二 上，且弟二介電層覆蓋第二線 200903672 5twf.doc/n -介電表面：第:;以=較遠離基板的-第 =ΐΤ第二介電表面埋入第二介電 料過第-介電層以連接弟:導電孔道之— 第四線路圖案-體成形，其中弟一導電孔道與 二介電層以連接第二線路圖案。 孔遏之一端穿過第 在本發明之-料财 子層，其位於第—介電層及第;第 在本發明之一實施例中 ^間。 子層，其位於第-介電層及第―導^更包括-第. 在本發明之—實施例中，此結之間。 Ο 電鍍種 電鍍種 電鍍種 子層，其位於第一線路圖案及第—I更包括一第-在本發明之一實施例中，此結電孔道之間 子層二:位於第二介電層及第四括—第 在本發明之—實施例中，此結間。 子曰，其位於第二介電層及第二 匕括-第二電 在本發明之一實施例中，此結L遏之間。 1 子層，其位於第二線路圖案及第_更包括〜苐〜 基於上述，本發明可在介b孔道4:電鑛種 案的過程中同時製作導電孔道，、㊆製作 !·生連二=電層之另—面的線路圖索^述内ά里線格圖案】 為邊本發明之上述和其他目的、 易懂，下文特舉多個實施例，麵合優點能更明顯 Μ ’作詳細說 200903672 ^twf.doc/n 明如下 【實施方式】 圖1Α至1Ε繪示本發明之一實施例的内埋式緩路於構 製程。本實施例可製作出一雙層線路板，即具有兩層^路 圖案的線路板。 請參考圖1Α，首先提供一基板1〇〇、一第—緩路圖我 102及一介電層1〇4,其中第一線路圖案1〇2及介電声 配置在基板100之一基板表面10此上，且介電層 第一線路圖案1〇2。在本實施例中，基板1〇〇 :二 板。 一支揮 請參考圖1Β，經由雷射加工移除局部 以形成—凹陷圖案觸於介電層⑽之 ^層1〇4’ 過介電層⑽之至少-貫孔‘ =!：购’ Ο^, the contact density of the line carrier of the as-chip and the wiring density must also be able to match. In addition to the line carrier for the I chip package, the line carrier used in the motherboard of the electronic product gradually develops toward a high wiring density as the electronic product is turned into a product. Therefore, the demand for line carriers with high wiring density is gradually increasing. The way in which the line carrier is made includes roughly the stacking method (proc,) and the method (9). After you have made the patterned circuit layer on the surface of the dielectric layer, the desired patterned circuit layer and dielectric layer are laminated into a layered structure, and then plated through holes. (Plated thnmgh hole, the 'TH^ step to connect at the same level _ the secret layer. The layering method is to form a patterned circuit layer on a substrate sequentially, and in the process of sequentially making == circuit layer Medium--and fabricating a V-via (via) via-layer patterned circuit layer. [Invention] The present invention provides a built-in buried circuit structure process for use in a dielectric layer of 200903672^ /ii is applied to the buried dielectric layer to pass through the dielectric layer to connect the dielectric layer=line pattern, and at the same time, the wiring pattern provided by the present invention is electrically connected to the dielectric layer Two fields = road structure, which has a conductive ^ to the present invention - a two internal buried circuit pattern. A 1 line pattern and a dielectric process. Provided - based on the substrate - substrate table - Line job and dielectric case. Then, through laser processing 'two: layer Covering the 'th line; trapping the pattern in one of the dielectric layers: the dielectric layer to form the j-through hole' wherein the through hole exposes the first line through the dielectric layer and at least electroplated to fill the conductive material a portion of the person. Then, the road pattern is formed in the recess pattern, and is formed to remove the second line pattern beyond the through hole. Then, the line pattern is applied to the dielectric surface. In the second embodiment, in the embodiment, the process further includes removing the substrate. In the embodiment, the method of removing the second line pattern includes _ or grinding. (10) (4) π points in the trapping system, via the coffee _Material filling, (4) The second step into the second step includes the situation that the conductive material is called by the chemical electric clock =, and the hole is violent... The electric material is formed on the seed layer of the electric clock to fill the through hole and subfill. The recessed pattern is formed to form a second line pattern. In an embodiment of the present invention, removing the portion of the second line pattern that exceeds four 200903672 5twf.doc/n trap pattern further includes removing the electroplated seed layer to 'flatten the electricity The mineral seed layer to the part of the dielectric meter f beyond the concave pattern, in the hair In the embodiment, the removal method includes etching or grinding. The invention of the seed layer proposes an internal buried circuit junction electric circuit, a second green circuit diagram, a dielectric layer, and Brother-face and opposite--coating_ conductive hole. Eight buried: the first side of the electric layer. The second line is on the second side. The first edge of the road is the end of the road and the second line pattern; = the first layer of the invention: in one of the inventions _ (layer ', located in the division and second line & ^ including 1 money in the implementation of one of the invention θ θ = and · conductive holes between. Including - electroplating seed Ο the invention of the electric 趟 seed board two - the 'line outline pattern, a: line: road structure process. Provide - the second dielectric chip line pattern, - 筮 ^ substrate - the first; , the line pattern and the first - the layer and the case and the second line slightly pattern and the second brother:: the electrical layer covers the first line 4 - the surface of the substrate surface of the substrate 2 layer is arranged on the substrate relative to The first =: then 'via the laser plus; the first f! layer covering the second v-four trap pattern in the first - the first part of the dielectric layer, the first layer of the dielectric layer - the dielectric surface , 200903672 > twf.d〇c/n sub-formed through at least the first dielectric layer - a local via hole exposing the first line pattern, wherein the second dielectric layer of the first via portion is formed to form - F35 removes a second dielectric surface by laser processing and forms a hole; the recessed pattern is in the hole of the second dielectric layer, wherein the second through hole exposes the first: at least the second layer of the dielectric layer Electroplating breaks the conductive material into the first/pattern portion. Then, the trapped pattern and the second through hole are formed, and the first hole, the second concave portion, the first conductive hole, and the first conductive line are slightly patterned in the second concave pattern of the first concave pattern, The two guides: the in-hole, - fourth line pattern is removed from the third line pattern beyond the second pass in the second through hole. Then, the third line pattern is recessed to the first dielectric sheet 7, and the portion of the case is flattened beyond the material of the second recess pattern, and the second dielectric pattern is removed. The fourth line pattern is flattened to the first embodiment of the invention, including etching or grinding. * 'Part of the second line pattern in one embodiment of the invention includes a butterfly or a lapping. **Part 4 of the present invention, in one embodiment of the present invention, the via-recess pattern, the second recess pattern, and the first filling include forming a hole in the conductive material by chemical plating, the surface, the first- The through hole and the surface of the electric meter portion exposed by the first through hole are formed to form a first electroplating:: the local conductive material is comprehensively formed in the second dielectric layer, and the second electric circuit is formed by the chemical electric surface The local surface of the pattern is formed to form a || 200903672 5twf.d〇c/n electroplated seed layer. Then, 'the electro-electroplating is performed on the seed layer of the electric ore to fill the first through hole to form the first" = the first line is filled in the first to form the third line _ 2 hole, and the second plating seed layer is formed. In the embodiment of the present invention, the portion of the 'removing the third line=the case includes the removal of the first difficult sub-layer. ^In the embodiment of the invention in which the portion of the four figures is exceeded, in the embodiment of the invention, the first electricity is removed: =. Ways include etching or grinding. Another ten-layer part=invention--in the embodiment, removing the fourth line=_ part further includes removing the second electric^ beyond the four patterns, and dividing to flatten the second electric_sub-layer to the first One of the inventions of the cream steals you from the electric surface. The way to Ο includes _ or grinding. Removing a portion of the second logger seed layer; the 线路-type circuit structure includes a substrate, a dielectric layer, a third line pattern electrical layer, a second conductive via, and at least a second guiding fourth line pattern At least one first-plate-first-substrate surface: The hole line pattern is disposed on the base substrate table _-second base=road pattern on the opposite substrate surface of the substrate, and the first dielectric layer is disposed on the surface of the second substrate Jθ covers the two line patterns. Secondly, and the second dielectric layer covers the second line 200003672 5twf.doc / n - dielectric surface: the:: = second, away from the substrate - the second dielectric surface buried in the second dielectric The first dielectric layer is connected to the second: a fourth circuit pattern-body shape, wherein the first conductive hole and the second dielectric layer are connected to the second line pattern. One end of the pore suppressor passes through the first layer of the present invention, which is located between the first dielectric layer and the first embodiment of the present invention. The sub-layer, which is located between the first dielectric layer and the first-conducting layer, includes - in the embodiment of the invention, between the junctions.电镀 electroplating electroplating seed plating layer, which is located in the first circuit pattern and further includes a first embodiment in the embodiment of the present invention, the sub-layer two between the junction holes: located in the second dielectric layer and The fourth bracket - in the embodiment of the invention, this knot. A sub-electrode, which is located between the second dielectric layer and the second sub-secondary-second electrical power, is in the embodiment of the invention. 1 sub-layer, which is located in the second line pattern and the _ more includes ~ 苐 ~ Based on the above, the present invention can simultaneously make conductive holes in the process of the b-hole 4: electric ore species case, and the seventh production! = the other side of the electrical layer, the circuit diagram of the inner layer, and the other objects, which are easy to understand, and the following are specific examples, the advantages of the surface can be more obvious. DETAILED DESCRIPTION OF THE INVENTION [0002] The following is a schematic diagram of an embedded slow-path construction process according to an embodiment of the present invention. In this embodiment, a two-layer circuit board, that is, a circuit board having a two-layer pattern, can be fabricated. Referring to FIG. 1A, first, a substrate 1 , a first and a slow circuit diagram 102 and a dielectric layer 1 〇 4 are provided, wherein the first line pattern 1 〇 2 and the dielectric sound are disposed on a substrate surface of the substrate 100. 10, and the dielectric layer first line pattern 1〇2. In this embodiment, the substrate 1 is: two plates. Referring to FIG. 1A, the portion is removed by laser processing to form a recessed pattern that touches the dielectric layer (10) layer 1〇4' over the dielectric layer (10) at least the through hole '=!: purchase'
⑽之-孔塾二：其例如是第-線路圖案 請參考圖ΪΓ i A 及：入凹陷_ Ϊ電導電孔道112於貫孔⑽二凹陷圖案106 ;因主意的是， ，、中^电孔道112 電鍍形成而一體成 線路圖案102。 牙過，1電層104以連接第一 在經由電鍍將導 之步驟中，可材科填人凹陷_家心 匕括先經由化學電鍍將1G6及貫孔108 電材料全面性形成 200903672 υυιιυυο /Jtwf.doc/n 在介電表面1〇4a、貫孔ω8 線路_ Κ)2的局部的表面，;貝2⑽所暴露之第一 接著，、經由電解電鑛將導電材料^成電鍍種子層m。 上，以填滿貫孔⑽來形成導電孔道成f讀種子層m 案1〇6來形成第二線路圖案11〇。 2，並填滿四陷圖 請參考圖m，移除第二線路(10) - 孔塾二: For example, the first line pattern, please refer to the figure ΪΓ i A and: the recess _ Ϊ electrically conductive hole 112 in the through hole (10) two recessed pattern 106; because of the idea, , , ^ ^ electric hole 112 is formed by electroplating and integrated into a line pattern 102. Tooth over, 1 electric layer 104 to connect first in the step of guiding through electroplating, can be filled with depressions _ home heart including first through electroless plating 1G6 and through hole 108 electrical material comprehensive formation 200003672 υυιιυυο / Jtwf .doc/n On the surface of the dielectric surface 1〇4a, the local surface of the through hole ω8 line _ Κ) 2, and the first exposure exposed by the shell 2 (10), the conductive material is electroplated into the seed layer m via electrolytic ore. The second wiring pattern 11 is formed by filling the through holes (10) to form the conductive vias to read the seed layer m. 2, and fill the four traps, please refer to Figure m, remove the second line
C Ο =106㈣分’以平整化·二線路= a。同時，移除電鍍種子層114护、 ，丨電表面 部分，以平整化電鑛種子層114至介:曰圖案106的 :例中’移除第二線路圖案uo之部2 =〇4a。在本實 或研磨。在移除電鍍種子層114之、式可包括蝕刻 分之後，電鑛種子層114將位於介電^ :圖案106的部 案⑽之間、位於介電層104及導電第二線路圖 第一線路圖案1〇2及導電孔道112之間=2之間、位於 別埋之移除人t板1⑻。至:b，介電層1〇4及分 八彡丨电層104之一介電表面1〇4a及相對 面職的第一線路圖案j μ電表 埋式線路結構15〇。 線路圖案11G構成一内 內神^實施例中，此内埋式線路結構150可作為-且者 ===線了’但本發明並^實施： 板可配合後續製程來製作多層線路 尸具有兩層以上之線路圖案的線路板。 圖2八至2D繪示本發明之另—每 結構製铲另貝細例的内埋式線路 王。本貝施例可衣作出-四層線路板，即具有四層 12 200903672 -------Stwf.doc/n 線路圖案的線路板。 請參考圖Μ，首先提供—基板2〇〇、 202、一第二線路圖案2〇4、—楚人 弟一線略圖案 電層208，其中第一線路圖案2〇2 ^層I06及―第二介 在基板200之一第一基板表面2〇如 二電層206配置 覆蓋第一線路圖案202，而第_ & ，且第—介電層206 層208配置在基板200之相對於第路2〇4及第二介電 η Ο 二基板表面2_上，且第二介心m面萬的-第 204。 曰 復盖第二線路圖案 ，本實施例中’基板2〇〇可為 為了笔性連接第—線路圖案202及第-:板。此外， 板200更可具有一導電通道2〇1，发路圖案204,基 第—^路圖案202及第二線路圖案=。牙基板而連接 206,以形^^第26經由f射加'移除局部之第-介電岸 ❿战弟—凹陷圖幸210於馀入 不；丨电層 一介電表面206a卜# π、 、弟電層206之—第 第-貫孔d中上Π成=第-介電層裹之至少： 之局部，复例 Μ貝孔 暴露出第—線路圖荦2〇2 請同樣2Β—線rr。2之-孔塾。 電層208,以带^ μ 、工由田射加工移除局部之第二 之—第二介電2:二凹陷圖案214於第二介電層咖 之至少—第」 ％上’並形成穿過第二介電岸2〇8 路圖素2〇4心:2!6，其中^貫孔加暴露“二^ 請參考圖& H如是弟—線路圖案204之-孔墊。 2c’經由電鐘將導電材料填人第1陷圖 13 200903672 ι/υιινυο ^ / ,^twf.d〇c/n =、第:貫:L212、第二凹陷圖案2Μ及第二貫孔216 以形成一弟二線路圖案218於第〜 、L216, 一導電孔道220於第一貫孔2 H—木10内、一第 於第二凹陷圖案214内、一第、一第四線略圖案222 -内。值得注意的是，第二孔 請—體成形，其中第 二4三線路圖 ηC Ο = 106 (four) minutes ' flattened · two lines = a. At the same time, the electroplated seed layer 114 is removed, and the surface portion of the electroplated seed is leveled to flatten the electric ore seed layer 114 to the 曰 pattern 106: in the example, the portion 2 of the second line pattern uo is removed 2 = 〇 4a. In this case or grinding. After the electroplated seed layer 114 is removed, the electro-deposited seed layer 114 will be located between the portions (10) of the dielectric pattern 106, the dielectric layer 104, and the first line of the conductive second wiring pattern. Between the pattern 1〇2 and the conductive via 112=2, the buried person t board 1(8) is located. To: b, the dielectric layer 1〇4 and the dielectric surface 1〇4a of one of the eight electrical layers 104 and the first line pattern of the opposite side of the circuit. The circuit pattern 11G constitutes an inner inner structure. In the embodiment, the buried circuit structure 150 can be used as - and === line. However, the present invention is implemented: the board can be used in conjunction with subsequent processes to make a multi-layer line with two bodies. A circuit board with a line pattern above the layer. Fig. 2 to Fig. 2D show the other embodiment of the present invention. The Benbee can be made into a four-layer circuit board, that is, a circuit board having four layers of 12 200903672 -------Stwf.doc/n line patterns. Referring to FIG. Μ, firstly, a substrate 2〇〇, 202, a second line pattern 2〇4, and a second line pattern electric layer 208 are provided, wherein the first line pattern 2〇2^ layer I06 and “second” A first substrate surface 2, such as a second electrical layer 206, is disposed on the substrate 200 to cover the first wiring pattern 202, and the first and second dielectric layers 206 are disposed on the substrate 200 opposite to the second surface. 4 and the second dielectric η Ο the second substrate surface 2_, and the second dielectric center m-thousands - 204.曰 Covering the second line pattern, in the embodiment, the substrate 2 can be connected to the first line pattern 202 and the first: board for the pen. In addition, the board 200 further has a conductive path 2〇1, an outgoing pattern 204, a base pattern 202, and a second line pattern=. The tooth substrate is connected to the 206, and the shape is removed by the ^^26th through the f-additional part of the first-dielectric shore ❿ ❿ — 凹陷 凹陷 凹陷 图 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 210 , the first layer of the electric layer 206 - the first through hole d = at least the part of the first dielectric layer wrapped, the second part of the boring hole is exposed to the first line diagram 荦 2 〇 2 Please also 2 Β - Line rr. 2 - hole 塾. The electric layer 208 is removed by a field, and the second portion of the second dielectric 2: the second recess pattern 214 is formed on the second dielectric layer The second dielectric bank 2〇8 road picture 2〇4 heart: 2!6, which ^ hole hole plus exposure "two ^ please refer to the picture & H if the brother - line pattern 204 - hole pad. 2c' via electricity The clock fills the conductive material with the first trap 13 200903672 ι/υιινυο ^ / , ^twf.d〇c/n =, the first: L212, the second recessed pattern 2Μ and the second through hole 216 to form a second brother The circuit pattern 218 is in the first to the L216, and the conductive via 220 is in the first through hole 2 H-wood 10, in the second recess pattern 214, and in the first and fourth line outline patterns 222 -. The second hole is formed by body shaping, wherein the second 4th three-way diagram η
Q 介電層2〇6以連接第一線路圖查孔道220之1穿過第-與第四線路圖案222 一體成;Ί〇2’而第二導電孔道224 -端穿過第二介電層由；中;二導電孔道⑽之 通道加連接第三線路圖案218。—線路圖案204及導電 在本實施例巾，在經由電 圖案21〇、第二凹_ # 214、_ 弟-凹陷 216之步驟中，可先 3孔212及第二貫孔 在第一介電表面、第—;電材料全面性形成 所暴露之第-線路圖案2局到第一貫孔犯 電_ 226,並經由化學形成-第-在第二介電表面2〇8a、第二貫孔電材料全面性形成 所暴露之第二線路圖案204的局部5卿二貫孔216 電鍍種子層228。 刃丨的表面，以形成一第二 接著’經由電解電鍍將導 層上，以填滿第—貫孔212 ^形成^第-電鑛種子 填滿第-凹關案21G來—電孔道220，並 電解電鑛將導電材料形成在第二;218，並經由 滿第二貫孔m來形成第二Π子層细上，以填 孔逼224，並填滿第二凹 14 200903672 …*一 —.Jtwf.doc/n 陷圖案214來形成第四線路圖案222。 Γ ο h请參考圖，移除第三線路圖案218之超出第一凹 陷圖案210的部分’以平整化第三線路圖案218至第一介 =表面206a。在本實施例中，移除第三線路圖案218之部 刀的^式可包括钱刻或研磨。在移除第三線路圖案218之 超出，一凹陷圖案210的部分之後，第一電鍍種子層226 第—介電層206及第三線路圖案218之間、位於第一 I %»層206及第一導電孔道220之間、位於第一線路圖案 202及第一導電孔道220之間。 5月同樣參考圖2D，移除第四線路圖案222之超出第 =凹陷圖案214的部分，以平整化第四線路圖案222至第 w %表面208a。在本實施例中，移除第四線路圖案 之部分的方式可包括蝕刻或研磨。在移除第四線路圖案 222之超出第二凹陷圖案214的部分之後，第二電鍍種^ 層=8位於第二介電層2〇8及第四線路圖案222之^、位 於第二介電層208及第二導電孔道224之間、位於第二線 路圖案204及第二導電孔道224之間。 圖2D之結構為—内埋式線路結構25〇。在本實施例 中，此内埋式線路結構250可作為一具有内埋式線路之四 層線路板，但本發明並不侷限於本實施例來製作四層線路 板，亦可配合後續製程來製作多層線路板，即具有四層以 上之線路圖案的線路板。 综上所述，本發明提供一種内埋式線路結構製程，其 乃是經由雷射加工在介電層上形成凹陷圖案及貫孔，並以 15 200903672 /〇fw£doc/n VO1UJUO “ 電鍍將導電材料填人凹 凹陷圖案内，並同成線路圖案在 明可在介電層之—面製 孔内。因此，本發 導=，上述内埋線路圖==二同， —面的線路圖案。 逆接主’丨电層史另 Ο 雖然本發明已以這些實施例揭露如上，然 發明’任何所屬技術領域中具有通常知識者， 因此本發明之’當可作些許之更動與潤·， 為準。 Μ關當減附之申請專利範圍所界定者 〇 【圖式簡單說明】製程圖认至1崎示本發明之—實施㈣内埋式線路結構 ，2Α至2D繪示本發明之另一實施例的内埋式 結構製程 線路 【主要元件符號說明】 1〇〇 :基板 100a :基板表面 102 :第一線路圖案 104 :介電層 104a:介電表面 106 ··凹陷圖案 108 :貫孔 110 .弟—線路圖案 112:導電孔道 一 114 :電鑛種子層 150 :内埋式線i結構 200 ·'基板 16 200903672 \J\J L i\J\J KJ / / 6twf.doc/n 200a :第一基板表面 212 ： 200b :第二基板表面 214 ： 201 :導電通道 216 ： 202 :第一線路圖案 218 ： 204 :第二線路圖案 220 ： 206 :第一介電層 222 : 206a:第一介電表面 224 ： 208 :第二介電層 226 ： 208a :第二介電表面 228 ： 210 :第一凹陷圖案 250 ： 第一貫孔 第二凹陷圖案 第二貫孔 第三線路圖案 第一導電孔道 第四線路圖案 第二導電孔道 第一電鍍種子層 第二電鍍種子層 内埋式線路結構The Q dielectric layer 2〇6 is formed integrally with the first and fourth wiring patterns 222 by connecting the first wiring pattern trace 220; the second conductive via 224-end passes through the second dielectric layer. The third line pattern 218 is connected to the channel of the second conductive via (10). - the line pattern 204 and the conductive in the embodiment of the towel, in the step of passing the electrical pattern 21 〇, the second concave _ # 214, _ 弟 - recess 216, the first 3 holes 212 and the second through holes in the first dielectric The surface, the first; the electrical material comprehensively forms the exposed first-line pattern 2 to the first through-hole _ 226, and is formed via the chemical-first-on the second dielectric surface 2 〇 8a, the second through hole The electrical material is comprehensively formed into a portion of the exposed second line pattern 204 that is etched into the seed layer 228. The surface of the blade is formed to form a second subsequent 'electrode plating to fill the conductive layer to fill the first through hole 212 ^ to form the first - electric ore seed to fill the first - recessed case 21G - the electrical channel 220, And electrolyzing the ore to form a conductive material in the second; 218, and forming a second layer of the second layer through the second through hole m, to fill the hole 224, and fill the second concave 14 200903672 ... * a - .Jtwf.doc/n traps pattern 214 to form fourth line pattern 222. Referring to the figure, the portion of the third line pattern 218 beyond the first recess pattern 210 is removed to planarize the third line pattern 218 to the first dielectric surface 206a. In the present embodiment, the form of removing the portion of the third line pattern 218 may include money carving or grinding. After removing the portion of the third line pattern 218 beyond the recess pattern 210, the first plating seed layer 226 between the first dielectric layer 206 and the third line pattern 218 is located at the first I % » layer 206 and A conductive via 220 is located between the first trace pattern 202 and the first conductive via 220. Referring also to FIG. 2D in May, the portion of the fourth line pattern 222 that is beyond the = recess pattern 214 is removed to planarize the fourth line pattern 222 to the wth surface 208a. In this embodiment, the manner of removing portions of the fourth line pattern may include etching or grinding. After removing the portion of the fourth line pattern 222 that is beyond the second recess pattern 214, the second plating layer=8 is located at the second dielectric layer 2〇8 and the fourth line pattern 222, and is located at the second dielectric layer. The layer 208 and the second conductive via 224 are located between the second line pattern 204 and the second conductive via 224. The structure of Fig. 2D is a buried circuit structure 25A. In this embodiment, the buried circuit structure 250 can be used as a four-layer circuit board with a buried line. However, the present invention is not limited to the embodiment to fabricate a four-layer circuit board, and can also be used in conjunction with subsequent processes. A multilayer circuit board is produced, that is, a circuit board having a wiring pattern of four or more layers. In summary, the present invention provides a buried wiring structure process in which a recess pattern and a through hole are formed on a dielectric layer by laser processing, and the plating is performed by 15 200903672 /〇fw£doc/n VO1UJUO The conductive material is filled in the recessed recess pattern, and the same line pattern is formed in the hole of the dielectric layer. Therefore, the present invention has the above-mentioned buried circuit pattern==two identical, the surface pattern of the surface </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Μ 。 当 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 减 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制Embedded structure process circuit of the embodiment [Main component symbol description] 1 〇〇: substrate 100a: substrate surface 102: first line pattern 104: dielectric layer 104a: dielectric surface 106 · recessed pattern 108: through hole 110 Brother - Line Pattern 112: Electroporation channel 114: electric ore seed layer 150: buried wire i structure 200 · 'substrate 16 200903672 \J\JL i\J\J KJ / / 6twf.doc/n 200a : first substrate surface 212 : 200b : Second substrate surface 214 : 201 : conductive path 216 : 202 : first line pattern 218 : 204 : second line pattern 220 : 206 : first dielectric layer 222 : 206a : first dielectric surface 224 : 208 : second Dielectric layer 226 : 208a : second dielectric surface 228 : 210 : first recess pattern 250 : first consistent hole second recess pattern second through hole third line pattern first conductive via fourth line pattern second conductive via First plating seed layer second plating seed layer buried wiring structure
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