TW200901371A - Semiconductor devices including interlayer conductive contacts and methods of forming the same - Google Patents

Abstract

In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width.

Description

200901371 ζδΐ /upu IX. Description of the Invention: [Technology Leading to Invention] The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device including an interlayer semiconductor contact window and a method of fabricating the same. [Prior Art]

1 Nowadays, due to the increasing emphasis on the high integration of electronic devices, high-speed, low-power and high-density semiconductor devices are gaining favor. To achieve this goal, it is required to manufacture semiconductor devices based on higher integration and to fabricate components with low resistivity materials. However, as the pattern of components of the manufacturing apparatus is getting smaller and smaller and the spacing between adjacent patterns is getting smaller, the possibility of leakage current flowing between adjacent patterns and components is greatly increased. In order to illustrate this problem, a common group of semiconductor devices is currently used as an example. The first layer is formed by dielectric radiation (4), and the layer is layered on the first interlayer dielectric layer (for example, nitride). ^ A second interlayer dielectric layer is formed on the termination layer. A copper bit line _ is formed in the second layer, and the latter is in contact with the lower: 丨1 contact. The etch stop layer is loosened from the top of the lower first 乂^ Therefore, in the case of forming a copper bit line diagram: in the case where the junction is often more than the interface between the dielectric layers, the etch-stop layer and the first layer termination layer, steel diffusion = copper diffusion. Even if the residual layer is not used The dielectric layer between the second interlayer dielectric layer and the second interlayer dielectric layer is shortened by the semiconductor device by the semiconductor device. This intensifies the phase zA and the (6) element between adjacent bit line patterns. The possibility of leakage current flowing through 200901371, especially the possibility of intermediate diffusion through the copper diffusion between the interface between the dielectric layer and the first interlayer dielectric layer. In addition, with the accumulation degree Increase the relative shortening of the distance between the contact windows of the lower slaughter room, n relative misalignment (mis Alignment ), so that another form of leakage current may occur between the lower contact window and the adjacent line. 发明, SUMMARY OF THE INVENTION The present invention relates to the blank conductor method, and the half (four) device is more integrated. High and does not increase „ J^,^T^^^^(contact Plug)t^ , the possibility of flow. The possibility of leakage current caused by any diffusion of adjacent interconnects can be increased:: The distance between the plug and the adjacent interconnect line to reduce the leakage current therebetween can also achieve the above purpose. 攸Reducing the lower package; the first part of the semiconductor device that penetrates the first opening of the first insulating layer - the upper portion of the first conductor pattern of the conductance, ,, the first sees a recess 2; the height of the lower contact window region; the top surface of the first guide of the second width with respect to the second conductor pattern The width is smaller than the first width. The lower portion of the a-body pattern, the second 200901371 may include a conductor barrier layer on the upper portion of the first conductor pattern. The semiconductor device may further include a second insulating layer on the first insulating layer, wherein the second conductor The pattern is located in the second opening that penetrates the second insulating layer. The conductor device may further include an insulated linear spacer on the sidewall of the second opening, wherein the sum of the width of the insulated linear spacer and the width of the bottom of the second opening is less than or equal to the first width. An insulated linear spacer on the sidewall of the second opening, wherein a sum of a width of the insulated linear spacer and a width of the second opening bottom is greater than the first width. The _σ semiconductor device may further include a third conductor on the first insulating layer The pattern 'the third conductor pattern is adjacent to the second conductor pattern in the horizontal direction with respect to the lower first conductor pattern. The length of the leakage current path between the first conductor pattern and the third conductor pattern along the upper boundary of the first insulating layer is greater than The horizontal distance between the two-body pattern and the third conductor pattern. The semiconductor device may further include a first conductor pattern on the first insulating layer, the third conductor pattern is drawn in a horizontal direction with respect to the lower first conductor pattern, wherein the second conductor pattern bottom and the third conductor pattern 2 are along The length of the diffusion path of the upper boundary of the insulating layer is greater than the horizontal distance between the first ν body pattern and the third conductor pattern. There may be a _stop layer between the insulating layer and the second insulating layer. - The first conductor pattern in the thin body may include - the phase plug of the lower contact window region of the following material extending in the horizontal direction of the semiconductor device; and the second conductor pattern may include the following objects ί The lower jaw-conductor pattern extends in the horizontal direction of the semiconductor I. 200901371 2δΐ/υρι! The inner wiring of the exhibition; and the conductor plug. The semiconductor device may further include sidewall spacers on the first open sidewall of the top surface of the first conductor pattern. The lower contact window region can include at least one of the following: a substrate, a doped region of the substrate, an epitaxial layer, a gate of the transistor, a germanide region, and a conductor contact. The semiconductor device may be, for example, a non-volatile memory device or a volatile δ memory device such as DRAM, SRAM, reverse flash memory, inverse or flash memory, MRAM, RRAM And similar. In another aspect, a semiconductor device includes: a first insulating layer on a lower contact window region of the semiconductor device, the first insulating layer having a top surface; and a bit = a first through the first opening of the first insulating layer a conductor pattern, which is a first portion of the first conductor pattern of the first view; a second edge layer on the first insulating layer; and a second conductor that penetrates the second insulating layer and is in contact with the top surface of the first conductor pattern # The pattern is a lower portion of the second conductor pattern of the second width, the second visibility is less than the first width; and the third conductor pattern that penetrates the second insulating layer on the first insulating layer is opposite to the third conductor pattern a conductor pattern is adjacent to the second conductor pattern in a horizontal direction, wherein a length of the diffusion path between the bottom of the second conductor pattern and the bottom of the second conductor pattern along the upper boundary of the first insulating layer is greater than the second conductor bribe and the third guide The horizontal distance between the two. The top surface of the first conductor pattern may be recessed with respect to the top of the first insulating layer such that the top surface of the first conductor pattern is smaller than the lower contact window region of the first conductor pattern with respect to the top surface of the first insulating layer The height of 200901371 degrees. ^ The upper portion of a conductor pattern may comprise a conductor barrier layer. The first conductor pattern may be located in the second opening that penetrates the second insulating layer. The shape m', the r body may further comprise an insulated wire spring wall on the sidewall of the second opening, wherein the sum of the width of the insulated linear spacer and the width of the bottom of the second opening is less than or equal to the first width. The body skirting may further comprise an insulated wire & wall on the side wall of the second opening, and wherein the sum of the width of the insulated linear spacer and the width of the bottom of the second opening is greater than the first width. The length of the leakage current path along the first insulating layer between the first conductor pattern and the third conductor pattern may be greater than the horizontal distance between the first conductor pattern and the third conductor pattern. An etch stop layer may be present between the first insulating layer and the second insulating layer. In a semiconductor device, the first conductor pattern may include: a lower portion of the lower contact window region extending in a horizontal direction of the semiconductor device = a wiring; and a conductor plug; and the second conductor pattern includes the following -. Relative to the lower first conductor - along the inner conductor of the semi-conducting; and the conductor plug. The semiconductor device may further include sidewall spacers on the first open sidewall of the top surface of the first conductor pattern. The lower contact window region may include at least one of the following: a substrate, a doped region of the substrate, a crystal layer, a gate of the transistor, and a conductor contact. In another aspect, the method for manufacturing a semiconductor device includes: providing a top surface on a lower contact window region of a semi-conductor 200901371 Z&l/upu device; and forming a second edge layer in the first insulating layer Μ first opening to expose the lower connection=£ domain, and providing a width of the first conductor pattern in FIG. 4, and the top surface of the first conductor pattern is indented relative to the first to make the first conductor pattern a height of the top surface relative to the /, lower contact window region sweeping the height of the first insulating surface relative to the o 2 window; and providing a second conductor pattern in contact with the top surface of the first conductor pattern, the lower portion of the second conductor pattern The second wide sound, the 5 touch width is smaller than the first width. Further, the second layer. The method may further include providing a conductor barrier on the upper portion of the conductor pattern to provide the second conductor pattern, including: the first insulating layer a second insulating layer; forming a second opening in the second insulating layer to 4 = a top surface of the conductor pattern; and providing a second conductor pattern in contact with the second top surface in the second opening. The conductor pattern method may further comprise Formed on the sidewall of the second opening The insulating wall ′ wherein the sum of the width of the insulated linear spacer and the second opening σ bottom=degree is less than or equal to the first width. A rabbit method may further comprise forming an insulated wire wall on the second open π sidewall, wherein the insulated wire The sum of the width of the spacer and the bottom of the second opening is greater than the first width. The method may further include: providing the third conductor with a third conductor pattern on the first insulating layer - the lower conductor pattern is horizontally The second conductor pattern 'where the first conductor pattern and the third conductor pattern are along the 11th 200901371 - the length of the insulating material scale diameter is larger than the third conductor. The method f can include: on the first insulating layer Forming a third conductor pattern 荦, the third conductor f is diffused with respect to the lower first conductor pattern in the horizontal direction, wherein the bottom of the second conductor pattern and the bottom of the third conductor pattern Pa/α, the upper boundary of the edge layer The length of the path is greater than the horizontal distance between the second conductive pattern and the third conductive pattern. The body provides the H material before the first insulating layer and the first conductor pattern & the _ termination layer, wherein ^ the first insulating layer = First - open ^ Forming the first-conductor pattern in the first "" prior to providing the engraved termination layer. The method may further include providing a termination layer on the first insulating reed before providing the second insulating layer, wherein in the first insulating layer Forming the first opening 2, opening in the first opening, forming the first conductor pattern and then providing the money to terminate the layer row 0, and providing the first conductor pattern may further comprise one of the following steps: forming the first part of the method And extending the top portion relative to the lower contact window region in a half direction, the horizontal direction of the device to form a first inner wiring pattern; and, for the conductor plug; and the step of providing the second conductor pattern may further comprise one of the following two steps Providing an inner wire extending in a horizontal direction of the semiconductor device relative to the lower first conductor pattern; and providing a conductor plug. The method can include providing sidewall spacers on the first open wall on the top surface of the first conductor pattern. The lower contact window region includes at least one of the following: a substrate, 12 200901371 ^.oi / v/uii., and a region, an epitaxial layer, a gate of the transistor, a germanide region, and an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is embodied in other forms, and is not necessarily limited to the embodiments described below. Under the circumstance, the first and second words are used to describe each component, but it should not be restricted by such words. Such words are used to distinguish each jm element from the second element. Similarly, the second = 奎^ can be named as the "element" without departing from the scope of the invention. This is to say that d "and/or" is intended to include any or all of the associated enumerated items, or combinations thereof. 2 Solution 'When a component is "on another component" or "connected to" an i component, it may be "directly on", or a straight component. 3U is connected to another component, and there may be a middle element connected to it. , or on: another element or "directly connected to other words used to describe the relationship between the elements can be similar, > 醢 ~, "between::" and "directly at ... to, = The present invention is located on another element; there is an intermediate element, or a possible phase between the two = 13 200901371 The terminology used in the description is for the purpose of describing the particular embodiments of the invention The singular forms "a", "an", "the" It is also to be understood that the subject matter of the specification, and the s The existence of f, components, components and/or combinations thereof. (d) In accordance with the present invention - the plane of the turn-around of the real estate: Hao connected to its lower interlayer conductor plug (such as the interlayer contact plug) Ι-Γ intercepted ffi 1A is a cross-section according to the invention - an embodiment A cross-sectional view of the line only. Fig. 2c shows a second embodiment of the method of fabricating a semiconductor device according to the invention - an isolation region 102 is provided in the semiconductor substrate 100 as shown in Figs. 1B and 2A. The area between the isolation areas 1〇2. The contact window region includes two: 3, a heterogeneous region, a worm layer, a transistor, a stellite & field, and a conductor contact window. In the present invention, the connection is made, but in the embodiment of the present invention, 3 = the gate of the crystal, 汲. The terminal of the electricity day, such as electricity, the source, and the top surface thereof is a ruthenium region. As shown in Figure 2Α, the first layer is above. In the embodiment - the first interlayer insulation; = the lower structure of the interlayer insulation layer 108 using the conventional manufacturing method i: 1 = the first! 200901371, a first opening nGa is formed in the insulating layer 108, from which the lower main region 104 is exposed, in this example, the top of the first opening or (_

WU, as shown in Figure 2B below. It should be noted that the opening formed in the opening and the resulting structural material are swayed, and the sloping side wall naturally formed by the money engraving method. A contact barrier layer (Gptk) barrier layer is formed in the contact opening to prevent metal ions generated in the conductor pattern to be formed in the first opening 110a from diffusing into the interlayer insulating layer 108. A conductor layer is added to the resultant structure to fill the first opening u〇a and contact the lower main pure 104. In the case of firing, the conductor layer comprises a layer of a layer deposited by physical vapor deposition (pVD), chemical vapor deposition (CVD) or electroless plating (eiectr〇ies Splating) according to a conventional manufacturing method. The conductor layer is then planarized to form a first conductor pattern 112a in the first opening u?a. The conductor layer can be made of a conductor material of a high integration method (including a low-resistivity metal material such as A1 or Cu), and can include a wetting layer or a barrier layer such as Τί, Τ &, Μο, ΓΠχί^ , Ί^Νγ, Τΰί2:17,

TixZryNz, NbxNy, ZrxNy, WxNy, VxNy, HfkNy, MoxNy,

RexNy and TixSiyNz. As shown in Fig. 2B, the top of the first conductor pattern 112a is recessed in the first opening 110a. The resulting recess can be formed by a chemical mechanical polishing method (CMP), a back-to-back method, or a dry etching method according to a conventional manufacturing method. When CMp is used, a slurry may be selected to remove the top of the first conductor pattern i12a (e.g., a tungsten layer) without removing or minimally removing the top of the first interlayer insulating layer 108. The top surface of the obtained recessed first conductor pattern 113a 15 200901371 ^οι /υριι is positioned lower than the top surface of the first interlayer insulating layer 108, and thus is recessed in the first opening 110a. Also, the width of the recessed first conductor pattern U3a is equal to or slightly smaller than the width W1a of the first opening. A selective barrier layer 114 may be provided on the resulting recessed first conductor pattern 113a. The barrier layer 114 acts as a diffusion barrier and blocks the reaction between the bulk material of the recessed first conductor pattern 113a and the conductor pattern I% to be deposited thereon (see Fig. 2C). For example, the barrier layer 114 may include coating using cvd, atomic layer deposition (ALD), or electroless plating.

CoWP'CoP and CoB. When a selective barrier layer pattern is used, the top surface of the resulting barrier layer 114 is positioned lower than the top surface of the first interlayer insulating layer (10), and the first conductor pattern of the combined recess is received in the first opening 110a. The haf can be coated with a selective termination layer ii6 on the top surface of the resulting structure. The money layer 116 can be conformally coated so that it is coated with the upper portion of the first opening ma s.iT ^. In various embodiments, the side termination layer can include and/or be a single layer or multiple layers. The second etch 2 is selected to be applied to the second layer of the resulting structure. When the material of the first interlayer insulating layer (10) stops the interlayer insulating layer 118, the remaining layer 118 is not required. For example, t, the first = structure is coated with the second interlayer _ 〇.rrkU ° interlayer insulating layer 108 may include oxidized stone eve _

SiCOH, and preferably includes a low dielectric dielectric interference material 4 minus adjacent maps ^ one layer, recording layer 118 fine f know the manufacturing method ^ 200901371.

The case of 'opening the second interlayer insulating layer 118' in this case 'the second opening; the second = two openings 120a* - the conductor pattern singular (10) two: 12 = the lower concave selective resistance _ m In the top of the top portion 113a, in the example, the second of the second openings is formed by the width Wla of the lower first opening. No.: On the other side of the adjacent 12Qb dew (four) edge top surface. A selective barrier layer (not shown) may be formed in the opening of the contact window to block

In the second opening 12Ga, (4), n ions (for example, copper ions) may be formed in the second phase insulating layer of the county, and the selective barrier layer may include a single layer or a plurality of layers of blue, and TiN. As shown in Fig. 2C, a selective metal seed layer (e.g., a copper seed layer) is conformally applied to the resulting structure, such as a second opening 120a, 120b, by a PVD process. Next, a low resistance conductor material 125 is applied to fill the second openings 120a, 120b. For example, the conductor material 125 can comprise electroplated copper or supercritical-fluidcopper coated using conventional manufacturing techniques. The coated conductor fill material is then separated into individual conductor patterns 125a, 125b (see Figure IB) using a CMP process to form, for example, individual bit lines of the device. The resulting device has a recessed first conductor pattern or recessed first conductor pattern/barrier layer U3a/114 having a width Wla as shown in Fig. 1B. The embodiments in which the first conductor pattern 113a or the recessed first conductor pattern /P and the barrier layer 113a/114 are recessed are collectively referred to as "recessed first conductor pattern 113a" for the present specification. The top surface of the recessed first conductor pattern 113a is lower than the top surface of the first layer 17 200901371 ζ, οι / υριι between the insulating layers 108. The bottom of the first of the second conductor patterns is lower than the first interlayer insulation on the top surface of the concave pattern a: a conductor pattern is formed. Moreover, the first i2=J or the bottom of the second conductor pattern is recessed below the f-conductor _ ^ °

The width of the part is Wla. The first one of the second conductor patterns of the adjacent second coffee patterns in the second conductor pattern is spaced apart from the second sib in the horizontal direction, and the second adjacent one of the second conductor patterns is 125b The distance from the concave-conductor pattern 113a in the horizontal direction is the distance - the distance si1 is the width WlaA of the depressed first conductor pattern 113a and the width W2a' of the first 125a of the second conductor pattern.仏 is smaller than the second distance Sib. As described above, in the contact window configuration of the embodiment, the diffusion path length (diffiision path lengtti) DL between the adjacent first and second of the second conductor patterns 125a, 125b is greater than the second Horizontal distance Slb. The reason is that the diffusion path length includes not only the horizontal distance between the first and the first ones 125a, 125b in the second conductor pattern, but also the first 125a in the second conductor pattern (and thus the contact recess) The vertical distance of the top surface of a conductor pattern n3a. The indentation distance effectively increases the length of the diffusion path between the first and second 125a, 125b of the second conductor pattern. The large diffusion path length DL reduces the leakage current effect between the first and second 125a, 125b of the second conductor pattern to reduce the associated constraints in the design process to further increase the integration of the resulting device. Meanwhile, in the contact window configuration of the present embodiment, the leakage current path length between the depressed first guide 18 200901371 ΔΟί /Wpil body pattern 113a and the adjacent second 125b of the second conductor pattern is larger than the recessed portion The horizontal distance between the one conductor pattern 113a and the second 125b adjacent to the second conductor pattern, or the distance Sla. The reason for this is that the leakage current path length includes not only the horizontal distance between the recessed first conductor pattern and the adjacent second conductor pattern 125b but also the vertical distance of the first conductor pattern 113a trapped in the first opening n〇a. This will effectively increase the leakage current path length between the first conductor pattern 113a and the second adjacent 125b of the second conductor pattern, thereby also reducing the relevant constraints in the design process, so as to further improve the integration of the resulting device. . In the embodiments described herein, the word "first conductor pattern" includes both plug contact windows and line contact windows. The word "second conductor pattern" ^ includes plug contact windows and line contact windows. For example, when the ^- or the second conductor pattern includes the wire-contact window, the bit line extending in the horizontal direction is disposed on the device. In the embodiment, the conductor may be in the first interlayer insulating layer 1G8. The formation of t2, the former 'on the surface of the lower first insulating layer 108 on the lower side will be the selective side termination layer 116 shown in Fig. 1. Then, as shown in the figure (4) and penetrate the first: (10)_conductor The layer, as described above, is opened through the etch stop layer u 仃 千 千, to form the body pattern mountain a. _ interlayer insulating layer 1 〇 8 of the first conductor pattern, so that the resulting first - can be Touching the first surface 19 200901371 barrier layer 114 ° then 'by coating the second interlayer insulating layer 118 and the second conductive material layer 125 and then patterning the layer 125 (as described above in connection with Figures 2B and 2C), The crucible can be completed. In this embodiment, the side of the top surface of the recessed first conductor pattern 113a and the There is no selective etch stop layer 116 on the sidewall of the upper portion of the opening u〇a between the recessed first conductor pattern 113a. Conversely, the material of the first interlayer insulating layer 118 fills the first opening 11 位于 in the recess first Figure 3 is a cross-sectional view of the embodiment of Figure 1 taken along a section line in accordance with another embodiment of the present invention. This embodiment is generally similar to the above Figure 1 and Figure 2 - Figure 2C The embodiment is different in that a linear spacer 16 is present on the sidewall of the second opening 120a, 120b. In this embodiment, after the second opening 12A is formed, the second opening 12 is formed in the second opening. A linear spacer 16 is provided on the sidewalls of 〇a, 120b. In one embodiment, conformal deposition may be performed using an insulating material such as Si〇2 or SiN, followed by etching to expose the top surface of the recessed first conductor pattern i13a The linear spacer 160 is formed in this manner. When the linear spacer 16 is present in the second openings 120a, 120b, the width W2a of the obtained second conductor patterns 125a', 125b1 is compared with FIG. 1B and FIG. 2A - the embodiment described in Figure 2C can One step reduction. This can increase the critical distance, that is, the first horizontal distance Sla, and the second horizontal distance Sib', thereby effectively increasing the adjacent first and second 125a' in the second conductor pattern. a diffusion path length DL between 125b' (see FIG. 1β), and effectively increasing the length of the leakage current path between the depressed first conductor pattern l13a and the second adjacent 125b' of the second conductor pattern, thereby enhancing Advantages of the foregoing embodiments of the present invention. 20 200901371 δοι/υρη FIG. 4 is a cross-sectional view of the embodiment of FIG. 1 taken along section line w according to another embodiment of the present invention. This embodiment is generally similar to the embodiment described above in connection with FIG. 3, except that this embodiment illustrates the second opening before the formation of the linear spacers ι6〇 on the sidewalls of the second openings 120a', 120b' The initial width Wg may be greater than or equal to the width W1a of the lower first conductor pattern 113a. In this embodiment, after the second opening i2〇a is formed, a linear spacer 160 is provided on the sidewall of the second opening in the second opening 120a, 120b, the latter being relatively wider than the embodiment of FIG. The linear spacer wall wo. As described above, the conformal deposition may be performed by an insulating material such as Si 2 or SiN, and then etched to expose the top surface of the recessed first conductor pattern 丨丨 3 a to form the linear spacer 160 in this manner. When the linear spacers 160' are present in the second openings l2a, 12b, the width of the resulting second conductor patterns 125a, i25b is reduced (as described above in connection with Fig. 3), thereby achieving the aforementioned advantages. Figure 5 is a cross-sectional view of the embodiment of Figure 1A taken along section line I, in accordance with another embodiment of the present invention. This embodiment is generally similar to the embodiment described above in connection with Figures 1B and 2A-2C, with the difference that sidewall spacers 150 are present on the sidewalls of the first opening 11a. In this embodiment, the sidewall spacers 150 are provided on the top surface of the first opening 丨 10a on the top surface of the lower first conductive pattern 113a after forming the recessed first conductor pattern 113a. In an embodiment, an insulating material may be used for deposition, and then anisotropic etching is performed to control the width of the resulting spacer and expose the top surface of the recessed first conductor pattern 11a, thereby forming a sidewall gap. Wall 150. When the sidewall spacer 15$ is present in the first opening 1 i〇a, a misalignment between the first 125a of the second conductor pattern and the 21st 200901371-conductor pattern 113a is allowed in the manufacturing process. For example, the first 125a in the second conductor pattern is too close to the left side of the first conductor pattern U3a, or the right edge 'the sidewall spacer 15G can ensure the 125a and the first conductor pattern in the second conductor pattern. The actual contact point of the coffee is located on the top surface of the first conductor pattern 113a at a distance from the outer edge of the first conductor pattern. Thereby the advantages of the invention can be achieved. 6A is a top plan view of a non-volatile memory semiconductor device including a phase (4) in the form of a bit line pattern that is connected to a lower interlayer conductor plug (eg, an interlayer contact plug), in accordance with an embodiment of the present invention. line. Figure

f is a cross-sectional view of the apparatus of Fig. 6A along section line M. Figure 6C is a cross-sectional view of the apparatus of Figure 6A taken along section line n_im in accordance with another embodiment of the present invention. Fig. 61) is a cross-sectional view taken along line 冚-冚 of Fig. 6A taken along the section line. 7A and 7E' are cross-sectional views showing a method of manufacturing the apparatus of Figs. 6A to 6D taken along a section line ΙΙ-ΙΓ according to an embodiment of the present invention, and Fig. 7A " - Fig. 7E'' is along a section line A cross-sectional view of a method of manufacturing the apparatus of Figs. 6A-6D taken by ΠΙ-ΙΙΓ. In the embodiment of Figures 6A-6D, the non-volatile memory device includes first and second main pures 2a, 204b formed on a semiconductor substrate. The first and second active regions 2〇4a, 204b are defined by the isolation region 202 (see FIGS. 7A' and 7A"). The first and second first conductor patterns 21 are separated by 21, and become transparent. The first openings 2Ha, 214b of the first and second interlayer insulating layers 2, 8 and 212 are in contact with the doped regions 206d of the first and second active regions 2a, 4a, 2 and 4b (see FIG. 7B, and Figure 7B"). First and second second guides 22 200901371 'The top surface width of the upper/twist 11 body patterns 218a, 218b is Wlb and is recessed with respect to the top surface of the second insulating layer 212 (see Fig. %, and Fig. 7c) In the example, the top surfaces of the first and second first conductor patterns 218a, 218b have selective barrier layers 22a, 22b. The first and second second conductor patterns 228a, 228b are The foregoing manner is formed to penetrate the openings 226a, 226b in the third interlayer insulating layer μ# and is in contact with the first and second first conductor patterns 218a, 218b (see FIG. 7D' and FIG. 7D"). A selective etch stop layer 222 is provided on the top surface of the insulating layer 2i2 ( (see Fig. 7A, and Fig. 7A). Word lines WL, ground selection lines (gr_d lines) GSL, common source lines (c〇mm〇ns〇urce iines) c% 2i〇 and string select lines (SSL) at the device level Stretch in the direction. As is conventional in the configuration of existing non-volatile memory devices, word line WL includes a channel layer, a charge storage layer, and a blocking insulating layer (between the substrate and the gate). The first and second conductor patterns 228a, 228b in this example include bit lines extending in a second horizontal direction of the device. Although the above figures [enclose the NAND-type non-volatile memory device, the same principle applies to the NOR-type non-volatile memory device and other non-volatile memory devices. Device configuration. As in the above example, the visibility W2b of the first and second second conductor patterns 228a, 228b is smaller than the visibility Wlb of the first and second first conductor patterns 218a, 218b. Therefore, the length of the diffusion path between the adjacent first and second second conductor patterns 228a, 228b is greater than the horizontal distance S2b between the patterns 228a, 228b. Similarly, the leakage current path length between the first 218a of the first conductor pattern and the second 228b of the second conductor pattern is greater than the horizontal distance Sib of the pattern 218a, 23 200901371 ^.οι /υμη 2 . In this way, the features and advantages of the embodiments described in this embodiment. In the embodiment of the circle 6C, the above-mentioned advantages are achieved by providing the sidewall spacers 25〇(10) at the upper portion of the first-opening π 2Ha, 214b according to the embodiment of Fig. 5 described above. 8A is a top plan view of a volatile memory device according to an embodiment of the present invention, including adjacent layers connected to the lower interlayer conductor; interlayer contact plugs, in the form of a bit line pattern. Section of the apparatus of Figure 8A taken at section line W: a cross-sectional view of the apparatus of Figure 8A taken along section line VV. Figure = Sectional view of the device taken along section line VI-VI. Figure 卯 is a cross-sectional view of the apparatus of Figure 8A taken along section V-V, respectively, in accordance with another embodiment of the present invention. ViV and FIG. 9A - FIG. 9C' are manufacturing method of the device according to an embodiment IV of the present invention. FIG. 9A - FIG. 9C" is the drawing of FIG. 8A - FIG. 8f taken along the section and line v_v'. A cross-sectional view of the method, and Fig. 9A, Fig., Fig. 9A, is a cross-sectional view showing a method of manufacturing the apparatus of Figs. 8A to 8F taken along the section line. In the embodiment of FIG. 8A to FIG. 8F, the volatile memory includes the first and second and second active regions 3〇4a, 3 formed in the semiconductor substrate 3, which are hidden by the isolation region 302 (see Figure 9A, - Figure 9A, "). On the resulting structure =ra6, 'i defines doping "& between the idler line structure 3〇6 on the active region. In the first and second active regions 304a 24, 200901371. The bit line pads 310a, 310b are formed on 304b, and are brought into contact with the dummy regions 308a, 308b of the active regions 304a, 304b (see FIG. 9B1 - FIG. 9 Β · Π). First and second The extending directions of the one conductor pattern 318a, 318b penetrate the first openings 316a, 316b formed in the first interlayer insulating layer 314, and are in contact with the lower bit line pads 310a, 310b. The first and second first conductor patterns The top surface width of 318&, 318b is Wlc, and it is recessed with respect to the top surface of the first interlayer insulating layer 314 (see Fig. 9C, Fig. 9C"). In this example, the first

And the top surface of the second first conductor patterns 318a, 318b includes selective barrier layers 321a, 321b. The first and second second conductor patterns are formed to pass through, and the second interlayer insulating layer 324 is in contact with the first and first conductor patterns 318a, 318b, respectively. A selective etch stop layer 322 is provided on the top surface of the second interlayer insulating layer 14 . Cover layers 330a, 330b are provided on the first and second second conductors _ 328a. The storage node contact window (st0, etc.) is passed through the second interlayer insulating layer 324 and the first interlayer insulating layer 3i4, and is in contact with the blood. A lower portion of the resulting structure is then placed in contact with the upper portion of the storage node contact window 336. Forming a dielectric layer on the portion and forming an upper extension GU on the resulting structure, and in the first horizontal direction of the resulting device, 328 two people, the first and second second conductor patterns, the upper portion thereof The two lines in the horizontal direction are extended. The D-type volatile memory device is listed in the full-text diagram. However, the phase 25 200901371, the same principle applies to other volatile memory device configurations. Similar to the above example The width W2c of the first and second second conductor patterns 328a, 328b is smaller than the width Wlc of the first and second first conductor patterns 320a, 320b. Therefore, between the adjacent first and second second conductor patterns 328a, 328b The diffusion path length is greater than the horizontal distance S2c between the patterns 328a, 328b. Similarly, the leakage current path length between the first one of the first conductor patterns 318a and the second one of the second conductor patterns is greater than between the patterns 318a, 328b The horizontal distance Sic. In this way, the present embodiment can realize the features and advantages of the foregoing embodiments. In the embodiment of FIG. 8E and FIG. 8F, in the manner of the foregoing FIG. 5, the linear spacer is used in the first form. Openings 316a, 316b The upper portion provides a sidewall spacer 350 to achieve the aforementioned advantages. Figure 10 is a block diagram of a memory system including memory devices using interlayer conductor patterns in accordance with various embodiments of the present invention. Memory system 400 includes generating instructions And the address controller (c〇mmand and address Signais) C/A memory controller 4〇2 and the memory module 404 including a plurality of memory devices 406. The memory module 404 receives instructions and addresses from the memory controller 402. Signal C/A, and correspondingly store data I/O to at least one memory device 4〇6 and retrieve data DATA I/O from at least one memory. Each memory device includes a plurality of data contacts. The clock unit and the short code H, the latter receives the command and the address signal 'and generates the money and the money to access the data and read the light-and-addressable key unit for access. Each of the memory The components (including the controller moving, the memory module tearing and tapping 26 20090137; the memory device 406) can use the interlayer conductor pattern disclosed in the present specification, and the embodiments of the present invention disclosed in the present specification can be used. Applicable to a variety of conductors, such as one of the forwarding device or one of the volatile memory, such as DRAM, SRAM, reverse flash memory, reverse or flash memory, PRAM, MRAM, RRA1V [and The present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the invention, and any skilled person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of the appended claims. 〃 [Simple Description of the Drawings] FIG. 1A is an example of a section taken along section line 14 according to an embodiment of the present invention. Cutaway view. 2A-2C are cross-sectional views of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. , ,

Figure 3 is a cross-sectional view of the embodiment of Figure 1 taken along section line in accordance with another embodiment of the present invention. Figure 4 is a cross-sectional view of the embodiment of Figure 1 taken along a section line in accordance with another embodiment of the present invention. Figure 5 is a cross-sectional view of the embodiment of Figure 1 taken along section line 14 in accordance with another embodiment of the present invention. 6A is a top plan view of a non-volatile memory semiconductor device including adjacent regions in the form of a bit line pattern coupled to a lower interlayer conductor plug (eg, an interlayer contact plug) in accordance with an embodiment of the present invention. Connection ^ 27 200901371 is a cross-sectional view of the device of Figure 6A taken along section line 11_11. Figure 叱 is a cross-sectional view of the apparatus of Figure 6A taken along section line ΙΙ-ΙΓ in accordance with another embodiment of the present invention. Figure 6D is a cross-sectional view of the device of Figure 6 taken along section line ΙΙΙ-ΙΙΓ. Figure 7A - Figure 7A is a cross-sectional view of the apparatus of Figure 6A to Figure 6D taken along section line π-ιγ, and Figure 7A, '- Figure 7E" is along the section, in accordance with an embodiment of the present invention. A cross-sectional view of the manufacturing method of the device of Figs. 6A to 6D taken in line ΙΙΙ-ΙΙΓ. FIG. 8A is a top plan view of a volatile memory semiconductor 2 including a neighboring conductor profile in the form of a bit line pattern, such as a layer: contact plug, in accordance with an embodiment of the present invention. Line _, section of the device after interception = ί section line V, taken as a sectional view of the apparatus of Fig. 8A. Fig. 8 is a cross-sectional view of the device of Fig. 8. V and V_V screenshots 9A1 - Fig. 9e is a sectional view of the manufacturing method according to the present invention, FIG. 8A_ffl taken along line hatching FIG. 9A, and FIG. 9C" is a cross-sectional view along the surface line v_v. : Figure 9A, ", Figure 8 2 2 Figure 8F of the Agricultural VI-vi' cut: Figure -, the device of the L method: the face line Figure 10 is a memory to find the structure of the block 1 view. According to various embodiments of the present invention, the memory of the interlayer contact window is used to contain the [main component symbol description] ~ body device. 28 200901371 ζδΐ/υρη 100 : substrate 102 : isolation region 104 : active region 106 : impurity region 108 : first interlayer insulating layer 110 a : first opening 112 a : first conductor pattern 113 a : first conductor pattern 114 : barrier layer 116: money stop layer 118: second interlayer insulating layer 120a, 120b, 120a, 120b': second opening 125: conductor material 125a: second conductor pattern 125b: second conductor pattern 125a', 125b': second Conductor pattern 150: sidewall spacer 160: linear spacer 160': linear spacer 200: substrate 202: isolation region 204a first active region 204b second active region 206d doped region 29 200901371 208: first interlayer insulation Layer 210: common source line 212: second interlayer insulating layer 214a, 214b: first opening 218a: first conductor pattern 218b: first conductor pattern 220a, 220b: barrier layer 222: etch stop layer 224: third layer Insulating layers 226a, 228a: openings 228a, 228b: second conductor pattern 250: sidewall spacers 300: substrate 302. isolation regions 304a, 304b: active regions 306: gate line structures G 308a, 308b: doped regions 310a, 310b: bit line liner 314: first interlayer insulation 316a, 316b: first openings 318a, 318b: first conductor patterns 321a, 321b: barrier layer 322: etch stop layer 324: second interlayer insulating layer 30 200901371; 328a, 328b: second conductor patterns 330a, 330b: covered Layer 336: storage node contact window 338: lower electrode structure 340: capacitor dielectric layer 342: upper electrode structure 350: sidewall spacer 400: memory system '402: controller 404: memory module 406: memory device DL: diffusion Path length Ι-Γ : section line ΙΙ-ΙΓ : section line ΙΙΙ-ΙΙΓ : section line IV-IV': section line (V-V': section line vi-vr: section line GL1, GL2: transistor gate line GSL: ground selection line Sla: first distance Sla': first horizontal distance Sib': second horizontal distance Sib: second distance 31 200901371 Z-Ol /υριι S2a: second distance S2b: horizontal distance S2c: horizontal distance SSL : string selection line

Wla, W2a, W2a': width

Wlb, W2b, Wlc, W2c: Width

Wg: initial width WL: word line C/A: command and address signal 32

Claims (1)

20090137L X X. Patent Application Range: 1. A semiconductor device comprising: an edge layer of a lower contact window region of the semiconductor device, the first insulating layer having a top surface; a first opening pattern of the insulating layer, the upper portion of the first conductor pattern is a first treasure, and a top surface of the first conductor conductor pattern is opposite to the first insulating layer; a top surface of a conductor pattern; a height of the lower contact window region thereof; and a second conductor pattern in contact with the top surface of the I body pattern The second width is less than the first width. The semiconductor device described in the first item, wherein the upper portion of the conductor pattern includes a conductor barrier layer. 3. The semiconductor package of claim i, further comprising a second insulating layer on the first insulating layer and wherein the second conductive pattern is located in the second insulating layer Two openings. 4. The semiconductor device according to claim 4, wherein the semiconductor device further comprises an insulated line between the sidewalls of the second opening, and a width of the gap between the JL and the bottom of the second opening. The sum of the widths is less than or equal to the first width. 5. The semiconductor device of claim 3, further comprising an insulated linear gap on the sidewall of the second opening, and wherein the width of the 33 200901371 and the width of the bottom of the opening: The semiconductor device according to claim 3, wherein the third conductor pattern on the first insulating layer is read by the third g pair «lower-conductor_ horizontal direction: Garden case, And a length of a leakage current path between the first conductor pattern and the third conductor pattern along an upper boundary of the first insulating layer is greater than a distance between the first conductor pattern and the third conductor pattern Horizontal distance. The semiconductor device of claim 3, further comprising a third conductor pattern on the first insulating layer, the third conductor pattern being horizontally opposite to the lower first conductor pattern Adjacent to the second conductor pattern, a length of a diffusion path between a bottom of the second conductor pattern and a bottom of the third conductor pattern along an upper boundary of the first insulating layer is greater than a length of the second conductor pattern The horizontal distance between the third conductor patterns. 8. The semiconductor device of claim 3, further comprising an etch stop layer between the first insulating layer and the second insulating layer. a semiconductor device: wherein the first conductor pattern comprises one of: an interconnect extending in a horizontal direction of the lower contact window region along a horizontal direction of the semiconductor device; and a conductor plug; and wherein the second The conductor pattern includes one of the following: opposite the 34 200901371, the lower first conductor pattern along the semi-wire, and the conductor plug. In the horizontal direction of the conductor device, the semiconductor device described in the first paragraph of the 申 申 晴 ^ ^ ^ ^ ^ ^ ^ ^ 范围 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The semiconductor device of item 1, wherein the lower contact window region comprises at least one of the following: And conductor contact window. The semiconductor device of the invention, wherein the device is a non-volatile memory device of the following items, wherein the device is a non-volatile memory device, Memory devices, DRAM, SRAM, reverse (4) memory, reverse or flash § _ _ body device, PRAM, MRAM and. 13. A semiconductor device comprising: a first insulating layer on a lower contact window region of the semiconductor device; the first insulating layer having a top surface; and a first layer penetrating the first insulating layer a first conductor pattern in an opening, the upper portion of the first conductor pattern is a first width; a second insulating layer on the first insulating layer; penetrating the second insulating layer and the first a second conductor pattern of the conductor pattern in contact with the second conductor pattern 'the second conductor pattern> is a second width, the second width is smaller than the first width; and 'is located in the first insulation layer Passing through the third conductor pattern of the second insulating layer, the third conductor pattern is adjacent to the second conductor pattern in a horizontal direction with respect to the lower first body image & 35 200901371 The length of the diffusion path of the upper boundary of the dynasty/environment layer is greater than the horizontal distance between the corpuscle pattern and the third conductor pattern. The m-patent 1-13 item semi-conducting «sets the top surface of the right (4) case relative to the top surface of the first insulating layer Γ., ten m ' ^ to make the first conductor The height of the top surface relative to the eight-contact window region is less than the top surface of the semiconductor device according to claim 13 of the above-mentioned patent application. The upper portion of the first conductor pattern includes a conductor barrier layer. The second conductor pattern is located in the semi-seat position as recited in claim 16 of the invention, as described in claim 13: the insulated linear spacers on the side walls of the second opening and Less than or equal to the first width. Further, as shown in claim 16, the insulated linear spacers on the side wall of the second opening are as described in claim 16; = the width of the insulated wire _ wall and the second opening (4) The jin is greater than the first width. I. The total length of the visibility of 19. The length between the first conductor pattern and the third conductor pattern as described in claim 16 of the patent application section 36 200901371 side = the length of the leakage current path is greater than the first conductor pattern The horizontal distance from the two conductor patterns. Including the 13 items of the material, it is more layered. The etching device between the first insulating layer and the second insulating layer terminates the semiconductor device according to claim 13: The following first conductor pattern includes: - relative to the line region The semiconductor device is extended in the horizontal direction, and the conductor plug; and the armpit 5 is in the middle. The second conductor pattern includes - an inner wiring extending in a horizontal direction of the semiconductor device with respect to the wiring pattern, and a conductor plug. For example, the semi-conducting material described in claim 13 is further provided with the first opening side wall on the top surface of the side conductor pattern (%, ten, as described in claim 13 of the patent application scope) The semiconductor device, wherein the lower contact window region comprises at least one of the following: a plate, a transistor, a dream 24, a method of manufacturing a semiconductor device, including: in a contact edge layer _ a first opening to expose the lower 37 200901371 pattern: a conductor, the first conductor of the first conductor - the top layer of the conductor layer - the top surface of the conductor pattern a facet: an indentation 'so that a height of the lower contact window region of the first-instance-first insulating layer is less than a height; and a top surface of the track relative to the lower contact window region thereof The second guide width of the handle surface of the body map is smaller than the second width of the lower portion of the pattern, and the second method of the second method is the second generation of the conductor conductor device (S^ is described by J. Providing a conductor barrier layer on the upper portion of the pattern. The method of manufacturing the semiconductor device according to Item 24, wherein the step of providing the second conductor pattern comprises: providing the first insulating layer a second insulating layer; forming a second opening in the second insulating layer to expose the top surface of the first conductor pattern; and providing the second opening with the first conductor pattern The method of manufacturing a semiconductor device according to claim 26, further comprising forming an insulated linear spacer on the sidewall of the second opening, wherein The sum of the width of the insulated linear spacer and the first view of the bottom of the second opening is less than or equal to the first width. 28. The manufacturing semi-guided device according to claim 26 of the patent application. The method 'is further included in the second opening An insulated linear gap 38 is formed on the wall. 200901371: 1 / wall, wherein the sum of the width of the insulated linear spacer and the second width of the bottom of the second opening is greater than the first width. The method for manufacturing a semiconductor device according to Item 26, further comprising: providing a third conductor pattern on the first insulating layer, the third conductor pattern being horizontally opposite to the lower first conductor pattern Adjacent to the second conductor pattern, The length of the leakage current path between the first conductor pattern and the third conductor pattern along the upper boundary of the first insulating layer is greater than the level between the first impurity pattern and the third conductor pattern distance. 30. The method of manufacturing a semiconductor device according to claim 26, further comprising: forming a third conductor pattern on the first insulating layer, wherein the third guide boat is disposed under the The first conductor pattern is adjacent to the first conductor pattern in a horizontal direction, and a length of the diffusion path between the bottom of the conductor pattern and the bottom of the third conductor pattern along the upper boundary of the first insulating layer is greater than The horizontal distance between the second conductor pattern and the third conduction__. 31. The method of fabricating a semiconductor device according to claim 5, further comprising: before the providing the second insulating layer, the first insulating layer and the first guiding film Forming the first ι σ in the insulating layer and forming the first conductor pattern in the first port prior to providing the _ termination 32. As described in claim 26 Manufacturing a half; = 39 of 200901371 The method further includes providing an etch stop layer on the providing of the _ layer, and ???; the edge layer is preceded by the first-insulation--opening π and the first core insulating The formation in the layer is followed by the provision of the _ termination layer. The step of manufacturing the semiconductor device according to the first embodiment of the semiconductor device of the material 34 includes the following: forming the first conductor pattern and describing the next _ field _ half And forming a first-inner line pattern; and extending in a direction to provide a conductor plug; and wherein the step of providing the second conductor pattern further comprises providing a relative conductor-conductor pattern along the following steps The semiconductor package is internally connected in a horizontal direction; and a conductor plug is provided. 34. The method of fabricating a semiconductor package of claim 24, further comprising providing a sidewall spacer on the sidewall of the first opening on the top surface of the first conductor. 35. The method of fabricating a semiconductor device according to claim 24, wherein the lower contact window region comprises at least one of: a substrate, a doped region of the substrate, a doped layer, and an electric The gate of the crystal, the area of the ashes, and the contact window of the conductor.