TW200905931A - Nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

Light emitting efficiency is improved by reducing thermal damage of an active layer (3) by forming a p-type semiconductor layer (4) at a low temperature and reducing a forward direction voltage (Vf). A nitride semiconductor device is provided with an active layer (3) composed of a multiquantum well containing indium; a first nitride semiconductor layer (41) containing a p-type impurity; a second nitride semiconductor layer (42) containing a p-type impurity at a concentration lower than that of the p-type impurity in the first nitride semiconductor layer (41); a third nitride semiconductor layer (43) containing a p-type impurity at a concentration higher than that of the p-type impurity in the second nitride semiconductor layer (42); and a fourth nitride semiconductor layer (44) containing a p-type impurity at a concentration lower than that of the p-type impurity in the third nitride semiconductor layer (43). In a method for manufacturing such nitride semiconductor device, a material gas is supplied by a carrier gas not containing hydrogen, and at last a part of the first nitride semiconductor layer (41) to the fourth nitride semiconductor layer (44) is formed.

Description

200905931 IX. Description of the invention [Technical field to which the invention pertains] Method, special P-type half), etc., conductor A1N) The characteristic ^ 1 ' 0 is, for example, the S layer (n-nitride structure, the conductor layer is output to the barrier layer, Mulit- The present invention relates to a nitride-based semiconductor device having a weighted sub-well structure and supplying a source gas to form a conductor layer, and a method of manufacturing the same, and a method of manufacturing the same. (LED: Light Emitting Diode uses a nitride-based semiconductor layer made of a group III nitride-based semiconductor layer. As an example of a group III nitride-based semiconductor, there are aluminum nitride (GaN, GaN), nitrogen. Indium (InN) or the like, and the III-nitride semiconductor layer is represented by AlxInyGai.x.yN (0$XS yS 1 , OS x + yS 1 ). Nitrogen using a bismuth nitride semiconductor The order of the compound semiconductor having a n-type group III nitride-based semi-conductive semiconductor layer on the substrate, the active layer (light-emitting layer), and the p-type III semiconductor layer (p-type semiconductor layer) Carry out the stratification, The light generated by recombination of the positive hole supplied from the Ρ-type semiconductor layer and the electron supplied from the η-type half in the active layer is external (for example, refer to Patent Document 1). As an active layer, the well layer can be used. A multi-quantum well (MQW: Quantum Well) structure in which a plurality of layers are sandwiched by a plurality of layers (see, for example, Patent Document 2). Further, by lowering the forward voltage (Vf), In the case of the P-type semiconductor layer, the two-layer structure or the three-layer structure is disclosed (for example, refer to Patent Document 3 and Patent Document 4). [Patent Document 1] Japanese Patent Laid-Open No. 1 [Patent Document 2] Japanese Laid-Open Patent Publication No. 2004-55719 (Patent Document 3) Japanese Patent No. 325 438 (Patent Document 4) Japanese Patent No. 331466 (Summary of the Invention) When the P-type semiconductor layer is formed into a multilayer structure, it is necessary to lower the temperature damage in order to reduce the thermal damage to the active layer, and it is necessary to lower the forward voltage (V f ). Light efficiency. Conventionally, in the formation of a p-type semiconductor layer doped with a p-type dopant, 'a carrier gas containing hydrogen (H2) and nitrogen (n2) is used for the supply of the material gas. However, hydrogen is contained. In the case where a carrier gas is formed to form a p-type semiconductor layer, the p-type dopant is less likely to be activated by a hydrogen atom taken in together with the p-type dopant, and this causes a p-type of the p-type semiconductor layer. Therefore, after the formation of the p-type semiconductor layer, it is necessary to perform annealing for removing hydrogen atoms from the p-type semiconductor layer, which is greatly increased in manufacturing engineering. In view of the above problems, the present invention provides a nitride-based semiconductor device in which a p-type semiconductor layer is formed at a low temperature, thermal damage to an active layer is lowered, and a forward voltage (Vf) is lowered to improve luminous efficiency. The present invention provides a method of producing a nitride-based semiconductor device which does not require an annealing process for removing hydrogen atoms from a P-type semiconductor layer. -5-200905931 [Means for Solving the Problem] An active layer formed of a multiple quantum well containing indium according to one aspect of the present invention for achieving the above object, and a first nitrogen containing P-type impurities disposed on the layer The compound semiconductor layer includes a P-type impurity-based semiconductor layer having a lower P-type impurity concentration than the first-stage semiconductor layer on the first nitride-based semiconductor layer, and is disposed on the second nitride-based semiconductor The third nitride-based semiconductor layer containing the P-type impurity P-type impurity of the second nitride-based semiconductor layer and the nitride-based semiconductor layer are contained in a lower concentration of the P-type impurity than the third nitride-based impurity A nitride-based semiconductor device of a fourth nitride layer of a p-type impurity. According to another embodiment, an active layer including a large amount of indium and a first nitride-based semiconductor layer containing P disposed on the active layer and disposed on the first nitrogen conductor layer are provided. A second nitride-based semiconductor layer having a lower P-type impurity than the first nitride-based semiconductor layer is a nitride-based semiconductor device having an oxide electrode and a bright electrode on the second nitride-based semiconductor layer. According to another embodiment, a plurality of semiconductors each containing a p-type dopant are formed on the active layer including forming an n-type semi-engineering and forming an active layer on the n-type semiconductor layer to form a germanium type. The semiconductor layer is engineered to provide the above-mentioned activity, and the first nitride layer on the nitride layer is disposed on the second nitride layer, and the third semiconductor layer semiconductor weight is not pure, and the configuration is arranged. A method of manufacturing a nitride-based semiconductor device in which at least a part of the plurality of nitride-based semiconductor layers are formed by supplying a source gas to a carrier gas through a carrier of a nitride-based hydrogen carrier -6-200905931. [Effect of the Invention] According to the nitride-based semiconductor device of the present invention, the p-type semiconductor layer can be formed at a low temperature, the thermal damage to the active layer can be reduced, and the forward voltage Vf can be lowered to improve the luminous efficiency. According to the present invention, a method of manufacturing a nitride-based semiconductor device which does not require annealing of a hydrogen atom from a P-type semiconductor layer can be provided. [Embodiment] [Best Mode for Carrying Out the Invention] Next, an embodiment of the present invention will be described with reference to the drawings, and the same or similar symbols are attached to the same or similar parts in the following description. However, the drawing is a pattern, and it should be noted that it is different from the actual composition. In addition, of course, there are some cases in which the dimensional relationships or ratios of the drawings are different from each other. In addition, the embodiment shown in the following is an example of an apparatus or a method for embodying an embodiment of the invention, and the embodiment of the invention is not limited to the arrangement of each constituent member, and the like. The embodiments of the invention are directed to various modifications within the scope of the patent application. [First Embodiment] 200905931 A schematic cross-sectional structural view of a nitride-based semiconductor device according to a first embodiment of the present invention is shown in Fig. 1, and an enlarged mode cross-sectional structure of an active layer portion is as shown in the figure. 1 (b) shows the performance. As shown in FIG. 1, the nitride-based semiconductor device according to the first embodiment includes a substrate 1, a buffer layer 6 disposed on the substrate 1, and a buffer layer 6 disposed thereon, and an n-type impurity is added as an impurity. The n-type semiconductor layer 2 is disposed on the n-type semiconductor layer at a lower concentration than the n-type semiconductor layer 2, the n-type impurity is used as a barrier layer 7 for adding impurities, and the active layer 3 disposed on the barrier layer 7 And a p-type semiconductor layer 4 disposed on the active layer 3, and an oxide electrode 5 disposed on the p-type semiconductor layer 4. The active layer 3 is as shown in FIG. 1(b), and has an alternating barrier layer 3 1 1~3 1 η, 3 1 0 and a barrier layer 3 1 1~3 1 η, 3 1 0, band gap For the laminated structure of the small well layer 3 2 1 to 3 2η, for the following, the first barrier layer 3 1 1 to the nth barrier layer 3 1 η which are collectively referred to as the active layer 3 are "blocking layer 3". 1". The film thickness of the uppermost barrier layer 310 of the above laminated structure may be other than the barrier layer of the laminated structure other than the final barrier layer 310 (the first barrier layer 31 1) The thickness of the ~n barrier layer 3 1 η ) is formed thick. In the nitride-based semiconductor device shown in FIG. 1, the p-type dopant of the final barrier layer 310 is formed from the first main surface of the final barrier layer 3 1 0 bonded to the p-type semiconductor layer 4. The film thickness direction of the final barrier layer 310 is decremented, and the p-type dopant is not present for the second main surface facing the first main surface. For the substrate 1 , for example, a c-plane (000 1 ), a sapphire substrate of 0.25° outer angle, or the like is used, and the n-type semiconductor layer 2, the active layer 3, and the p-type half-8-200905931 conductor layer 4 are each composed of a group III nitride. A semiconductor is formed on the substrate, and the buffer layer 6, the n-type semiconductor layer 2, the barrier layer 7, the active layer 3, and the p-type semiconductor layer 4 are sequentially laminated. (Buffer layer) The buffer layer 6 is formed by, for example, forming an α1 ν layer having a thickness of about 10 to 5 Å, and crystallizing the A1 Ν buffer layer 6 by, for example, about 900 ° C to 950 ° C. The temperature is increased at a high temperature, and the aluminum (tma) used as the A1 raw material of the A1N buffer layer 6 is used as the N raw material (NH3), and the H2 gas is used as the carrier, and the pulsedly When it is supplied to the reaction chamber, the A1N buffer layer 6 is crystal grown. For example, the number of cycles may be about 3 to 5. By using trimethylaluminum (TMA)' and ammonia (Nh3) to make H2 gas as a carrier and intermittently supplying it to the reaction chamber, a thin A1N buffer layer 6 having a thickness of about 10 to 50 angstroms can be obtained. The growth is carried out, and the 'crystallinity can be formed while being well maintained. According to the nitride-based semiconductor device of the first embodiment, the crystallinity and surface morphology of the group-111 nitride-based semiconductor formed on the high-temperature A1N buffer layer can be improved. (Barrier Layer) The barrier layer 7 disposed between the n-type semiconductor layer 2 and the active layer 3 is, for example, an n-type impurity, and may have a film thickness of about 50 nm which is not added to lxl〇17/CitT3 and which is added as an impurity. The extent of the group III nitride system semiconducting 200905931 body, for example, a GaN layer or the like. In the nitride-based semiconductor device shown in FIG. 1, for example, in the case where S i is added as an impurity of about 3×10 18 /cm_3, a barrier layer is added by using S i as an impurity of about 3×10 16 /cnT 3 . When it is disposed between the n-type semiconductor layer 2 and the active layer 3, diffusion of Si from the n-type semiconductor layer 2 to the active layer 3 for the manufacturing process after the formation of the active layer 3 and its engineering can be prevented. That is, it is prevented that Si does not diffuse in the active layer 3, and the luminance of the light generated in the active layer 3 is lowered, and more, between the n-type semiconductor layer 2 and the p-type semiconductor layer 4, in order to emit light in the active layer 3. When a bias voltage is applied, electrons supplied from the n-type semiconductor layer 2 to the active layer 3 can be prevented from reaching the p-type semiconductor layer 4 through the active layer 3, and light output from the nitride-based semiconductor device can be prevented. The brightness is reduced. The Si concentration of the barrier layer 7 is less than lxl 017cnT3. When the Si concentration of the barrier layer 7 is too high, the electrons supplied by the indium from the n-type semiconductor layer 2 exceed the active layer 3 and overflow to the p-type semiconductor layer. 4, and in the p-type semiconductor layer 4, recombined with the positive hole, the ratio of recombination in the active layer 3 is reduced, the brightness of light generated in the active layer 3 is lowered, and on the other hand, the Si of the barrier layer 7 When the concentration is too low, the carrier density of electrons injected from the n-type semiconductor layer 2 to the active layer 3 cannot be increased. Therefore, the Si concentration of the barrier layer 7 is desirably less than 5 χ 1016 〜 lxl 017 / cnT3. As described above, in the nitride-based semiconductor device according to the first embodiment, the barrier layer 7 is disposed between the n-type semiconductor layer 2 and the active layer 3, thereby preventing the n-type semiconductor from being manufactured. Layer 2 to -10 200905931 The diffusion of S i of the active layer 3 and the overflow of the electrons of the n-type semiconductor layer 2 to the p-type semiconductor layer 4 at the time of light emission can be prevented from being nitrided semiconductor device The luminance of the output light is lowered, and as a result, the deterioration of the quality of the nitride-based semiconductor device shown in Fig. 1 can be prevented. (n-type semiconductor layer) The n-type semiconductor layer 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 supplies a positive hole to the active layer 3, and is supplied to the active layer 3 via the supplied electrons and the positive holes. In the case of recombination, luminescence is generated. The n-type semiconductor layer 2 may be a group 111 nitride-based semiconductor having a film thickness of 1 to 6 or less, such as a GaN layer, in which an n-type impurity such as bismuth (Si) is added as an impurity. (P-type semiconductor layer) The p-type semiconductor layer 4 may be an in-nitride-based semiconductor having a film thickness of 0.05 to 1 W, which is a p-type impurity added as an impurity, such as a GaN layer or the like, and is a p-type impurity. Magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), bismuth (Be), carbon (C) and the like can be used. The configuration example of the p-type semiconductor layer 4 is more specifically described below, that is, the p-type semiconductor layer 4 is provided on the upper portion of the active layer 3 and contains the p-type impurity as shown in FIG. 1(a). The nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42 which is disposed on the first nitride-based semiconductor layer 41 and contains a p-type impurity having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 41 And a third nitride-based semiconductor disposed on the second nitride-based semiconducting-11 - 200905931 bulk layer 42 and containing a P-type impurity having a higher concentration than the second nitride-based semiconductor layer 42 is placed in the third nitride system The semiconductor layer 43 contains a p-type unpurified semiconductor layer 44 having a lower concentration than the p-type impurity of the second semiconductor layer 43. The thickness of the second nitride-based semiconductor layer 42 is formed to be thicker than the thickness of the first semiconductor layer 41 or the third nitride-based semiconductor layer 43. Here, the material and thickness of each layer will be specifically described, and the first nitride-based semiconductor containing the p-type impurity in the upper portion of the layer 3, for example, Mg, may be added as an impurity to a p-type GaN layer of about 2x1 02 QC] 50 nm. form. It is disposed on the first nitride-based semiconductor layer 41, and the p-type impurity of the compound-containing semiconductor layer 41 has a low concentration of p. The second nitride-based semiconductor layer 42 has, for example, M g added thereto to have a thickness of about 4×10 019 cn T3. The formation of 〇〇nm degree. The second nitride-based semiconductor layer 42 is disposed on the second nitride-based semiconductor layer 42. The p-type impurity of the compound-containing semiconductor layer 42 has a high concentration of p. The third nitride-based semiconductor layer 43 has a thickness of, for example, about 1×10 2 cm·3. A p-type of about 40 nm. The P-type impurity layer 43 disposed on the third nitride-based semiconductor layer 43 and having a low concentration p of the p-type impurity of the compound-based semiconductor layer 43 and the fourth nitrogen-nitride system containing the 3 nitride-based compound The fourth nitrogen is disposed on the active body layer 41, and is m·3, and the thickness is about equal to that of the first nitrogen-type impurity, and the impurity is added to the impurity layer. The GaN layer is different from the second nitrogen-type impurity, and the impurity is added to the GaN layer. Nitrogen-type impurities -12- 200905931

For the fourth nitride-based semiconductor layer 44, for example, Mg is formed as p-type GaN having a thickness of about 1 to about 10,000 cm·3 and a thickness of about 1 nm. In the nitride-based device according to the first embodiment of the present invention, the P-type semiconductor layer 4 formed on the active layer 3 made of a multiple quantum well containing indium is as described above, and the p-type having a Mg concentration of 4 is different. The GaN layer is doped with the above concentration, and the P-type is grown at a low temperature of about 800 ° C in order to reduce thermal damage to the active layer 3 . The first nitride-based semiconductor layer closest to the active layer 3

The higher the Mg concentration, the higher the luminescence intensity. Therefore, the higher the Mg concentration, the higher the Mg content of the second nitride-based semiconductor layer 42 is. When Mg is excessively added, the crystal defects due to Mg increase, and the film resistance is increased. Therefore, it is desirable that the third nitride-based semiconductor layer 43 is a layer which is a half of the 1019cnT3. The third nitride-based semiconductor layer 43 is preferably a layer smaller than the second nitride-based layer 42 because it is a layer for determining the amount of positive hole injection. The higher the Mg concentration is. The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for obtaining resistance contact with the oxygen electrode 5, and is substantially used as the hollowed-up oxide electrode 5, for example, using Ga or A1 as 1 X ] 102 t > In the case of the Zn0 electrode to which the impurity is added, Mg is concentrated when the voltage Vf in the forward direction of the nitride-based semiconductor device is concentrated. For the fourth nitride-based semiconductor layer 44, Mg is added to the impurity. The GaN layer is formed on the upper layer of the semiconductor layer of the pure additive layer. ~900 °C 1 series of indium high, the desired impurity is high, and the layer 3 is semiconductorized, as 019~5 X is the degree of reduction, -13- 200905931 When the p-type GaN layer is grown in four layers, it is close to the third nitride-based semiconductor layer 43 of the p-side electrode 1A, and the fourth nitride-based semiconductor layer 44 is required to have a positive hole concentration in the film. In addition, the amount of H 2 gas in the carrier gas is increased. In addition, the first nitride-based semiconductor layer 41 ′ close to the active layer 3 does not need to increase the amount of H 2 gas in the carrier gas. When the growth of the 112 carrier gas is extended, the active layer 3 is crystallized, and when the p-type GaN layer is grown, the V/III ratio is increased as much as possible, and the low-resistance film can be grown. Further, the forward voltage (Vf) of the light-emitting element can be lowered. According to the nitride-based semiconductor device of the first embodiment, the P-type semiconductor layer can be formed at a low temperature, the thermal damage to the active layer can be lowered, and the forward voltage (Vf) can be lowered to improve the luminous efficiency. (Active Layer) The active layer 3 is formed by sandwiching each of the first barrier layer 3 1 1 to the n-th barrier layer 3 1 η and the final barrier layer 3 1 0 ' as shown in FIG. 1( b ). Multi-quantum well (MQW) structure (n: natural number) of the first well layer 32 1 to the n-th well layer 32n, that is, the activity is sandwiched by the barrier layer 31 which is larger than the well layer 3 2 band gap Layer 3 is a sandwich-like quantum well structure 'as a unit-pair structure' and has a n-layered structure of its unit-pair η pair structure. Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 is disposed between the second barrier layer 312 and the third barrier layer. Between 313, and the 'nth well layer 32n is disposed between the nth barrier layer 3 1 η and the final barrier layer 3 1 0 'the active layer 3 of the -14 - 200905931 1 barrier layer 311 by The buffer layer 6 is disposed on the n-type semiconductor layer 2, and the p-type semiconductor layer 4 (4 1 to 44 ) is disposed on the final barrier layer 3 1 0 of the active layer 3 . The well layers 321 to 32 η are formed, for example, via an InxGa^NCiXxSi) layer, and the barrier layers 3 1 1 to 3 1 η, 3 1 0 are formed, for example, via a GaN layer, and the logarithmic system of the multiple quantum well is, for example, 6~ The characteristics of 1 1 are, however, the ratio of the indium (In) of the calcium (Ga) of the well layers 321 to 32 η { X / ( 1 -X )} is appropriately selected in accordance with the wavelength of light generated. Further, the thickness of the well layers 321 to 32n is, for example, about 2 to 3 nm, and is desirably 2. The thickness of the barrier layers 311 to 31 η, 310 is about 7 to 18 nm, and is about 1 6 · 5 nm. The characteristics are 〇 for the nitrogen of the first embodiment. In the compound semiconductor device, the relationship between the light emission output and the logarithm of the quantum well is expressed as shown in FIG. In the nitride-based semiconductor device according to the first embodiment, the band structure of the luminescence phenomenon in the active layer 3 is schematically shown in Fig. 5 . FIG. 6 is a view showing a mode of a band structure in the case where the MQB is five pairs in FIG. 6(a) for the band structure of the luminescence phenomenon in the active layer 3 in the nitride-based semiconductor device according to the first embodiment. Fig. 6(b) is a schematic diagram showing a band structure in the case where MQW is eight pairs, and Fig. 6(c) is a pattern diagram showing a band structure in the case where MQW is 12 pairs. In the conventional structure, since the logarithm of the MQW is 4 to 5 pairs, the electrons supplied from the n-type semiconductor layer 2 flow through the active layer -15-200905931 to the layer 3 as shown in Fig. 6 (a). The semiconductor layer 4, at this time, the positive hole supplied from the p-type half 4 is brought into contact with electrons before reaching the active layer 3, and the positive hole concentration reaching the active layer 3 is decreased, whereby the brightness is reduced. This is because the effective mass of the positive hole is lower than the electron mobility from the positive hole of the P-type semiconductor layer 4, and before reaching the active layer 3, the electron reaches the p-type semiconductor layer 4, and is recombined. . On the other hand, as shown in FIG. 6(c), the logarithm of MQW is larger than that of 12 pairs, since the active layer 3 is thick, and the positive hole supplied from the n-type half 2 cannot travel in the active layer 3. Therefore, the active layer 3, the recombination of the electrons and the positive holes is not sufficiently generated, and the brightness of the LED is raised. In the case of ensuring the amount of injection from the p-type semiconductor layer 4 to the positive hole of the active layer 3, and ensuring the amount of electrons injected from the n-type semiconductor layer 2 to the sufficient amount of electrons, the MQW system in which the luminescence phenomenon is carried out The number of movements of the electrons from the p-type semiconductor layer 4 may be 2 to 3, and the mobility of the electrons is lower than that of the positive holes, and the MQW in the active layer 3 of the luminescence phenomenon is close to the p-type layer 4. The pair of side numbers. In addition, as shown in FIG. 4, the logarithm of the MQW is Ϊ, the output system indicates the maximum 値Ρ2, and on the other hand, for the MQW of 5 or 12, the illuminating output ρ is the case where the logarithm of the degree MQW is less than 5 or greater than In the case of 1 2, it is difficult to ensure the light output P. The conductor layer is re-arranged to the height of the LED, and the hole reaches the positive hole. The conductor layer is sufficient for the layer 3 of the layer 3, and then the semiconductor is given, and the logarithm of the luminescence is sufficient for -16-200905931 The electrons supplied from the n-type semiconductor layer 2 and the positive holes supplied from the p-type 4 in the nitride-based semiconductor according to the first embodiment, in order to be effective for bonding the active layer in the active layer 3 The logarithm of MQW within 3 is optimized. (Final barrier layer) The film thickness of the final barrier layer 310 is formed thicker than the diffusion distance of Mg from the p-type semiconductor layer 3. In the nitride-based semiconductor device shown in FIG. 1, the concentration of the most P-type impurity of 31 is from the first main surface bonded to the P-type semiconductor termination barrier layer 3 10 along the final barrier layer 3 1 0 is decremented 'for the second main surface opposite to the first main surface, the unshaped impurity. The final barrier film thickness do of the nitride-based semiconductor device shown in FIG. 1 is for the formation of the p-type semiconductor layer 4 and the subsequent formation of the p-type semiconductor layer 4 from the p-type semiconductor layer 4 to the active layer 3 The well layer 32 of layer 3 is set, that is, the p-type impurity thickness dO of the semiconductor layer 4 diffused to the final barrier layer 3丨〇 is the layer 3 3 0 that does not reach the opposite p-type semiconductor layer*. The thickness of the second main surface of the first main surface (the surface of the final barrier layer 3 i 〇 layer 3 2η). The Mg concentration of the final barrier layer 3 i bonded to the p-type semiconductor layer 4 is, for example, about 2×1 〇2 G c ηΤ3, toward the final barrier layer 3 of the first main surface] The second main surface, the Mg concentration device, is a semiconductor layer, and the other is the pure material of the ρ layer 3 10 in the thickness direction of the end layer of the living barrier layer 4, and the film is set from the P type. The first main barrier to the well is gradually -17-200905931, and the decrease is not affected by the distance from the first main surface to about 7 to the Mg concentration of about 1 016 cm·3. Below the limit, that is, the M g system does not diffuse to the final second main surface by the extent that the final barrier layer 3 丨 0 is about 10 nm, and therefore, for the final second main surface joined to the active layer 3, There is no Mg present, that is, MG is not diffused to prevent light generated in the active layer 3, however, the first barrier layer 31 to the nth barrier layer 3 1 η may also be The same 'however, the film thickness dl~dn is from the n-type half to the positive hole of the active layer 3 and then reaches the nth well layer 3 2 η, which can be generated via the nth well layer 32n, The thickness of the sub-aperture and the positive hole, and when the first barrier layer 311 to the n-th barrier are d 1 to d η, the light efficiency of the positive hole in the active layer 3 is hindered. For example, the final resistance The film thickness d0 of the barrier layer 31 is luxurious, and the film thickness of the first barrier layer 31 1 to the nth barrier layer 3 In is about 7 to 18 nm. The table 1 well layer 321 to the n layer 32 n 2 to 3 As described above, in the nitrogen device according to the first embodiment, the final thickness dO bonded to the P-type semiconductor layer 4 is set to diffuse from the p-type semiconductor layer 4 to the active > dopant The thickness of the well layer 3 2 reaching the active layer 3 is measured by the analysis according to the nitride-based semiconductor device shown in FIG. 1 via the film thickness d0 of 310 as a diffusion distance of Mg from the position of 8 nm. The film thickness d 0 is used as the barrier layer 3 1 0 of the barrier layer 3 1 0 in the n well layer 3 2n 1 brightness decreases. Film thickness d 1~d η Injecting the conductor layer 2 It is necessary to set the movement of the film thickness of the recombined illuminating Ϊ 3 In, and the hair 5 26. The degree of 5 nm d 1 ~ d η is about ρ type of the film layer 3 of the compound-based semiconductor barrier layer 3 10 , that is, if the final barrier layer is set, -18-200905931 When the film thickness of the entire active layer 3 is controlled to increase, the diffusion of the P-type impurity from the p-type semiconductor layer 4 to the well layer 3 of the active layer 3 can be prevented, and as a result, the p-type for the well layer 32 is not generated. The luminance of light caused by the diffusion of impurities is lowered, and a nitride-based semiconductor device that controls the deterioration of the quality of the nitride-based semiconductor device can be manufactured. (Electrode structure) The nitride-based semiconductor device according to the first embodiment further includes an n-side electrode 200 to which a voltage is applied to the n-type semiconductor layer 2 and a voltage applied to the p-type semiconductor layer 4 as shown in FIG. The ρ side electrode 1 00, and as shown in FIG. 3, the surface of the n-type semiconductor layer 2 exposed to the surface of the p-type semiconductor layer 4, the active layer 3, the barrier layer 7, and the n-type semiconductor layer 2 is exposed on the mesa. The η side electrode 200 is disposed. The x-side electrode 100 is disposed on the p-type semiconductor layer 4 by the oxide electrode 5, or the p-side electrode 100 may be directly disposed on the p-type semiconductor layer 4 and disposed on the fourth nitrogen. The transparent electrode formed of the oxide electrode 5 of the semiconductor layer 44 includes, for example, ZnO, IT 0 or ZnO containing indium. The n-side electrode 200 is made of, for example, an aluminum (Al) film, a multilayer film of Ti/Ni/Au or Al/Ti/Au, Al/Ni/Au, Al/Ti/Ni/Au, or from the upper layer Au-Sn a multilayer film of / T i / A u / N i / A1, the ρ side electrode 100 is composed of, for example, an A1 film, a palladium (Pd)-gold (Au) alloy film, and a Ni/Ti/Au multilayer film. Or a multilayer film of the upper layer Au-Sn/Ti/Au, and the n-side electrode 200 is electrically connected to the n-type semiconductor layer 2, and the p-side electrode 1 is made of an oxygen-19-200905931 compound electrode 5 A resistor is connected to the p-type semiconductor layer 4. In order to mount the nitride-based semiconductor device according to the first embodiment of the present invention in a flip-chip structure, the surface of the p-side electrode 1 and the surface of the n-side electrode 200 may be measured from the substrate 1. The height is formed at the same height. It is also possible to have a structure in which the transparent electrode film ΖηΟ is formed as the oxide electrode 5, and ΖηΟ' is covered by a reflective laminated film which reflects the wavelength λ of the light emitted, and the reflective laminated film has λ/4ηι and λ. The layered structure of /4η2 (the refractive index of the layer of the '112-layer layer) is used as the material used for the layered structure. For example, for blue light of Λ = 45 Onm, Zr〇2 ( η can be used. = 2·12) is a laminated structure with SiO 2 (η = 1·46), and the thickness of each layer in this case is such that ZrO 2 is, for example, about 53 nm, and SiO 2 is, for example, about 77 nm, and is formed as For other materials in the laminated structure, Ti〇2, ai2o3, etc. may also be used. According to the nitride-based semiconductor device according to the first embodiment, the light that is emitted in the active layer 3 can be taken out without being absorbed by the p-side electrode 1A, thereby being lifted. External luminous efficiency. (Manufacturing Method) Hereinafter, an example of a method of manufacturing the nitride-based semiconductor device of the first embodiment shown in FIG. 1 will be described. However, the method for manufacturing the nitride-based semiconductor device described below is an example and includes The case of the modification "which can be realized by various manufacturing methods other than this is a matter of course. Here, an example in which a sapphire substrate is applied to the substrate 1 will be described. -20- 200905931 (a) First, the A1N buffer layer 6 is grown on the sapphire substrate 1 by a known organometallic chemical vapor phase growth method (MOCVD method), for example, at about 900 ° C to 95 (TC). To a high degree of temperature, trimethylaluminum (TMA) and ammonia (NH3) are intermittently supplied to the reaction chamber via H2 gas as a carrier, and the thickness is about 10 to 50 Å in a short time. The thin A1N buffer layer 6 is grown. (b) Next, the GaN layer to be the n-type semiconductor layer 2 is grown on the A1N buffer layer 6 by a Μ 0 CVD method or the like, for example, a substrate on which the A1N buffer layer 6 is to be formed. 1. After the heat is washed, the substrate temperature is set to 1 000 ° C, and the n-type semiconductor layer 2 of the n-type impurity is added to the A1N buffer layer 6 to carry out the growth of 1 to 5 degrees, for the n-type. In the semiconductor layer 2, for example, a GaN film of S i may be added as a n-type impurity as a concentration of impurities of 3 χ 1 〇18 crn·3, and a trimethyl group may be added as an impurity. Gallium (TMG), ammonia (NH3) and formane (SiH4) are supplied as raw material gases to form n The semiconductor layer 2 〇 (C) is then applied to the n-type semiconductor layer 2 as a barrier layer 7 so that a GaN film of Si is added to a concentration of impurity which is not more than 1×10 _ 17 cm −3 ′, for example, 8×10 〇i 6 cm·3, for example, A film is formed to a thickness of about 200 nm. In this case, the same material gas as that in the case of forming the n-type semiconductor layer 2 can be applied. (d) Next, the active layer 3 is formed on the n-type semiconductor layer 2, for example, 'interlayer lamination is performed on the GaN film. The barrier layer 31 and the well layer 3 2 ' formed of the InGaN film form the active layer 3, specifically, the substrate temperature and the flow rate of the material gas when the active layer 3 is formed, and the interaction is continuous. 200905931 The barrier layer 31 and the well layer 32 are grown to form an active layer 3 formed by laminating the barrier layer 31 and the well layer 32, that is, the well layer 32 and the well are layered by adjusting the substrate temperature and the flow rate of the material gas. The layer 32 has a band gap as the large barrier layer 31. As a unit project, the unit project is made as n times, for example, 8 times, and the alternating layered barrier layer 3 1 and the well layer 3 2 are obtained. a laminated structure. For example, the barrier layer 31 is formed by the substrate temperature Ta, The well layer 32 is formed at a temperature Tb (Ta>Td), that is, the first barrier layer 311 is formed at a time t10 to ttl1 at which the substrate temperature is set to Ta, and then the substrate temperature is set to Tb at time til, The first well layer 321 is formed at time t11 to t20, and thereafter, the second barrier layer 312 is formed from the substrate temperature Ta at time t20 to t21, and the substrate temperature Tb is obtained at time t21 to t3. The second well layer 3 22 is formed, and the n-th barrier layer 31n is formed from the substrate temperature Ta at the time tn0 to tnl, and the n-well layer 32n is formed from the substrate temperature Tb at the time tn 1 to te. The laminated structure of the barrier layer 31 and the well layer 32 is alternately laminated. The case where the barrier layer 31 is formed is used as a material gas. For example, TMG gas is supplied to the film formation at a flow rate of 20 slm (standard L/min) at a flow rate of 20 slm (standard cc/min) at 300 sccm (standard cc/min). On the other hand, the formation of the well layer 3 2 is used as a raw material gas, for example, TMG gas, trimethyl indium (TMI) gas at 300 cc Ccm, and NH 3 gas at a flow rate of 280 sccm, at 20 slm The flow rate is supplied to the processing device, respectively. However, the TMG gas system is used as a raw material gas for Ga atoms, the TMI gas system is used as a raw material gas for In atoms, and NH3 gas-22-200905931 is supplied as a raw material gas for nitrogen atoms. Forming the undoped GaN film as 1 to the extent that the undoped GaN film is formed as the final barrier layer 310, forming the active layer 3 shown in FIG. 1, as described above, the final barrier layer The film thickness d0 of 3 10 is a p-type dopant which diffuses from the P-type semiconductor layer 4 to the active layer 3, and is set to a thickness of the well layer 32 which does not reach the active layer 3. (e) Next, the substrate temperature is taken as 80 ° C to 900 ° C ' on the final barrier layer 310, and the P-type semiconductor layer 4 in which the P-type impurity is added to the impurity is made 0 0 5 5 1 The degree of W is formed. The p-type semiconductor layer 4 is, for example, a p-type impurity, and is formed into a four-layer structure in which Mg is added as an impurity, and the first nitride-based semiconductor layer 41 disposed on the upper portion of the active layer 3 is about 2×10 2 QCrrT3 and has a thickness of about 50 nm. The P-type GaN layer is formed, and the second nitride-based semiconductor layer 42 is formed of a p-type GaN layer having a thickness of about 42×10 19 cm −3 and a thickness of about 100 nm, and the third nitride-based semiconductor layer 43 is, for example, about 1×10 G G T T 3 , and has a thickness of about 40 nm. The p-type GaN layer is formed to a certain extent, and the fourth nitride-based semiconductor layer 44 is formed of a p-type GaN layer having a thickness of about 8×1 0I9cnT3 and a thickness of about 10 nm. When Mg is added to the impurity, TMG gas, NH3, and dicyclopentadienyl magnesium (CpdMg) gas are supplied as a material gas to form a p-type semiconductor layer 4 (41 to 44), and a germanium-type semiconductor layer 4 (41~). When 44) is formed, 'from the P-type semiconductor layer 4 (4 1 to 44), Mg is diffused to the active layer 3' but via the final barrier layer 3 10 to prevent the diffusion of μ g to the well layer 32 of the active layer 3. -23- 200905931 Here, the formation of the P-type semiconductor layer 4 will be described in more detail. The temperature distribution when the four p-type semiconductor layers (41 to 44) are formed in the nitride-based semiconductor device according to the first embodiment is as shown in Fig. 7(a), and the hydrogen flow is explained. The graph of the condition is shown in Fig. 7 (b), and the graph showing the other conditions of the hydrogen flow is shown in Fig. 7 (c), and the graph showing the other conditions of the hydrogen flow is shown. As shown in Fig. 7(d), a graph showing still other conditions of hydrogen flow is shown in Fig. 7(e). In the nitride-based semiconductor device according to the first embodiment of the present invention, the temperature distribution when forming the p-type semiconductor layers (41 to 44) of four layers is as shown in FIG. 8(a), and the description is also made. The graph of the conditions of the nitrogen gas flow is shown in Fig. 8 (b), and the graph showing the conditions of the ammonia gas flow is shown in Fig. 8 (c). With respect to the temperature distributions shown in Fig. 7 (a) and Fig. 8 (a), the period T1 of the time t1 to t2 is the period during which the first nitride-based semiconductor layer 41 is formed, and the period T2 of the time t2 to t3 is formed. In the period of the second nitride-based semiconductor layer 421, the period T3 at the time t3 to t4 is a period in which the third nitride-based semiconductor layer 431 is formed, and the period T4 at the time t4 to t5 is the formation of the fourth nitride-based semiconductor layer 44. In the period of time t5 to t6, the period T5 is a period in which the substrate temperature is cooled from 850 ° C to 35 ° C. The nitride-based semiconductor device according to the first embodiment of the present invention includes a process of forming the n-type semiconductor layer 2, and a process of forming the active layer 3 on the n-type semiconductor layer 2, and on the active layer 3. , Laminating each -24-200905931 A P-type GaN layer containing a plurality of P-type impurities, forming a nitrided semiconductor layer (4 1 to 44) at a low temperature of about 800 ° C to 900 ° C, without containing hydrogen The carrier gas is supplied to the source gas to form at least a part of a plurality of P-type GaN layers. When the P-type semiconductor layer 4 is formed by supplying the source gas through the carrier gas containing no hydrogen, Mg is not activated by the hydrogen atom taken in from the Mg, and becomes a p-type which inhibits the P-type semiconductor layer 4. Therefore, after forming the P-type semiconductor layer 4, it is necessary to perform annealing for removing the hydrogen atoms and p-type the P-type semiconductor layer 4 (hereinafter referred to as "P-type annealing"). However, according to the method of manufacturing the nitride-based semiconductor device according to the first embodiment, at least one of the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is contained in the case where hydrogen is not contained. When the gas is supplied to the raw material gas of Mg, the p-type annealing process can be omitted, and any portion of the P-type semiconductor layer 4 formed by the carrier gas containing no hydrogen can be arbitrarily set, for example, not included. The first nitride-based semiconductor layer 41 to the third nitride-based semiconductor layer 43 are formed by the carrier gas of hydrogen, and only the fourth nitride-based semiconductor layer 44 can be formed via the carrier gas containing no hydrogen. For example, as shown in FIG. 7(b), among the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44, the second nitride-based semiconductor layer 42 having a large thickness is formed, or the Mg concentration is high. The first nitride-based semiconductor layer 41 is formed by a carrier gas not containing hydrogen. However, it is preferable to omit the P-type annealing process. For example, FIG. 7(c) is a first nitride-based half. -25-200905931 In the conductor layer 41 to the fourth nitride-based semiconductor layer 44, the first nitride-based semiconductor layer 41 to the third nitride-based semiconductor layer 43 are formed via a carrier gas containing no hydrogen. 7(d) shows an example in which the first nitride-based semiconductor layer 41 and the third nitride-based semiconductor layer 43 are formed via a carrier gas not containing hydrogen, and FIG. 7(e) shows that the second nitrogen is used. The compound semiconductor layer 42 and the third nitride-based semiconductor layer 43 are formed via a carrier gas not containing hydrogen. On the other hand, as shown in FIG. 7(b) to FIG. 7(e), the fourth nitride-based semiconductor layer 44 bonded to the p-side electrode 100 is preferably made of hydrogen in order to make the crystal state as good as possible. In the case where a carrier gas is supplied to supply a raw material gas of Mg, it is preferable that the raw material gas of Mg is supplied through a carrier gas containing hydrogen, and it is formed by a carrier gas not containing hydrogen, and is added by impurities. The crystalline state of the p-type semiconductor layer of Mg is preferred. In the following, a P-type film formation method for the method for producing a nitride-based semiconductor device according to the first embodiment will be described. However, the P-type film formation method described below is an example and includes the deformation thereof. For example, the case where it can be realized by various manufacturing methods other than the above is 'of course, as a p-type impurity, and Mg is used, and as shown in FIG. 7(b), it is exemplarily described via a carrier containing no hydrogen. The first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42 are formed by the gas, and the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44 are formed via a carrier gas containing hydrogen. As shown in Fig. 7 and Fig. 8, the substrate temperature at which the p-type semiconductor layer 4 is formed is -26-200905931, Τρ is 85 ° C, and the pressure is set in common at 200 Torr. (Project 1) The N3 gas is supplied as a carrier gas at time t1 to t2, and is supplied as a source gas, and each of NH3 gas, TMG gas, and Cp22Mg gas is supplied to a processing apparatus to form a first nitride-based semiconductor layer 4. (1) The first nitride-based semiconductor layer 41 having a film thickness = 50 nm and a Mg concentration = 2 χ 102GCnT3 is formed at a time point t1 to t2. (2) The N2 gas is supplied as a carrier gas at the time t2 to t3, and the raw material gas is supplied, and the NH3 gas, the TMG gas, and the Cp22Mg gas are supplied to the processing apparatus to form the second nitride-based semiconductor layer 42. The time t2 to t3 is 21 minutes, and the second nitride-based semiconductor layer 42 having a film thickness of 100 nm and a Mg concentration of 4 x 1 〇 19 cm_3 is formed. (Project 3) In the case of time t3 to t4, H2 gas is supplied as a carrier gas, N2 gas is used as a material gas, and NH3 gas, TMG gas, and CP22Mg gas are supplied to a processing device to form a third nitride system. The semiconductor layer 43 is divided into three points at time t3 to t4 to form a third nitride-based semiconductor layer 43 having a film thickness of 40 nm and a Mg concentration of lx102 Qcm_3. (Project 4) In the case of time t4 to t5, H2 gas is supplied as a carrier gas, N2 gas is used as a material gas, and NH3 gas, TMG gas, and CP22Mg gas are supplied to a processing device to form a fourth nitride system. In the semiconductor layer 44, the fourth nitride-based semiconductor layer 44 having a film thickness = 10 nm and a Mg concentration = 8 x 1019 cm_3 is formed at a time t4 to t5. (Project 5) At the time t5 to t6, the n2 gas is supplied as a carrier gas, and the substrate temperature is lowered from the temperature Tp (85 0 °C) to a temperature Td (3 50 °C) or less, that is, P-type -27-200905931 annealing was carried out at 400 ° C or higher. In the above-described engineering process 5, the P-type semiconductor layer 4 including the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is formed, and the first nitride-based semiconductor layer 41 having a high Mg concentration is used. Since the second nitride-based semiconductor layer 42 ′ having a large thickness is formed by a carrier gas not containing H 2 gas, the P-type semiconductor layer 4 can be obtained even if P-type semiconductor layer is not formed. When the carrier containing the H 2 gas is supplied, the crystal state of the fourth nitride-based semiconductor layer 44 is improved, that is, the crystal state of the surface joined to the p-side electrode 100 of the p-type semiconductor layer 4 is good. Contact with the p-side electrode 100 of the P-type semiconductor layer 4 is good. According to the formation process of the P-type semiconductor layer 4 as described above, the p-type semiconductor layer 4 is formed by supplying a carrier gas containing no H 2 gas, and the P-type semiconductor layer 4 is not taken together with the P-type impurity. Therefore, it is not necessary to remove the p-type annealing of H2 from the P-type semiconductor layer 4, and the manufacturing process of the nitride-based semiconductor device can be shortened. (f) Next, the oxide electrode 5 is formed on the upper portion of the P-type semiconductor layer 4 by vapor deposition, sputtering, or the like, and as the oxide electrode 5, for example, ZnO, ITO, or ZnO containing indium may be used. In any case, an η-type impurity such as G a or A1 or a high-concentration impurity may be added to the extent of lxlO19 to 51xl021cm·3. (g) Next, after the oxide electrode 5 is patterned, the reflective laminated film 8 that reflects the light wavelength λ that emits light on the coated oxide electrode 5 is formed by vapor deposition, sputtering, or the like. As the material used for the anti--28-200905931 shot film 8, for example, for the blue light of λ=450ηπι, Zr02 can be used (n = 2. 12) A laminate structure of SiO 2 (n = 1 - 46), and the thickness of each layer in this case is such that Zr 〇 2 is, for example, about 53 nm, and SiO 2 is, for example, about 77 nm. (h) Next, the uranium engraving is performed using a residual etching technique such as reactive ion etching (RIE: Reactive Ion Etching) until the reflective laminated film 8 and the p-type semiconductor layer 4 to the n-type semiconductor layer 2 are formed. Further, the surface of the n-type semiconductor layer 2 is exposed. (i) Next, on the surface of the exposed n-type semiconductor layer 2, the n-side electrodes 200, 300 are formed by vapor deposition, sputtering, or the like, and the oxide electrode 5 on the p-type semiconductor layer 4 is also patterned. After the formation, the side electrode 1 is formed by vapor deposition, sputtering, or the like, and the nitride-based semiconductor device shown in FIG. 3 is completed. (Modification) The schematic cross-sectional structure of the nitride-based semiconductor device according to the modification of the first embodiment is as shown in Fig. 2 (a), and the pattern cross-sectional structure in which the active layer portion is enlarged is as shown in Fig. 2. (b) Performance as shown. As shown in FIG. 2, the nitride-based semiconductor device according to the modification of the first embodiment includes a substrate 1 and a buffer layer 6 disposed on the substrate 1, and is disposed on the buffer layer 6, and the n-type impurity is made. The n-type semiconductor layer 2 added for the impurity, and the barrier layer 7 disposed on the n-type semiconductor layer at a lower concentration than the n-type semiconductor layer 2, adding the n-type impurity as an impurity, and disposed on the barrier layer 7 The active layer 3, and the P-type semiconductor layer 4 disposed on the active layer 3 on -29 to 200905931, and the oxide electrode 5 disposed on the p-type semiconductor layer 4. A nitride-based semiconductor device according to a modification of the first embodiment includes a third nitride-based semiconductor layer 43 which is disposed on the upper portion of the active layer 3 and contains a P-type impurity, and is disposed on the third nitride-based semiconductor layer. a fourth nitride-based semiconductor layer containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride-based semiconductor layer, and a fourth nitride-based semiconductor layer disposed on the fourth nitride-based semiconductor layer and transparent by the oxide electrode 5 electrode. Further, the transparent electrode includes a nitride-based semiconductor device in which ZnO, ITO or indium-containing ZnO is added to the ZnO, ITO or indium-containing ZnO in which Ga or A1 impurities are added to 1×1〇19 to 5×10 2 cm 3 or less. In the structure of the nitride-based semiconductor device of the second embodiment, the P-type semiconductor layer 4 is formed of the third nitride-based semiconductor layer 43 disposed directly on the upper portion of the active layer 3, and is disposed on the third nitrogen. The compound semiconductor layer 43 has a two-layer structure including a fourth nitride-based semiconductor layer having a p-type impurity having a lower concentration than the p-type impurity of the third nitride-based semiconductor layer. The third nitride-based semiconductor layer 43 which is formed directly on the upper portion of the active layer 3 is, for example, Mg, which is about 1×1〇2()Cm·3 added as an impurity, and p-type GaN having a thickness of about 40 nm. The layer is formed. The fourth nitride-based semiconductor layer 44' which is disposed on the third nitride-based semiconductor layer 43 and contains a p-type impurity having a lower concentration than the p-type impurity of the third nitride-based semiconductor layer 43 is made of Mg as an impurity. The addition of about 8xl 〇 19crrT3' thickness of about 10nm p-type GaN layer is formed -30-200905931. In the nitride-based semiconductor device according to the second embodiment of the present invention, the P-type semiconductor layer 4 formed over the active layer 3 made of a multiple quantum well containing indium is as described above, and has a different Mg concentration. a P-type GaN layer of a layer structure, doped with the above concentration, and a P-type GaN layer is used to lower the thermal damage to the active layer 3 to a low temperature of about 800 ° C to 900 ° C Grow up. The third nitride-based semiconductor layer 43 closest to the active layer 3 is a layer which determines the amount of positive hole injection into the active layer 3, so the higher the Mg concentration, the higher the luminescence intensity. Therefore, the higher the Mg concentration, the higher the Mg concentration. High expectations. The fourth nitride-based semiconductor layer 44 is a p-type GaN layer that is in contact with the oxide electrode 5, and is substantially vacant, and is used as the oxide electrode 5. For example, Ga or A1 is used as 1χ1019~5χ. In the case of the ZnO electrode to which the impurity is added, the Mg concentration in the case of reducing the forward voltage Vf of the nitride-based semiconductor device is increased, and Mg is added to the impurity in the fourth nitride-based semiconductor layer 44. When the p-type GaN layer is grown in four layers, it is close to the third nitride-based semiconductor layer 43 of the p-side electrode 100, and the fourth nitride-based semiconductor layer 44 is required to increase the positive hole concentration in the film. Therefore, the amount of H 2 gas in the carrier gas is increased, or alternatively, the third nitride-based semiconductor layer 43 close to the active layer 3 is grown by the N 2 carrier gas without increasing the amount of H 2 gas in the carrier gas. The extension of the active layer 3 proceeds to crystal growth. The nitride-based semiconductor device A1N buffer layer 6, the n-type semiconductor layer 2, the barrier layer 7, the active layer -31 - 200905931 3, the p-type semiconductor layer 4, and the final barrier layer in the modification of the first embodiment. The layer 3 1 0 'reflective laminated film 8 and the electrode structure are the same as those of the nitride-based semiconductor device according to the first embodiment, and therefore will not be described. According to the nitride-based semiconductor device according to the first embodiment and its modification, the p-type semiconductor layer can be formed at a low temperature to reduce thermal damage to the active layer and to reduce the forward voltage (vf) to improve luminous efficiency. [Second Embodiment] A method for producing a nitride-based semiconductor device according to a second embodiment of the present invention includes a process of forming an n-type semiconductor layer and a process of forming an active layer on an n-type semiconductor layer and activity. a layer in which a plurality of nitride-based semiconductors each containing a cerium-type dopant are stacked to form a bismuth-type semiconductor layer, and a source gas is supplied through a carrier not containing hydrogen to form at least a plurality of nitride-based semiconductor layers. portion. FIG. 9 shows an example of a nitride-based semiconductor device manufactured by the above-described manufacturing method, and the nitride-based semiconductor device shown in FIG. 9 includes a substrate 1 and an n-type semiconductor layer 2 disposed on the substrate 1, and As shown in FIG. 9, the p-type semiconductor layer 4 has a first nitride-based semiconductor as the active layer 3 on the arrangement-type semiconductor layer 2 and the nitride-based semiconductor device in which the p-type semiconductor layer 4 is disposed on the active layer 3. The detailed structure of the layer 41 to the fourth nitride-based semiconductor layer 44 with respect to the p-type semiconductor layer 4 will be described later. The nitride-based semiconductor device shown in FIG. 9 further includes an n-side electrode 200 to which a voltage is applied to the n-type semiconductor layer 2, and a p-side electrode 10 0, η side to which a voltage is applied to the p-type half-32-200905931 conductor layer 4. The electrode 200 is disposed on the surface of the n-type semiconductor layer 2 in which the p-type semiconductor layer 4, the active layer 3 and the n-type semiconductor are exposed, and the p 100 is disposed on the germanium semiconductor layer 4 The η side electrode 200 is made of an aluminum (Α1) film, and the ρ side electrode 100 is made of, for example, a titanium (Ti) nickel (Ni) film, or an indium tin oxide (ITO) film, or a zinc oxide (transparent electrode such as a film). Or a palladium (Pd)-gold (Au) alloy film, and the n-side electrode 200 is electrically connected to the n-type semiconductor layer 2, and the pole 100 is electrically connected to the germanium-type semiconductor layer 4. The nitride shown in FIG. In the semiconductor device, the n-type half 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 is supplied to the positive layer 3, and the electrons and the positive holes are supplied to the active layer 3 to cause light emission. For the substrate 1, for example, a sapphire substrate or the like may be used, and the η bulk layer 2 may be a 将-type dopant. Si) and the like: 0. A group III nitride-based semiconductor having a degree of 2 to 5 Å, for example, a GaN layer active layer 3 has a quantum well structure in which a barrier layer having a larger band gap than a well layer 32 is sandwiched, and an active layer structure is formed. The eyebrow can also be a quantum well structure with a barrier layer sandwiching the well layer, a bit structure, or a multi-weight MQW) structure (η: natural number) of the unit structure of the n-th layer. The active layer 3 of the MQW structure is, for example, as shown in FIG. 1A, having the first barrier layer η barrier layer 3 1 η and the final barrier layer 3 10 , respectively, the 321st to the nth layers Specifically, the first well layer 321 is formed by, for example, a film or a ΖηΟ of the side layer of the mesa layer 2, and a film thickness of the side of the electric conductor layer to the semi-conducting semiconductor. :31 and f 3 is used as a single well (in the case, the 3 1 1 to the 1st well layer is placed between the barrier layer 3 1 1 and the second barrier layer 3 12 of the 33-200905931, and the illustration is omitted. The second well layer 3 22 is disposed between the second barrier layer 312 and the third barrier layer (not shown), and the nth well layer 32 η is disposed on the nth barrier layer 31 η and the final barrier Between the layers 3 10 , the first barrier layer 31 1 of the active layer 3 is disposed on the n-type semiconductor layer 2, and the 阻-type semiconductor layer is disposed on the final barrier layer 3 1 0 of the active layer 3 The first nitride-based semiconductor layer 41 of 4 is formed of, for example, a GaN layer, and the well layer 32 is formed, for example, of an indium gallium nitride (InGaN) film, however, for the calcium of the well layer 32 ( The ratio of indium (In ) of Ga) is appropriately set in accordance with the wavelength of light generated. In addition, as the barrier layer 31, an InGaN film having a smaller composition than the well layer 321η may be used. P-type semiconductor layer 4 may be a group III nitride-based semiconductor doped with a p-type dopant, such as a GaN layer, etc., and as a p-type impurity, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium may be used. (Ca ),铍( Be) 'Charcoal C), etc., in the following, the case where Mg is doped as a p-type dopant is exemplarily described. The p-type semiconductor layer 4 shown in Fig. 9 has a sequential layered yttrium nitride. The structure of the semiconductor layer 41, the second nitride-based semiconductor layer 42, the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44, which is doped with a P-type dopant and doped with Mg Examples of the film thickness and the Mg concentration of the nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 are as follows. (1) The first nitride-based semiconductor layer 41: film thickness = 50 nm, Mg concentration = 2x 1 020crrT3 -34- 200905931 (2) Second nitride-based semiconductor layer 42: film thickness = i 〇 0 nm, concentration = 4 x l 019 cn T3 (3) Third nitride-based semiconductor layer 43: film thickness = 4 Onm, Mg degree = lxl 0 2 0 cm·3 (4) Fourth nitride-based semiconductor layer 44: film thickness=i〇nm, Mg degree=8×1019cnT3 As described above, 'the P-type semiconductor layer is formed by supplying a source gas through a carrier gas not containing hydrogen. In the case of 4, M g is not activated by hydrogen ions taken in from the Mg, and the formation of the p-type semiconductor layer 4 is hindered, so that P-type semiconductor is formed. After the layer 4, it is necessary to remove the hydrogen atom and to form a p-type igniting fire in which the P-type semiconductor layer 4 is p-type. However, according to the manufacturing method of the nitride-based semiconductor device according to the second embodiment, When at least one of the first nitride-based semiconductor layer 41 to the fourth nitrogen-based semiconductor layer 44 is formed by supplying a source gas of Mg to a carrier gas containing no hydrogen, the p-type annealing process can be omitted, for example, The second nitride-based semiconductor layer 42 having a large thickness among the first nitride-based half layer 41 to the fourth nitride-based semiconductor layer 44 or the first nitride having a high Mg concentration is formed through the carrier gas containing no hydrogen. It is preferable that the semiconductor 41 is omitted, but the point of the p-type annealing process is omitted. On the other hand, the fourth nitride-based half layer 44 bonded to the p-side electrode 100 is preferably formed so that the crystal state is as good as possible, and the source gas of Mg is supplied through the carrier gas. a case where a raw material gas of Mg is supplied via a carrier gas containing hydrogen,

When Mg is concentrated and the original P is desubulted and the hydrogenation ratio of the chemically-conductive layer is -35-200905931, the crystal state of the nitride-based semiconductor layer in which Mg is added due to impurities is formed as compared with the case where it is formed by a carrier gas containing no hydrogen. It is better. In the following, a method of manufacturing a nitride-based semiconductor device according to the second embodiment will be described as an example of manufacturing a nitride-based semiconductor device shown in FIG. 9. However, the nitride-based semiconductor device described below will be described below. The manufacturing method is an example, and the modified example is exemplified by various manufacturing methods, and it is a matter of course that the p-type impurity is made of Mg, and the hydrogen is not exemplified. When the first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42' are formed by the carrier gas, the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44 are formed by the carrier gas containing hydrogen. . As a manufacturing method, GaN is grown on the sapphire substrate 1 by a known organometallic chemical vapor deposition method (MOCVD method), for example, after the substrate 1 is thermally washed, the substrate temperature is set to 1 〇〇〇. °C, on the substrate 1, as the n-type semiconductor layer 2, for example, a GaN film doped with Si at a concentration of about 3 X1 018 cm·3 is grown to a degree of 1 to 5 (four). At this time, trimethylgallium (TMG) is used. Ammonia (NH3) and formane (SiH4) are supplied as a material gas to form an n-type semiconductor layer 2. Next, for example, the barrier layer 31 formed of a GaN film and the well layer 32 formed of an InGaN film are alternately laminated, and the active layer 3 is formed on the n-type semiconductor layer 2, specifically, the active layer 3 is formed to be adjusted. At the same time, the substrate temperature and the flow rate of the material gas simultaneously alternately cause the barrier layer 31 and the well layer 3 2 band gap to grow into a large well layer 32, forming an active layer 3 formed by laminating the barrier layer 31 and the well layer 32. In the case where the active layer 3 is in the MQW structure, the project of stacking the barrier layer 31 and the well layer 32 by adjusting the substrate temperature and the flow rate of the material gas in the period of -36-200905931 is used as a unit project, and the unit project is The MQW structure of the alternating layered barrier layer 31 and the well layer 32 is obtained as η times 'for example, 8 times. 11 shows an example of the laminated barrier layer 31 and the well layer 32. The barrier layer 31 is formed by the substrate temperature Ta shown in FIG. 11, and the well layer 3 2 is formed by the substrate temperature Tb, that is, for setting the substrate temperature. At the time t1 to til of Ta, the first barrier layer 311 is formed, and then the substrate temperature is lowered to become the substrate temperature Tb at the time til ~ t 12', and the first well layer 3 is formed by the substrate temperature Tb at the time. 1, then, at time t13 to t20, the substrate temperature is raised to the substrate temperature Ta, and the second barrier layer 312 is formed at time t20 to t21. The same applies to the substrate temperature Ta and the substrate temperature Tb. The barrier layer 31 and the well layer 32 are alternately formed, and the n-th barrier layer 3 1 η is formed at the times tn0 to tn1, and the substrate temperature is lowered to the substrate temperature Tb ' at the time tn1 at the time tn 1 to tn2. Tn2, the nth well layer 32n is formed, and at the time tn3~teO, the substrate temperature is raised to become the substrate temperature Ta, and at the time te0 to tel, the final barrier layer 31 is formed to complete the active layer 3, however, at the substrate temperature Can be made in the warming or cooling 31 or 32 wells parietal layer growth, or growth were interrupted. The case where the barrier layer 31 is formed is used as a material gas, for example, TMG gas is supplied to the film formation at 300 sccm (standard cc/min) and NH 3 gas at a flow rate of 20 slm (standard L/min). The processing device, on the other hand, the formation of the well layer 3 2 as a raw material gas -37-200905931, for example, TMG gas, 300 sccm, trimethyl indium (TMI) gas, at a flow rate of 280 sccm, ΝΗ 3 The gas 'is supplied to the processing device by 2〇51111^1111', but the 'TMG gas system is used as the raw material gas of Ga atom, the TMI gas system is used as the raw material gas of In atom, and the NH3 gas system is used as nitrogen. The raw material gas of the atom is supplied. Next, on the active layer 3, a p-type semiconductor layer 4 doped with Mg as a P-type dopant is formed, as shown in FIGS. 12(a) and 12(b), which is referred to as a p-type semiconductor layer 4. An example of the conditions for laminating the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is as shown in Fig. 12(a), which is a temperature profile when the P-type semiconductor layer 4 is formed, as shown in Fig. 12 (b). The growth conditions of the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 are shown, and the substrate temperature Tp of the p-type semiconductor layer 4 is formed as shown in FIGS. 12(a) and 12(b). The system is set at a frequency of 800 to 90 (TC, pressure is commonly used in the range of 100 to 300 Torr, and Figures i2(a) and 12(b) show that the first nitride system is formed via a carrier gas not containing hydrogen. The semiconductor layer 41 and the second nitride-based semiconductor layer 42 are formed by the carrier gas containing hydrogen to form the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44. (Project 1) t 1, as a carrier gas, supplying N2 gas at a flow rate of 2 to 10 s 1 m, as a raw material gas, supplying nh3 gas, Tmg gas, dicyclopentanyl magnesium (Cp22Mg) gas, respectively. The first nitride-based semiconductor layer 41 is formed by the device, and the first nitride-based semiconductor layer 41 having a film thickness of 50 nm and a Mg concentration of 2×1〇2〇cnl-3 is formed at a time t0 to u. 38- 200905931 (Project 2) For the supply of n2 gas at a flow rate of 2 to 1 〇slm as a carrier gas at time t1 to t2, as a raw material gas, NH3 gas, gas, dicyclopentadienyl magnesium (CpJMg) Each of the gases 'is supplied to the buried device to form the second nitride-based semiconductor layer 42 and the time u to t2 is 21 minutes to form a second nitrogen having a film thickness = 10 nm and a Mg concentration = 4 x 1 〇 19 cm -3 . The compound semiconductor layer 42. (Engineering 3) The N gas is supplied as a carrier gas at a flow rate of 10 to 2 〇slm at a time t2 to t3, and the N2 gas is supplied at a k ® of 2 to 1 〇sim. As the source gas, each of the NH3 gas and the TMG gas 'CpjMg gas is supplied to the processing apparatus to form the third nitride-based semiconductor layer 43, and the time between the times t2 and t3 is set to 1 minute to form a film thickness of ~4 〇 nm. The third nitride-based semiconductor layer μ Mg (engineering 4) having a Mg concentration = lxl 〇 2 〇 cm -3 is a flow rate of 10 to 20 slm as a carrier gas at time U to t4 I to the gas, the gas flow 2~1〇slm% is supplied in the 'as the raw material gas, the NH3 gas, TMG gas,

Each of the Cps2 Mg gas is supplied to the processing apparatus to form a fourth nitride-based semiconductor layer (P-type layer) 44, and the time t3 to t4 is set to 3, and the film thickness is -1〇nm, and the Mg concentration is 8xl〇19cnr3. The fourth nitride-based semiconductor layer 44 工程 (Project 5) is for supplying the N 2 gas at a time of 2 〇 sim as a carrier gas at time t4 to t5, and the substrate temperature is from the temperature Tp ( 8 5 0 C The temperature is lowered to below the temperature T d (3 5 〇 it), for example, the temperature is lowered to room temperature 'that is, p-type annealing performed at 400 T: or more is not performed. -39-200905931 The p-type semiconductor layer 4 including the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is formed through the above-described processes 1 to 5', and the first nitride system having a high Mg concentration is used. The semiconductor layer 41 and the second nitride-based semiconductor layer 42 having a large thickness are formed by a carrier gas not containing H 2 gas. Therefore, even if P-type annealing is not performed, a P-type semiconductor layer can be obtained. The semiconductor layer 4 is formed by supplying a carrier containing H 2 gas, and the crystal state of the fourth nitride-based semiconductor layer 44 is improved, that is, bonding to the p-side electrode 1 of the p-type semiconductor layer 4 The crystal state of the surface is good, and the contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good. Then, the surface of the n-type semiconductor layer 2 is exposed and removed by reactive ion etching or the like, and the surface of the n-type semiconductor layer 2 is exposed to the surface of the n-type semiconductor layer 2, and then exposed to the n-type semiconductor. The surface of the layer 2 is formed by vapor deposition to form the n-side electrode 200, and the p-type semiconductor layer 4' is formed by vapor deposition to form the p-side electrode 1 〇〇, thereby completing the nitride-based semiconductor device shown in FIG. FIG. 13 shows a current If flowing from the p-side electrode 至 to the n-side electrode 200 for the case where the voltage V f is applied between the ρ-side electrode 丨〇〇 and the η-side electrode 200, for the figure 1 3 'Characteristic a is the if-vf characteristic in which the p-type semiconductor layer 4 is formed through the above-described items 1 to 5, and p-type annealing is not performed, and the characteristic B is formed by supplying a carrier gas containing h2. The If_vf special case of the p-type semiconductor layer 4 in the case of performing p-type annealing is understood from Fig. 13. Even if the p-type annealing is not performed, the forward voltage is equal to or lower than that in the case of performing p-type annealing. -40- 200905931. According to the nitride-based semiconductor device and the manufacturing method according to the second embodiment, the p-type semiconductor layer 4 is formed by supplying a carrier gas containing no H 2 gas, and the H 2 is not taken in together with the P-type impurity. In the case of the p-type semiconductor layer 4, it is not necessary to remove the H22 p-type annealing from the p-type semiconductor layer 4, and the manufacturing process of the nitride-based semiconductor device can be shortened. [Other Embodiments] As described above, the present invention has been described with reference to the first embodiment to the second embodiment. However, the description and drawings of one of the embodiments of the present invention are exemplified, and when the configuration of the invention is limited, It is incomprehensible, and it is clear from the disclosure that the various embodiments of the industry, the embodiments and the application techniques are clear. In the description of the above-described embodiment, the first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42' are formed by a carrier gas containing no hydrogen, and the carrier gas is formed by a carrier gas containing hydrogen. 3, in the case of the nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44, any portion of the p-type semiconductor layer 4 formed by a carrier gas not containing hydrogen may be arbitrarily set 'for example, may not be contained The i-th nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 are formed by the carrier gas of hydrogen, and only the fourth nitride-based semiconductor layer 44 is formed via the carrier gas containing hydrogen. Thus, the present invention encompasses various embodiments and the like not described herein. -41 - 200905931 [Industrial Example] The nitride-based semiconductor device of the present invention can be fully utilized in a nitride-based semiconductor device including an LED device of the quantum well structure, such as an LD device. Fig. 1 is a schematic cross-sectional structural view of a nitride-based semiconductor device according to a first embodiment of the present invention, (a) a schematic cross-sectional structural view of a nitride-based semiconductor device portion, and (b) an active layer portion Expand the schematic section structure diagram. (Fig. 2) is a schematic cross-sectional structural view of a nitride-based semiconductor device according to a modification of the first embodiment of the present invention, and (a) a schematic cross-sectional structural view of a nitride-based semiconductor device portion, (b) An enlarged schematic cross-sectional structural view of the active layer portion. (Fig. 3) is a schematic cross-sectional view showing the formation of the p-side electrode and the n-side electrode of the nitride-based semiconductor device according to the first embodiment of the present invention. FIG. 4 is a view showing the relationship between the light-emission output and the logarithm of the quantum well in the nitride-based semiconductor device according to the first embodiment of the present invention. FIG. 5 is a view for explaining the first aspect of the present invention. A schematic diagram of a frequency band structure of a light-emitting phenomenon in the MQW layer of a nitride semiconductor device of the embodiment. [Fig. 6] is a band structure for explaining the luminescence phenomenon in the MQW layer of the nitride-based semiconductor device according to the first embodiment of the present invention - 42-200905931, (a) the MQW layer is 5 pairs. Schematic diagram of the band structure' (b) Schematic diagram of the band structure in the case where the MQW layer is eight pairs, and (c) Schematic diagram of the band structure in the case where the MQW layer is 12 pairs. [ Fig. 7] (a) is a temperature distribution diagram for forming a p-type semiconductor layer (41 to 44) having a four-layer structure in the nitride-based semiconductor device according to the first embodiment of the present invention, (b) A diagram illustrating the conditions of hydrogen flow, (c) a diagram illustrating other conditions of hydrogen flow, (d) a diagram illustrating still other conditions of hydrogen flow, and (e) a diagram illustrating still other conditions of hydrogen flow. [Fig. 8] (a) is a temperature distribution diagram for forming a p-type semiconductor layer (4 1 to 44) having a four-layer structure in the nitride-based semiconductor device according to the first embodiment of the present invention. b) a diagram illustrating the conditions of nitrogen flow, and (c) a diagram illustrating the conditions of ammonia flow. [Fig. 9] is a schematic view showing an example of a nitride-based semiconductor device manufactured by a method of manufacturing a nitride-based semiconductor device according to a second embodiment of the present invention. [Fig. 10] Fig. 10 is a schematic view showing a structural example of an active layer of a nitride-based semiconductor device manufactured by a method for producing a nitride-based semiconductor device according to a second embodiment of the present invention. [Fig. Π] is a gas flow pattern diagram showing growth of crystals in the active layer shown in Fig. 1 . (Fig. 12) is a view for explaining a method of manufacturing a nitride-based semiconductor device according to a second embodiment of the present invention, and (a) is a temperature cross-sectional view showing the formation of a p-type semi-43-200905931 conductor layer, ( b) shows a table of growth conditions of the p-type semiconductor layer. [Fig. 13] is an I-V characteristic diagram showing a current flowing from the side electrode to the n side electrode in a case where a voltage is applied between the p-side electrode and the n-side electrode. [Main component symbol description] 1 : Substrate 2 : n-type semiconductor layer 3 : active layer 4 : p-type semiconductor layer 5 = oxide electrode 6 · 'buffer layer 7 : barrier layer 3 1 : barrier layer (GaN layer) 32 Well layer (InGaN layer) 41: First nitride-based semiconductor layer 42: Second nitride-based semiconductor layer 43: Third nitride-based semiconductor layer 44: Fourth nitride-based semiconductor layer 1 〇〇: P-side electrode 2 0 0 : η side electrode 3 1 〇: final barrier layer 3 1 1~3 1 η : barrier layer -44- 200905931

Claims (1)

200905931 X. Patent Application No. 1. A nitride-based semiconductor device characterized by having an active layer formed of a plurality of quantum wells, and a P-type impurity-based semiconductor layer disposed on the upper portion of the active layer, and disposed in the foregoing a second nitride-based semiconductor layer containing a p-type impurity having a low P-type impurity concentration in the first nitride-based semiconductor layer, and a second nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer, including the second a third nitride-based semiconductor layer having a p-type impurity concentration of p-type impurity in the nitride-based semiconductor layer and a third-type nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer, wherein the concentration of the p-type impurity containing the third nitride-based semiconductor layer is low The fourth nitride-based semiconductor layer of p. 2. The nitride-based semiconductor according to the first aspect of the invention, wherein the thickness of the second nitride-based semiconductor layer is higher than that of the precursor-based semiconductor layer or the third nitride-based semiconductor layer and the fourth nitride-based semiconductor The thickness of the layer is formed by the thickness. The nitride device according to claim 1 or 2, further comprising a transparent electrode formed of the oxide electrode disposed on the fourth nitride layer. 4. The nitride-based semiconductor of claim 3, wherein the transparent electrode comprises ZnO 'ITO or contains indium, and the first nitrogen containing indium has a lower impurity than the foregoing type of impurity. There is a device of the above-described type of impure object, the first nitrogen or the semiconductor system of the above-mentioned system, and the ZnO-46 - 200905931 5 - the nitride-based semiconductor device of the third aspect of the patent application 'where the 'transparent The electrode contains either zn〇, ITO or ZnO containing indium as the impurity concentration lx 1019~5xl021cnT3. 6. The nitride-based semiconductor device according to any one of claims 1 to 5, wherein the first to fourth nitride-based semiconductor layers are all based on G aN ' via 80 ° C to 9 0 0. (The formation of low temperature growth is: 7. A nitride semiconductor device characterized by comprising an active layer formed of a plurality of quantum wells containing indium, and a first nitride containing p-type impurities disposed on the upper portion of the active layer a semiconductor layer, and a second nitride-based semiconductor layer which is disposed on the first nitride-based semiconductor layer and contains a p-type impurity having a lower P-type impurity than the first nitride-based semiconductor layer, and is disposed on the surface The nitride-based semiconductor device according to the seventh aspect of the invention, wherein the transparent electrode comprises ZnO, IT◦ or indium. 9. The nitride-based semiconductor device according to claim 7, wherein the transparent electrode comprises Ga or A1' as an impurity concentration of 1 X 10 19 to 5 x 10 2 km 3 Any one of ZnO, ITO or ZnO containing indium added. i. The nitride device of any one of the seventh to the ninth to the ninth aspect of the invention is a semiconductor device, wherein the former Each of the first and second nitride-based semiconductor layers is formed by a low temperature growth of 800 t to 900 according to GaN. 11 A method for producing a nitride-based semiconductor device, which is characterized in that an n-type is formed. Engineering of a semiconductor layer, and engineering of forming an active layer on the n-type semiconductor layer, and engineering of forming a p-type semiconductor layer by laminating a plurality of nitride-based semiconductors each containing a p-type dopant on the active layer And a method of producing a nitride-based semiconductor device according to the first aspect of the invention, wherein the method of manufacturing the nitride-based semiconductor device according to the first aspect of the invention, wherein The carrier gas containing hydrogen is supplied to the source gas to form a part of the plurality of nitride-based semiconductor packages. The method for producing a nitride-based semiconductor device according to the first aspect of the invention is further included On the p-type semiconductor layer, the structure of the ?-side electrode is combined with the aforementioned side of the plurality of nitride-based semiconductor layers. The nitride-based semiconductor package in which the electrode is bonded is formed by supplying the source gas through a carrier gas containing hydrogen. 1 4. A method of manufacturing a nitride semiconductor device according to any one of claims n to 13 Wherein the foregoing active layer, the alternating layer barrier layer and the well layer having a smaller band gap than the barrier layer are formed. 1 5 · The nitrogen of any of the items n to 4 of the patent application scope In the method of manufacturing a semiconductor device, the n-type semiconductor, the active layer, and the p-type semiconductor layer are formed of a cerium nitride semiconductor. -48- 200905931 1 6 . The method for producing a nitride-based semiconductor device according to any one of item 1, wherein the P-type dopant is a magnesium-49-