200905832 九、發明說明： 【發明所屬之技術領域] 本發明係有關於半導體封裝構造之立體堆疊技術， 特別係有關於一種多杈體之可堆疊半導體封裝構造，可 運用於高密度封裝堆疊模組的架構（Package_ Package module, POP) 〇 【先前技術】 隨著電子產品的微小化發展趨勢，印刷電路板表面 可供設置半導體封裝構造的面積越來越小。故有一種半 導體封裝構造之立體堆疊技術，是將複數個可堆疊半導 體封裝構造相互堆疊一起，成為封裝堆疊模組 (Package-On-Package module, POP)» 以符合小型表面接 合面積與高密度元件設置之要求。然而，銲接缺陷在封 裝堆疊之接合過程中是一大問題’封裝構造之微間距端 子與端子之間的銲接界面更容易受到應力而產生斷 裂，導致電性斷路。 富士通（Fujitsu)公司於美國專利第6476503以及泰 斯拉（Tessera)公司於美國專利公開第2006/0138647號 各提出一種可應用於封裝堆疊之微接觸架構，利用柱狀 或針狀的凸塊銲接至銲料内。 請參閱第1圖所示’一種習知可堆疊半導體封裝構 造1 00主要包含一晶片載體1 1 0、一晶片i 20以及複數 個單柱凸塊1 30。該晶片載體11〇係具有一上表面丨丨丨與 一下表面11 2，其中該上表面111係設有複數個轉接墊丨丨3， 200905832 該下表面112係設有複數個外接墊丨丨4。該晶片12〇係設置 該晶>1載體110，並利用複數個銲線121通過該晶片載體110 之打線槽孔11 5電性連接至該晶片載體丨丨〇，並以一封膠體 140密封該些銲線1 21。該些單柱凸塊丨3〇係對應設置於該 些外接墊114，連接在每一外接墊上11 4上是一個單柱凸塊 Π0。並利用銲料150銲接至下方可堆疊半導體封裝構造 100之轉接墊113，藉以達到微接觸之型態，可增加訊號 接腳數（highpin count)並可增加走線面積，更可以縮小 封裝堆疊間隙（small POP stacking stand〇ff) 〇 然而，對於應力抵抗性會變得較為敏感，當應力產生在 該些單柱凸塊1 3 0之銲接界面時，裂縫會沿著該些單柱凸塊 1 3 0之表面擴張，導致電性斷路。此外，在封裝堆疊時，應 回銲上述銲料15〇,銲料15〇變得具有流動性，一旦該晶片 載體10之—曲或是壓合力0不平均。鲜料會溢流 擴散，導致該些單柱凸& 130之間的微接觸接點為橋接短 路。 【發明内容】 一本發明之主要目的係在於提供一種多柱體之可堆疊 半導體封裝構造，每—外接墊上設置之凸塊組係、由複數 :導體柱所組成，能增加銲料接合面積，達成較高的產 -耐用度。此外’能使凸塊組之銲接界面形狀複雜化， 藉以降低裂縫成長可能。 、本發明之次一目的係在於提供一種多柱體之可堆疊 半導體封裴構造，每一外接墊上設置之凸塊組具有銲料 6 200905832 填入間隙，可使銲料填入並收藏在凸塊組内’即使基板 傾斜或輕曲仍不會擠壓銲料導致橋接短路。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種多柱體之可堆疊半導體 封裝構造主要包含一晶片載體、一晶片以及複數個下凸塊 組。該晶片載體係具有一上表面與一下表面，其中該上表面 係設有複數個轉接墊，該下表面係設有複數個外接墊。該晶 片係叹置並電性連接至該晶片載體。該些下凸塊組係對應設 置於忒些外接墊，連接在每一外接墊上的下凸塊組係由複數 個導體柱所組成，在同_下凸塊組之相鄰導體柱之間係形成 有料填入間隙。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現 在剛述之可堆疊半導體封裝構造中，該銲料填入間 隙係可由相鄰導體柱之頂面往底部收斂。 ί 在前述之可堆疊半導體封裝構造中，同一下凸塊組 之導體柱係可為矩陣排列。 在前述之可堆疊半導體封裝構造中，每一下凸塊組 係可包含一中央導體柱以及複數個周邊導體柱。 在前述之可堆疊半導體封裝構造中，可另包含有複 數個上凸塊組，其係對應設置於該些轉接墊，連接在每 一轉接墊上的上凸塊組係由複數個導體柱所組成，在同 上凸塊組之相鄰導體柱之間係形成有銲料填入間隙。 在前述之可堆疊半導體封裝構造中，每—上凸塊組 7 200905832 之導體柱係可與縱向對應之下凸塊組之導體柱為 配置。 在前述之可堆疊半導體封裝構造中，該些上凸 之相鄰導體柱之銲料填入間隙係可輿對應下凸塊 相鄰導體柱之銲料填入間隙為相等且垂直。 在前述之可堆疊半導體封裝構造中，該晶片載 可為一多層印刷電路板。 在前述之可堆疊半導體封裝構造中，該晶片載 可具有一打線槽孔，並以複數個銲線通過該打線槽 性連接該晶片與該晶片載體。 在前述之可堆疊半導體封裝構造中，可另包含 封膠體，其係形成於該打線槽孔並突出於該下表面 密封該些銲線。 在前述之可堆疊半導體封裝構造中，該晶片之 動面係可貼設於該晶片載體之該上表面。 在前述之可堆疊半導體封裝構造中，該晶片之 面係可顯露於該晶片載體之該上表面。 在前述之可堆疊半導體封裝構造中，該晶片係可 於該晶片載體之該下表面，該些下凸塊組係排列於該晶 側邊。 在前述之可堆疊半導體封裝構造中，該晶片之一 係可顯露於該晶片載體之該下表面。 在前述之可堆疊半導體封裝構造中，可另包含有 耦合元件，其係形成於該晶片之顯露背面。 交錯 塊組 組之 體係 體係 孔電 有一 ，以 一主 一背 設置 片之 背面 献 8 200905832 在前述之可堆疊半 私现甘产 導體封裝構造中，可另包含有一密 封勝，其係形成於該晶3有 乂 執體之该下表面。 隹刖述之可堆疊 ^ 體封裝構造中，該些導體柱係可 '、有頂乍底寬之梯形戴面。 【實施方式】 依據本發明之第一i 奋 ±4 ^ ^ ^ 、體λ施例，揭示一種多柱體之 可堆豐+導體封裝構造。 請參閱第2圖所示 ^ ^ ,πη . ^ ^ 其係為兩顆可堆疊半導體封裝 構造200之堆疊組合 不受限地，可在往上堆疊更多 顆可堆疊半導體封裝構 受夕 — k 2〇〇，如三顆、四顆或更多。 母一可堆疊半導體封裝 構龟200主要包含一晶片載體 2 1 〇、一晶片2 2 0以及複齡柄 ^ 數個下凸塊組230。該晶片載體210 係可為一多層印刷電路 电路板’具有雙面電性導通之結構。 該晶片載體210係具有一上表面m與-下表面212’其 中該上表面211係設有複數個轉接墊213，可作為該晶片載 體210之第一墊，該下表面212係設有複數個外接塾214 可作為該晶片載體21〇之第二塾。 該晶片220係設置並電性連接至該晶片載體2 i 0，例如， 可以利用黏晶材料將該晶片220之主動面貼設在該晶片載體 2 1 0之該上表面2 1 1 ’再以打線形成之銲線2 2 1將該晶 片220之銲墊電性連接至該晶片載體2 1 0之内接指（圖未繪 出）。在本實施例中，該晶片載體2 1 0係可具有一打線 槽孔2 1 5，並以該些銲線22 I通過該打線槽孔2 1 5電性 連接該晶片220與該晶片載體210。該晶片220之一背 9 200905832 面則可顯露於該晶片载體21〇之該上表面2ΐι。在不同 實施例中，該晶片220可利用凸塊（圖未繪出）覆晶接合至該 晶片載體210，達到晶片設置與電性連接之目的。 在本實施例之具體架構中，該可堆疊半導體封裝構造 200可另包含有一封膠體24〇 ’以壓模或點膠方式，形 成於該打線槽孔215並可突出於該下表面212，以密封 該些銲線2 2 1。 ( β亥些下凸塊組230係對應設置於該些外接墊214,即每一 外接塾214上連接有_下凸塊組23Q。如第3圖所示，連接 在每外接I 214上的下凸塊組23〇係由複數個導體柱 23 232所組成，在本實施例中，每—下凸塊組係可 匕3中央導體柱23 1以及複數個周邊導體柱232，利 用/中央導體柱231可以確保該些周邊導體柱232之間 ’.、不會過A而與该中央導體柱2 3 i達到等距微間隙。 忒些導體柱231、232可為電鍍形成之銅柱、打線形成之金 柱、钱刻厚銅層所形成之銅柱、或其它金屬柱體。較佳地， 5卜下凸塊組230之導體柱231、232係可為矩陣排列。 第4B圖所不，在同一下凸塊組之相鄰導體柱 231、232之間係形成有銲料填入間隙S1或S2。其中，銲料 真、門隙S1為相鄰導體柱231、232之頂面距離；鲜料填入 間隙S 2為相_導h n 。n ,, 柱23 1、232之底部距離。較佳地，該銲 料填入間隙係可由相鄰導體柱231、232之頂面往底部收 P輝料填人間隙S 1大^銲料填人間隙S2。藉由毛細 現象’在回銲溫度時可將具流動性之銲料25〇填入並收 10 200905832200905832 IX. Description of the Invention: [Technical Field] The present invention relates to a three-dimensional stacking technology for a semiconductor package structure, and more particularly to a multi-body stackable semiconductor package structure that can be applied to a high-density package stacking module Package (Package_ Package module, POP) 〇 [Prior Art] With the trend toward miniaturization of electronic products, the area of printed circuit board surfaces that can be used to set up semiconductor package structures is getting smaller and smaller. Therefore, there is a three-dimensional stacking technology of a semiconductor package structure in which a plurality of stackable semiconductor package structures are stacked on each other to form a package-on-package module (POP) to conform to a small surface joint area and a high-density element. Requirements for setup. However, soldering defects are a major problem in the bonding process of the package stack. The solder interface between the micro-pitch terminals and the terminals of the package structure is more susceptible to stress and breaks, resulting in an electrical break. Fujitsu Corporation, U.S. Patent No. 6,476, 503, and Tessera, U.S. Patent Publication No. 2006/0138647, each of which is incorporated herein by reference. Into the solder. Referring to Fig. 1, a conventional stackable semiconductor package structure 100 mainly includes a wafer carrier 110, a wafer i20, and a plurality of single pillar bumps 130. The wafer carrier 11 has an upper surface and a lower surface 11 2, wherein the upper surface 111 is provided with a plurality of transfer pads 3, 200905832. The lower surface 112 is provided with a plurality of external pads. 4. The wafer 12 is provided with the crystal > 1 carrier 110, and is electrically connected to the wafer carrier 通过 through the wire slot 11 5 of the wafer carrier 110 by a plurality of bonding wires 121, and sealed by a gel 140. The bonding wires 1 21 . The single-column bumps 3 are correspondingly disposed on the external pads 114, and are connected to each of the external pads 114 as a single-column bump Π0. And solder 150 is soldered to the transfer pad 113 of the lower stackable semiconductor package structure 100, thereby achieving the micro contact type, which can increase the number of signal pins (highpin count) and increase the trace area, and can also reduce the package stack gap. (small POP stacking stand〇ff) However, it becomes more sensitive to stress resistance. When stress is generated at the welding interface of the single-column bumps 130, the cracks will follow the single-column bumps 1 The surface expansion of 30 causes an electrical disconnection. Further, in the case of package stacking, the above solder 15 turns back, and the solder 15 turns into fluidity once the wafer carrier 10 is bent or the pressing force 0 is not uniform. The fresh material will overflow and spread, resulting in the micro-contact between the single-column & 130 being a bridging short circuit. SUMMARY OF THE INVENTION A main object of the present invention is to provide a multi-column stackable semiconductor package structure, each of which is provided with a bump set on the external pad, which is composed of a plurality of conductor posts, which can increase the solder joint area and achieve Higher production - durability. In addition, the shape of the welding interface of the bump group can be complicated, thereby reducing the possibility of crack growth. A second object of the present invention is to provide a multi-column stackable semiconductor package structure, the bump set provided on each external pad has solder 6 200905832 filled in the gap, and the solder can be filled and stored in the bump set. Inside 'even if the substrate is tilted or lightly bent, it will not squeeze the solder and cause a bridge short circuit. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-column stackable semiconductor package structure mainly comprises a wafer carrier, a wafer, and a plurality of lower bump groups. The wafer carrier has an upper surface and a lower surface, wherein the upper surface is provided with a plurality of transfer pads, and the lower surface is provided with a plurality of external pads. The wafer is slanted and electrically connected to the wafer carrier. The lower bump groups are correspondingly disposed on the plurality of outer pads, and the lower bump group connected to each of the outer pads is composed of a plurality of conductor columns, and is adjacent between adjacent conductor columns of the same lower bump group A material is formed to fill the gap. The object of the present invention and solving the technical problems can be further achieved by the following technical measures. In the stackable semiconductor package construction just described, the solder fill gap can be converged from the top surface of the adjacent conductor post to the bottom. In the foregoing stackable semiconductor package construction, the conductor pillars of the same lower bump group may be arranged in a matrix. In the foregoing stackable semiconductor package construction, each of the lower bump assemblies may include a central conductor post and a plurality of peripheral conductor posts. In the foregoing stackable semiconductor package structure, a plurality of upper bump groups may be further included, which are correspondingly disposed on the transfer pads, and the upper bump groups connected to each of the transfer pads are composed of a plurality of conductor posts. The composition is such that a solder filling gap is formed between adjacent conductor posts of the same bump group. In the foregoing stackable semiconductor package construction, the conductor post of each of the upper bump groups 7 200905832 can be configured with the conductor posts of the bump groups below the longitudinal direction. In the foregoing stackable semiconductor package structure, the solder fill gaps of the adjacent adjacent conductor posts may be equal and perpendicular to the solder fill gaps of the adjacent bumps of the lower bumps. In the aforementioned stackable semiconductor package construction, the wafer carrier can be a multilayer printed circuit board. In the foregoing stackable semiconductor package construction, the wafer carrier may have a wire slot, and the wire and the wafer carrier are connected by the wire bonding wire by a plurality of bonding wires. In the foregoing stackable semiconductor package structure, an encapsulant may be further formed on the wire slot and protrudes from the lower surface to seal the bonding wires. In the foregoing stackable semiconductor package construction, the moving surface of the wafer can be attached to the upper surface of the wafer carrier. In the foregoing stackable semiconductor package construction, the face of the wafer may be exposed on the upper surface of the wafer carrier. In the foregoing stackable semiconductor package construction, the wafer is on the lower surface of the wafer carrier, and the lower bump groups are arranged on the crystal side. In the aforementioned stackable semiconductor package construction, one of the wafers may be exposed on the lower surface of the wafer carrier. In the foregoing stackable semiconductor package construction, a coupling element may be further included, which is formed on the exposed back surface of the wafer. The system of the interleaved block group has one hole, and the back side of the main piece and one back set piece is provided. 200905832 In the foregoing stackable semi-private carbon product conductor package structure, a seal may be further included, which is formed in the The crystal 3 has the lower surface of the body. In the stackable structure of the body package, the conductor pillars can have a trapezoidal wear with a top and a bottom width. [Embodiment] According to the first embodiment of the present invention, a multi-column stackable + conductor package structure is disclosed. Please refer to Fig. 2 ^ ^ , πη . ^ ^ which is a stacking combination of two stackable semiconductor package structures 200. Unrestricted stacking of more stackable semiconductor packages can be carried out 2〇〇, such as three, four or more. The mother-stackable semiconductor package turtle 200 mainly comprises a wafer carrier 2 1 〇, a wafer 2 2 0 and a plurality of lower bump groups 230. The wafer carrier 210 can be a multilayer printed circuit board having a double-sided electrically conductive structure. The wafer carrier 210 has an upper surface m and a lower surface 212'. The upper surface 211 is provided with a plurality of transfer pads 213 as a first pad of the wafer carrier 210. The lower surface 212 is provided with a plurality of pads An external port 214 can serve as the second port of the wafer carrier 21〇. The wafer 220 is disposed and electrically connected to the wafer carrier 2 i 0 . For example, the active surface of the wafer 220 may be pasted on the upper surface 2 1 1 ' of the wafer carrier 210 by using a die bonding material. The bonding wire formed by the wire 2 2 1 electrically connects the pad of the wafer 220 to the internal finger of the wafer carrier 2 1 0 (not shown). In this embodiment, the wafer carrier 210 can have a wire slot 2 1 5 , and the wire 220 and the wafer carrier 210 are electrically connected to the wafer carrier 210 through the wire slot 22 1 . . One of the back faces of the wafer 220, 200905832, can be exposed on the upper surface 2 of the wafer carrier 21〇. In various embodiments, the wafer 220 can be flip-chip bonded to the wafer carrier 210 by bumps (not shown) for wafer placement and electrical connection. In the specific structure of the embodiment, the stackable semiconductor package structure 200 may further include a glue body 〇 'in a die or a dispensing manner, formed in the wire slot 215 and protrudes from the lower surface 212 to The wire bonds 2 2 1 are sealed. The β-lower bump group 230 is correspondingly disposed on the external pads 214, that is, each of the external ports 214 is connected with a lower bump group 23Q. As shown in FIG. 3, it is connected to each external I 214. The lower bump group 23 is composed of a plurality of conductor posts 23 232. In this embodiment, each of the lower bump groups can be a central conductor post 23 1 and a plurality of peripheral conductor posts 232, using / central conductor The pillars 231 can ensure that the peripheral conductor pillars 232 are '., do not pass A and reach the equidistant micro-gap with the central conductor pillars 2 3 i. The conductor pillars 231 and 232 can be copper pillars formed by electroplating and wire bonding. The formed gold pillar, the copper pillar formed by the thick copper layer, or other metal cylinders. Preferably, the conductor pillars 231, 232 of the lower bump group 230 may be arranged in a matrix. A solder fill gap S1 or S2 is formed between the adjacent conductor posts 231, 232 of the same lower bump group. The solder true, the gate gap S1 is the top surface distance of the adjacent conductor pillars 231, 232; The fill gap S 2 is the phase _ hn 。 n, the bottom distance of the pillars 23 1 , 232. Preferably, the solder fill gap can be adjacent The top surface of the body columns 231, 232 is filled with a P-filling gap S 1 large ^ solder filling gap S2. By capillary phenomenon 'at the reflow temperature, the flowable solder 25 can be filled in and collected. 10 200905832
藏在該些導體柱231，之間的薛料填入間隙sus2 内’不會有受擠壓往外溢流之問題。銲料25〇係銲接一 車乂上方可堆疊半導體封裝構造200之該些外接墊214上 之下凸塊組230與較下方可堆疊半導體封農…00之 轉接墊2U，達到半導體封裝堆疊(叫因此，在一 具體結構中，該些導體柱23卜232係具有頂窄底寬之梯形 截面’如半圓錐體形或半方錐體形。依正負光阻的選擇與飯 刻液的調配可利用過度曝光、不㈣光或不^刻的技術， 以具體製成該些導體柱2S1、2S2的形狀。 通常該些銲料250係可為無錯銲劑，以錫96 5%_銀 3/0-銅0.5%之銲料而言，在到達回銲溫度約攝氏7度 以上，最高溫約為攝氏245度時能產生焊接之濕潤性。 而該些導體柱23丨、232則係可為銅柱、金柱或是具有熔 點高於上述回銲溫度之金屬。 因此，利用該些下凸塊組230增加了銲料25〇接合面 積與接合形狀複雜度，達成較高的銲接可靠度並降低裂 縫（crack)成長可能。即使在應力作用下，有其中一周邊 導體柱232與銲料250斷裂，但只要是中央導體柱23ι 或其餘導體柱23 2仍與銲料250保持焊接’則不會有斷 裂斷路的問題，提高了封裝堆疊（P0P)的產品耐用度。 依據本發明之第二具體實施例，揭示另一種半導體 封裝堆疊裝置，請參閱第5圖所示，該可堆疊半導體封 裝構造300主要包含一晶月載體310、—晶片32〇以及複數 個下凸塊組3 3 〇，與第一實施例大致相同。但該可堆疊半導 200905832 體封裝構造300另包含有複數個上凸塊組34〇。 該晶片載體3 10係具有-上表面3U輿—下表面川， 其^該上表面川係設有複數個轉接塾313，該下表面312 係设有複數個外接墊3 j 4。哕曰 ^ °亥曰日片320係設置並電性連接至 該晶片載體31(^該些下凸塊組33 J υ诔對應設置於該些外接 墊314，連接在每一外接墊上314的 下凸塊、，且3 3 0係由複數 個導體柱331所組成，在同一下凸诗 塊組330之相鄰導體柱331 之間係形成有銲料填入間隙S3， M供知科360之填入與容 藏0 第5及6圖所不，該些上凸塊組340係對應設置 於該些轉接墊3 1 3，遠技A** 关墊”3連接在母_轉接墊313上的上凸塊 ，，且34〇係由複數個導體柱 所組成。在同一上凸塊組 340之相鄰導體柱341之 J J 了死^成有銲料填入間隙 4。較佳地’每—上凸塊組34()之導體柱川係可與縱 向對應之下凸塊組330之導體柱331為交錯配置，具有 齒接扣合之功效。而上凸塊組34〇之相鄰導體柱341之 辉料填入間隙S4可與下凸塊組33〇之相鄰導體柱331 之銲料填人間隙S3為等距Μ直。因此，當該些可堆 疊半導體封裝構造3GG相互堆疊，銲料⑽連接對應之下凸 塊組330與上凸塊組34〇,具有更大的銲接面積與更複 雜的銲接形狀’以增加封裝堆疊產αΜρ〇ρ 的焊 接點可靠性’並可防止銲料36〇之溢流。 本發明之第三具體實施例請參閱第7圖，複數個可 堆疊半導體封裳㈣400相互堆疊在一印刷電路板1〇 12 200905832 上。該可堆疊半導體封裝構造400主要包含一晶片載體 4 1 〇、一晶片420以及複數個下凸塊組43〇。該晶片載體4 1 0 係具有一上表面411與一下表面412。其中，該上表面411 係設有複數個第一墊41 3，如轉接墊。該下表面4丨2係設有 複數個第二墊414 ,如外接墊。在本實施例中，該晶片42〇 具有複數個凸塊42 1 ’利用覆晶接合技術，該些凸塊42 1能 令該晶片420設置並電性連接至該晶片載體4丨〇。並能以一 如底部填充膠之封膠體440密封該些凸塊42 1。 在本實施例中，該晶片420設置於該晶片載體41〇之該 下表面412 ’即該些下凸塊組430係排列於該晶片42〇之側 邊，故該晶片載體410之該上表面411為平坦狀，不易於碰 傷該晶片420與該些下凸塊組43〇。較佳地，該晶片42〇之 —背面係顯露於該晶片載體4 i 〇之該下表面4丨2，以利散熱。 該些下凸塊組430係對應設置於該些第二墊414，連接在 每一第二墊414上的下凸塊組430係由複數個導體柱43丨所 組成’在同一下凸塊組43〇之相鄰導體柱43丨之間係形成有 銲料填入間隙，以捉附銲料45〇。 再如第7圖所示，當複數個可堆疊半導體封裝構造4〇〇 相互堆疊在一印刷電路板1 〇上，較佳地，每一可堆疊 半導體封裝構造400另包含有一熱耦合元件460，如導熱 介面物質（Thermal Interface Material，TIM)或散熱膏，其係 形成於該晶片420之顯露背面，可熱耦合至該印刷電路板i 〇 或下方之可堆疊半導體封裝構造4〇0之晶片載體41〇， 以均勻散熱。在一更詳細的具體結構中，每一可堆疊半 200905832 導體封裝構造4GG係另包含有—密封谬47G，如底部填充 膠，其係形成於該晶片載體410之該下表面412，以密封該 些銲料450與該晶片42〇,避免塵埃落入或沉積在封裝堆疊 間隙（POP gap)，消除可能的污染或電性短路。 以上所述，僅是本發明的較佳實施例而已，並非對 本毛明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 p利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、#同變化與修飾，均仍屬於本發明技術方案^ 範圍内。 >' 、 【圖式簡單說明】 第1圖：習知多個可堆疊半導體封裝構造之載面示音 圖。 〇 第2圖：依據本發明之第一具體實施例，—種多柱體之 可堆疊半導體封裝構造相互堆疊之截面示章 圖。 第3圖：依據本發明之第一具體實施例，該可堆疊半導 體封裝構造之下凸塊組之立體示意圖。 第4A與4B圖：依據本發明之第一具體實施例，在該 可堆疊半導體封裝構造中一下凸塊組之複數 個導體柱之頂面與底部比對示意圖。 第5圖：依據本發明之第二具體實施例，另一種多柱體 14 200905832 之可堆疊半導體封裝構造相互堆疊之截面示 意圖。 第6圖：依據本發明之第二具體實施例，該可堆疊半導 體封裝構造之上凸塊組對應下凸塊組之導體 柱錯位關係之示意圖。 第7圖：依據本發明之第三具體實施例，複數個多柱體It is hidden in the conductor posts 231, and the Xue material is filled into the gap sus2. There is no problem of being squeezed out. Solder 25 is soldered to a truss above the stack of semiconductor pads 200 of the semiconductor package structure 200, and the bump set 230 and the lower stackable semiconductor package 00 are connected to the semiconductor package stack (called Therefore, in a specific structure, the conductor pillars 23 and 232 have a trapezoidal cross section of a narrow bottom width, such as a semi-conical shape or a semi-pyramid shape. The selection of positive and negative photoresists and the preparation of the rice engraving can be utilized excessively. Exposure, no (four) light or non-engraving technology to specifically form the shape of the conductor posts 2S1, 2S2. Usually these solders 250 can be error-free flux, with tin 96 5% _ silver 3 / 0 - copper For 0.5% solder, the wettability of the weld can be produced when the reflow temperature reaches about 7 degrees Celsius and the highest temperature is about 245 degrees Celsius. The conductor posts 23丨 and 232 can be copper pillars and gold. The pillars are either metal having a melting point higher than the reflow temperature described above. Therefore, the use of the lower bump sets 230 increases the joint area of the solder 25 and the joint shape complexity, achieving higher welding reliability and reducing cracks. Growing up. Even under stress, there is A peripheral conductor post 232 is broken from the solder 250, but as long as the central conductor post 23i or the remaining conductor post 23 2 remains soldered to the solder 250, there is no problem of breakage and breakage, which improves the product durability of the package stack (P0P). According to a second embodiment of the present invention, another semiconductor package stacking device is disclosed. Referring to FIG. 5, the stackable semiconductor package structure 300 mainly includes a crystal carrier 310, a wafer 32, and a plurality of lower layers. The bump set 3 3 〇 is substantially the same as the first embodiment. However, the stackable semi-conductive 200905832 body package structure 300 further includes a plurality of upper bump groups 34. The wafer carrier 3 10 has an upper surface 3U舆- the lower surface of the river, the upper surface of the Chuan system is provided with a plurality of transfer rafts 313, the lower surface 312 is provided with a plurality of external mats 3 j 4 . 哕曰 ^ ° 曰 曰 片 片 320 sets and electrical Connected to the wafer carrier 31 (the lower bump groups 33 J υ诔 are correspondingly disposed on the external pads 314 , the lower bumps connected to each of the external pads 314 , and the 3 3 0 is composed of a plurality of conductor posts 331 consists of the same lower convex group A solder fill gap S3 is formed between adjacent conductor posts 331 of 330, M is filled and filled by Zhike 360. No. 5 and FIG. 6, the upper bump groups 340 are correspondingly disposed on the Some of the transfer pads 3 1 3 , the far-reaching A ** pads 3 are connected to the upper bumps on the mother _ transfer pads 313, and the 34 turns are composed of a plurality of conductor posts. The JJ of the adjacent conductor post 341 of 340 is filled with solder to fill the gap 4. Preferably, the conductor column of each of the upper bump group 34() can be a conductor of the bump group 330 corresponding to the longitudinal direction. The posts 331 are in a staggered configuration and have the effect of a snap fit. The glow filling gap S4 of the adjacent conductor post 341 of the upper bump group 34 is equidistant from the solder filling gap S3 of the adjacent conductor post 331 of the lower bump group 33〇. Therefore, when the stackable semiconductor package structures 3GG are stacked on each other, the solder (10) is connected to the corresponding lower bump group 330 and the upper bump group 34, having a larger soldering area and a more complicated soldering shape to increase the package stack. The solder joint reliability of αΜρ〇ρ can prevent the overflow of the solder 36. Referring to Figure 7 of the third embodiment of the present invention, a plurality of stackable semiconductor packages (four) 400 are stacked on each other on a printed circuit board 1 〇 12 200905832. The stackable semiconductor package structure 400 mainly includes a wafer carrier 4 1 , a wafer 420 and a plurality of lower bump groups 43 . The wafer carrier 410 has an upper surface 411 and a lower surface 412. The upper surface 411 is provided with a plurality of first pads 41 3 , such as an adapter pad. The lower surface 4丨2 is provided with a plurality of second pads 414, such as external pads. In the present embodiment, the wafer 42 has a plurality of bumps 42 1 ' using flip chip bonding techniques, and the bumps 42 1 enable the wafer 420 to be disposed and electrically connected to the wafer carrier 4 . The bumps 42 1 can be sealed with a sealant 440 such as an underfill. In this embodiment, the wafer 420 is disposed on the lower surface 412 of the wafer carrier 41, that is, the lower bump groups 430 are arranged on the side of the wafer 42, so the upper surface of the wafer carrier 410. 411 is flat and does not easily damage the wafer 420 and the lower bump groups 43. Preferably, the back surface of the wafer 42 is exposed on the lower surface 4丨2 of the wafer carrier 4i to facilitate heat dissipation. The lower bump groups 430 are correspondingly disposed on the second pads 414, and the lower bump groups 430 connected to each of the second pads 414 are composed of a plurality of conductor posts 43 ' 'in the same lower bump group A solder fill gap is formed between the adjacent conductor posts 43A of the 43 , to catch the solder 45 〇. As shown in FIG. 7, when a plurality of stackable semiconductor package structures 4 are stacked on each other on a printed circuit board, preferably, each stackable semiconductor package structure 400 further includes a thermal coupling element 460. For example, a Thermal Interface Material (TIM) or a thermal grease is formed on the exposed back surface of the wafer 420, and is thermally coupled to the printed circuit board i or the wafer carrier of the stackable semiconductor package structure 4〇0 41〇, to evenly dissipate heat. In a more detailed embodiment, each stackable half 200905832 conductor package construction 4GG further includes a sealing cartridge 47G, such as an underfill, formed on the lower surface 412 of the wafer carrier 410 to seal the The solder 450 is etched with the wafer 42 to prevent dust from falling or depositing in the POP gap, eliminating possible contamination or electrical shorting. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the above embodiments are in accordance with the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, variations, and modifications made by the invention are still within the scope of the technical solution of the present invention. >', [Simple description of the drawing] Fig. 1: A schematic diagram of a carrier surface of a plurality of stackable semiconductor package structures. 〇 Fig. 2 is a cross-sectional view showing a stack of stacked semiconductor packages of a multi-column according to a first embodiment of the present invention. Figure 3 is a perspective view of a bump set under the stackable semiconductor package construction in accordance with a first embodiment of the present invention. 4A and 4B are views showing a comparison of a top surface and a bottom portion of a plurality of conductor posts of a lower bump group in the stackable semiconductor package structure in accordance with a first embodiment of the present invention. Fig. 5 is a cross-sectional view showing the stacked semiconductor package structures of another multi-column 14 200905832 stacked on each other in accordance with a second embodiment of the present invention. Figure 6 is a schematic view showing the misalignment relationship of the conductor pillars of the lower bump group corresponding to the bump group on the stackable semiconductor package structure according to the second embodiment of the present invention. Figure 7: According to a third embodiment of the present invention, a plurality of multi-columns
之可堆疊半導體封裝構造相互堆疊在一印刷 電路板上之截面示意圖。 【主要元件符號說明】 10 印刷電路板 1〇〇可堆疊半導體封裝構造A cross-sectional view of the stackable semiconductor package structures stacked on one another on a printed circuit board. [Main component symbol description] 10 Printed circuit board 1〇〇 Stackable semiconductor package structure
π 0晶片載體 1 1 3轉接墊 120晶片 140封膠體 2〇〇可堆疊半導體封裝構造 210晶片載體 211上表面 2 1 3轉接墊 220晶片 230下凸塊組 240封膠體 3〇〇可堆疊半導體封裝構造 310晶片載體 311上表面 3 1 3轉接墊 3 1 4外接墊 111上表面 11 4外接墊 121銲線 1 5 0鲜料 2 1 4外接墊 221銲線 23 1中央導體柱 250銲料 112下表面 11 5打線槽孔 1 3 0單柱凸塊 2 1 2下表面 2 1 5打線槽孔 232周邊導體柱 3 1 2下表面 15 200905832 3 20晶片 321銲線 330下凸塊組 331導體柱 340上凸塊組 341導體柱 3 50封膠體 360銲料 400可堆疊半導體封裝構造π 0 wafer carrier 1 1 3 transfer pad 120 wafer 140 encapsulant 2 〇〇 stackable semiconductor package structure 210 wafer carrier 211 upper surface 2 1 3 transfer pad 220 wafer 230 lower bump set 240 encapsulant 3 〇〇 stackable Semiconductor package structure 310 wafer carrier 311 upper surface 3 1 3 transfer pad 3 1 4 external pad 111 upper surface 11 4 external pad 121 bonding wire 1 5 0 fresh material 2 1 4 external pad 221 wire 23 1 central conductor column 250 solder 112 lower surface 11 5 wire slot 1 3 0 single column bump 2 1 2 lower surface 2 1 5 wire slot hole 232 peripheral conductor column 3 1 2 lower surface 15 200905832 3 20 wafer 321 wire bonding 330 lower bump group 331 conductor Column 340 on bump set 341 conductor post 3 50 sealant 360 solder 400 stackable semiconductor package construction
4 1 0晶片載體 413第一墊 420晶片 430下凸塊組 41 1上表面 414第二墊 421凸塊 431導體柱 412下表面 460熱耦合元件 440封膠體 450銲料 470密封膠 S 1 銲料填入間隙S2 銲料填入間隙 S3 銲料填入間隙S4 銲料填入間隙 164 1 0 wafer carrier 413 first pad 420 wafer 430 lower bump set 41 1 upper surface 414 second pad 421 bump 431 conductor post 412 lower surface 460 thermal coupling element 440 sealant 450 solder 470 sealant S 1 solder fill Gap S2 Solder fill gap S3 Solder fill gap S4 Solder fill gap 16