200905805 九、發明說明： 【發明所屬之技術領域】 本發明提供一種嵌入式靜態隨機存取記憶體的製作方 法’尤指一種可以降低嵌入式靜態隨機存取記憶體之隨機 單一位元故障之方法。 【先前技術】 在肷入式靜怨隨機存取記憶體(embedded static random access memory ; embedded SRAM)中，包含有邏輯 電路(logic circuit)和與邏輯電路連接之靜態隨機存取記憶 體。靜悲機存取5己憶體本身係屬於一種揮發性(volatile) 的記憶單元(memory cell)，亦即當供給靜態隨機存取記憶 體之電力消失之後，所儲存之資料會同時抹除。靜態隨機 存取記憶體儲存資料之方式是利用記憶單元内電晶體的導 電狀態來達成’靜態隨機存取記憶體的設計是採用互耦合 電晶體為基礎’沒有電容器放電的問題，不需要不斷充電 以保持資料不流失’也就是不需作記憶體更新的動作，這 與同屬揮發性記憶體的動態隨機存取記憶體(Dynamic Random Access Memory ; DRAM)利用電容器帶電狀態儲存 資料的方式並不相同。靜態隨機存取記憶體之存取速度相 當快，因此有在電腦系統中當作快取記憶體(cache memQI7) 等之應用。 200905805 請參考第1圖，第1圖為一典型六電晶體靜態隨機存 取記憶體（six-transistor SRAM; 6T-SRAM)記憶單元之電路 圖。此6T-SRAM記憶單元10係由上拉電晶體(puii_Up transistor) 12 和 14、下拉電晶體（Pull-Down transistor)16 和 18以及存取電晶體(Access transistor)20和22構成正反器 (flip-flop)，其中上拉電晶體12和14及下拉電晶體16和 18構成栓鎖電路(iatch) ’使資料可以栓鎖在儲存結點 (Storage Node)24或26。其中，上拉電晶體12和14係作 為主動負載之用，其亦可以一般之電阻來取代做為上拉元 件，在此情況下即為四電晶體靜態隨機存取記憶體 (four-transistor SRAM; 4T-SRAM)。 一般而言，6T-SRAM記憶單元1〇之上拉電晶體12、 14 係由 P 型金氧半導體(P_type metal 〇xide semie(md⑽ PMOS)電晶體所組成，而下拉電晶體16、18和存取電晶體 20、22則是由N型金氧半導體(N_type metal 〇xide semiconductor ;NMOS)電晶體所組成。其中，上拉電晶體 12和下拉電晶體16構成之串接電路28，其兩端點分別耦 接於一電壓源32與一接地線34 ;同樣地，上拉電晶體14 與下拉電晶體18構成之串接電路3〇，其兩端點亦分別柄 接於電壓源32與接地線34。 此外，在儲存結點24處，係分別電連接有下拉電晶體 7 200905805 18和上拉電晶體14之閘極（gate)、及下拉電晶體16、上 拉電晶體12和存取電晶體20的汲極(Drain);同樣地，在 儲存結點26上’亦分別電連接有下拉電晶體16和上拉電 晶體12之閘極、及下拉電晶體18、上拉電晶體14和存取 電晶體22的汲極。至於存取電晶體2〇和22的閘極則耦接 至子元線(Word Line)36，而存取電晶體20和22的源極 (Source)則分別耦接至相對應之位元線(Data Line)3 8。 隨著製程線寬的縮減，如何增加電晶體的有效電容值 一直是電晶體製程中極欲改善的問題。因為電晶體中的閘 極在閘極介電層（gate dielectric layer)介面處於反轉態 (inversion)的條件下，具有比金屬還少的電流載子密度。這 將會造成較低的有效電容值，通常將此有效電容值轉換並 以介電層反轉厚度(dielectric inversion thickness，Tox INV) 來表示。目前增加電晶體有效電容值的方法大致有兩種， 其一是對電晶體中閘極介電層材質的改善，例如，高介電 常數(high-K)材料的使用或是降低閘極介電層的厚度；另一 為降低閘極的空乏區。其中，降低閘極空乏區普遍使用的 方式是在複晶石夕閘極摻雜原子(dopant atoms)或離子植入 (implant)，以提高閘極在閘極介電層介面中的載子密度。 目前業界最常使用的離子植入方式為在閘極之閘極導 電層（gate conductive layer)沉積之後，隨即對形成N型金氧 200905805 半導體電晶體的閘極導電層進行一 N+複晶石夕佈植製程(N+ polysilicon implant) ’ 如美國專利 US 2003/0032231 A1 中之 第38、47段所揭示的步驟，藉以有效達到降低介電層反轉 厚度(Tox_INV)的功效。 請參考第2圖，第2圖為一簡化的嵌入式靜態隨機存 取記憶體之佈局圖，其包含有一半導體基底40，半導體基 底40上定義有一記憶單元區（memory cell area)42和一邏輯 區44(logic area)，然後再依電路設計與功能屬性之不同， 於半導體基底40之記憶單元區42和邏輯區44中分別形成 複數個主動區域46，以及所需之N型摻雜井48和P型摻 雜井50。接著，於N型摻雜井48和P型摻雜井50以及主 動區域46上形成一圖案化矽層52,因此定義出一 6T-SRAM 5己憶早元60於s己憶早元區42，並同時定義出一邏輯元件 (logic device)80於邏輯區44中，此邏輯元件80為一互補 式金氧半導體（complementary metal-oxide semiconductor ; CMOS)。其中，如第2圖所示，記憶單元區42的6t_sram 記憶單元60包含有上拉電晶體62和64、下拉電晶體66 和68、以及存取電晶體70、72。而上拉電晶體62和下拉 電晶體66共用同一閘極74，上拉電晶體64和下拉電晶體 68共用同一閘極76，存取電晶體7〇和72共用同一閘極 78。此外，邏輯區44中的邏輯元件8〇包含有p型金氧半 導體電晶體82和N型金氧半導體電晶體84，其問極分別 200905805 為86和88 。 若利用習知降低閘極空乏區的方式，例如美國專利 2003/0032231 A卜對形成N型金氧半導體電晶體的閘木 電層進行一 N+複晶矽佈植製程，則第2圖中p型 °、 、 ☆雜并 50上的閘極即為摻雜N+離子的閘極。值得注意的是 拉電晶體62和下拉電晶體66共用同一閘極74，同後\上 上拉電晶體62和下拉電晶體％共用另一閘極74，亦苣 於P型摻雜井50上共用之閘極74、76的部份分別為N货 電晶體66、68的閘極，佈植有N+離子，而在N型捡卞杈 48上共用之閘極74、76的部份是沒有佈植N+離子:雜外 用來當作上拉電晶體62、64的閘極。 在理想情況下’這兩個位於p型摻雜井5〇上之 晶體66、68對應的閘極74、76會具有相同濃度的n把電 但是由於在定義主祕域的過程中時常會產生些子， 如滅⑽㈣’在侧閘極製程巾間極線寬的變異1移 N+複晶石夕佈植$程遮罩之偏移等製程或其他非製程肉从及 素’常常使得靜態隨機存取記憶體中兩個相對稱的= 74、乃具有不對稱的n+離子濃度。這種不對稱的離^ =成上拉電晶體62和64在汲極端之相對飽和電J農 差異增加，因而導致此記憶單元故障，亦即該靜ς二 取記憶體所儲存的位元故障。所以，雖 10 200905805 體電晶體的閘極佈植N+離子可以減少介電層反轉厚度 (Tox_INV)以增加電晶體的有效電容值，但卻大大地增加記 憶體記憶陣列（memory array)中隨機單一位元(Random Single Bit ； RSB)故障的機率。 因此，如何提供一種可降低嵌入式靜態隨機存取記憶 體隨機單一位元故障機率的製程方法，仍為業界目前亟待 研究的方向。 / 【發明内容】 本發明之主要目的在於提供一種製作嵌入式靜態隨機 存取記憶體的方法，以降低隨機單一位元故障的機率。 根據本發明之申請專利範圍，係提供一種製作嵌入式 靜態隨機存取記憶體的方法。首先，提供一半導體基底， , 其上定義有一邏輯區和一記憶單元區，且該邏輯區和該記 憶單元區又分別定義有至少一第一導電型式元件區和至少 一第二導電型式元件區。接著形成一圖案化遮罩，覆蓋該 記憶單元區以及該邏輯區之該第二導電型式元件區，並曝 露該邏輯區之該第一導電型式元件區。然後對曝露之該邏 輯區的該第一導電型式元件區進行一第一導電型式之離子 佈植製程，最後去除該圖案化遮罩。 200905805 根據本發明之申請專利範圍，其另揭露一種製作嵌入 式靜態隨機存取記憶體的方法。首先，提供一半導體基底， 其上定義有一邏輯區和一記憶單元區，該邏輯區又定義有 至少一 NMOS電晶體區和至少一 PMOS電晶體區，且該記 憶單元區又定義有至少一上拉電晶體區和至少一下拉電晶 體區。接著形成一圖案化遮罩，覆蓋該記憶單元區之該上 拉電晶體區、該下拉電晶體區與該邏輯區之該PMOS電晶 體區，並曝露該邏輯區之該NMOS電晶體區。最後對曝露 之該邏輯區的該NMOS電晶體區進行一 N型離子佈植製 程，並去除該圖案化遮罩。 根據本發明之申請專利範圍，其又揭露一種製作嵌入 式靜態隨機存取記憶體的方法。首先，提供一半導體基底， 其上定義有一邏輯區和一記憶單元區，該邏輯區又定義有 至少一 NMOS電晶體區和至少一 PMOS電晶體區，且該記 憶單元區又定義有至少一上拉電晶體區和至少一下拉電晶 體區。接著形成一圖案化遮罩，覆蓋該記憶單元區之該上 拉電晶體區、該下拉電晶體區與該邏輯區之該NMOS電晶 體區，並曝露該邏輯區之該PMOS電晶體區。最後對曝露 之該邏輯區的該PMOS電晶體區進行一 P型離子佈植製 程，並去除該圖案化遮罩。 200905805 【實施方式】 請參考第3圖，第3圖為本發明之嵌入式靜態隨機存 取記憶體之佈局圖，其包含有一半導體基底100，半導體 基底100上定義有一記憶單元區（memory cell area)102和一 邏輯區（logic area) 104，然後再依電路設計與功能屬性之 不同，於半導體基底100之記憶單元區102和邏輯區1〇4 中分別形成複數個主動區域106，以及所需之N型摻雜井 108和P型摻雜井110，因此，形成於N型摻雜井1〇8上 的元件為P型導電型式元件，而形成於P型摻雜井11〇上 的元件為N型導電型式元件，亦即本第一較佳實施例之n 型摻雜井108可包含複數個p型導電型式元件區，且每— P型導電型式元件區可用以形成一 P型導電型式元件，而p 型摻雜井110可包含複數個N型導電型式元件區，且每一 N型導電型式元件區可用以形成一 n型導電型式元件。接 著’於N型摻雜井108和P型摻雜井110以及主動區域1〇6 上形成圖案化矽層112,然後進行相對應之源極/汲極佈植 製程，因此定義出一 6T-SRAM記憶單元120於記憶單元區 102 ’並同時定義出一邏輯元件(i〇gic device)i4〇於邏輯區 104中，此邏輯元件140可為一互補式金氧半導體。 其中，如第3圖所示，記憶單元區1〇2的6T_SRAM記 憶單元120包含有上拉電晶體122和124、下拉電晶體126 和128、以及存取電晶體130、132。而上拉電晶體122和 13 200905805 ,下拉電晶體126共用同一閘極134,上拉電晶體124和下 拉電晶體128共用同1極136，存取電晶體13〇和132 共用同-閘極135。此外，邏輯區1〇4中的邏輯元件14〇 包含有P型金氧半導體電晶體142和N型金氧半導體電晶 體144 ’其閘極分別為146和148。 ▲第4圖至第6圖為本發明第一較佳實施例之彼入式靜 ,存取記Μ的製造方法^意圖，其顯*如何製作出 第3圖之佈局圖的製程示意圖，其中為彰顯本發明之特徵 並簡化說明，第4圖到第6圖僅顯示出第3圖中記憶單元 區102和邏輯區104中沿著切線ΑΑ，、切線Ββ,和切線cc, 之剖面示意圖。請參考第4圖，首先提供一半導體基底 100 ’例如一矽基底或一絕緣層上覆矽（silic〇n 〇n Insulat沉； SOI)基底等。半導體基底loo包含有至少一 n型摻雜井108 和至少一 P型摻雜井110,並利用淺溝渠138加以隔離， 、 隨後於半導體基底1〇〇上覆蓋一由矽氧化合物、氮石夕化合 物等絕緣材料所構成之介電層150，並於介電層15〇上覆 蓋一由多晶矽、金屬矽化物等導電材料所構成之矽層152。 接著’如第5圖所示，於記憶單元區102的石夕層152 上覆蓋一圖案化遮罩154，例如一光阻圖案，同時於邏輯 • 區1〇4之>1型摻雜井1〇8上的矽層152上覆蓋圖案化遮罩 154，亦即僅曝露出邏輯區104的P型摻雜井11()上的石夕層 14 200905805 :::二曝露_層152進行，離子佈植製程 156,接者移除圖案化遮罩154。根據本 施例，N+離子佈值製程156的N+離子可為鱗離弟匕 型摻質，佈植能量為4〜5Kev，佈植劑量 方公分(i〇nS/CmV 咖離子/平 接著，如第6圖所示，姓刻石夕層152以及介電_ 15〇(未 148 3 其中閘極134、135和146是沒有佈值離 子的閘極〜、有閘極148有佈植Ν+離子。此外，上述第$ 離Γ:植製程156亦可以第6圖所示之閘極形 範:4製程順序之均等變化輿修飾，屬本 敢後’於閘極134、135、146和14R从 雁夕相丨辟工 的側壁形成相對 應之側壁子，然後提供一圖案化遮罩 換雜井108 μ ^ . ^爪）覆蓋於Ν型 修雜开108上，接著再進行一 Ν型源極 於扮^ 久極佈植製程，以 、歪摻雜井110之半導體基底1〇〇中形 釦、、》托广^ 丁〜成所需之源極區 :極£(未顯示）；在去除圖案化遮罩之後，隨後再提供 一圖案化遮罩（未顯示）覆蓋於P型摻雜井110上，接著進 行 P型源極/汲極佈植製程，以於N型摻雜井108之半導 一氐中1 〇〇形成源極區和汲極區（未顯示），去除圖案化 遮罩。根據本發明之較佳實施例，N⑽極/汲極佈植製程 15 200905805 的離子可為磷離子等之N型摻質，佈植能量約為3Kev，佈 植劑量為2〜3E15離子/平方公分(i〇ns/cm2)。值得注意的 是，此N型源極/汲極佈植製程亦可以同時佈植於下拉電晶 體126、128或是存取電晶體130、132的閘極上，這種N 型源極/汲極離子可視為一種補償離子，以作為記憶單元區 102之各電晶體的閘極省略N+離子佈值製程156之補償。 々凊參考第7圖至第10圖，第7圖至第1〇圖為本發明 第:較佳.實施例之嵌入式靜態隨機存取記憶體的製造方法 不忍=，其顯示本發明另一種如何製作出第3圖之佈局圖 的製程示思圖，其中為彰顯本發明之特徵並簡化說明， 〇圖僅顯示出第3圖中記憶單元區1〇2和邏輯ρ 104中外芏丄上 々、饵(aa 如第〇者刀線AA’、切線BB’和切線CC，之剖面示意圖。 7圖所示，首先提供一半導體基底1〇〇，例如一 底或-' 紹《立〇 土 至少〜、、€緣層上覆矽（s〇I)基底等。半導體基底1〇〇包含有 N型摻雜井108和至少一 P型摻雜井110，並利用 淺溝渠J m 含矽& 加以隔離，隨後於半導體基底100上覆蓋—包 化合物、氮矽化合物等絕緣材料之介電層150，並 於介電層^ 兀 料之 上覆蓋一包含多晶石夕、金屬石夕化物等導電材 ^夕層152。 镇著 上覆蓋’如第8圖所示’於記憶單元區的矽層152 圖案化遮罩154，例如一光阻圖案，同時於邏輯 16 200905805 區104的N型摻雜井1〇8上的石夕層上覆蓋圖案化 154亦即僅曝路出邏輯區1〇4的p型換雜井⑽上的石夕層 152。|^即’對曝露出的石夕層152進行—離子佈值製程 156 ’接著移除圖案化遮罩154。依照本發明之第二較佳實 知例》亥N+離子佈值製程156❺N+離子彳為罐離子等之 N型摻質，佈植能量為4〜5Kev，佈植劑量約為5E15離子/ 平方公分(i〇ns/cm2)。 然後，如第9圖所示，於邏輯區1〇4的p型摻雜井ιι〇 上的矽層152覆蓋一圖案化遮罩158，例如一光阻圖案， 亦即曝露出5己憶單元區102的矽層152和邏輯區1〇4之N 型摻雜井1G8上㈣層152。隨即，對曝露出的㈣152 進行一 P+離子佈植製程16〇，然後移除圖案化遮罩158。 如習知相關技者與通常知識者所熟知，上述第9圖所示 之P+離子佈植製程160亦可以在第8圖所示之N+離子佈 值製程156之刖實施’此冑p+、N+離子佈植順序之均等變 化與修飾’皆應屬本發明之涵蓋範圍。 接著’如第1〇圖所示’蝕刻矽層152以及介電層15〇 (未顯示）以形成閘極134、135、146和148，树完成如第 2圖所示之佈局圖。其中間極134、135和146是有佈值^ 離子的閘極’而閘極148是有佈植N+離子的閘極。此外， 上述第8圖和第9圖所示<Ν+、ρ+離子佈植製程156、⑽ 200905805 . 亦可以第10圖所示之閘極形成之後實施，此等製程順序之 均等變化與修飾，皆應屬本發明之涵蓋範圍。 最後’於各閘極134、135、146和148的侧壁形成相 對應之側壁子’然後提供一圖案化遮罩（未顯示）覆蓋於N 型摻雜井l〇8_h，接著再進行- >^源極/汲極佈植製程， 以^ p型摻雜井110之半導體基底1〇〇 +形成源極區和汲 極區（未顯示）’而在去除圖案化遮罩之後，隨後再提供一 圖案化遮罩（未顯示）覆蓋於p型摻雜井110上，接著進行 一 P型源極/汲極佈植製程，以於摻雜井1〇8之半導體 基底中形成源極區和彡及極區（未顯示），去除圖案化遮罩。 根據本發明之難實施例，N魏極你_植製程的離子 可為磷離子等型摻質，佈植能量約為3Kev,佈植劑量 為2〜3E15離子/平方公分(ions/cm2)。同樣地，此N型源極 //及極佈植製私亦可以同時佈植於下拉電晶體1、1或 、是存取電晶體13G、132的閘極上’這種N型源極/没極離 子可視為一種補償離子，以作為記憶單元區1〇2之各電晶 體的閘極省略N+離子佈植製程156之補償。 請參考第η圖至第13圖，第u圖至第13圖為本發 明第三較佳實施例之鼓入式靜態隨機存取記憶體的製造方 法示意圖，其顯示本發明又-種如何製作出第3圖之佈局 圖的製程示意圖，其中為彰顯本發明之特徵並簡化說明， 18 200905805 第1 1圖至笛q Q π 3圖僅顯示出第3圖中記憶單元區i〇2和邏 輯區104中> & σ者切線AA，、切線BB，和切線CC，之剖面示意 圖。如第〗1闽 _ 、 圖所示’首先提供一半導體基底100，例如一 =基底或—絕緣層上覆邦01)基底等。半導體基底100包 3有至V Ν型摻雜井108和至少一 Ρ型摻雜井110，並 利用淺溝渠Α h加以隔離’隨後於半導體基底100上覆蓋 由夕氧化合物、氮矽化合物等絕緣材料所構成之介電層 並於；I電層150上覆蓋一由多晶矽、金屬矽化物等導 電材料所構成切層152。 接著’如第12圖所示，於記憶單元區102的矽層152 上覆蓋一圖案化遮罩17〇，例如一光阻圖案，同時於邏輯 區1〇4之P型摻雜井11〇上的矽層152上覆蓋圖案化遮罩 17〇’亦即僅曝露出邏輯區104的N型摻雜井108上的矽層 152。隨即，對曝露出的矽層152進行一 p+離子佈植製程 ’接著移除圖案化遮罩17〇。 接著’如第13圖所示，蝕刻矽層152以及介電層15〇 (未顯示）以形成閘極134、135、146和148，亦即完成如第 3圖所示之佈局圖。其中閘極134、I%和i48是沒有佈值 離子的閘極’只有閘極146有佈植P+離子。此外，上述第 12圖所示之P+離子佈植製程172亦可以第13圖所示之閘 極形成之後實施’此等製程順序之均等變化與修飾，皆應 19 200905805 屬本發明之涵蓋範圍。 最後’於閘極134、135、146和148的 應之側壁子，然後提供一圖案化遮罩（未顯示^壁形成相對 摻雜井108上，接著再進行—N型源極覆蓋於N型 於P型摻雜井m之半導體基底謂中形成戶，製程’以 和没極區(未顯示）；在去除圖案化遮罩之後， 一圖案化遮罩（未顯示）覆蓋於P型摻雜井11〇上，接著進 仃一 p型源極/汲極佈植製程，以於N型摻雜井ι〇8之半導 體基底中1〇〇形成源極區和汲極區（未顯示），去除圖案化 遮罩。值得〉主意的是，此P型源極/汲極佈植製程亦可以同 時佈植於上拉電晶體122和124,這種P型源極/汲極離子 可視為—種補償離子，以作為記憶單元區102之各電晶體 的閘極省略p+離子佈值製程156之補償。 第14圖至第17圖為本發明第四較佳實施例之嵌入式 靜悲隨機存取記憶體的製造方法示意圖，其顯示本發明再 種如何製作出第3圖之佈局圖的製程示意圖，其中為彰 顯本發明之特徵並簡化說明，第14圖至第17圖僅顯示出 第3圖中記憶單元區1〇2和邏輯區1〇4中沿著切線AA’、 切線BB’和切線CC，之剖面示意圖。如第14圖所示，首先 提供—半導體基底100 ,例如一矽基底或一絕緣層上覆矽 (S〇I)基底等。半導體基底100包含有至少一 N型摻雜井 20 200905805 108和至少一 P型摻雜井110，並利用淺溝渠138加以隔 離，隨後於半導體基底100上覆蓋一包含矽氧化合物、氮 矽化合物等絕緣材料之介電層150，並於介電層150上覆 蓋一包含多晶矽、金屬矽化物等導電材料之矽層152。 接著，如第15圖所示，於記憶單元區102的矽層152 上覆蓋一圖案化遮罩170，例如一光阻圖案，同時於邏輯 區104的P型摻雜井110上的矽層152上覆蓋圖案化遮罩 170,亦即僅曝露出邏輯區104的N型摻雜井108上的矽層 152。隨即，對曝露出的矽層152進行一 P+離子佈植製程 172，接著移除圖案化遮罩170。 然後，如第16圖所示，於邏輯區104的N型摻雜井 108上的矽層152上覆蓋一圖案化遮罩174,例如一光阻圖 案，亦即曝露出記憶單元區102的矽層152和邏輯區104 之P型摻雜井110上的矽層152。隨即，對曝露出的矽層 152進行一 N+離子佈植製程176，然後移除圖案化遮罩 174。如習知相關技藝者與通常知識者所熟知，上述第16 圖所示之N+離子佈植製程176亦可以在第15圖所示之P+ 離子佈植製程Π2之前實施，此等P+、N+離子佈值順序之 均等變化與修飾，皆應屬本發明之涵蓋範圍。 接著，如第17圖所示，蝕刻矽層152以及介電層150 21 200905805 •(未顯示）以形成閘極134、135 ' 146和148，亦即完成如第 2圖所示之佈局圖。其中閘極134、135和148是有佈值讲 離子的閘極，而閘極146是有佈植！>+離子的問極。此外， 上述第15圖和第16圖所示之p+、N^子佈植製程Μ、 176亦可以帛17圖所示之閘極形成之後實施，此等製程順 序之均等變化與修飾，皆應屬本發明之涵蓋範圍。 、 最後，於閘極m、135、！46和148的側壁形成相對 :之側壁子’然後提供—圖案化遮罩(未顯示）覆蓋於N型 夕雜井108上，接著再進行—N型源極/沒極佈植製程，以 摻雜井11〇之半導體基底！⑼中形成所需之 和錄區（未顯示）；在去除圖案化料之後，隨後再提^ /圖案化料(麵*)覆蓋於p型摻料110上，接著進 P型源極/没極佈植製程，以於N型摻雜井⑽之半導 遮ΓΙ’ ：成源極區和沒極區(未顯示)，去除圖案化 味饮 病是，❹魏極/祕佈植製程亦可以同 時佈植於上拉電晶雜《 可Μ這種？型源極/沒極離子 Τ視為-種_離子，以作為記憶單㈣ 的閑極省略Ρ+離子佈值製 各電曰曰體 留先====取記憶體製程之特點在於保 饰植製程，但是r ?金氣半導體電晶體的Ν+離子 子隐早疋區中的N型金氧半導體電晶 22 200905805 體進行此N+離子佈植製程。因此本發明能有效解決靜態隨 機存取記憶體中互為對稱之閘極其離子濃度不對稱的問 題，進而降低靜態隨機存取記憶體隨機單一位元故障的機 率，但同時仍可保留了邏輯區之電晶體適當的介電層反轉 厚度(Tox_INV)。值得注意的是，本發明之嵌入式靜態隨機 存取記憶體製程中的記憶單元，並不限定於6T- S RAM記憶 單元，其適用於所有的諸如4T-SRAM等之靜態隨機存取記 憶體和其他反向器等之半導體製程。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖為典型六電晶體靜態隨機存取記憶體記憶單元之電 路圖。 第2圖為習知嵌入式靜態隨機存取記憶體之佈局圖。 第3圖為本發明嵌入式靜態隨機存取記憶體之佈局圖。 第4圖至第6圖為本發明第一較佳實施例之嵌入式靜態隨 機存取記憶體沿著第2圖中的切線AA’，BB’，CC’之製程剖 面示意圖。 第7圖至第10圖為本發明第二較佳實施例之嵌入式靜態隨 機存取記憶體沿著第2圖中的切線八八’，：83’，（：0：’之製程剖 23 200905805 面示意圖。 第11圖至第13圖為本發明第三較佳實施例之嵌入式靜態 隨機存取記憶體沿著第2圖中的切線AA’，BB’，CC’之製程 剖面示意圖。 第14圖至第17圖為本發明第四較佳實施例之嵌入式靜態 隨機存取記憶體沿著第2圖中的切線AA’，BB’，CC’之製程 剖面示意圖。 【主要元件符號說明】 10、60、120 :六電晶體靜態隨機存取記憶體記憶單元 12、14、62、64、122、124 :上拉電晶體 16、18、66、68、126、128 :下拉電晶體 20、22、70、72、130、132 :存取電晶體 24、26 :儲存結點 28、30 :串接電路 32 :電壓源 34 :接地線 36 :字元線 38 :位元線 40、100 :半導體基底 42、102 :記憶單元區 44、104 :邏輯區 46、106 :主動區域 24 200905805 48、108 : N型摻雜井 50、110 : P型摻雜井 52、112 :圖案化矽層 74、76、78、134、135、136 ··共用閘極 80、140 :邏輯元件 82、142 : P型金氧半導體電晶體 84、144 : N型金氧半導體電晶底 86、88、146、148 :閘極 138 :淺溝渠 150 :介電層 152 :矽層 154、158、170、174 :圖案化遮罩 156、176 : N+離子佈值製程 160、172 : P+離子佈值製程 25200905805 IX. Description of the Invention: [Technical Field] The present invention provides a method for fabricating an embedded static random access memory, especially a method for reducing random single bit failure of embedded static random access memory . [Prior Art] In an embedded static random access memory (embedded SRAM), a logic circuit and a static random access memory connected to a logic circuit are included. The memory of the memory is a volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data is erased at the same time. The way SRAM stores data is to use the conductive state of the transistor in the memory cell to achieve 'the design of static random access memory is based on mutual coupling transistor'. There is no capacitor discharge, and there is no need to continuously charge. In order to keep the data from being lost, that is, the operation of updating the memory is not required. This is not the case that the dynamic random access memory (DRAM) of the same volatile memory uses the state of the capacitor to store data. the same. SRAM access speed is relatively fast, so it is used as a cache memory (cache memQI7) in computer systems. 200905805 Please refer to Figure 1. Figure 1 is a circuit diagram of a typical six-transistor SRAM (6T-SRAM) memory cell. The 6T-SRAM memory cell 10 is composed of a puii_up transistor 12 and 14, a pull-down transistor 16 and 18, and an access transistor 20 and 22 to form a flip-flop ( Flip-flop), in which the pull-up transistors 12 and 14 and the pull-down transistors 16 and 18 constitute an iatch 'make the data latched at the storage node 24 or 26. Among them, the pull-up transistors 12 and 14 are used as active loads, and can also be replaced by a general resistor as a pull-up component, in this case a four-transistor static random access memory (four-transistor SRAM). ; 4T-SRAM). In general, the pull-up transistors 12 and 14 of the 6T-SRAM memory cell 1 are composed of a P-type metal 〇xide semie (md(10) PMOS) transistor, and the pull-down transistors 16, 18 and The transistor 20, 22 is composed of an N-type metal 〇xide semiconductor (NMOS) transistor, wherein the pull-up transistor 12 and the pull-down transistor 16 form a series circuit 28, both ends of which The points are respectively coupled to a voltage source 32 and a ground line 34. Similarly, the pull-up transistor 14 and the pull-down transistor 18 form a series circuit 3〇, and the two ends are also respectively connected to the voltage source 32 and the ground. Line 34. Further, at the storage node 24, a pull-down transistor 7 200905805 18 and a gate of the pull-up transistor 14 are connected, and a pull-down transistor 16, a pull-up transistor 12, and an access are electrically connected. Drain of the transistor 20; likewise, the gate of the pull-down transistor 16 and the pull-up transistor 12, and the pull-down transistor 18, the pull-up transistor 14 are electrically connected to the storage node 26, respectively. And accessing the drain of the transistor 22. As for the gates of the access transistors 2 and 22, the gate is coupled to The source line (Word Line) 36, and the sources of the access transistors 20 and 22 are respectively coupled to the corresponding bit line (Data Line) 38. How to increase as the process line width is reduced The effective capacitance value of the transistor has been a problem that is extremely desired to be improved in the transistor process because the gate in the transistor has a ratio in the state of the gate dielectric layer interface in the inversion state. The metal also has less current carrier density. This will result in a lower effective capacitance value, which is usually converted by the dielectric inversion thickness (Tox INV). There are two main methods for the effective capacitance value. One is to improve the material of the gate dielectric layer in the transistor, for example, the use of a high dielectric constant (high-K) material or to reduce the thickness of the gate dielectric layer. The other is to reduce the depletion region of the gate. Among them, the way to reduce the common use of the gate depletion zone is to increase the gate in the doped stone or the implant atom. Carrier density in the gate dielectric interface The most commonly used ion implantation method in the industry is to perform an N+ double-coated spar on the gate conductive layer forming the N-type gold oxide 200905805 semiconductor transistor after deposition of the gate conductive layer of the gate. The N+ polysilicon implant 'has the steps disclosed in paragraphs 38 and 47 of US Patent No. 2003/0032231 A1, thereby effectively achieving the effect of reducing the dielectric layer inversion thickness (Tox_INV). Referring to FIG. 2, FIG. 2 is a simplified embedded static random access memory (DRAM) layout including a semiconductor substrate 40 having a memory cell area 42 and a logic defined thereon. A logic area 44, and then a plurality of active regions 46 and a desired N-type doping well 48 are formed in the memory cell region 42 and the logic region 44 of the semiconductor substrate 40, respectively, depending on circuit design and functional properties. And P-type doping well 50. Next, a patterned germanium layer 52 is formed on the N-type doping well 48 and the P-type doping well 50 and the active region 46, thus defining a 6T-SRAM 5 reminiscent of the early 60 in the suffix early zone 42 At the same time, a logic device 80 is defined in the logic region 44. The logic device 80 is a complementary metal-oxide semiconductor (CMOS). Here, as shown in FIG. 2, the 6t_sram memory unit 60 of the memory cell region 42 includes pull-up transistors 62 and 64, pull-down transistors 66 and 68, and access transistors 70, 72. The pull-up transistor 62 and the pull-down transistor 66 share the same gate 74. The pull-up transistor 64 and the pull-down transistor 68 share the same gate 76, and the access transistors 7A and 72 share the same gate 78. In addition, the logic element 8 in the logic region 44 includes a p-type MOS transistor 82 and an N-type MOS transistor 84, the terminals of which are 86 and 88, respectively, 200905805. If a conventional method of reducing the gate depletion region is used, for example, U.S. Patent No. 2003/0032231 A, for the formation of an N-type polycrystalline silicon germanium for the formation of an N-type MOS transistor, an N+ polysilicon implantation process is illustrated. The gates on the types °, , ☆, and 50 are the gates doped with N+ ions. It should be noted that the pull-up transistor 62 and the pull-down transistor 66 share the same gate 74, and the upper-upper pull-up transistor 62 and the pull-down transistor % share the other gate 74, which is also used on the P-type doping well 50. The portions of the shared gates 74, 76 are respectively the gates of the N cargo transistors 66, 68, which are implanted with N+ ions, and the portions of the gates 74, 76 shared on the N-type 捡卞杈 48 are not The implanted N+ ions are used as the gates of the pull-up transistors 62, 64. Ideally, the two gates 74, 76 of the two crystals 66, 68 located on the p-type doping well 5 will have the same concentration of n-power but will often be generated during the process of defining the main domain. Some of them, such as the extinction (10) (four) 'variation in the width of the line width between the side gate process towel 1 shift N + polycrystalline stone eve planting process offset or other non-process meat from the prime 'often make static random Two symmetry = 74 in the access memory have an asymmetric n+ ion concentration. This asymmetry is increased by the relative saturation of the pull-up transistors 62 and 64 at the 汲 extreme, which leads to the failure of the memory unit, that is, the bit failure of the memory stored in the static memory. . Therefore, although 10/0505805 the gate of the body transistor implants N+ ions can reduce the dielectric layer inversion thickness (Tox_INV) to increase the effective capacitance of the transistor, but greatly increase the randomness in the memory memory array. The probability of a single single bit (Random Single Bit; RSB) failure. Therefore, how to provide a process method for reducing the probability of random single bit failure in embedded static random access memory is still in the industry. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a method of fabricating an embedded static random access memory to reduce the probability of random single bit failure. According to the scope of the invention, there is provided a method of fabricating an embedded static random access memory. First, a semiconductor substrate is provided, wherein a logic region and a memory cell region are defined, and the logic region and the memory cell region respectively define at least a first conductive pattern device region and at least a second conductive pattern device region. . A patterned mask is then formed overlying the memory cell region and the second conductive pattern component region of the logic region and exposing the first conductive pattern component region of the logic region. Then, a first conductivity type ion implantation process is performed on the first conductive pattern element region of the exposed logic region, and finally the patterned mask is removed. A method of fabricating an embedded static random access memory is disclosed in the patent application scope of the present invention. First, a semiconductor substrate is provided, and a logic region and a memory cell region are defined thereon. The logic region further defines at least one NMOS transistor region and at least one PMOS transistor region, and the memory cell region defines at least one upper portion. Pulling the crystal region and at least pulling the transistor region at a time. A patterned mask is then formed covering the upper pull-up crystal region of the memory cell region, the pull-down transistor region and the PMOS transistor region of the logic region, and exposing the NMOS transistor region of the logic region. Finally, an N-type ion implantation process is performed on the NMOS transistor region of the exposed logic region, and the patterned mask is removed. In accordance with the scope of the present invention, a method of fabricating an embedded static random access memory is disclosed. First, a semiconductor substrate is provided, and a logic region and a memory cell region are defined thereon. The logic region further defines at least one NMOS transistor region and at least one PMOS transistor region, and the memory cell region defines at least one upper portion. Pulling the crystal region and at least pulling the transistor region at a time. A patterned mask is then formed covering the upper pull-up crystal region of the memory cell region, the pull-down transistor region and the NMOS transistor region of the logic region, and exposing the PMOS transistor region of the logic region. Finally, a P-type ion implantation process is performed on the PMOS transistor region of the exposed logic region, and the patterned mask is removed. 200905805 [Embodiment] Please refer to FIG. 3, which is a layout diagram of the embedded static random access memory of the present invention, which includes a semiconductor substrate 100 on which a memory cell area is defined. 102 and a logic area 104, and then forming a plurality of active regions 106 in the memory cell region 102 and the logic region 1-4 of the semiconductor substrate 100, respectively, depending on circuit design and functional properties, and The N-type doping well 108 and the P-type doping well 110, therefore, the elements formed on the N-type doping well 1〇8 are P-type conductive type elements, and the elements formed on the P-type doping well 11〇 The N-type conductivity type component, that is, the n-type doping well 108 of the first preferred embodiment may include a plurality of p-type conductivity type device regions, and each of the P-type conductivity type device regions may be used to form a P-type conductive The pattern component, and the p-type well 110 may comprise a plurality of N-type conductivity type device regions, and each of the N-type conductivity pattern regions may be used to form an n-type conductivity pattern device. Then, a patterned germanium layer 112 is formed on the N-type doping well 108 and the P-type doping well 110 and the active region 1〇6, and then the corresponding source/drain plating process is performed, thus defining a 6T- The SRAM memory unit 120 is in the memory cell region 102' and defines a logic device (i) in the logic region 104. The logic device 140 can be a complementary metal oxide semiconductor. Here, as shown in Fig. 3, the 6T_SRAM memory cell 120 of the memory cell region 1〇2 includes pull-up transistors 122 and 124, pull-down transistors 126 and 128, and access transistors 130 and 132. The pull-up transistors 122 and 13 200905805, the pull-down transistor 126 share the same gate 134, the pull-up transistor 124 and the pull-down transistor 128 share the same pole 136, and the access transistors 13A and 132 share the same-gate 135 . Further, the logic element 14A in the logic region 1-4 includes a P-type MOS transistor 142 and an N-type MOS transistor 144' whose gates are 146 and 148, respectively. ▲Fig. 4 to Fig. 6 are schematic diagrams showing the manufacturing method of the in-cell static and access recording according to the first preferred embodiment of the present invention, and showing how to fabricate the layout diagram of Fig. 3, wherein To clarify the features of the present invention and to simplify the description, FIGS. 4 to 6 only show cross-sectional views along the tangent ΑΑ, the tangent Ββ, and the tangent line cc in the memory cell region 102 and the logic region 104 in FIG. Referring to Figure 4, a semiconductor substrate 100' is first provided, for example, a germanium substrate or an insulating layer overlying silicon (Sinus) substrate. The semiconductor substrate loo includes at least one n-type doping well 108 and at least one P-type doping well 110, and is isolated by shallow trenches 138, and then covered on the semiconductor substrate 1 by a silicon oxide compound, nitrous oxide The dielectric layer 150 is made of an insulating material such as a compound, and the dielectric layer 15 is covered with a germanium layer 152 made of a conductive material such as polysilicon or metal telluride. Then, as shown in FIG. 5, a patterned mask 154, such as a photoresist pattern, is coated on the shoal layer 152 of the memory cell region 102, and is simultaneously doped in the logic region 1〇4> The patterned layer 152 on the 1 〇 8 is covered with a patterned mask 154, that is, only the shi layer 14 200905805:::two exposed _ layer 152 on the P-type doping well 11 () of the logic region 104 is exposed. The ion implantation process 156 removes the patterned mask 154. According to the embodiment, the N+ ion of the N+ ion cloth value process 156 can be a scaled doped type dopant, the implantation energy is 4~5Kev, and the implantation dose is square centimeter (i〇nS/CmV coffee ion/flat, such as As shown in Fig. 6, the surname engraved layer 152 and the dielectric _ 15 〇 (not 148 3 where the gates 134, 135 and 146 are gates without the value of ions ~, there are gates 148 with implants + ions In addition, the above-mentioned $ Γ Γ: 植 加工 156 can also be shown in Figure 6 of the gate shape: 4 process sequence of the equal change 舆 modified, belongs to the ' after the gate 134, 135, 146 and 14R from The side wall of Yanxi Xiangyu formed a corresponding side wall, and then provided a patterned mask to replace the well 108 μ ^ . ^ claws over the 修 type tamping 108, and then a Ν type source In the process of dressing up, the semiconductor substrate of the doped well 110 is shaped like a button, and the source region of the semiconductor substrate is as follows: extremely expensive (not shown); After patterning the mask, a patterned mask (not shown) is then provided overlying the P-type doping well 110, followed by a P-type source/drain implant process for N The semi-conducting well 108 of the doping well 108 forms a source region and a drain region (not shown) to remove the patterned mask. According to a preferred embodiment of the invention, the N(10) pole/drainage implant process 15 The ions of 200905805 can be N-type dopants such as phosphorus ions, the implantation energy is about 3Kev, and the implantation dose is 2~3E15 ions/cm 2 (i〇ns/cm2). It is worth noting that this N-type source The /pole bucking process can also be implanted on the pull-down transistors 126, 128 or the gates of the access transistors 130, 132. This N-type source/drain ion can be regarded as a compensating ion for use as a memory. The gates of the transistors of the cell region 102 omits the compensation of the N+ ion fabric process 156. Referring to Figures 7 through 10, Figures 7 through 1 are the first embodiment of the present invention: The manufacturing method of the embedded static random access memory is not tolerated, and it shows another process diagram of how to make the layout diagram of the third figure of the present invention. In order to highlight the features of the present invention and simplify the description, the figure only shows In the third figure, the memory cell area 1〇2 and the logic ρ 104 are in the outer 芏丄, bait (aa as the first Schematic diagram of the cutting line AA', the tangent line BB' and the tangent line CC. In the figure 7, firstly, a semiconductor substrate 1〇〇 is provided, for example, a bottom or a ‘““《〇土 at least ~, Covering (s〇I) substrate, etc. The semiconductor substrate 1 includes an N-type doping well 108 and at least one P-type doping well 110, and is isolated by a shallow trench J m containing 矽 & The dielectric layer 150 of an insulating material such as a compound or a ruthenium compound is coated on the surface of the dielectric layer 150, and a conductive material layer 152 including a polycrystalline stone, a metal ceramsite or the like is covered on the dielectric layer. The town is covered with a patterned mask 154, such as a photoresist pattern, as shown in Fig. 8 in the memory cell region, while being on the N-type doping well 1〇8 of the logic 16 200905805 region 104. The Shihua layer is covered with a pattern 154, that is, only the Shishi layer 152 on the p-type well (10) of the logic region 1〇4 is exposed. |^ ie, the exposed lithographic layer 152 is subjected to an ion-clothing process 156' followed by removal of the patterned mask 154. According to the second preferred embodiment of the present invention, the N+ ion cloth value process 156❺N+ ion 彳 is an N-type dopant of a can ion, etc., the implantation energy is 4~5Kev, and the implantation dose is about 5E15 ion/cm 2 ( I〇ns/cm2). Then, as shown in FIG. 9, the germanium layer 152 on the p-type doping well ι of the logic region 1〇4 covers a patterned mask 158, such as a photoresist pattern, that is, exposing the 5 memory cells. The germanium layer 152 of the region 102 and the (four) layer 152 of the N-type doping well 1G8 of the logic region 1〇4. Immediately, a (P) ion implantation process of 16 〇 is performed on the exposed (4) 152, and then the patterned mask 158 is removed. As is well known to those skilled in the art and those skilled in the art, the P+ ion implantation process 160 shown in FIG. 9 can also be implemented after the N+ ion cloth value process 156 shown in FIG. Equal variations and modifications of the ion implantation sequence are intended to be within the scope of the present invention. Next, the etched germanium layer 152 and the dielectric layer 15 〇 (not shown) are formed as shown in Fig. 1 to form gates 134, 135, 146 and 148, and the tree completes the layout as shown in Fig. 2. The intermediate poles 134, 135 and 146 are gates having a value of ions and the gates 148 are gates having N+ ions implanted. In addition, the above-mentioned Figs. 8 and 9 show <Ν+, ρ+ ion implantation process 156, (10) 200905805. It can also be implemented after the formation of the gate shown in Fig. 10, and the equalization of these process sequences is Modifications are intended to be within the scope of the invention. Finally, the sidewalls of each of the gates 134, 135, 146 and 148 are formed to form corresponding sidewalls' and then a patterned mask (not shown) is provided overlying the N-type doping wells 8_h, followed by - > ;^ source/drainage process, with the semiconductor substrate 1〇〇+ of the p-type doping well 110 forming the source and drain regions (not shown), after removing the patterned mask, and then A patterned mask (not shown) is provided overlying the p-type doping well 110, followed by a P-type source/drain implant process to form a source region in the semiconductor substrate of the doped well 1〇8 And the 彡 and polar regions (not shown), remove the patterned mask. According to a difficult embodiment of the present invention, the ions of the N-electrode process can be phosphorous ion-type dopants, the implantation energy is about 3Kev, and the implantation dose is 2~3E15 ions/cm 2 (ions/cm 2 ). Similarly, the N-type source//and the pole implant can also be implanted at the same time on the pull-down transistor 1, 1 or on the gate of the access transistor 13G, 132 'This N-type source / no The polar ions can be regarded as a compensating ion to compensate for the elimination of the N+ ion implantation process 156 as the gate of each of the transistors in the memory cell region 1〇2. Referring to FIG. 11 to FIG. 13 , FIG. 9 to FIG. 13 are schematic diagrams showing a manufacturing method of a sump-type static random access memory according to a third preferred embodiment of the present invention, which shows how the present invention is produced. The process diagram of the layout diagram of FIG. 3, in order to highlight the features of the present invention and simplify the description, 18 200905805 1st 1st to the flute q Q π 3 diagram only shows the memory cell area i〇2 and logic in FIG. In section 104, >& σ is a schematic cross-sectional view of tangent AA, tangent BB, and tangent CC. For example, the first substrate is provided with a semiconductor substrate 100, such as a substrate or an insulating layer overlying substrate, and the like. The semiconductor substrate 100 includes 3 to V Ν type doping wells 108 and at least one Ρ type doping well 110, and is isolated by shallow trenches ' h, and then covered on the semiconductor substrate 100 by an oxide compound such as a cerium compound or a cerium compound. The dielectric layer formed by the material is covered on the I electrical layer 150 by a cut layer 152 composed of a conductive material such as polysilicon or metal telluride. Then, as shown in FIG. 12, a patterned mask 17 is placed on the germanium layer 152 of the memory cell region 102, such as a photoresist pattern, while being on the P-type doping well 11 of the logic region 1〇4. The germanium layer 152 overlies the patterned mask 17', that is, only the germanium layer 152 on the N-type well 108 of the logic region 104 is exposed. Immediately, the exposed ruthenium layer 152 is subjected to a p+ ion implantation process' followed by removal of the patterned mask 17'. Next, as shown in Fig. 13, the germanium layer 152 and the dielectric layer 15 (not shown) are etched to form the gates 134, 135, 146 and 148, i.e., the layout as shown in Fig. 3 is completed. Where gates 134, I%, and i48 are gates without eluted ions. Only gate 146 has implanted P+ ions. In addition, the P+ ion implantation process 172 shown in Fig. 12 can also be performed after the gates shown in Fig. 13 are formed. The equalization and modification of the process sequences are all covered by the present invention. Finally, the sidewalls of the gates 134, 135, 146, and 148 are then provided with a patterned mask (not shown to be formed on the opposite doping well 108, followed by - N-type source overlying the N-type Forming a semiconductor in the semiconductor substrate of the P-type doping well m, a process of 'and the immersion region (not shown); after removing the patterned mask, a patterned mask (not shown) overlying the P-type doping On the well 11〇, a p-type source/drainage implantation process is performed to form a source region and a drain region (not shown) in the semiconductor substrate of the N-type well ι8. The patterned mask is removed. It is worthwhile to note that this P-type source/drain implant process can also be implanted on pull-up transistors 122 and 124 at the same time. This P-type source/drain ion can be regarded as — The compensation ions are used as the gates of the transistors of the memory cell region 102 to omit the compensation of the p+ ion cloth value process 156. Figures 14 to 17 illustrate the embedded static memory of the fourth preferred embodiment of the present invention. A schematic diagram of a method for manufacturing a memory, which shows how the process of the present invention can be used to create a layout diagram of FIG. In the drawings, in order to highlight the features of the present invention and to simplify the description, FIGS. 14 to 17 only show the tangential line AA' and the tangent line BB' in the memory cell region 1〇2 and the logic region 1〇4 in FIG. A cross-sectional view of the tangential line CC. As shown in Fig. 14, first, a semiconductor substrate 100 is provided, such as a germanium substrate or an insulating layer overlying germanium (S〇I) substrate, etc. The semiconductor substrate 100 includes at least one N-type doping. The well 20 200905805 108 and the at least one P-type doping well 110 are separated by a shallow trench 138, and then the semiconductor substrate 100 is covered with a dielectric layer 150 containing an insulating material such as a silicon oxide compound or a nitrogen cerium compound. The dielectric layer 150 is covered with a germanium layer 152 comprising a conductive material such as polysilicon or metal germanide. Next, as shown in FIG. 15, a patterned mask 170 is covered on the germanium layer 152 of the memory cell region 102, for example, The photoresist pattern simultaneously covers the patterned mask 170 on the germanium layer 152 on the P-type well 110 of the logic region 104, that is, only the germanium layer 152 on the N-type well 108 of the logic region 104 is exposed. Immediately, a P+ ion implantation is performed on the exposed ruthenium layer 152. The pattern 172 is followed by removing the patterned mask 170. Then, as shown in FIG. 16, the germanium layer 152 on the N-type well 108 of the logic region 104 is overlaid with a patterned mask 174, such as a photoresist. The pattern, that is, the germanium layer 152 of the memory cell region 102 and the germanium layer 152 on the p-type doping well 110 of the logic region 104. The exposed germanium layer 152 is then subjected to an N+ ion implantation process 176, and then The patterned mask 174 is removed. As is well known to those skilled in the art, the N+ ion implantation process 176 shown in FIG. 16 can also be preceded by the P+ ion implantation process 第2 shown in FIG. Implementation, such equal changes and modifications of the order of P+, N+ ion cloth values are all within the scope of the present invention. Next, as shown in Fig. 17, the germanium layer 152 and the dielectric layer 150 21 200905805 (not shown) are etched to form gates 134, 135' 146 and 148, i.e., the layout shown in Fig. 2 is completed. Among them, the gates 134, 135 and 148 are gates with a value of ions, and the gates 146 are implanted! >+ ion's question. In addition, the p+ and N^ sub-distribution processes Μ and 176 shown in the above-mentioned 15th and 16th drawings can also be implemented after the formation of the gate shown in FIG. 17, and the equalization and modification of the process sequences should be It is within the scope of the invention. Finally, at the gate m, 135,! The sidewalls of 46 and 148 are opposed to each other: the sidewalls are then provided - a patterned mask (not shown) overlying the N-type well 108, followed by an -N source/polar implant process to incorporate The semiconductor substrate of the well 11! The desired recording area (not shown) is formed in (9); after the patterning material is removed, the patterning material (face*) is subsequently overlaid on the p-type dopant 110, followed by the P-type source/none. Extremely implanted process, for the semi-conducting concealer of the N-type doping well (10): into the source region and the non-polar region (not shown), to remove the pattern of taste and drink, is the Wei Wei / secret cloth planting process Can be planted on the top of the electric crystals at the same time. Type source / immersion ion Τ is regarded as a kind of _ ion, as a memory single (four) idle pole Ρ 离子 + ion cloth value system of each electric body first ==== take memory system is characterized by preservation The process of planting, but the N-type MOS semiconductor crystal in the Ν+ ion crypto-deuterium region of the r-type gold-gas semiconductor transistor is performed by the N+ ion implantation process. Therefore, the present invention can effectively solve the problem that the symmetrical gates in the static random access memory are extremely asymmetric in ion concentration, thereby reducing the probability of random single bit failure of the static random access memory, but still retaining the logic region. The appropriate dielectric layer of the transistor is reversed in thickness (Tox_INV). It should be noted that the memory unit in the embedded static random access memory system of the present invention is not limited to the 6T-S RAM memory unit, and is applicable to all static random access memories such as 4T-SRAM. And semiconductor processes such as other inverters. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the invention are intended to be included in the scope of the present invention. [Simple diagram of the diagram] Figure 1 is a circuit diagram of a typical six-cell SRAM memory cell. Figure 2 is a layout diagram of a conventional embedded static random access memory. Figure 3 is a layout diagram of the embedded static random access memory of the present invention. 4 to 6 are schematic cross-sectional views showing the process of the embedded static random access memory according to the first preferred embodiment of the present invention along the tangent lines AA', BB', CC' in Fig. 2. 7 to 10 are embedded static random access memories according to a second preferred embodiment of the present invention along the tangent eight eight', 83', (: 0: ' process section 23 in FIG. FIG. 11 to FIG. 13 are schematic cross-sectional views showing a process of the embedded static random access memory according to the third preferred embodiment of the present invention along a tangent line AA′, BB′, CC′ in FIG. 2 . 14 to 17 are schematic cross-sectional views showing the process of the embedded static random access memory according to the fourth preferred embodiment of the present invention along the tangent lines AA', BB', CC' in Fig. 2. [Main component symbols Description] 10, 60, 120: hexa-crystal SRAM memory cells 12, 14, 62, 64, 122, 124: pull-up transistors 16, 18, 66, 68, 126, 128: pull-down transistors 20, 22, 70, 72, 130, 132: access transistor 24, 26: storage node 28, 30: series circuit 32: voltage source 34: ground line 36: word line 38: bit line 40, 100: semiconductor substrate 42, 102: memory cell region 44, 104: logic region 46, 106: active region 24 200905805 48, 108: N-type doping well 50, 110: P-type doping wells 52, 112: patterned germanium layers 74, 76, 78, 134, 135, 136 · · common gates 80, 140: logic elements 82, 142: P-type MOS transistors 84, 144: N-type MOS semiconductor crystal bottom 86, 88, 146, 148: gate 138: shallow trench 150: dielectric layer 152: germanium layer 154, 158, 170, 174: patterned mask 156, 176 : N+ ion cloth value process 160, 172: P+ ion cloth value process 25